| stats.txt (9285:9901180cd573) | stats.txt (9312:e05e1b69ebf2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.084599 # Number of seconds simulated 4sim_ticks 84599483500 # Number of ticks simulated 5final_tick 84599483500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.084594 # Number of seconds simulated 4sim_ticks 84594088000 # Number of ticks simulated 5final_tick 84594088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 50330 # Simulator instruction rate (inst/s) 8host_op_rate 84358 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 32239425 # Simulator tick rate (ticks/s) 10host_mem_usage 239332 # Number of bytes of host memory used 11host_seconds 2624.10 # Real time elapsed on the host | 7host_inst_rate 94248 # Simulator instruction rate (inst/s) 8host_op_rate 157968 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 60367706 # Simulator tick rate (ticks/s) 10host_mem_usage 238096 # Number of bytes of host memory used 11host_seconds 1401.31 # Real time elapsed on the host |
| 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221362960 # Number of ops (including micro ops) simulated | 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221362960 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 220032 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 124672 # Number of bytes read from this memory 16system.physmem.bytes_read::total 344704 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 220032 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 220032 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 3438 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 1948 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 5386 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 2600867 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 1473673 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 4074540 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 2600867 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 2600867 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 2600867 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 1473673 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 4074540 # Total bandwidth to/from this memory (bytes/s) | 14system.physmem.bytes_read::cpu.inst 220544 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 124864 # Number of bytes read from this memory 16system.physmem.bytes_read::total 345408 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 220544 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 220544 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 3446 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 1951 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 5397 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 2607085 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 1476037 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 4083122 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 2607085 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 2607085 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 2607085 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 1476037 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 4083122 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 5399 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 5664 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 345408 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 345408 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 265 # Reqs where no action is needed 39system.physmem.perBankRdReqs::0 309 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 318 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 319 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 318 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 313 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 372 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 333 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 312 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 261 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 280 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 363 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 438 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 441 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 357 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 367 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 298 # Track reads on a per bank basis 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 73system.physmem.totGap 84594067000 # Total gap between requests 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 5399 # Categorize read packet sizes 81system.physmem.readPktSize::7 0 # Categorize read packet sizes 82system.physmem.readPktSize::8 0 # Categorize read packet sizes 83system.physmem.writePktSize::0 0 # categorize write packet sizes 84system.physmem.writePktSize::1 0 # categorize write packet sizes 85system.physmem.writePktSize::2 0 # categorize write packet sizes 86system.physmem.writePktSize::3 0 # categorize write packet sizes 87system.physmem.writePktSize::4 0 # categorize write packet sizes 88system.physmem.writePktSize::5 0 # categorize write packet sizes 89system.physmem.writePktSize::6 0 # categorize write packet sizes 90system.physmem.writePktSize::7 0 # categorize write packet sizes 91system.physmem.writePktSize::8 0 # categorize write packet sizes 92system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 93system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 94system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 95system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 96system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 97system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 98system.physmem.neitherpktsize::6 265 # categorize neither packet sizes 99system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 101system.physmem.rdQLenPdf::0 4217 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 943 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 188 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 41 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 134system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 167system.physmem.totQLat 16379877 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 123109877 # Sum of mem lat for all requests 169system.physmem.totBusLat 21596000 # Total cycles spent in databus access 170system.physmem.totBankLat 85134000 # Total cycles spent in bank access 171system.physmem.avgQLat 3033.87 # Average queueing delay per request 172system.physmem.avgBankLat 15768.48 # Average bank access latency per request 173system.physmem.avgBusLat 4000.00 # Average bus latency per request 174system.physmem.avgMemAccLat 22802.35 # Average memory access latency 175system.physmem.avgRdBW 4.08 # Average achieved read bandwidth in MB/s 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 177system.physmem.avgConsumedRdBW 4.08 # Average consumed read bandwidth in MB/s 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 180system.physmem.busUtil 0.03 # Data bus utilization in percentage 181system.physmem.avgRdQLen 0.00 # Average read queue length over time 182system.physmem.avgWrQLen 0.00 # Average write queue length over time 183system.physmem.readRowHits 4777 # Number of row buffer hits during reads 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes 185system.physmem.readRowHitRate 88.48 # Row buffer hit rate for reads 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 187system.physmem.avgGap 15668469.53 # Average gap between requests |
| 30system.cpu.workload.num_syscalls 400 # Number of system calls | 188system.cpu.workload.num_syscalls 400 # Number of system calls |
| 31system.cpu.numCycles 169198968 # number of cpu cycles simulated | 189system.cpu.numCycles 169188177 # number of cpu cycles simulated |
| 32system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 33system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 190system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 191system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 34system.cpu.BPredUnit.lookups 20690463 # Number of BP lookups 35system.cpu.BPredUnit.condPredicted 20690463 # Number of conditional branches predicted 36system.cpu.BPredUnit.condIncorrect 2250102 # Number of conditional branches incorrect 37system.cpu.BPredUnit.BTBLookups 15079710 # Number of BTB lookups 38system.cpu.BPredUnit.BTBHits 13739283 # Number of BTB hits | 192system.cpu.BPredUnit.lookups 20680258 # Number of BP lookups 193system.cpu.BPredUnit.condPredicted 20680258 # Number of conditional branches predicted 194system.cpu.BPredUnit.condIncorrect 2246160 # Number of conditional branches incorrect 195system.cpu.BPredUnit.BTBLookups 15085015 # Number of BTB lookups 196system.cpu.BPredUnit.BTBHits 13721428 # Number of BTB hits |
| 39system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 40system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 41system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. | 197system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 198system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 199system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. |
| 42system.cpu.fetch.icacheStallCycles 27218141 # Number of cycles fetch is stalled on an Icache miss 43system.cpu.fetch.Insts 227440359 # Number of instructions fetch has processed 44system.cpu.fetch.Branches 20690463 # Number of branches that fetch encountered 45system.cpu.fetch.predictedBranches 13739283 # Number of branches that fetch has predicted taken 46system.cpu.fetch.Cycles 59726319 # Number of cycles fetch has run and was not squashing or blocked 47system.cpu.fetch.SquashCycles 19306281 # Number of cycles fetch has spent squashing 48system.cpu.fetch.BlockedCycles 65395131 # Number of cycles fetch has spent blocked 49system.cpu.fetch.MiscStallCycles 224 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 50system.cpu.fetch.PendingTrapStallCycles 1651 # Number of stall cycles due to pending traps 51system.cpu.fetch.CacheLines 25701311 # Number of cache lines fetched 52system.cpu.fetch.IcacheSquashes 473765 # Number of outstanding Icache misses that were squashed 53system.cpu.fetch.rateDist::samples 169122323 # Number of instructions fetched each cycle (Total) 54system.cpu.fetch.rateDist::mean 2.213301 # Number of instructions fetched each cycle (Total) 55system.cpu.fetch.rateDist::stdev 3.334482 # Number of instructions fetched each cycle (Total) | 200system.cpu.fetch.icacheStallCycles 27164568 # Number of cycles fetch is stalled on an Icache miss 201system.cpu.fetch.Insts 227213982 # Number of instructions fetch has processed 202system.cpu.fetch.Branches 20680258 # Number of branches that fetch encountered 203system.cpu.fetch.predictedBranches 13721428 # Number of branches that fetch has predicted taken 204system.cpu.fetch.Cycles 59660749 # Number of cycles fetch has run and was not squashing or blocked 205system.cpu.fetch.SquashCycles 19257155 # Number of cycles fetch has spent squashing 206system.cpu.fetch.BlockedCycles 65568957 # Number of cycles fetch has spent blocked 207system.cpu.fetch.MiscStallCycles 236 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 208system.cpu.fetch.PendingTrapStallCycles 1768 # Number of stall cycles due to pending traps 209system.cpu.fetch.CacheLines 25653013 # Number of cache lines fetched 210system.cpu.fetch.IcacheSquashes 474244 # Number of outstanding Icache misses that were squashed 211system.cpu.fetch.rateDist::samples 169131808 # Number of instructions fetched each cycle (Total) 212system.cpu.fetch.rateDist::mean 2.211225 # Number of instructions fetched each cycle (Total) 213system.cpu.fetch.rateDist::stdev 3.333765 # Number of instructions fetched each cycle (Total) |
| 56system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 214system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 57system.cpu.fetch.rateDist::0 111062519 65.67% 65.67% # Number of instructions fetched each cycle (Total) 58system.cpu.fetch.rateDist::1 3230504 1.91% 67.58% # Number of instructions fetched each cycle (Total) 59system.cpu.fetch.rateDist::2 2469579 1.46% 69.04% # Number of instructions fetched each cycle (Total) 60system.cpu.fetch.rateDist::3 3091757 1.83% 70.87% # Number of instructions fetched each cycle (Total) 61system.cpu.fetch.rateDist::4 3527779 2.09% 72.95% # Number of instructions fetched each cycle (Total) 62system.cpu.fetch.rateDist::5 3730060 2.21% 75.16% # Number of instructions fetched each cycle (Total) 63system.cpu.fetch.rateDist::6 4582508 2.71% 77.87% # Number of instructions fetched each cycle (Total) 64system.cpu.fetch.rateDist::7 2803800 1.66% 79.53% # Number of instructions fetched each cycle (Total) 65system.cpu.fetch.rateDist::8 34623817 20.47% 100.00% # Number of instructions fetched each cycle (Total) | 215system.cpu.fetch.rateDist::0 111136116 65.71% 65.71% # Number of instructions fetched each cycle (Total) 216system.cpu.fetch.rateDist::1 3216747 1.90% 67.61% # Number of instructions fetched each cycle (Total) 217system.cpu.fetch.rateDist::2 2468197 1.46% 69.07% # Number of instructions fetched each cycle (Total) 218system.cpu.fetch.rateDist::3 3082745 1.82% 70.89% # Number of instructions fetched each cycle (Total) 219system.cpu.fetch.rateDist::4 3525528 2.08% 72.98% # Number of instructions fetched each cycle (Total) 220system.cpu.fetch.rateDist::5 3731818 2.21% 75.18% # Number of instructions fetched each cycle (Total) 221system.cpu.fetch.rateDist::6 4565922 2.70% 77.88% # Number of instructions fetched each cycle (Total) 222system.cpu.fetch.rateDist::7 2807540 1.66% 79.54% # Number of instructions fetched each cycle (Total) 223system.cpu.fetch.rateDist::8 34597195 20.46% 100.00% # Number of instructions fetched each cycle (Total) |
| 66system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 67system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 68system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 224system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 225system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 226system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 69system.cpu.fetch.rateDist::total 169122323 # Number of instructions fetched each cycle (Total) 70system.cpu.fetch.branchRate 0.122285 # Number of branch fetches per cycle 71system.cpu.fetch.rate 1.344218 # Number of inst fetches per cycle 72system.cpu.decode.IdleCycles 40123368 # Number of cycles decode is idle 73system.cpu.decode.BlockedCycles 55633776 # Number of cycles decode is blocked 74system.cpu.decode.RunCycles 46741593 # Number of cycles decode is running 75system.cpu.decode.UnblockCycles 9842729 # Number of cycles decode is unblocking 76system.cpu.decode.SquashCycles 16780857 # Number of cycles decode is squashing 77system.cpu.decode.DecodedInsts 365282924 # Number of instructions handled by decode 78system.cpu.rename.SquashCycles 16780857 # Number of cycles rename is squashing 79system.cpu.rename.IdleCycles 47679812 # Number of cycles rename is idle 80system.cpu.rename.BlockCycles 14629061 # Number of cycles rename is blocking 81system.cpu.rename.serializeStallCycles 22937 # count of cycles rename stalled for serializing inst 82system.cpu.rename.RunCycles 48366453 # Number of cycles rename is running 83system.cpu.rename.UnblockCycles 41643203 # Number of cycles rename is unblocking 84system.cpu.rename.RenamedInsts 356095908 # Number of instructions processed by rename 85system.cpu.rename.ROBFullEvents 40 # Number of times rename has blocked due to ROB full 86system.cpu.rename.IQFullEvents 17377193 # Number of times rename has blocked due to IQ full 87system.cpu.rename.LSQFullEvents 22149388 # Number of times rename has blocked due to LSQ full 88system.cpu.rename.RenamedOperands 410376112 # Number of destination operands rename has renamed 89system.cpu.rename.RenameLookups 987879370 # Number of register rename lookups that rename has made 90system.cpu.rename.int_rename_lookups 977929387 # Number of integer rename lookups 91system.cpu.rename.fp_rename_lookups 9949983 # Number of floating rename lookups | 227system.cpu.fetch.rateDist::total 169131808 # Number of instructions fetched each cycle (Total) 228system.cpu.fetch.branchRate 0.122232 # Number of branch fetches per cycle 229system.cpu.fetch.rate 1.342966 # Number of inst fetches per cycle 230system.cpu.decode.IdleCycles 40083092 # Number of cycles decode is idle 231system.cpu.decode.BlockedCycles 55790408 # Number of cycles decode is blocked 232system.cpu.decode.RunCycles 46646195 # Number of cycles decode is running 233system.cpu.decode.UnblockCycles 9876583 # Number of cycles decode is unblocking 234system.cpu.decode.SquashCycles 16735530 # Number of cycles decode is squashing 235system.cpu.decode.DecodedInsts 364948187 # Number of instructions handled by decode 236system.cpu.rename.SquashCycles 16735530 # Number of cycles rename is squashing 237system.cpu.rename.IdleCycles 47642140 # Number of cycles rename is idle 238system.cpu.rename.BlockCycles 14699446 # Number of cycles rename is blocking 239system.cpu.rename.serializeStallCycles 23267 # count of cycles rename stalled for serializing inst 240system.cpu.rename.RunCycles 48304644 # Number of cycles rename is running 241system.cpu.rename.UnblockCycles 41726781 # Number of cycles rename is unblocking 242system.cpu.rename.RenamedInsts 355757826 # Number of instructions processed by rename 243system.cpu.rename.ROBFullEvents 35 # Number of times rename has blocked due to ROB full 244system.cpu.rename.IQFullEvents 17417112 # Number of times rename has blocked due to IQ full 245system.cpu.rename.LSQFullEvents 22198638 # Number of times rename has blocked due to LSQ full 246system.cpu.rename.FullRegisterEvents 51 # Number of times there has been no free registers 247system.cpu.rename.RenamedOperands 410011414 # Number of destination operands rename has renamed 248system.cpu.rename.RenameLookups 986948203 # Number of register rename lookups that rename has made 249system.cpu.rename.int_rename_lookups 977030227 # Number of integer rename lookups 250system.cpu.rename.fp_rename_lookups 9917976 # Number of floating rename lookups |
| 92system.cpu.rename.CommittedMaps 259428603 # Number of HB maps that are committed | 251system.cpu.rename.CommittedMaps 259428603 # Number of HB maps that are committed |
| 93system.cpu.rename.UndoneMaps 150947509 # Number of HB maps that are undone due to squashing 94system.cpu.rename.serializingInsts 1877 # count of serializing insts renamed 95system.cpu.rename.tempSerializingInsts 1873 # count of temporary serializing insts renamed 96system.cpu.rename.skidInsts 89979833 # count of insts added to the skid buffer 97system.cpu.memDep0.insertedLoads 89683170 # Number of loads inserted to the mem dependence unit. 98system.cpu.memDep0.insertedStores 32866708 # Number of stores inserted to the mem dependence unit. 99system.cpu.memDep0.conflictingLoads 59054771 # Number of conflicting loads. 100system.cpu.memDep0.conflictingStores 19177166 # Number of conflicting stores. 101system.cpu.iq.iqInstsAdded 343137266 # Number of instructions added to the IQ (excludes non-spec) 102system.cpu.iq.iqNonSpecInstsAdded 5038 # Number of non-speculative instructions added to the IQ 103system.cpu.iq.iqInstsIssued 271920674 # Number of instructions issued 104system.cpu.iq.iqSquashedInstsIssued 307949 # Number of squashed instructions issued 105system.cpu.iq.iqSquashedInstsExamined 121254430 # Number of squashed instructions iterated over during squash; mainly for profiling 106system.cpu.iq.iqSquashedOperandsExamined 247003349 # Number of squashed operands that are examined and possibly removed from graph 107system.cpu.iq.iqSquashedNonSpecRemoved 3792 # Number of squashed non-spec instructions that were removed 108system.cpu.iq.issued_per_cycle::samples 169122323 # Number of insts issued each cycle 109system.cpu.iq.issued_per_cycle::mean 1.607834 # Number of insts issued each cycle 110system.cpu.iq.issued_per_cycle::stdev 1.514763 # Number of insts issued each cycle | 252system.cpu.rename.UndoneMaps 150582811 # Number of HB maps that are undone due to squashing 253system.cpu.rename.serializingInsts 1844 # count of serializing insts renamed 254system.cpu.rename.tempSerializingInsts 1841 # count of temporary serializing insts renamed 255system.cpu.rename.skidInsts 90083407 # count of insts added to the skid buffer 256system.cpu.memDep0.insertedLoads 89641616 # Number of loads inserted to the mem dependence unit. 257system.cpu.memDep0.insertedStores 32814586 # Number of stores inserted to the mem dependence unit. 258system.cpu.memDep0.conflictingLoads 59002795 # Number of conflicting loads. 259system.cpu.memDep0.conflictingStores 19228439 # Number of conflicting stores. 260system.cpu.iq.iqInstsAdded 342836678 # Number of instructions added to the IQ (excludes non-spec) 261system.cpu.iq.iqNonSpecInstsAdded 4827 # Number of non-speculative instructions added to the IQ 262system.cpu.iq.iqInstsIssued 271794183 # Number of instructions issued 263system.cpu.iq.iqSquashedInstsIssued 309279 # Number of squashed instructions issued 264system.cpu.iq.iqSquashedInstsExamined 120959244 # Number of squashed instructions iterated over during squash; mainly for profiling 265system.cpu.iq.iqSquashedOperandsExamined 246380396 # Number of squashed operands that are examined and possibly removed from graph 266system.cpu.iq.iqSquashedNonSpecRemoved 3581 # Number of squashed non-spec instructions that were removed 267system.cpu.iq.issued_per_cycle::samples 169131808 # Number of insts issued each cycle 268system.cpu.iq.issued_per_cycle::mean 1.606996 # Number of insts issued each cycle 269system.cpu.iq.issued_per_cycle::stdev 1.512238 # Number of insts issued each cycle |
| 111system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 270system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 112system.cpu.iq.issued_per_cycle::0 47444811 28.05% 28.05% # Number of insts issued each cycle 113system.cpu.iq.issued_per_cycle::1 46907027 27.74% 55.79% # Number of insts issued each cycle 114system.cpu.iq.issued_per_cycle::2 33033517 19.53% 75.32% # Number of insts issued each cycle 115system.cpu.iq.issued_per_cycle::3 20154930 11.92% 87.24% # Number of insts issued each cycle 116system.cpu.iq.issued_per_cycle::4 13461767 7.96% 95.20% # Number of insts issued each cycle 117system.cpu.iq.issued_per_cycle::5 4965301 2.94% 98.13% # Number of insts issued each cycle 118system.cpu.iq.issued_per_cycle::6 2426983 1.44% 99.57% # Number of insts issued each cycle 119system.cpu.iq.issued_per_cycle::7 577544 0.34% 99.91% # Number of insts issued each cycle 120system.cpu.iq.issued_per_cycle::8 150443 0.09% 100.00% # Number of insts issued each cycle | 271system.cpu.iq.issued_per_cycle::0 47364329 28.00% 28.00% # Number of insts issued each cycle 272system.cpu.iq.issued_per_cycle::1 46969212 27.77% 55.78% # Number of insts issued each cycle 273system.cpu.iq.issued_per_cycle::2 33133132 19.59% 75.37% # Number of insts issued each cycle 274system.cpu.iq.issued_per_cycle::3 20170100 11.93% 87.29% # Number of insts issued each cycle 275system.cpu.iq.issued_per_cycle::4 13409099 7.93% 95.22% # Number of insts issued each cycle 276system.cpu.iq.issued_per_cycle::5 4965437 2.94% 98.15% # Number of insts issued each cycle 277system.cpu.iq.issued_per_cycle::6 2407480 1.42% 99.58% # Number of insts issued each cycle 278system.cpu.iq.issued_per_cycle::7 564206 0.33% 99.91% # Number of insts issued each cycle 279system.cpu.iq.issued_per_cycle::8 148813 0.09% 100.00% # Number of insts issued each cycle |
| 121system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 122system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 123system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 280system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 281system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 282system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 124system.cpu.iq.issued_per_cycle::total 169122323 # Number of insts issued each cycle | 283system.cpu.iq.issued_per_cycle::total 169131808 # Number of insts issued each cycle |
| 125system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 284system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 126system.cpu.iq.fu_full::IntAlu 134207 5.09% 5.09% # attempts to use FU when none available 127system.cpu.iq.fu_full::IntMult 0 0.00% 5.09% # attempts to use FU when none available 128system.cpu.iq.fu_full::IntDiv 0 0.00% 5.09% # attempts to use FU when none available 129system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.09% # attempts to use FU when none available 130system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.09% # attempts to use FU when none available 131system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.09% # attempts to use FU when none available 132system.cpu.iq.fu_full::FloatMult 0 0.00% 5.09% # attempts to use FU when none available 133system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.09% # attempts to use FU when none available 134system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.09% # attempts to use FU when none available 135system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.09% # attempts to use FU when none available 136system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.09% # attempts to use FU when none available 137system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.09% # attempts to use FU when none available 138system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.09% # attempts to use FU when none available 139system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.09% # attempts to use FU when none available 140system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.09% # attempts to use FU when none available 141system.cpu.iq.fu_full::SimdMult 0 0.00% 5.09% # attempts to use FU when none available 142system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.09% # attempts to use FU when none available 143system.cpu.iq.fu_full::SimdShift 0 0.00% 5.09% # attempts to use FU when none available 144system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.09% # attempts to use FU when none available 145system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.09% # attempts to use FU when none available 146system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.09% # attempts to use FU when none available 147system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.09% # attempts to use FU when none available 148system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.09% # attempts to use FU when none available 149system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.09% # attempts to use FU when none available 150system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.09% # attempts to use FU when none available 151system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.09% # attempts to use FU when none available 152system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.09% # attempts to use FU when none available 153system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.09% # attempts to use FU when none available 154system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.09% # attempts to use FU when none available 155system.cpu.iq.fu_full::MemRead 2238473 84.87% 89.96% # attempts to use FU when none available 156system.cpu.iq.fu_full::MemWrite 264949 10.04% 100.00% # attempts to use FU when none available | 285system.cpu.iq.fu_full::IntAlu 133221 5.02% 5.02% # attempts to use FU when none available 286system.cpu.iq.fu_full::IntMult 0 0.00% 5.02% # attempts to use FU when none available 287system.cpu.iq.fu_full::IntDiv 0 0.00% 5.02% # attempts to use FU when none available 288system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.02% # attempts to use FU when none available 289system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.02% # attempts to use FU when none available 290system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.02% # attempts to use FU when none available 291system.cpu.iq.fu_full::FloatMult 0 0.00% 5.02% # attempts to use FU when none available 292system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.02% # attempts to use FU when none available 293system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.02% # attempts to use FU when none available 294system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.02% # attempts to use FU when none available 295system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.02% # attempts to use FU when none available 296system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.02% # attempts to use FU when none available 297system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.02% # attempts to use FU when none available 298system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.02% # attempts to use FU when none available 299system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.02% # attempts to use FU when none available 300system.cpu.iq.fu_full::SimdMult 0 0.00% 5.02% # attempts to use FU when none available 301system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.02% # attempts to use FU when none available 302system.cpu.iq.fu_full::SimdShift 0 0.00% 5.02% # attempts to use FU when none available 303system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.02% # attempts to use FU when none available 304system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.02% # attempts to use FU when none available 305system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.02% # attempts to use FU when none available 306system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.02% # attempts to use FU when none available 307system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.02% # attempts to use FU when none available 308system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.02% # attempts to use FU when none available 309system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.02% # attempts to use FU when none available 310system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.02% # attempts to use FU when none available 311system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.02% # attempts to use FU when none available 312system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.02% # attempts to use FU when none available 313system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.02% # attempts to use FU when none available 314system.cpu.iq.fu_full::MemRead 2254463 85.01% 90.03% # attempts to use FU when none available 315system.cpu.iq.fu_full::MemWrite 264273 9.97% 100.00% # attempts to use FU when none available |
| 157system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 158system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 316system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 317system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 159system.cpu.iq.FU_type_0::No_OpClass 1212573 0.45% 0.45% # Type of FU issued 160system.cpu.iq.FU_type_0::IntAlu 177106081 65.13% 65.58% # Type of FU issued 161system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.58% # Type of FU issued 162system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.58% # Type of FU issued 163system.cpu.iq.FU_type_0::FloatAdd 1583088 0.58% 66.16% # Type of FU issued | 318system.cpu.iq.FU_type_0::No_OpClass 1212759 0.45% 0.45% # Type of FU issued 319system.cpu.iq.FU_type_0::IntAlu 177009113 65.13% 65.57% # Type of FU issued 320system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.57% # Type of FU issued 321system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.57% # Type of FU issued 322system.cpu.iq.FU_type_0::FloatAdd 1584136 0.58% 66.16% # Type of FU issued |
| 164system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.16% # Type of FU issued 165system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.16% # Type of FU issued 166system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.16% # Type of FU issued 167system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.16% # Type of FU issued 168system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.16% # Type of FU issued 169system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.16% # Type of FU issued 170system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.16% # Type of FU issued 171system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.16% # Type of FU issued --- 9 unchanged lines hidden (view full) --- 181system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.16% # Type of FU issued 182system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.16% # Type of FU issued 183system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.16% # Type of FU issued 184system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.16% # Type of FU issued 185system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.16% # Type of FU issued 186system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.16% # Type of FU issued 187system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.16% # Type of FU issued 188system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.16% # Type of FU issued | 323system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.16% # Type of FU issued 324system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.16% # Type of FU issued 325system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.16% # Type of FU issued 326system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.16% # Type of FU issued 327system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.16% # Type of FU issued 328system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.16% # Type of FU issued 329system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.16% # Type of FU issued 330system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.16% # Type of FU issued --- 9 unchanged lines hidden (view full) --- 340system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.16% # Type of FU issued 341system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.16% # Type of FU issued 342system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.16% # Type of FU issued 343system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.16% # Type of FU issued 344system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.16% # Type of FU issued 345system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.16% # Type of FU issued 346system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.16% # Type of FU issued 347system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.16% # Type of FU issued |
| 189system.cpu.iq.FU_type_0::MemRead 68507215 25.19% 91.35% # Type of FU issued 190system.cpu.iq.FU_type_0::MemWrite 23511717 8.65% 100.00% # Type of FU issued | 348system.cpu.iq.FU_type_0::MemRead 68507132 25.21% 91.36% # Type of FU issued 349system.cpu.iq.FU_type_0::MemWrite 23481043 8.64% 100.00% # Type of FU issued |
| 191system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 192system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 350system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 351system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 193system.cpu.iq.FU_type_0::total 271920674 # Type of FU issued 194system.cpu.iq.rate 1.607106 # Inst issue rate 195system.cpu.iq.fu_busy_cnt 2637629 # FU busy when requested 196system.cpu.iq.fu_busy_rate 0.009700 # FU busy rate (busy events/executed inst) 197system.cpu.iq.int_inst_queue_reads 710614385 # Number of integer instruction queue reads 198system.cpu.iq.int_inst_queue_writes 460072874 # Number of integer instruction queue writes 199system.cpu.iq.int_inst_queue_wakeup_accesses 264170911 # Number of integer instruction queue wakeup accesses 200system.cpu.iq.fp_inst_queue_reads 5294864 # Number of floating instruction queue reads 201system.cpu.iq.fp_inst_queue_writes 4624558 # Number of floating instruction queue writes 202system.cpu.iq.fp_inst_queue_wakeup_accesses 2540762 # Number of floating instruction queue wakeup accesses 203system.cpu.iq.int_alu_accesses 270691856 # Number of integer alu accesses 204system.cpu.iq.fp_alu_accesses 2653874 # Number of floating point alu accesses 205system.cpu.iew.lsq.thread0.forwLoads 19027871 # Number of loads that had data forwarded from stores | 352system.cpu.iq.FU_type_0::total 271794183 # Type of FU issued 353system.cpu.iq.rate 1.606461 # Inst issue rate 354system.cpu.iq.fu_busy_cnt 2651957 # FU busy when requested 355system.cpu.iq.fu_busy_rate 0.009757 # FU busy rate (busy events/executed inst) 356system.cpu.iq.int_inst_queue_reads 710390564 # Number of integer instruction queue reads 357system.cpu.iq.int_inst_queue_writes 459507075 # Number of integer instruction queue writes 358system.cpu.iq.int_inst_queue_wakeup_accesses 264054683 # Number of integer instruction queue wakeup accesses 359system.cpu.iq.fp_inst_queue_reads 5290846 # Number of floating instruction queue reads 360system.cpu.iq.fp_inst_queue_writes 4594594 # Number of floating instruction queue writes 361system.cpu.iq.fp_inst_queue_wakeup_accesses 2539782 # Number of floating instruction queue wakeup accesses 362system.cpu.iq.int_alu_accesses 270581714 # Number of integer alu accesses 363system.cpu.iq.fp_alu_accesses 2651667 # Number of floating point alu accesses 364system.cpu.iew.lsq.thread0.forwLoads 19012084 # Number of loads that had data forwarded from stores |
| 206system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 365system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 207system.cpu.iew.lsq.thread0.squashedLoads 33033584 # Number of loads squashed 208system.cpu.iew.lsq.thread0.ignoredResponses 33172 # Number of memory responses ignored because the instruction is squashed 209system.cpu.iew.lsq.thread0.memOrderViolation 306303 # Number of memory ordering violations 210system.cpu.iew.lsq.thread0.squashedStores 12350992 # Number of stores squashed | 366system.cpu.iew.lsq.thread0.squashedLoads 32992030 # Number of loads squashed 367system.cpu.iew.lsq.thread0.ignoredResponses 32876 # Number of memory responses ignored because the instruction is squashed 368system.cpu.iew.lsq.thread0.memOrderViolation 306652 # Number of memory ordering violations 369system.cpu.iew.lsq.thread0.squashedStores 12298870 # Number of stores squashed |
| 211system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 212system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 370system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 371system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 213system.cpu.iew.lsq.thread0.rescheduledLoads 49574 # Number of loads that were rescheduled | 372system.cpu.iew.lsq.thread0.rescheduledLoads 49471 # Number of loads that were rescheduled |
| 214system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 215system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 373system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 374system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 216system.cpu.iew.iewSquashCycles 16780857 # Number of cycles IEW is squashing 217system.cpu.iew.iewBlockCycles 570141 # Number of cycles IEW is blocking 218system.cpu.iew.iewUnblockCycles 256886 # Number of cycles IEW is unblocking 219system.cpu.iew.iewDispatchedInsts 343142304 # Number of instructions dispatched to IQ 220system.cpu.iew.iewDispSquashedInsts 262882 # Number of squashed instructions skipped by dispatch 221system.cpu.iew.iewDispLoadInsts 89683170 # Number of dispatched load instructions 222system.cpu.iew.iewDispStoreInsts 32866708 # Number of dispatched store instructions 223system.cpu.iew.iewDispNonSpecInsts 1845 # Number of dispatched non-speculative instructions 224system.cpu.iew.iewIQFullEvents 170649 # Number of times the IQ has become full, causing a stall 225system.cpu.iew.iewLSQFullEvents 30071 # Number of times the LSQ has become full, causing a stall 226system.cpu.iew.memOrderViolationEvents 306303 # Number of memory order violations 227system.cpu.iew.predictedTakenIncorrect 1331965 # Number of branches that were predicted taken incorrectly 228system.cpu.iew.predictedNotTakenIncorrect 1023841 # Number of branches that were predicted not taken incorrectly 229system.cpu.iew.branchMispredicts 2355806 # Number of branch mispredicts detected at execute 230system.cpu.iew.iewExecutedInsts 268743201 # Number of executed instructions 231system.cpu.iew.iewExecLoadInsts 67386869 # Number of load instructions executed 232system.cpu.iew.iewExecSquashedInsts 3177473 # Number of squashed instructions skipped in execute | 375system.cpu.iew.iewSquashCycles 16735530 # Number of cycles IEW is squashing 376system.cpu.iew.iewBlockCycles 583808 # Number of cycles IEW is blocking 377system.cpu.iew.iewUnblockCycles 272322 # Number of cycles IEW is unblocking 378system.cpu.iew.iewDispatchedInsts 342841505 # Number of instructions dispatched to IQ 379system.cpu.iew.iewDispSquashedInsts 257255 # Number of squashed instructions skipped by dispatch 380system.cpu.iew.iewDispLoadInsts 89641616 # Number of dispatched load instructions 381system.cpu.iew.iewDispStoreInsts 32814586 # Number of dispatched store instructions 382system.cpu.iew.iewDispNonSpecInsts 1824 # Number of dispatched non-speculative instructions 383system.cpu.iew.iewIQFullEvents 184475 # Number of times the IQ has become full, causing a stall 384system.cpu.iew.iewLSQFullEvents 30365 # Number of times the LSQ has become full, causing a stall 385system.cpu.iew.memOrderViolationEvents 306652 # Number of memory order violations 386system.cpu.iew.predictedTakenIncorrect 1330858 # Number of branches that were predicted taken incorrectly 387system.cpu.iew.predictedNotTakenIncorrect 1021453 # Number of branches that were predicted not taken incorrectly 388system.cpu.iew.branchMispredicts 2352311 # Number of branch mispredicts detected at execute 389system.cpu.iew.iewExecutedInsts 268621044 # Number of executed instructions 390system.cpu.iew.iewExecLoadInsts 67379328 # Number of load instructions executed 391system.cpu.iew.iewExecSquashedInsts 3173139 # Number of squashed instructions skipped in execute |
| 233system.cpu.iew.exec_swp 0 # number of swp insts executed 234system.cpu.iew.exec_nop 0 # number of nop insts executed | 392system.cpu.iew.exec_swp 0 # number of swp insts executed 393system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 235system.cpu.iew.exec_refs 90490770 # number of memory reference insts executed 236system.cpu.iew.exec_branches 14773340 # Number of branches executed 237system.cpu.iew.exec_stores 23103901 # Number of stores executed 238system.cpu.iew.exec_rate 1.588326 # Inst execution rate 239system.cpu.iew.wb_sent 267665043 # cumulative count of insts sent to commit 240system.cpu.iew.wb_count 266711673 # cumulative count of insts written-back 241system.cpu.iew.wb_producers 215305025 # num instructions producing a value 242system.cpu.iew.wb_consumers 378544002 # num instructions consuming a value | 394system.cpu.iew.exec_refs 90456785 # number of memory reference insts executed 395system.cpu.iew.exec_branches 14766526 # Number of branches executed 396system.cpu.iew.exec_stores 23077457 # Number of stores executed 397system.cpu.iew.exec_rate 1.587706 # Inst execution rate 398system.cpu.iew.wb_sent 267534302 # cumulative count of insts sent to commit 399system.cpu.iew.wb_count 266594465 # cumulative count of insts written-back 400system.cpu.iew.wb_producers 215217179 # num instructions producing a value 401system.cpu.iew.wb_consumers 378376353 # num instructions consuming a value |
| 243system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 402system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 244system.cpu.iew.wb_rate 1.576320 # insts written-back per cycle 245system.cpu.iew.wb_fanout 0.568771 # average fanout of values written-back | 403system.cpu.iew.wb_rate 1.575728 # insts written-back per cycle 404system.cpu.iew.wb_fanout 0.568791 # average fanout of values written-back |
| 246system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 405system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 247system.cpu.commit.commitSquashedInsts 121862932 # The number of squashed insts skipped by commit | 406system.cpu.commit.commitSquashedInsts 121559121 # The number of squashed insts skipped by commit |
| 248system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards | 407system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards |
| 249system.cpu.commit.branchMispredicts 2250269 # The number of times a branch was mispredicted 250system.cpu.commit.committed_per_cycle::samples 152341466 # Number of insts commited each cycle 251system.cpu.commit.committed_per_cycle::mean 1.453071 # Number of insts commited each cycle 252system.cpu.commit.committed_per_cycle::stdev 1.928588 # Number of insts commited each cycle | 408system.cpu.commit.branchMispredicts 2246323 # The number of times a branch was mispredicted 409system.cpu.commit.committed_per_cycle::samples 152396278 # Number of insts commited each cycle 410system.cpu.commit.committed_per_cycle::mean 1.452548 # Number of insts commited each cycle 411system.cpu.commit.committed_per_cycle::stdev 1.926116 # Number of insts commited each cycle |
| 253system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 412system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 254system.cpu.commit.committed_per_cycle::0 52729760 34.61% 34.61% # Number of insts commited each cycle 255system.cpu.commit.committed_per_cycle::1 57497101 37.74% 72.36% # Number of insts commited each cycle 256system.cpu.commit.committed_per_cycle::2 14043120 9.22% 81.57% # Number of insts commited each cycle 257system.cpu.commit.committed_per_cycle::3 11929275 7.83% 89.40% # Number of insts commited each cycle 258system.cpu.commit.committed_per_cycle::4 4291590 2.82% 92.22% # Number of insts commited each cycle 259system.cpu.commit.committed_per_cycle::5 2949185 1.94% 94.16% # Number of insts commited each cycle 260system.cpu.commit.committed_per_cycle::6 1071112 0.70% 94.86% # Number of insts commited each cycle 261system.cpu.commit.committed_per_cycle::7 989747 0.65% 95.51% # Number of insts commited each cycle 262system.cpu.commit.committed_per_cycle::8 6840576 4.49% 100.00% # Number of insts commited each cycle | 413system.cpu.commit.committed_per_cycle::0 52678390 34.57% 34.57% # Number of insts commited each cycle 414system.cpu.commit.committed_per_cycle::1 57577424 37.78% 72.35% # Number of insts commited each cycle 415system.cpu.commit.committed_per_cycle::2 14059718 9.23% 81.57% # Number of insts commited each cycle 416system.cpu.commit.committed_per_cycle::3 11956991 7.85% 89.42% # Number of insts commited each cycle 417system.cpu.commit.committed_per_cycle::4 4305123 2.82% 92.24% # Number of insts commited each cycle 418system.cpu.commit.committed_per_cycle::5 2949818 1.94% 94.18% # Number of insts commited each cycle 419system.cpu.commit.committed_per_cycle::6 1066386 0.70% 94.88% # Number of insts commited each cycle 420system.cpu.commit.committed_per_cycle::7 992195 0.65% 95.53% # Number of insts commited each cycle 421system.cpu.commit.committed_per_cycle::8 6810233 4.47% 100.00% # Number of insts commited each cycle |
| 263system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 264system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 265system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 422system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 423system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 424system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 266system.cpu.commit.committed_per_cycle::total 152341466 # Number of insts commited each cycle | 425system.cpu.commit.committed_per_cycle::total 152396278 # Number of insts commited each cycle |
| 267system.cpu.commit.committedInsts 132071192 # Number of instructions committed 268system.cpu.commit.committedOps 221362960 # Number of ops (including micro ops) committed 269system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 270system.cpu.commit.refs 77165302 # Number of memory references committed 271system.cpu.commit.loads 56649586 # Number of loads committed 272system.cpu.commit.membars 0 # Number of memory barriers committed 273system.cpu.commit.branches 12326938 # Number of branches committed 274system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. 275system.cpu.commit.int_insts 220339549 # Number of committed integer instructions. 276system.cpu.commit.function_calls 0 # Number of function calls committed. | 426system.cpu.commit.committedInsts 132071192 # Number of instructions committed 427system.cpu.commit.committedOps 221362960 # Number of ops (including micro ops) committed 428system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 429system.cpu.commit.refs 77165302 # Number of memory references committed 430system.cpu.commit.loads 56649586 # Number of loads committed 431system.cpu.commit.membars 0 # Number of memory barriers committed 432system.cpu.commit.branches 12326938 # Number of branches committed 433system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. 434system.cpu.commit.int_insts 220339549 # Number of committed integer instructions. 435system.cpu.commit.function_calls 0 # Number of function calls committed. |
| 277system.cpu.commit.bw_lim_events 6840576 # number cycles where commit BW limit reached | 436system.cpu.commit.bw_lim_events 6810233 # number cycles where commit BW limit reached |
| 278system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 437system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 279system.cpu.rob.rob_reads 488726782 # The number of ROB reads 280system.cpu.rob.rob_writes 703273689 # The number of ROB writes 281system.cpu.timesIdled 1665 # Number of times that the entire CPU went into an idle state and unscheduled itself 282system.cpu.idleCycles 76645 # Total number of cycles that the CPU has spent unscheduled due to idling | 438system.cpu.rob.rob_reads 488508126 # The number of ROB reads 439system.cpu.rob.rob_writes 702620216 # The number of ROB writes 440system.cpu.timesIdled 1506 # Number of times that the entire CPU went into an idle state and unscheduled itself 441system.cpu.idleCycles 56369 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 283system.cpu.committedInsts 132071192 # Number of Instructions Simulated 284system.cpu.committedOps 221362960 # Number of Ops (including micro ops) Simulated 285system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated | 442system.cpu.committedInsts 132071192 # Number of Instructions Simulated 443system.cpu.committedOps 221362960 # Number of Ops (including micro ops) Simulated 444system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated |
| 286system.cpu.cpi 1.281119 # CPI: Cycles Per Instruction 287system.cpu.cpi_total 1.281119 # CPI: Total CPI of All Threads 288system.cpu.ipc 0.780567 # IPC: Instructions Per Cycle 289system.cpu.ipc_total 0.780567 # IPC: Total IPC of All Threads 290system.cpu.int_regfile_reads 567776084 # number of integer regfile reads 291system.cpu.int_regfile_writes 302793169 # number of integer regfile writes 292system.cpu.fp_regfile_reads 3492670 # number of floating regfile reads 293system.cpu.fp_regfile_writes 2212557 # number of floating regfile writes 294system.cpu.misc_regfile_reads 139469476 # number of misc regfile reads | 445system.cpu.cpi 1.281038 # CPI: Cycles Per Instruction 446system.cpu.cpi_total 1.281038 # CPI: Total CPI of All Threads 447system.cpu.ipc 0.780617 # IPC: Instructions Per Cycle 448system.cpu.ipc_total 0.780617 # IPC: Total IPC of All Threads 449system.cpu.int_regfile_reads 567639196 # number of integer regfile reads 450system.cpu.int_regfile_writes 302703765 # number of integer regfile writes 451system.cpu.fp_regfile_reads 3495797 # number of floating regfile reads 452system.cpu.fp_regfile_writes 2211250 # number of floating regfile writes 453system.cpu.misc_regfile_reads 139399302 # number of misc regfile reads |
| 295system.cpu.misc_regfile_writes 844 # number of misc regfile writes | 454system.cpu.misc_regfile_writes 844 # number of misc regfile writes |
| 296system.cpu.icache.replacements 5445 # number of replacements 297system.cpu.icache.tagsinuse 1641.882453 # Cycle average of tags in use 298system.cpu.icache.total_refs 25692314 # Total number of references to valid blocks. 299system.cpu.icache.sampled_refs 7414 # Sample count of references to valid blocks. 300system.cpu.icache.avg_refs 3465.378203 # Average number of references to valid blocks. | 455system.cpu.icache.replacements 5641 # number of replacements 456system.cpu.icache.tagsinuse 1641.401127 # Cycle average of tags in use 457system.cpu.icache.total_refs 25643925 # Total number of references to valid blocks. 458system.cpu.icache.sampled_refs 7612 # Sample count of references to valid blocks. 459system.cpu.icache.avg_refs 3368.881372 # Average number of references to valid blocks. |
| 301system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 460system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 302system.cpu.icache.occ_blocks::cpu.inst 1641.882453 # Average occupied blocks per requestor 303system.cpu.icache.occ_percent::cpu.inst 0.801700 # Average percentage of cache occupancy 304system.cpu.icache.occ_percent::total 0.801700 # Average percentage of cache occupancy 305system.cpu.icache.ReadReq_hits::cpu.inst 25692314 # number of ReadReq hits 306system.cpu.icache.ReadReq_hits::total 25692314 # number of ReadReq hits 307system.cpu.icache.demand_hits::cpu.inst 25692314 # number of demand (read+write) hits 308system.cpu.icache.demand_hits::total 25692314 # number of demand (read+write) hits 309system.cpu.icache.overall_hits::cpu.inst 25692314 # number of overall hits 310system.cpu.icache.overall_hits::total 25692314 # number of overall hits 311system.cpu.icache.ReadReq_misses::cpu.inst 8997 # number of ReadReq misses 312system.cpu.icache.ReadReq_misses::total 8997 # number of ReadReq misses 313system.cpu.icache.demand_misses::cpu.inst 8997 # number of demand (read+write) misses 314system.cpu.icache.demand_misses::total 8997 # number of demand (read+write) misses 315system.cpu.icache.overall_misses::cpu.inst 8997 # number of overall misses 316system.cpu.icache.overall_misses::total 8997 # number of overall misses 317system.cpu.icache.ReadReq_miss_latency::cpu.inst 180939500 # number of ReadReq miss cycles 318system.cpu.icache.ReadReq_miss_latency::total 180939500 # number of ReadReq miss cycles 319system.cpu.icache.demand_miss_latency::cpu.inst 180939500 # number of demand (read+write) miss cycles 320system.cpu.icache.demand_miss_latency::total 180939500 # number of demand (read+write) miss cycles 321system.cpu.icache.overall_miss_latency::cpu.inst 180939500 # number of overall miss cycles 322system.cpu.icache.overall_miss_latency::total 180939500 # number of overall miss cycles 323system.cpu.icache.ReadReq_accesses::cpu.inst 25701311 # number of ReadReq accesses(hits+misses) 324system.cpu.icache.ReadReq_accesses::total 25701311 # number of ReadReq accesses(hits+misses) 325system.cpu.icache.demand_accesses::cpu.inst 25701311 # number of demand (read+write) accesses 326system.cpu.icache.demand_accesses::total 25701311 # number of demand (read+write) accesses 327system.cpu.icache.overall_accesses::cpu.inst 25701311 # number of overall (read+write) accesses 328system.cpu.icache.overall_accesses::total 25701311 # number of overall (read+write) accesses 329system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000350 # miss rate for ReadReq accesses 330system.cpu.icache.ReadReq_miss_rate::total 0.000350 # miss rate for ReadReq accesses 331system.cpu.icache.demand_miss_rate::cpu.inst 0.000350 # miss rate for demand accesses 332system.cpu.icache.demand_miss_rate::total 0.000350 # miss rate for demand accesses 333system.cpu.icache.overall_miss_rate::cpu.inst 0.000350 # miss rate for overall accesses 334system.cpu.icache.overall_miss_rate::total 0.000350 # miss rate for overall accesses 335system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20111.092586 # average ReadReq miss latency 336system.cpu.icache.ReadReq_avg_miss_latency::total 20111.092586 # average ReadReq miss latency 337system.cpu.icache.demand_avg_miss_latency::cpu.inst 20111.092586 # average overall miss latency 338system.cpu.icache.demand_avg_miss_latency::total 20111.092586 # average overall miss latency 339system.cpu.icache.overall_avg_miss_latency::cpu.inst 20111.092586 # average overall miss latency 340system.cpu.icache.overall_avg_miss_latency::total 20111.092586 # average overall miss latency | 461system.cpu.icache.occ_blocks::cpu.inst 1641.401127 # Average occupied blocks per requestor 462system.cpu.icache.occ_percent::cpu.inst 0.801465 # Average percentage of cache occupancy 463system.cpu.icache.occ_percent::total 0.801465 # Average percentage of cache occupancy 464system.cpu.icache.ReadReq_hits::cpu.inst 25643925 # number of ReadReq hits 465system.cpu.icache.ReadReq_hits::total 25643925 # number of ReadReq hits 466system.cpu.icache.demand_hits::cpu.inst 25643925 # number of demand (read+write) hits 467system.cpu.icache.demand_hits::total 25643925 # number of demand (read+write) hits 468system.cpu.icache.overall_hits::cpu.inst 25643925 # number of overall hits 469system.cpu.icache.overall_hits::total 25643925 # number of overall hits 470system.cpu.icache.ReadReq_misses::cpu.inst 9088 # number of ReadReq misses 471system.cpu.icache.ReadReq_misses::total 9088 # number of ReadReq misses 472system.cpu.icache.demand_misses::cpu.inst 9088 # number of demand (read+write) misses 473system.cpu.icache.demand_misses::total 9088 # number of demand (read+write) misses 474system.cpu.icache.overall_misses::cpu.inst 9088 # number of overall misses 475system.cpu.icache.overall_misses::total 9088 # number of overall misses 476system.cpu.icache.ReadReq_miss_latency::cpu.inst 147639500 # number of ReadReq miss cycles 477system.cpu.icache.ReadReq_miss_latency::total 147639500 # number of ReadReq miss cycles 478system.cpu.icache.demand_miss_latency::cpu.inst 147639500 # number of demand (read+write) miss cycles 479system.cpu.icache.demand_miss_latency::total 147639500 # number of demand (read+write) miss cycles 480system.cpu.icache.overall_miss_latency::cpu.inst 147639500 # number of overall miss cycles 481system.cpu.icache.overall_miss_latency::total 147639500 # number of overall miss cycles 482system.cpu.icache.ReadReq_accesses::cpu.inst 25653013 # number of ReadReq accesses(hits+misses) 483system.cpu.icache.ReadReq_accesses::total 25653013 # number of ReadReq accesses(hits+misses) 484system.cpu.icache.demand_accesses::cpu.inst 25653013 # number of demand (read+write) accesses 485system.cpu.icache.demand_accesses::total 25653013 # number of demand (read+write) accesses 486system.cpu.icache.overall_accesses::cpu.inst 25653013 # number of overall (read+write) accesses 487system.cpu.icache.overall_accesses::total 25653013 # number of overall (read+write) accesses 488system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000354 # miss rate for ReadReq accesses 489system.cpu.icache.ReadReq_miss_rate::total 0.000354 # miss rate for ReadReq accesses 490system.cpu.icache.demand_miss_rate::cpu.inst 0.000354 # miss rate for demand accesses 491system.cpu.icache.demand_miss_rate::total 0.000354 # miss rate for demand accesses 492system.cpu.icache.overall_miss_rate::cpu.inst 0.000354 # miss rate for overall accesses 493system.cpu.icache.overall_miss_rate::total 0.000354 # miss rate for overall accesses 494system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16245.543574 # average ReadReq miss latency 495system.cpu.icache.ReadReq_avg_miss_latency::total 16245.543574 # average ReadReq miss latency 496system.cpu.icache.demand_avg_miss_latency::cpu.inst 16245.543574 # average overall miss latency 497system.cpu.icache.demand_avg_miss_latency::total 16245.543574 # average overall miss latency 498system.cpu.icache.overall_avg_miss_latency::cpu.inst 16245.543574 # average overall miss latency 499system.cpu.icache.overall_avg_miss_latency::total 16245.543574 # average overall miss latency |
| 341system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 342system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 343system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 344system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 345system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 346system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 347system.cpu.icache.fast_writes 0 # number of fast writes performed 348system.cpu.icache.cache_copies 0 # number of cache copies performed | 500system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 501system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 502system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 503system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 504system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 505system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 506system.cpu.icache.fast_writes 0 # number of fast writes performed 507system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 349system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1358 # number of ReadReq MSHR hits 350system.cpu.icache.ReadReq_mshr_hits::total 1358 # number of ReadReq MSHR hits 351system.cpu.icache.demand_mshr_hits::cpu.inst 1358 # number of demand (read+write) MSHR hits 352system.cpu.icache.demand_mshr_hits::total 1358 # number of demand (read+write) MSHR hits 353system.cpu.icache.overall_mshr_hits::cpu.inst 1358 # number of overall MSHR hits 354system.cpu.icache.overall_mshr_hits::total 1358 # number of overall MSHR hits 355system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7639 # number of ReadReq MSHR misses 356system.cpu.icache.ReadReq_mshr_misses::total 7639 # number of ReadReq MSHR misses 357system.cpu.icache.demand_mshr_misses::cpu.inst 7639 # number of demand (read+write) MSHR misses 358system.cpu.icache.demand_mshr_misses::total 7639 # number of demand (read+write) MSHR misses 359system.cpu.icache.overall_mshr_misses::cpu.inst 7639 # number of overall MSHR misses 360system.cpu.icache.overall_mshr_misses::total 7639 # number of overall MSHR misses 361system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 132852000 # number of ReadReq MSHR miss cycles 362system.cpu.icache.ReadReq_mshr_miss_latency::total 132852000 # number of ReadReq MSHR miss cycles 363system.cpu.icache.demand_mshr_miss_latency::cpu.inst 132852000 # number of demand (read+write) MSHR miss cycles 364system.cpu.icache.demand_mshr_miss_latency::total 132852000 # number of demand (read+write) MSHR miss cycles 365system.cpu.icache.overall_mshr_miss_latency::cpu.inst 132852000 # number of overall MSHR miss cycles 366system.cpu.icache.overall_mshr_miss_latency::total 132852000 # number of overall MSHR miss cycles 367system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000297 # mshr miss rate for ReadReq accesses 368system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000297 # mshr miss rate for ReadReq accesses 369system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000297 # mshr miss rate for demand accesses 370system.cpu.icache.demand_mshr_miss_rate::total 0.000297 # mshr miss rate for demand accesses 371system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000297 # mshr miss rate for overall accesses 372system.cpu.icache.overall_mshr_miss_rate::total 0.000297 # mshr miss rate for overall accesses 373system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17391.281581 # average ReadReq mshr miss latency 374system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17391.281581 # average ReadReq mshr miss latency 375system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17391.281581 # average overall mshr miss latency 376system.cpu.icache.demand_avg_mshr_miss_latency::total 17391.281581 # average overall mshr miss latency 377system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17391.281581 # average overall mshr miss latency 378system.cpu.icache.overall_avg_mshr_miss_latency::total 17391.281581 # average overall mshr miss latency | 508system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1211 # number of ReadReq MSHR hits 509system.cpu.icache.ReadReq_mshr_hits::total 1211 # number of ReadReq MSHR hits 510system.cpu.icache.demand_mshr_hits::cpu.inst 1211 # number of demand (read+write) MSHR hits 511system.cpu.icache.demand_mshr_hits::total 1211 # number of demand (read+write) MSHR hits 512system.cpu.icache.overall_mshr_hits::cpu.inst 1211 # number of overall MSHR hits 513system.cpu.icache.overall_mshr_hits::total 1211 # number of overall MSHR hits 514system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7877 # number of ReadReq MSHR misses 515system.cpu.icache.ReadReq_mshr_misses::total 7877 # number of ReadReq MSHR misses 516system.cpu.icache.demand_mshr_misses::cpu.inst 7877 # number of demand (read+write) MSHR misses 517system.cpu.icache.demand_mshr_misses::total 7877 # number of demand (read+write) MSHR misses 518system.cpu.icache.overall_mshr_misses::cpu.inst 7877 # number of overall MSHR misses 519system.cpu.icache.overall_mshr_misses::total 7877 # number of overall MSHR misses 520system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 110101000 # number of ReadReq MSHR miss cycles 521system.cpu.icache.ReadReq_mshr_miss_latency::total 110101000 # number of ReadReq MSHR miss cycles 522system.cpu.icache.demand_mshr_miss_latency::cpu.inst 110101000 # number of demand (read+write) MSHR miss cycles 523system.cpu.icache.demand_mshr_miss_latency::total 110101000 # number of demand (read+write) MSHR miss cycles 524system.cpu.icache.overall_mshr_miss_latency::cpu.inst 110101000 # number of overall MSHR miss cycles 525system.cpu.icache.overall_mshr_miss_latency::total 110101000 # number of overall MSHR miss cycles 526system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for ReadReq accesses 527system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000307 # mshr miss rate for ReadReq accesses 528system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for demand accesses 529system.cpu.icache.demand_mshr_miss_rate::total 0.000307 # mshr miss rate for demand accesses 530system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for overall accesses 531system.cpu.icache.overall_mshr_miss_rate::total 0.000307 # mshr miss rate for overall accesses 532system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13977.529516 # average ReadReq mshr miss latency 533system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13977.529516 # average ReadReq mshr miss latency 534system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13977.529516 # average overall mshr miss latency 535system.cpu.icache.demand_avg_mshr_miss_latency::total 13977.529516 # average overall mshr miss latency 536system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13977.529516 # average overall mshr miss latency 537system.cpu.icache.overall_avg_mshr_miss_latency::total 13977.529516 # average overall mshr miss latency |
| 379system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 538system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 380system.cpu.dcache.replacements 56 # number of replacements 381system.cpu.dcache.tagsinuse 1423.300553 # Cycle average of tags in use 382system.cpu.dcache.total_refs 68703636 # Total number of references to valid blocks. 383system.cpu.dcache.sampled_refs 1986 # Sample count of references to valid blocks. 384system.cpu.dcache.avg_refs 34593.975831 # Average number of references to valid blocks. | 539system.cpu.dcache.replacements 57 # number of replacements 540system.cpu.dcache.tagsinuse 1426.186042 # Cycle average of tags in use 541system.cpu.dcache.total_refs 68712448 # Total number of references to valid blocks. 542system.cpu.dcache.sampled_refs 1990 # Sample count of references to valid blocks. 543system.cpu.dcache.avg_refs 34528.868342 # Average number of references to valid blocks. |
| 385system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 544system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 386system.cpu.dcache.occ_blocks::cpu.data 1423.300553 # Average occupied blocks per requestor 387system.cpu.dcache.occ_percent::cpu.data 0.347485 # Average percentage of cache occupancy 388system.cpu.dcache.occ_percent::total 0.347485 # Average percentage of cache occupancy 389system.cpu.dcache.ReadReq_hits::cpu.data 48189408 # number of ReadReq hits 390system.cpu.dcache.ReadReq_hits::total 48189408 # number of ReadReq hits 391system.cpu.dcache.WriteReq_hits::cpu.data 20513941 # number of WriteReq hits 392system.cpu.dcache.WriteReq_hits::total 20513941 # number of WriteReq hits 393system.cpu.dcache.demand_hits::cpu.data 68703349 # number of demand (read+write) hits 394system.cpu.dcache.demand_hits::total 68703349 # number of demand (read+write) hits 395system.cpu.dcache.overall_hits::cpu.data 68703349 # number of overall hits 396system.cpu.dcache.overall_hits::total 68703349 # number of overall hits 397system.cpu.dcache.ReadReq_misses::cpu.data 819 # number of ReadReq misses 398system.cpu.dcache.ReadReq_misses::total 819 # number of ReadReq misses 399system.cpu.dcache.WriteReq_misses::cpu.data 1789 # number of WriteReq misses 400system.cpu.dcache.WriteReq_misses::total 1789 # number of WriteReq misses 401system.cpu.dcache.demand_misses::cpu.data 2608 # number of demand (read+write) misses 402system.cpu.dcache.demand_misses::total 2608 # number of demand (read+write) misses 403system.cpu.dcache.overall_misses::cpu.data 2608 # number of overall misses 404system.cpu.dcache.overall_misses::total 2608 # number of overall misses 405system.cpu.dcache.ReadReq_miss_latency::cpu.data 26356000 # number of ReadReq miss cycles 406system.cpu.dcache.ReadReq_miss_latency::total 26356000 # number of ReadReq miss cycles 407system.cpu.dcache.WriteReq_miss_latency::cpu.data 66785500 # number of WriteReq miss cycles 408system.cpu.dcache.WriteReq_miss_latency::total 66785500 # number of WriteReq miss cycles 409system.cpu.dcache.demand_miss_latency::cpu.data 93141500 # number of demand (read+write) miss cycles 410system.cpu.dcache.demand_miss_latency::total 93141500 # number of demand (read+write) miss cycles 411system.cpu.dcache.overall_miss_latency::cpu.data 93141500 # number of overall miss cycles 412system.cpu.dcache.overall_miss_latency::total 93141500 # number of overall miss cycles 413system.cpu.dcache.ReadReq_accesses::cpu.data 48190227 # number of ReadReq accesses(hits+misses) 414system.cpu.dcache.ReadReq_accesses::total 48190227 # number of ReadReq accesses(hits+misses) | 545system.cpu.dcache.occ_blocks::cpu.data 1426.186042 # Average occupied blocks per requestor 546system.cpu.dcache.occ_percent::cpu.data 0.348190 # Average percentage of cache occupancy 547system.cpu.dcache.occ_percent::total 0.348190 # Average percentage of cache occupancy 548system.cpu.dcache.ReadReq_hits::cpu.data 48198272 # number of ReadReq hits 549system.cpu.dcache.ReadReq_hits::total 48198272 # number of ReadReq hits 550system.cpu.dcache.WriteReq_hits::cpu.data 20513902 # number of WriteReq hits 551system.cpu.dcache.WriteReq_hits::total 20513902 # number of WriteReq hits 552system.cpu.dcache.demand_hits::cpu.data 68712174 # number of demand (read+write) hits 553system.cpu.dcache.demand_hits::total 68712174 # number of demand (read+write) hits 554system.cpu.dcache.overall_hits::cpu.data 68712174 # number of overall hits 555system.cpu.dcache.overall_hits::total 68712174 # number of overall hits 556system.cpu.dcache.ReadReq_misses::cpu.data 735 # number of ReadReq misses 557system.cpu.dcache.ReadReq_misses::total 735 # number of ReadReq misses 558system.cpu.dcache.WriteReq_misses::cpu.data 1828 # number of WriteReq misses 559system.cpu.dcache.WriteReq_misses::total 1828 # number of WriteReq misses 560system.cpu.dcache.demand_misses::cpu.data 2563 # number of demand (read+write) misses 561system.cpu.dcache.demand_misses::total 2563 # number of demand (read+write) misses 562system.cpu.dcache.overall_misses::cpu.data 2563 # number of overall misses 563system.cpu.dcache.overall_misses::total 2563 # number of overall misses 564system.cpu.dcache.ReadReq_miss_latency::cpu.data 27231000 # number of ReadReq miss cycles 565system.cpu.dcache.ReadReq_miss_latency::total 27231000 # number of ReadReq miss cycles 566system.cpu.dcache.WriteReq_miss_latency::cpu.data 45096500 # number of WriteReq miss cycles 567system.cpu.dcache.WriteReq_miss_latency::total 45096500 # number of WriteReq miss cycles 568system.cpu.dcache.demand_miss_latency::cpu.data 72327500 # number of demand (read+write) miss cycles 569system.cpu.dcache.demand_miss_latency::total 72327500 # number of demand (read+write) miss cycles 570system.cpu.dcache.overall_miss_latency::cpu.data 72327500 # number of overall miss cycles 571system.cpu.dcache.overall_miss_latency::total 72327500 # number of overall miss cycles 572system.cpu.dcache.ReadReq_accesses::cpu.data 48199007 # number of ReadReq accesses(hits+misses) 573system.cpu.dcache.ReadReq_accesses::total 48199007 # number of ReadReq accesses(hits+misses) |
| 415system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) 416system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses) | 574system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) 575system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses) |
| 417system.cpu.dcache.demand_accesses::cpu.data 68705957 # number of demand (read+write) accesses 418system.cpu.dcache.demand_accesses::total 68705957 # number of demand (read+write) accesses 419system.cpu.dcache.overall_accesses::cpu.data 68705957 # number of overall (read+write) accesses 420system.cpu.dcache.overall_accesses::total 68705957 # number of overall (read+write) accesses 421system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses 422system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses 423system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000087 # miss rate for WriteReq accesses 424system.cpu.dcache.WriteReq_miss_rate::total 0.000087 # miss rate for WriteReq accesses 425system.cpu.dcache.demand_miss_rate::cpu.data 0.000038 # miss rate for demand accesses 426system.cpu.dcache.demand_miss_rate::total 0.000038 # miss rate for demand accesses 427system.cpu.dcache.overall_miss_rate::cpu.data 0.000038 # miss rate for overall accesses 428system.cpu.dcache.overall_miss_rate::total 0.000038 # miss rate for overall accesses 429system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32180.708181 # average ReadReq miss latency 430system.cpu.dcache.ReadReq_avg_miss_latency::total 32180.708181 # average ReadReq miss latency 431system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37331.190609 # average WriteReq miss latency 432system.cpu.dcache.WriteReq_avg_miss_latency::total 37331.190609 # average WriteReq miss latency 433system.cpu.dcache.demand_avg_miss_latency::cpu.data 35713.765337 # average overall miss latency 434system.cpu.dcache.demand_avg_miss_latency::total 35713.765337 # average overall miss latency 435system.cpu.dcache.overall_avg_miss_latency::cpu.data 35713.765337 # average overall miss latency 436system.cpu.dcache.overall_avg_miss_latency::total 35713.765337 # average overall miss latency | 576system.cpu.dcache.demand_accesses::cpu.data 68714737 # number of demand (read+write) accesses 577system.cpu.dcache.demand_accesses::total 68714737 # number of demand (read+write) accesses 578system.cpu.dcache.overall_accesses::cpu.data 68714737 # number of overall (read+write) accesses 579system.cpu.dcache.overall_accesses::total 68714737 # number of overall (read+write) accesses 580system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000015 # miss rate for ReadReq accesses 581system.cpu.dcache.ReadReq_miss_rate::total 0.000015 # miss rate for ReadReq accesses 582system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses 583system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses 584system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses 585system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses 586system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses 587system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses 588system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37048.979592 # average ReadReq miss latency 589system.cpu.dcache.ReadReq_avg_miss_latency::total 37048.979592 # average ReadReq miss latency 590system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24669.857768 # average WriteReq miss latency 591system.cpu.dcache.WriteReq_avg_miss_latency::total 24669.857768 # average WriteReq miss latency 592system.cpu.dcache.demand_avg_miss_latency::cpu.data 28219.859540 # average overall miss latency 593system.cpu.dcache.demand_avg_miss_latency::total 28219.859540 # average overall miss latency 594system.cpu.dcache.overall_avg_miss_latency::cpu.data 28219.859540 # average overall miss latency 595system.cpu.dcache.overall_avg_miss_latency::total 28219.859540 # average overall miss latency |
| 437system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 438system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 439system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 440system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 441system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 442system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 443system.cpu.dcache.fast_writes 0 # number of fast writes performed 444system.cpu.dcache.cache_copies 0 # number of cache copies performed | 596system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 597system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 598system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 599system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 600system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 601system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 602system.cpu.dcache.fast_writes 0 # number of fast writes performed 603system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 445system.cpu.dcache.writebacks::writebacks 14 # number of writebacks 446system.cpu.dcache.writebacks::total 14 # number of writebacks 447system.cpu.dcache.ReadReq_mshr_hits::cpu.data 394 # number of ReadReq MSHR hits 448system.cpu.dcache.ReadReq_mshr_hits::total 394 # number of ReadReq MSHR hits 449system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits 450system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits 451system.cpu.dcache.demand_mshr_hits::cpu.data 396 # number of demand (read+write) MSHR hits 452system.cpu.dcache.demand_mshr_hits::total 396 # number of demand (read+write) MSHR hits 453system.cpu.dcache.overall_mshr_hits::cpu.data 396 # number of overall MSHR hits 454system.cpu.dcache.overall_mshr_hits::total 396 # number of overall MSHR hits 455system.cpu.dcache.ReadReq_mshr_misses::cpu.data 425 # number of ReadReq MSHR misses 456system.cpu.dcache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses 457system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1787 # number of WriteReq MSHR misses 458system.cpu.dcache.WriteReq_mshr_misses::total 1787 # number of WriteReq MSHR misses 459system.cpu.dcache.demand_mshr_misses::cpu.data 2212 # number of demand (read+write) MSHR misses 460system.cpu.dcache.demand_mshr_misses::total 2212 # number of demand (read+write) MSHR misses 461system.cpu.dcache.overall_mshr_misses::cpu.data 2212 # number of overall MSHR misses 462system.cpu.dcache.overall_mshr_misses::total 2212 # number of overall MSHR misses 463system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14781500 # number of ReadReq MSHR miss cycles 464system.cpu.dcache.ReadReq_mshr_miss_latency::total 14781500 # number of ReadReq MSHR miss cycles 465system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 63139500 # number of WriteReq MSHR miss cycles 466system.cpu.dcache.WriteReq_mshr_miss_latency::total 63139500 # number of WriteReq MSHR miss cycles 467system.cpu.dcache.demand_mshr_miss_latency::cpu.data 77921000 # number of demand (read+write) MSHR miss cycles 468system.cpu.dcache.demand_mshr_miss_latency::total 77921000 # number of demand (read+write) MSHR miss cycles 469system.cpu.dcache.overall_mshr_miss_latency::cpu.data 77921000 # number of overall MSHR miss cycles 470system.cpu.dcache.overall_mshr_miss_latency::total 77921000 # number of overall MSHR miss cycles | 604system.cpu.dcache.writebacks::writebacks 15 # number of writebacks 605system.cpu.dcache.writebacks::total 15 # number of writebacks 606system.cpu.dcache.ReadReq_mshr_hits::cpu.data 302 # number of ReadReq MSHR hits 607system.cpu.dcache.ReadReq_mshr_hits::total 302 # number of ReadReq MSHR hits 608system.cpu.dcache.WriteReq_mshr_hits::cpu.data 4 # number of WriteReq MSHR hits 609system.cpu.dcache.WriteReq_mshr_hits::total 4 # number of WriteReq MSHR hits 610system.cpu.dcache.demand_mshr_hits::cpu.data 306 # number of demand (read+write) MSHR hits 611system.cpu.dcache.demand_mshr_hits::total 306 # number of demand (read+write) MSHR hits 612system.cpu.dcache.overall_mshr_hits::cpu.data 306 # number of overall MSHR hits 613system.cpu.dcache.overall_mshr_hits::total 306 # number of overall MSHR hits 614system.cpu.dcache.ReadReq_mshr_misses::cpu.data 433 # number of ReadReq MSHR misses 615system.cpu.dcache.ReadReq_mshr_misses::total 433 # number of ReadReq MSHR misses 616system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1824 # number of WriteReq MSHR misses 617system.cpu.dcache.WriteReq_mshr_misses::total 1824 # number of WriteReq MSHR misses 618system.cpu.dcache.demand_mshr_misses::cpu.data 2257 # number of demand (read+write) MSHR misses 619system.cpu.dcache.demand_mshr_misses::total 2257 # number of demand (read+write) MSHR misses 620system.cpu.dcache.overall_mshr_misses::cpu.data 2257 # number of overall MSHR misses 621system.cpu.dcache.overall_mshr_misses::total 2257 # number of overall MSHR misses 622system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17292000 # number of ReadReq MSHR miss cycles 623system.cpu.dcache.ReadReq_mshr_miss_latency::total 17292000 # number of ReadReq MSHR miss cycles 624system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 41315500 # number of WriteReq MSHR miss cycles 625system.cpu.dcache.WriteReq_mshr_miss_latency::total 41315500 # number of WriteReq MSHR miss cycles 626system.cpu.dcache.demand_mshr_miss_latency::cpu.data 58607500 # number of demand (read+write) MSHR miss cycles 627system.cpu.dcache.demand_mshr_miss_latency::total 58607500 # number of demand (read+write) MSHR miss cycles 628system.cpu.dcache.overall_mshr_miss_latency::cpu.data 58607500 # number of overall MSHR miss cycles 629system.cpu.dcache.overall_mshr_miss_latency::total 58607500 # number of overall MSHR miss cycles |
| 471system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses 472system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses | 630system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses 631system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses |
| 473system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses 474system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses 475system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses 476system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses 477system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses 478system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses 479system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34780 # average ReadReq mshr miss latency 480system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34780 # average ReadReq mshr miss latency 481system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35332.680470 # average WriteReq mshr miss latency 482system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35332.680470 # average WriteReq mshr miss latency 483system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35226.491863 # average overall mshr miss latency 484system.cpu.dcache.demand_avg_mshr_miss_latency::total 35226.491863 # average overall mshr miss latency 485system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35226.491863 # average overall mshr miss latency 486system.cpu.dcache.overall_avg_mshr_miss_latency::total 35226.491863 # average overall mshr miss latency | 632system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses 633system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses 634system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for demand accesses 635system.cpu.dcache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses 636system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for overall accesses 637system.cpu.dcache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses 638system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39935.334873 # average ReadReq mshr miss latency 639system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39935.334873 # average ReadReq mshr miss latency 640system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22651.041667 # average WriteReq mshr miss latency 641system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22651.041667 # average WriteReq mshr miss latency 642system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25966.991582 # average overall mshr miss latency 643system.cpu.dcache.demand_avg_mshr_miss_latency::total 25966.991582 # average overall mshr miss latency 644system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25966.991582 # average overall mshr miss latency 645system.cpu.dcache.overall_avg_mshr_miss_latency::total 25966.991582 # average overall mshr miss latency |
| 487system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 488system.cpu.l2cache.replacements 0 # number of replacements | 646system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 647system.cpu.l2cache.replacements 0 # number of replacements |
| 489system.cpu.l2cache.tagsinuse 2567.757374 # Cycle average of tags in use 490system.cpu.l2cache.total_refs 4009 # Total number of references to valid blocks. 491system.cpu.l2cache.sampled_refs 3834 # Sample count of references to valid blocks. 492system.cpu.l2cache.avg_refs 1.045644 # Average number of references to valid blocks. | 648system.cpu.l2cache.tagsinuse 2578.706153 # Cycle average of tags in use 649system.cpu.l2cache.total_refs 4200 # Total number of references to valid blocks. 650system.cpu.l2cache.sampled_refs 3851 # Sample count of references to valid blocks. 651system.cpu.l2cache.avg_refs 1.090626 # Average number of references to valid blocks. |
| 493system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 652system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 494system.cpu.l2cache.occ_blocks::writebacks 1.880074 # Average occupied blocks per requestor 495system.cpu.l2cache.occ_blocks::cpu.inst 2276.476463 # Average occupied blocks per requestor 496system.cpu.l2cache.occ_blocks::cpu.data 289.400837 # Average occupied blocks per requestor 497system.cpu.l2cache.occ_percent::writebacks 0.000057 # Average percentage of cache occupancy 498system.cpu.l2cache.occ_percent::cpu.inst 0.069473 # Average percentage of cache occupancy 499system.cpu.l2cache.occ_percent::cpu.data 0.008832 # Average percentage of cache occupancy 500system.cpu.l2cache.occ_percent::total 0.078362 # Average percentage of cache occupancy 501system.cpu.l2cache.ReadReq_hits::cpu.inst 3975 # number of ReadReq hits | 653system.cpu.l2cache.occ_blocks::writebacks 1.137844 # Average occupied blocks per requestor 654system.cpu.l2cache.occ_blocks::cpu.inst 2281.948056 # Average occupied blocks per requestor 655system.cpu.l2cache.occ_blocks::cpu.data 295.620253 # Average occupied blocks per requestor 656system.cpu.l2cache.occ_percent::writebacks 0.000035 # Average percentage of cache occupancy 657system.cpu.l2cache.occ_percent::cpu.inst 0.069640 # Average percentage of cache occupancy 658system.cpu.l2cache.occ_percent::cpu.data 0.009022 # Average percentage of cache occupancy 659system.cpu.l2cache.occ_percent::total 0.078696 # Average percentage of cache occupancy 660system.cpu.l2cache.ReadReq_hits::cpu.inst 4166 # number of ReadReq hits |
| 502system.cpu.l2cache.ReadReq_hits::cpu.data 31 # number of ReadReq hits | 661system.cpu.l2cache.ReadReq_hits::cpu.data 31 # number of ReadReq hits |
| 503system.cpu.l2cache.ReadReq_hits::total 4006 # number of ReadReq hits 504system.cpu.l2cache.Writeback_hits::writebacks 14 # number of Writeback hits 505system.cpu.l2cache.Writeback_hits::total 14 # number of Writeback hits 506system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 507system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits | 662system.cpu.l2cache.ReadReq_hits::total 4197 # number of ReadReq hits 663system.cpu.l2cache.Writeback_hits::writebacks 15 # number of Writeback hits 664system.cpu.l2cache.Writeback_hits::total 15 # number of Writeback hits |
| 508system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits 509system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits | 665system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits 666system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits |
| 510system.cpu.l2cache.demand_hits::cpu.inst 3975 # number of demand (read+write) hits | 667system.cpu.l2cache.demand_hits::cpu.inst 4166 # number of demand (read+write) hits |
| 511system.cpu.l2cache.demand_hits::cpu.data 39 # number of demand (read+write) hits | 668system.cpu.l2cache.demand_hits::cpu.data 39 # number of demand (read+write) hits |
| 512system.cpu.l2cache.demand_hits::total 4014 # number of demand (read+write) hits 513system.cpu.l2cache.overall_hits::cpu.inst 3975 # number of overall hits | 669system.cpu.l2cache.demand_hits::total 4205 # number of demand (read+write) hits 670system.cpu.l2cache.overall_hits::cpu.inst 4166 # number of overall hits |
| 514system.cpu.l2cache.overall_hits::cpu.data 39 # number of overall hits | 671system.cpu.l2cache.overall_hits::cpu.data 39 # number of overall hits |
| 515system.cpu.l2cache.overall_hits::total 4014 # number of overall hits 516system.cpu.l2cache.ReadReq_misses::cpu.inst 3438 # number of ReadReq misses 517system.cpu.l2cache.ReadReq_misses::cpu.data 393 # number of ReadReq misses 518system.cpu.l2cache.ReadReq_misses::total 3831 # number of ReadReq misses 519system.cpu.l2cache.UpgradeReq_misses::cpu.data 224 # number of UpgradeReq misses 520system.cpu.l2cache.UpgradeReq_misses::total 224 # number of UpgradeReq misses 521system.cpu.l2cache.ReadExReq_misses::cpu.data 1555 # number of ReadExReq misses 522system.cpu.l2cache.ReadExReq_misses::total 1555 # number of ReadExReq misses 523system.cpu.l2cache.demand_misses::cpu.inst 3438 # number of demand (read+write) misses 524system.cpu.l2cache.demand_misses::cpu.data 1948 # number of demand (read+write) misses 525system.cpu.l2cache.demand_misses::total 5386 # number of demand (read+write) misses 526system.cpu.l2cache.overall_misses::cpu.inst 3438 # number of overall misses 527system.cpu.l2cache.overall_misses::cpu.data 1948 # number of overall misses 528system.cpu.l2cache.overall_misses::total 5386 # number of overall misses 529system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 120837500 # number of ReadReq miss cycles 530system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14280000 # number of ReadReq miss cycles 531system.cpu.l2cache.ReadReq_miss_latency::total 135117500 # number of ReadReq miss cycles 532system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 53927000 # number of ReadExReq miss cycles 533system.cpu.l2cache.ReadExReq_miss_latency::total 53927000 # number of ReadExReq miss cycles 534system.cpu.l2cache.demand_miss_latency::cpu.inst 120837500 # number of demand (read+write) miss cycles 535system.cpu.l2cache.demand_miss_latency::cpu.data 68207000 # number of demand (read+write) miss cycles 536system.cpu.l2cache.demand_miss_latency::total 189044500 # number of demand (read+write) miss cycles 537system.cpu.l2cache.overall_miss_latency::cpu.inst 120837500 # number of overall miss cycles 538system.cpu.l2cache.overall_miss_latency::cpu.data 68207000 # number of overall miss cycles 539system.cpu.l2cache.overall_miss_latency::total 189044500 # number of overall miss cycles 540system.cpu.l2cache.ReadReq_accesses::cpu.inst 7413 # number of ReadReq accesses(hits+misses) 541system.cpu.l2cache.ReadReq_accesses::cpu.data 424 # number of ReadReq accesses(hits+misses) 542system.cpu.l2cache.ReadReq_accesses::total 7837 # number of ReadReq accesses(hits+misses) 543system.cpu.l2cache.Writeback_accesses::writebacks 14 # number of Writeback accesses(hits+misses) 544system.cpu.l2cache.Writeback_accesses::total 14 # number of Writeback accesses(hits+misses) 545system.cpu.l2cache.UpgradeReq_accesses::cpu.data 225 # number of UpgradeReq accesses(hits+misses) 546system.cpu.l2cache.UpgradeReq_accesses::total 225 # number of UpgradeReq accesses(hits+misses) 547system.cpu.l2cache.ReadExReq_accesses::cpu.data 1563 # number of ReadExReq accesses(hits+misses) 548system.cpu.l2cache.ReadExReq_accesses::total 1563 # number of ReadExReq accesses(hits+misses) 549system.cpu.l2cache.demand_accesses::cpu.inst 7413 # number of demand (read+write) accesses 550system.cpu.l2cache.demand_accesses::cpu.data 1987 # number of demand (read+write) accesses 551system.cpu.l2cache.demand_accesses::total 9400 # number of demand (read+write) accesses 552system.cpu.l2cache.overall_accesses::cpu.inst 7413 # number of overall (read+write) accesses 553system.cpu.l2cache.overall_accesses::cpu.data 1987 # number of overall (read+write) accesses 554system.cpu.l2cache.overall_accesses::total 9400 # number of overall (read+write) accesses 555system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.463780 # miss rate for ReadReq accesses 556system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.926887 # miss rate for ReadReq accesses 557system.cpu.l2cache.ReadReq_miss_rate::total 0.488835 # miss rate for ReadReq accesses 558system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.995556 # miss rate for UpgradeReq accesses 559system.cpu.l2cache.UpgradeReq_miss_rate::total 0.995556 # miss rate for UpgradeReq accesses 560system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994882 # miss rate for ReadExReq accesses 561system.cpu.l2cache.ReadExReq_miss_rate::total 0.994882 # miss rate for ReadExReq accesses 562system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463780 # miss rate for demand accesses 563system.cpu.l2cache.demand_miss_rate::cpu.data 0.980372 # miss rate for demand accesses 564system.cpu.l2cache.demand_miss_rate::total 0.572979 # miss rate for demand accesses 565system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463780 # miss rate for overall accesses 566system.cpu.l2cache.overall_miss_rate::cpu.data 0.980372 # miss rate for overall accesses 567system.cpu.l2cache.overall_miss_rate::total 0.572979 # miss rate for overall accesses 568system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35147.614892 # average ReadReq miss latency 569system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36335.877863 # average ReadReq miss latency 570system.cpu.l2cache.ReadReq_avg_miss_latency::total 35269.511877 # average ReadReq miss latency 571system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34679.742765 # average ReadExReq miss latency 572system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34679.742765 # average ReadExReq miss latency 573system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35147.614892 # average overall miss latency 574system.cpu.l2cache.demand_avg_miss_latency::cpu.data 35013.860370 # average overall miss latency 575system.cpu.l2cache.demand_avg_miss_latency::total 35099.238767 # average overall miss latency 576system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35147.614892 # average overall miss latency 577system.cpu.l2cache.overall_avg_miss_latency::cpu.data 35013.860370 # average overall miss latency 578system.cpu.l2cache.overall_avg_miss_latency::total 35099.238767 # average overall miss latency | 672system.cpu.l2cache.overall_hits::total 4205 # number of overall hits 673system.cpu.l2cache.ReadReq_misses::cpu.inst 3446 # number of ReadReq misses 674system.cpu.l2cache.ReadReq_misses::cpu.data 401 # number of ReadReq misses 675system.cpu.l2cache.ReadReq_misses::total 3847 # number of ReadReq misses 676system.cpu.l2cache.UpgradeReq_misses::cpu.data 265 # number of UpgradeReq misses 677system.cpu.l2cache.UpgradeReq_misses::total 265 # number of UpgradeReq misses 678system.cpu.l2cache.ReadExReq_misses::cpu.data 1552 # number of ReadExReq misses 679system.cpu.l2cache.ReadExReq_misses::total 1552 # number of ReadExReq misses 680system.cpu.l2cache.demand_misses::cpu.inst 3446 # number of demand (read+write) misses 681system.cpu.l2cache.demand_misses::cpu.data 1953 # number of demand (read+write) misses 682system.cpu.l2cache.demand_misses::total 5399 # number of demand (read+write) misses 683system.cpu.l2cache.overall_misses::cpu.inst 3446 # number of overall misses 684system.cpu.l2cache.overall_misses::cpu.data 1953 # number of overall misses 685system.cpu.l2cache.overall_misses::total 5399 # number of overall misses 686system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 97780500 # number of ReadReq miss cycles 687system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16770000 # number of ReadReq miss cycles 688system.cpu.l2cache.ReadReq_miss_latency::total 114550500 # number of ReadReq miss cycles 689system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 38537500 # number of ReadExReq miss cycles 690system.cpu.l2cache.ReadExReq_miss_latency::total 38537500 # number of ReadExReq miss cycles 691system.cpu.l2cache.demand_miss_latency::cpu.inst 97780500 # number of demand (read+write) miss cycles 692system.cpu.l2cache.demand_miss_latency::cpu.data 55307500 # number of demand (read+write) miss cycles 693system.cpu.l2cache.demand_miss_latency::total 153088000 # number of demand (read+write) miss cycles 694system.cpu.l2cache.overall_miss_latency::cpu.inst 97780500 # number of overall miss cycles 695system.cpu.l2cache.overall_miss_latency::cpu.data 55307500 # number of overall miss cycles 696system.cpu.l2cache.overall_miss_latency::total 153088000 # number of overall miss cycles 697system.cpu.l2cache.ReadReq_accesses::cpu.inst 7612 # number of ReadReq accesses(hits+misses) 698system.cpu.l2cache.ReadReq_accesses::cpu.data 432 # number of ReadReq accesses(hits+misses) 699system.cpu.l2cache.ReadReq_accesses::total 8044 # number of ReadReq accesses(hits+misses) 700system.cpu.l2cache.Writeback_accesses::writebacks 15 # number of Writeback accesses(hits+misses) 701system.cpu.l2cache.Writeback_accesses::total 15 # number of Writeback accesses(hits+misses) 702system.cpu.l2cache.UpgradeReq_accesses::cpu.data 265 # number of UpgradeReq accesses(hits+misses) 703system.cpu.l2cache.UpgradeReq_accesses::total 265 # number of UpgradeReq accesses(hits+misses) 704system.cpu.l2cache.ReadExReq_accesses::cpu.data 1560 # number of ReadExReq accesses(hits+misses) 705system.cpu.l2cache.ReadExReq_accesses::total 1560 # number of ReadExReq accesses(hits+misses) 706system.cpu.l2cache.demand_accesses::cpu.inst 7612 # number of demand (read+write) accesses 707system.cpu.l2cache.demand_accesses::cpu.data 1992 # number of demand (read+write) accesses 708system.cpu.l2cache.demand_accesses::total 9604 # number of demand (read+write) accesses 709system.cpu.l2cache.overall_accesses::cpu.inst 7612 # number of overall (read+write) accesses 710system.cpu.l2cache.overall_accesses::cpu.data 1992 # number of overall (read+write) accesses 711system.cpu.l2cache.overall_accesses::total 9604 # number of overall (read+write) accesses 712system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.452706 # miss rate for ReadReq accesses 713system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.928241 # miss rate for ReadReq accesses 714system.cpu.l2cache.ReadReq_miss_rate::total 0.478245 # miss rate for ReadReq accesses 715system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 716system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 717system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994872 # miss rate for ReadExReq accesses 718system.cpu.l2cache.ReadExReq_miss_rate::total 0.994872 # miss rate for ReadExReq accesses 719system.cpu.l2cache.demand_miss_rate::cpu.inst 0.452706 # miss rate for demand accesses 720system.cpu.l2cache.demand_miss_rate::cpu.data 0.980422 # miss rate for demand accesses 721system.cpu.l2cache.demand_miss_rate::total 0.562162 # miss rate for demand accesses 722system.cpu.l2cache.overall_miss_rate::cpu.inst 0.452706 # miss rate for overall accesses 723system.cpu.l2cache.overall_miss_rate::cpu.data 0.980422 # miss rate for overall accesses 724system.cpu.l2cache.overall_miss_rate::total 0.562162 # miss rate for overall accesses 725system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 28375.072548 # average ReadReq miss latency 726system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 41820.448878 # average ReadReq miss latency 727system.cpu.l2cache.ReadReq_avg_miss_latency::total 29776.579153 # average ReadReq miss latency 728system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 24830.863402 # average ReadExReq miss latency 729system.cpu.l2cache.ReadExReq_avg_miss_latency::total 24830.863402 # average ReadExReq miss latency 730system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 28375.072548 # average overall miss latency 731system.cpu.l2cache.demand_avg_miss_latency::cpu.data 28319.252432 # average overall miss latency 732system.cpu.l2cache.demand_avg_miss_latency::total 28354.880533 # average overall miss latency 733system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 28375.072548 # average overall miss latency 734system.cpu.l2cache.overall_avg_miss_latency::cpu.data 28319.252432 # average overall miss latency 735system.cpu.l2cache.overall_avg_miss_latency::total 28354.880533 # average overall miss latency |
| 579system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 580system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 581system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 582system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 583system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 584system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 585system.cpu.l2cache.fast_writes 0 # number of fast writes performed 586system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 736system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 737system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 738system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 739system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 740system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 741system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 742system.cpu.l2cache.fast_writes 0 # number of fast writes performed 743system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 587system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3438 # number of ReadReq MSHR misses 588system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 393 # number of ReadReq MSHR misses 589system.cpu.l2cache.ReadReq_mshr_misses::total 3831 # number of ReadReq MSHR misses 590system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 224 # number of UpgradeReq MSHR misses 591system.cpu.l2cache.UpgradeReq_mshr_misses::total 224 # number of UpgradeReq MSHR misses 592system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1555 # number of ReadExReq MSHR misses 593system.cpu.l2cache.ReadExReq_mshr_misses::total 1555 # number of ReadExReq MSHR misses 594system.cpu.l2cache.demand_mshr_misses::cpu.inst 3438 # number of demand (read+write) MSHR misses 595system.cpu.l2cache.demand_mshr_misses::cpu.data 1948 # number of demand (read+write) MSHR misses 596system.cpu.l2cache.demand_mshr_misses::total 5386 # number of demand (read+write) MSHR misses 597system.cpu.l2cache.overall_mshr_misses::cpu.inst 3438 # number of overall MSHR misses 598system.cpu.l2cache.overall_mshr_misses::cpu.data 1948 # number of overall MSHR misses 599system.cpu.l2cache.overall_mshr_misses::total 5386 # number of overall MSHR misses 600system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 109859500 # number of ReadReq MSHR miss cycles 601system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13039500 # number of ReadReq MSHR miss cycles 602system.cpu.l2cache.ReadReq_mshr_miss_latency::total 122899000 # number of ReadReq MSHR miss cycles 603system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6951000 # number of UpgradeReq MSHR miss cycles 604system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6951000 # number of UpgradeReq MSHR miss cycles 605system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48724500 # number of ReadExReq MSHR miss cycles 606system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48724500 # number of ReadExReq MSHR miss cycles 607system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 109859500 # number of demand (read+write) MSHR miss cycles 608system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 61764000 # number of demand (read+write) MSHR miss cycles 609system.cpu.l2cache.demand_mshr_miss_latency::total 171623500 # number of demand (read+write) MSHR miss cycles 610system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 109859500 # number of overall MSHR miss cycles 611system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 61764000 # number of overall MSHR miss cycles 612system.cpu.l2cache.overall_mshr_miss_latency::total 171623500 # number of overall MSHR miss cycles 613system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.463780 # mshr miss rate for ReadReq accesses 614system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.926887 # mshr miss rate for ReadReq accesses 615system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.488835 # mshr miss rate for ReadReq accesses 616system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.995556 # mshr miss rate for UpgradeReq accesses 617system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.995556 # mshr miss rate for UpgradeReq accesses 618system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994882 # mshr miss rate for ReadExReq accesses 619system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994882 # mshr miss rate for ReadExReq accesses 620system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463780 # mshr miss rate for demand accesses 621system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980372 # mshr miss rate for demand accesses 622system.cpu.l2cache.demand_mshr_miss_rate::total 0.572979 # mshr miss rate for demand accesses 623system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463780 # mshr miss rate for overall accesses 624system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980372 # mshr miss rate for overall accesses 625system.cpu.l2cache.overall_mshr_miss_rate::total 0.572979 # mshr miss rate for overall accesses 626system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31954.479348 # average ReadReq mshr miss latency 627system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33179.389313 # average ReadReq mshr miss latency 628system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32080.135735 # average ReadReq mshr miss latency 629system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31031.250000 # average UpgradeReq mshr miss latency 630system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31031.250000 # average UpgradeReq mshr miss latency 631system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31334.083601 # average ReadExReq mshr miss latency 632system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31334.083601 # average ReadExReq mshr miss latency 633system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31954.479348 # average overall mshr miss latency 634system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31706.365503 # average overall mshr miss latency 635system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31864.741924 # average overall mshr miss latency 636system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31954.479348 # average overall mshr miss latency 637system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31706.365503 # average overall mshr miss latency 638system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31864.741924 # average overall mshr miss latency | 744system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3446 # number of ReadReq MSHR misses 745system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 401 # number of ReadReq MSHR misses 746system.cpu.l2cache.ReadReq_mshr_misses::total 3847 # number of ReadReq MSHR misses 747system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 265 # number of UpgradeReq MSHR misses 748system.cpu.l2cache.UpgradeReq_mshr_misses::total 265 # number of UpgradeReq MSHR misses 749system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1552 # number of ReadExReq MSHR misses 750system.cpu.l2cache.ReadExReq_mshr_misses::total 1552 # number of ReadExReq MSHR misses 751system.cpu.l2cache.demand_mshr_misses::cpu.inst 3446 # number of demand (read+write) MSHR misses 752system.cpu.l2cache.demand_mshr_misses::cpu.data 1953 # number of demand (read+write) MSHR misses 753system.cpu.l2cache.demand_mshr_misses::total 5399 # number of demand (read+write) MSHR misses 754system.cpu.l2cache.overall_mshr_misses::cpu.inst 3446 # number of overall MSHR misses 755system.cpu.l2cache.overall_mshr_misses::cpu.data 1953 # number of overall MSHR misses 756system.cpu.l2cache.overall_mshr_misses::total 5399 # number of overall MSHR misses 757system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 85338517 # number of ReadReq MSHR miss cycles 758system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15342111 # number of ReadReq MSHR miss cycles 759system.cpu.l2cache.ReadReq_mshr_miss_latency::total 100680628 # number of ReadReq MSHR miss cycles 760system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 265265 # number of UpgradeReq MSHR miss cycles 761system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 265265 # number of UpgradeReq MSHR miss cycles 762system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32924486 # number of ReadExReq MSHR miss cycles 763system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32924486 # number of ReadExReq MSHR miss cycles 764system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85338517 # number of demand (read+write) MSHR miss cycles 765system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 48266597 # number of demand (read+write) MSHR miss cycles 766system.cpu.l2cache.demand_mshr_miss_latency::total 133605114 # number of demand (read+write) MSHR miss cycles 767system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85338517 # number of overall MSHR miss cycles 768system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 48266597 # number of overall MSHR miss cycles 769system.cpu.l2cache.overall_mshr_miss_latency::total 133605114 # number of overall MSHR miss cycles 770system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.452706 # mshr miss rate for ReadReq accesses 771system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.928241 # mshr miss rate for ReadReq accesses 772system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.478245 # mshr miss rate for ReadReq accesses 773system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 774system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 775system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994872 # mshr miss rate for ReadExReq accesses 776system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994872 # mshr miss rate for ReadExReq accesses 777system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.452706 # mshr miss rate for demand accesses 778system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980422 # mshr miss rate for demand accesses 779system.cpu.l2cache.demand_mshr_miss_rate::total 0.562162 # mshr miss rate for demand accesses 780system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.452706 # mshr miss rate for overall accesses 781system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980422 # mshr miss rate for overall accesses 782system.cpu.l2cache.overall_mshr_miss_rate::total 0.562162 # mshr miss rate for overall accesses 783system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 24764.514510 # average ReadReq mshr miss latency 784system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38259.628429 # average ReadReq mshr miss latency 785system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 26171.205615 # average ReadReq mshr miss latency 786system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 1001 # average UpgradeReq mshr miss latency 787system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 1001 # average UpgradeReq mshr miss latency 788system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 21214.230670 # average ReadExReq mshr miss latency 789system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 21214.230670 # average ReadExReq mshr miss latency 790system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 24764.514510 # average overall mshr miss latency 791system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 24714.079365 # average overall mshr miss latency 792system.cpu.l2cache.demand_avg_mshr_miss_latency::total 24746.270420 # average overall mshr miss latency 793system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 24764.514510 # average overall mshr miss latency 794system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 24714.079365 # average overall mshr miss latency 795system.cpu.l2cache.overall_avg_mshr_miss_latency::total 24746.270420 # average overall mshr miss latency |
| 639system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 640 641---------- End Simulation Statistics ---------- | 796system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 797 798---------- End Simulation Statistics ---------- |