1 2---------- Begin Simulation Statistics ----------
| 1 2---------- Begin Simulation Statistics ----------
|
3sim_seconds 0.087752 # Number of seconds simulated 4sim_ticks 87751730000 # Number of ticks simulated 5final_tick 87751730000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
| 3sim_seconds 0.087734 # Number of seconds simulated 4sim_ticks 87734048000 # Number of ticks simulated 5final_tick 87734048000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
6sim_freq 1000000000000 # Frequency of simulated ticks
| 6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 66952 # Simulator instruction rate (inst/s) 8host_op_rate 112217 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 44484510 # Simulator tick rate (ticks/s) 10host_mem_usage 236376 # Number of bytes of host memory used 11host_seconds 1972.64 # Real time elapsed on the host
| 7host_inst_rate 104988 # Simulator instruction rate (inst/s) 8host_op_rate 175969 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 69742772 # Simulator tick rate (ticks/s) 10host_mem_usage 239080 # Number of bytes of host memory used 11host_seconds 1257.97 # Real time elapsed on the host
|
12sim_insts 132071227 # Number of instructions simulated 13sim_ops 221363017 # Number of ops (including micro ops) simulated
| 12sim_insts 132071227 # Number of instructions simulated 13sim_ops 221363017 # Number of ops (including micro ops) simulated
|
14system.physmem.bytes_read::cpu.inst 219584 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 125440 # Number of bytes read from this memory
| 14system.physmem.bytes_read::cpu.inst 219520 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 125504 # Number of bytes read from this memory
|
16system.physmem.bytes_read::total 345024 # Number of bytes read from this memory
| 16system.physmem.bytes_read::total 345024 # Number of bytes read from this memory
|
17system.physmem.bytes_inst_read::cpu.inst 219584 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 219584 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 3431 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 1960 # Number of read requests responded to by this memory
| 17system.physmem.bytes_inst_read::cpu.inst 219520 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 219520 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 3430 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 1961 # Number of read requests responded to by this memory
|
21system.physmem.num_reads::total 5391 # Number of read requests responded to by this memory
| 21system.physmem.num_reads::total 5391 # Number of read requests responded to by this memory
|
22system.physmem.bw_read::cpu.inst 2502332 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 1429487 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 3931820 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 2502332 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 2502332 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 2502332 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 1429487 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 3931820 # Total bandwidth to/from this memory (bytes/s)
| 22system.physmem.bw_read::cpu.inst 2502107 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 1430505 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 3932612 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 2502107 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 2502107 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 2502107 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 1430505 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 3932612 # Total bandwidth to/from this memory (bytes/s)
|
30system.cpu.workload.num_syscalls 400 # Number of system calls
| 30system.cpu.workload.num_syscalls 400 # Number of system calls
|
31system.cpu.numCycles 175503461 # number of cpu cycles simulated
| 31system.cpu.numCycles 175468097 # number of cpu cycles simulated
|
32system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 33system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
| 32system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 33system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
34system.cpu.BPredUnit.lookups 20929970 # Number of BP lookups 35system.cpu.BPredUnit.condPredicted 20929970 # Number of conditional branches predicted 36system.cpu.BPredUnit.condIncorrect 2208761 # Number of conditional branches incorrect 37system.cpu.BPredUnit.BTBLookups 15515509 # Number of BTB lookups 38system.cpu.BPredUnit.BTBHits 13857635 # Number of BTB hits
| 34system.cpu.BPredUnit.lookups 20936810 # Number of BP lookups 35system.cpu.BPredUnit.condPredicted 20936810 # Number of conditional branches predicted 36system.cpu.BPredUnit.condIncorrect 2209025 # Number of conditional branches incorrect 37system.cpu.BPredUnit.BTBLookups 15519452 # Number of BTB lookups 38system.cpu.BPredUnit.BTBHits 13863485 # Number of BTB hits
|
39system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 40system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 41system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
| 39system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 40system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 41system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
42system.cpu.fetch.icacheStallCycles 27320294 # Number of cycles fetch is stalled on an Icache miss 43system.cpu.fetch.Insts 226942709 # Number of instructions fetch has processed 44system.cpu.fetch.Branches 20929970 # Number of branches that fetch encountered 45system.cpu.fetch.predictedBranches 13857635 # Number of branches that fetch has predicted taken 46system.cpu.fetch.Cycles 59854483 # Number of cycles fetch has run and was not squashing or blocked 47system.cpu.fetch.SquashCycles 19459786 # Number of cycles fetch has spent squashing 48system.cpu.fetch.BlockedCycles 71271521 # Number of cycles fetch has spent blocked 49system.cpu.fetch.MiscStallCycles 647 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 50system.cpu.fetch.PendingTrapStallCycles 5211 # Number of stall cycles due to pending traps 51system.cpu.fetch.CacheLines 25822554 # Number of cache lines fetched 52system.cpu.fetch.IcacheSquashes 471165 # Number of outstanding Icache misses that were squashed 53system.cpu.fetch.rateDist::samples 175426420 # Number of instructions fetched each cycle (Total) 54system.cpu.fetch.rateDist::mean 2.136612 # Number of instructions fetched each cycle (Total) 55system.cpu.fetch.rateDist::stdev 3.300359 # Number of instructions fetched each cycle (Total)
| 42system.cpu.fetch.icacheStallCycles 27317448 # Number of cycles fetch is stalled on an Icache miss 43system.cpu.fetch.Insts 226954156 # Number of instructions fetch has processed 44system.cpu.fetch.Branches 20936810 # Number of branches that fetch encountered 45system.cpu.fetch.predictedBranches 13863485 # Number of branches that fetch has predicted taken 46system.cpu.fetch.Cycles 59860939 # Number of cycles fetch has run and was not squashing or blocked 47system.cpu.fetch.SquashCycles 19465594 # Number of cycles fetch has spent squashing 48system.cpu.fetch.BlockedCycles 71226359 # Number of cycles fetch has spent blocked 49system.cpu.fetch.MiscStallCycles 837 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 50system.cpu.fetch.PendingTrapStallCycles 7164 # Number of stall cycles due to pending traps 51system.cpu.fetch.CacheLines 25821692 # Number of cache lines fetched 52system.cpu.fetch.IcacheSquashes 473022 # Number of outstanding Icache misses that were squashed 53system.cpu.fetch.rateDist::samples 175391237 # Number of instructions fetched each cycle (Total) 54system.cpu.fetch.rateDist::mean 2.137569 # Number of instructions fetched each cycle (Total) 55system.cpu.fetch.rateDist::stdev 3.300907 # Number of instructions fetched each cycle (Total)
|
56system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
| 56system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
57system.cpu.fetch.rateDist::0 117249103 66.84% 66.84% # Number of instructions fetched each cycle (Total) 58system.cpu.fetch.rateDist::1 3234615 1.84% 68.68% # Number of instructions fetched each cycle (Total) 59system.cpu.fetch.rateDist::2 2477718 1.41% 70.09% # Number of instructions fetched each cycle (Total) 60system.cpu.fetch.rateDist::3 3147881 1.79% 71.89% # Number of instructions fetched each cycle (Total) 61system.cpu.fetch.rateDist::4 3542128 2.02% 73.91% # Number of instructions fetched each cycle (Total) 62system.cpu.fetch.rateDist::5 3766355 2.15% 76.05% # Number of instructions fetched each cycle (Total) 63system.cpu.fetch.rateDist::6 4530628 2.58% 78.64% # Number of instructions fetched each cycle (Total) 64system.cpu.fetch.rateDist::7 2823565 1.61% 80.25% # Number of instructions fetched each cycle (Total) 65system.cpu.fetch.rateDist::8 34654427 19.75% 100.00% # Number of instructions fetched each cycle (Total)
| 57system.cpu.fetch.rateDist::0 117206877 66.83% 66.83% # Number of instructions fetched each cycle (Total) 58system.cpu.fetch.rateDist::1 3231358 1.84% 68.67% # Number of instructions fetched each cycle (Total) 59system.cpu.fetch.rateDist::2 2482815 1.42% 70.08% # Number of instructions fetched each cycle (Total) 60system.cpu.fetch.rateDist::3 3136542 1.79% 71.87% # Number of instructions fetched each cycle (Total) 61system.cpu.fetch.rateDist::4 3542923 2.02% 73.89% # Number of instructions fetched each cycle (Total) 62system.cpu.fetch.rateDist::5 3767949 2.15% 76.04% # Number of instructions fetched each cycle (Total) 63system.cpu.fetch.rateDist::6 4531829 2.58% 78.62% # Number of instructions fetched each cycle (Total) 64system.cpu.fetch.rateDist::7 2825666 1.61% 80.24% # Number of instructions fetched each cycle (Total) 65system.cpu.fetch.rateDist::8 34665278 19.76% 100.00% # Number of instructions fetched each cycle (Total)
|
66system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 67system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 68system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
| 66system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 67system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 68system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
69system.cpu.fetch.rateDist::total 175426420 # Number of instructions fetched each cycle (Total) 70system.cpu.fetch.branchRate 0.119257 # Number of branch fetches per cycle 71system.cpu.fetch.rate 1.293095 # Number of inst fetches per cycle 72system.cpu.decode.IdleCycles 40654970 # Number of cycles decode is idle 73system.cpu.decode.BlockedCycles 61059749 # Number of cycles decode is blocked 74system.cpu.decode.RunCycles 46547974 # Number of cycles decode is running 75system.cpu.decode.UnblockCycles 10189463 # Number of cycles decode is unblocking 76system.cpu.decode.SquashCycles 16974264 # Number of cycles decode is squashing 77system.cpu.decode.DecodedInsts 365977737 # Number of instructions handled by decode 78system.cpu.rename.SquashCycles 16974264 # Number of cycles rename is squashing 79system.cpu.rename.IdleCycles 48548849 # Number of cycles rename is idle 80system.cpu.rename.BlockCycles 16319097 # Number of cycles rename is blocking 81system.cpu.rename.serializeStallCycles 23046 # count of cycles rename stalled for serializing inst 82system.cpu.rename.RunCycles 48140036 # Number of cycles rename is running 83system.cpu.rename.UnblockCycles 45421128 # Number of cycles rename is unblocking 84system.cpu.rename.RenamedInsts 356799059 # Number of instructions processed by rename 85system.cpu.rename.ROBFullEvents 33 # Number of times rename has blocked due to ROB full 86system.cpu.rename.IQFullEvents 20636040 # Number of times rename has blocked due to IQ full 87system.cpu.rename.LSQFullEvents 22537767 # Number of times rename has blocked due to LSQ full 88system.cpu.rename.FullRegisterEvents 2198 # Number of times there has been no free registers 89system.cpu.rename.RenamedOperands 506554560 # Number of destination operands rename has renamed 90system.cpu.rename.RenameLookups 1130537584 # Number of register rename lookups that rename has made 91system.cpu.rename.int_rename_lookups 1120266837 # Number of integer rename lookups 92system.cpu.rename.fp_rename_lookups 10270747 # Number of floating rename lookups
| 69system.cpu.fetch.rateDist::total 175391237 # Number of instructions fetched each cycle (Total) 70system.cpu.fetch.branchRate 0.119320 # Number of branch fetches per cycle 71system.cpu.fetch.rate 1.293421 # Number of inst fetches per cycle 72system.cpu.decode.IdleCycles 40660130 # Number of cycles decode is idle 73system.cpu.decode.BlockedCycles 61009372 # Number of cycles decode is blocked 74system.cpu.decode.RunCycles 46541390 # Number of cycles decode is running 75system.cpu.decode.UnblockCycles 10201855 # Number of cycles decode is unblocking 76system.cpu.decode.SquashCycles 16978490 # Number of cycles decode is squashing 77system.cpu.decode.DecodedInsts 366073396 # Number of instructions handled by decode 78system.cpu.rename.SquashCycles 16978490 # Number of cycles rename is squashing 79system.cpu.rename.IdleCycles 48547252 # Number of cycles rename is idle 80system.cpu.rename.BlockCycles 16251189 # Number of cycles rename is blocking 81system.cpu.rename.serializeStallCycles 23056 # count of cycles rename stalled for serializing inst 82system.cpu.rename.RunCycles 48155491 # Number of cycles rename is running 83system.cpu.rename.UnblockCycles 45435759 # Number of cycles rename is unblocking 84system.cpu.rename.RenamedInsts 356858942 # Number of instructions processed by rename 85system.cpu.rename.ROBFullEvents 31 # Number of times rename has blocked due to ROB full 86system.cpu.rename.IQFullEvents 20674050 # Number of times rename has blocked due to IQ full 87system.cpu.rename.LSQFullEvents 22523448 # Number of times rename has blocked due to LSQ full 88system.cpu.rename.FullRegisterEvents 2249 # Number of times there has been no free registers 89system.cpu.rename.RenamedOperands 506627728 # Number of destination operands rename has renamed 90system.cpu.rename.RenameLookups 1130775437 # Number of register rename lookups that rename has made 91system.cpu.rename.int_rename_lookups 1120479419 # Number of integer rename lookups 92system.cpu.rename.fp_rename_lookups 10296018 # Number of floating rename lookups
|
93system.cpu.rename.CommittedMaps 320143989 # Number of HB maps that are committed
| 93system.cpu.rename.CommittedMaps 320143989 # Number of HB maps that are committed
|
94system.cpu.rename.UndoneMaps 186410571 # Number of HB maps that are undone due to squashing 95system.cpu.rename.serializingInsts 1911 # count of serializing insts renamed 96system.cpu.rename.tempSerializingInsts 1906 # count of temporary serializing insts renamed 97system.cpu.rename.skidInsts 95097015 # count of insts added to the skid buffer 98system.cpu.memDep0.insertedLoads 89808446 # Number of loads inserted to the mem dependence unit. 99system.cpu.memDep0.insertedStores 33130186 # Number of stores inserted to the mem dependence unit. 100system.cpu.memDep0.conflictingLoads 59201466 # Number of conflicting loads. 101system.cpu.memDep0.conflictingStores 19519303 # Number of conflicting stores. 102system.cpu.iq.iqInstsAdded 344515408 # Number of instructions added to the IQ (excludes non-spec) 103system.cpu.iq.iqNonSpecInstsAdded 7842 # Number of non-speculative instructions added to the IQ 104system.cpu.iq.iqInstsIssued 270869041 # Number of instructions issued 105system.cpu.iq.iqSquashedInstsIssued 254270 # Number of squashed instructions issued 106system.cpu.iq.iqSquashedInstsExamined 122674827 # Number of squashed instructions iterated over during squash; mainly for profiling 107system.cpu.iq.iqSquashedOperandsExamined 297005948 # Number of squashed operands that are examined and possibly removed from graph 108system.cpu.iq.iqSquashedNonSpecRemoved 6596 # Number of squashed non-spec instructions that were removed 109system.cpu.iq.issued_per_cycle::samples 175426420 # Number of insts issued each cycle 110system.cpu.iq.issued_per_cycle::mean 1.544061 # Number of insts issued each cycle 111system.cpu.iq.issued_per_cycle::stdev 1.467197 # Number of insts issued each cycle
| 94system.cpu.rename.UndoneMaps 186483739 # Number of HB maps that are undone due to squashing 95system.cpu.rename.serializingInsts 1903 # count of serializing insts renamed 96system.cpu.rename.tempSerializingInsts 1897 # count of temporary serializing insts renamed 97system.cpu.rename.skidInsts 95061023 # count of insts added to the skid buffer 98system.cpu.memDep0.insertedLoads 89836107 # Number of loads inserted to the mem dependence unit. 99system.cpu.memDep0.insertedStores 33126554 # Number of stores inserted to the mem dependence unit. 100system.cpu.memDep0.conflictingLoads 59108509 # Number of conflicting loads. 101system.cpu.memDep0.conflictingStores 19466725 # Number of conflicting stores. 102system.cpu.iq.iqInstsAdded 344545895 # Number of instructions added to the IQ (excludes non-spec) 103system.cpu.iq.iqNonSpecInstsAdded 7937 # Number of non-speculative instructions added to the IQ 104system.cpu.iq.iqInstsIssued 270906839 # Number of instructions issued 105system.cpu.iq.iqSquashedInstsIssued 256776 # Number of squashed instructions issued 106system.cpu.iq.iqSquashedInstsExamined 122697293 # Number of squashed instructions iterated over during squash; mainly for profiling 107system.cpu.iq.iqSquashedOperandsExamined 297019638 # Number of squashed operands that are examined and possibly removed from graph 108system.cpu.iq.iqSquashedNonSpecRemoved 6691 # Number of squashed non-spec instructions that were removed 109system.cpu.iq.issued_per_cycle::samples 175391237 # Number of insts issued each cycle 110system.cpu.iq.issued_per_cycle::mean 1.544586 # Number of insts issued each cycle 111system.cpu.iq.issued_per_cycle::stdev 1.467556 # Number of insts issued each cycle
|
112system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
| 112system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
113system.cpu.iq.issued_per_cycle::0 49131919 28.01% 28.01% # Number of insts issued each cycle 114system.cpu.iq.issued_per_cycle::1 52597597 29.98% 57.99% # Number of insts issued each cycle 115system.cpu.iq.issued_per_cycle::2 34344440 19.58% 77.57% # Number of insts issued each cycle 116system.cpu.iq.issued_per_cycle::3 18981960 10.82% 88.39% # Number of insts issued each cycle 117system.cpu.iq.issued_per_cycle::4 12711399 7.25% 95.63% # Number of insts issued each cycle 118system.cpu.iq.issued_per_cycle::5 4926918 2.81% 98.44% # Number of insts issued each cycle 119system.cpu.iq.issued_per_cycle::6 2079867 1.19% 99.63% # Number of insts issued each cycle 120system.cpu.iq.issued_per_cycle::7 541264 0.31% 99.94% # Number of insts issued each cycle 121system.cpu.iq.issued_per_cycle::8 111056 0.06% 100.00% # Number of insts issued each cycle
| 113system.cpu.iq.issued_per_cycle::0 49119269 28.01% 28.01% # Number of insts issued each cycle 114system.cpu.iq.issued_per_cycle::1 52565616 29.97% 57.98% # Number of insts issued each cycle 115system.cpu.iq.issued_per_cycle::2 34331484 19.57% 77.55% # Number of insts issued each cycle 116system.cpu.iq.issued_per_cycle::3 18982131 10.82% 88.37% # Number of insts issued each cycle 117system.cpu.iq.issued_per_cycle::4 12721464 7.25% 95.63% # Number of insts issued each cycle 118system.cpu.iq.issued_per_cycle::5 4942775 2.82% 98.44% # Number of insts issued each cycle 119system.cpu.iq.issued_per_cycle::6 2076613 1.18% 99.63% # Number of insts issued each cycle 120system.cpu.iq.issued_per_cycle::7 542627 0.31% 99.94% # Number of insts issued each cycle 121system.cpu.iq.issued_per_cycle::8 109258 0.06% 100.00% # Number of insts issued each cycle
|
122system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 123system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 124system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
| 122system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 123system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 124system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
125system.cpu.iq.issued_per_cycle::total 175426420 # Number of insts issued each cycle
| 125system.cpu.iq.issued_per_cycle::total 175391237 # Number of insts issued each cycle
|
126system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
| 126system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
127system.cpu.iq.fu_full::IntAlu 91065 3.49% 3.49% # attempts to use FU when none available 128system.cpu.iq.fu_full::IntMult 0 0.00% 3.49% # attempts to use FU when none available 129system.cpu.iq.fu_full::IntDiv 0 0.00% 3.49% # attempts to use FU when none available 130system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.49% # attempts to use FU when none available 131system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.49% # attempts to use FU when none available 132system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.49% # attempts to use FU when none available 133system.cpu.iq.fu_full::FloatMult 0 0.00% 3.49% # attempts to use FU when none available 134system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.49% # attempts to use FU when none available 135system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.49% # attempts to use FU when none available 136system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.49% # attempts to use FU when none available 137system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.49% # attempts to use FU when none available 138system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.49% # attempts to use FU when none available 139system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.49% # attempts to use FU when none available 140system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.49% # attempts to use FU when none available 141system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.49% # attempts to use FU when none available 142system.cpu.iq.fu_full::SimdMult 0 0.00% 3.49% # attempts to use FU when none available 143system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.49% # attempts to use FU when none available 144system.cpu.iq.fu_full::SimdShift 0 0.00% 3.49% # attempts to use FU when none available 145system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.49% # attempts to use FU when none available 146system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.49% # attempts to use FU when none available 147system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.49% # attempts to use FU when none available 148system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.49% # attempts to use FU when none available 149system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.49% # attempts to use FU when none available 150system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.49% # attempts to use FU when none available 151system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.49% # attempts to use FU when none available 152system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.49% # attempts to use FU when none available 153system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.49% # attempts to use FU when none available 154system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.49% # attempts to use FU when none available 155system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.49% # attempts to use FU when none available 156system.cpu.iq.fu_full::MemRead 2241508 85.86% 89.35% # attempts to use FU when none available 157system.cpu.iq.fu_full::MemWrite 277930 10.65% 100.00% # attempts to use FU when none available
| 127system.cpu.iq.fu_full::IntAlu 90563 3.50% 3.50% # attempts to use FU when none available 128system.cpu.iq.fu_full::IntMult 0 0.00% 3.50% # attempts to use FU when none available 129system.cpu.iq.fu_full::IntDiv 0 0.00% 3.50% # attempts to use FU when none available 130system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.50% # attempts to use FU when none available 131system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.50% # attempts to use FU when none available 132system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.50% # attempts to use FU when none available 133system.cpu.iq.fu_full::FloatMult 0 0.00% 3.50% # attempts to use FU when none available 134system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.50% # attempts to use FU when none available 135system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.50% # attempts to use FU when none available 136system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.50% # attempts to use FU when none available 137system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.50% # attempts to use FU when none available 138system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.50% # attempts to use FU when none available 139system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.50% # attempts to use FU when none available 140system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.50% # attempts to use FU when none available 141system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.50% # attempts to use FU when none available 142system.cpu.iq.fu_full::SimdMult 0 0.00% 3.50% # attempts to use FU when none available 143system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.50% # attempts to use FU when none available 144system.cpu.iq.fu_full::SimdShift 0 0.00% 3.50% # attempts to use FU when none available 145system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.50% # attempts to use FU when none available 146system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.50% # attempts to use FU when none available 147system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.50% # attempts to use FU when none available 148system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.50% # attempts to use FU when none available 149system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.50% # attempts to use FU when none available 150system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.50% # attempts to use FU when none available 151system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.50% # attempts to use FU when none available 152system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.50% # attempts to use FU when none available 153system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.50% # attempts to use FU when none available 154system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.50% # attempts to use FU when none available 155system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.50% # attempts to use FU when none available 156system.cpu.iq.fu_full::MemRead 2225289 85.92% 89.42% # attempts to use FU when none available 157system.cpu.iq.fu_full::MemWrite 273998 10.58% 100.00% # attempts to use FU when none available
|
158system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 159system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
| 158system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 159system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
160system.cpu.iq.FU_type_0::No_OpClass 1212815 0.45% 0.45% # Type of FU issued 161system.cpu.iq.FU_type_0::IntAlu 176257528 65.07% 65.52% # Type of FU issued 162system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.52% # Type of FU issued 163system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued 164system.cpu.iq.FU_type_0::FloatAdd 1592327 0.59% 66.11% # Type of FU issued 165system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.11% # Type of FU issued 166system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.11% # Type of FU issued 167system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.11% # Type of FU issued 168system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.11% # Type of FU issued 169system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.11% # Type of FU issued 170system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.11% # Type of FU issued 171system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.11% # Type of FU issued 172system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.11% # Type of FU issued 173system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.11% # Type of FU issued 174system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.11% # Type of FU issued 175system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.11% # Type of FU issued 176system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.11% # Type of FU issued 177system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.11% # Type of FU issued 178system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.11% # Type of FU issued 179system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued 180system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.11% # Type of FU issued 181system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued 182system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued 183system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued 184system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued 185system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued 186system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued 187system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued 188system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued 189system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued 190system.cpu.iq.FU_type_0::MemRead 68300084 25.22% 91.32% # Type of FU issued 191system.cpu.iq.FU_type_0::MemWrite 23506287 8.68% 100.00% # Type of FU issued
| 160system.cpu.iq.FU_type_0::No_OpClass 1212985 0.45% 0.45% # Type of FU issued 161system.cpu.iq.FU_type_0::IntAlu 176266302 65.07% 65.51% # Type of FU issued 162system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.51% # Type of FU issued 163system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.51% # Type of FU issued 164system.cpu.iq.FU_type_0::FloatAdd 1595268 0.59% 66.10% # Type of FU issued 165system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.10% # Type of FU issued 166system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.10% # Type of FU issued 167system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.10% # Type of FU issued 168system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.10% # Type of FU issued 169system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.10% # Type of FU issued 170system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.10% # Type of FU issued 171system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.10% # Type of FU issued 172system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.10% # Type of FU issued 173system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.10% # Type of FU issued 174system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.10% # Type of FU issued 175system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.10% # Type of FU issued 176system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.10% # Type of FU issued 177system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.10% # Type of FU issued 178system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.10% # Type of FU issued 179system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.10% # Type of FU issued 180system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.10% # Type of FU issued 181system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.10% # Type of FU issued 182system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.10% # Type of FU issued 183system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.10% # Type of FU issued 184system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.10% # Type of FU issued 185system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.10% # Type of FU issued 186system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.10% # Type of FU issued 187system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.10% # Type of FU issued 188system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.10% # Type of FU issued 189system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.10% # Type of FU issued 190system.cpu.iq.FU_type_0::MemRead 68329319 25.22% 91.32% # Type of FU issued 191system.cpu.iq.FU_type_0::MemWrite 23502965 8.68% 100.00% # Type of FU issued
|
192system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 193system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
| 192system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 193system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
194system.cpu.iq.FU_type_0::total 270869041 # Type of FU issued 195system.cpu.iq.rate 1.543383 # Inst issue rate 196system.cpu.iq.fu_busy_cnt 2610503 # FU busy when requested 197system.cpu.iq.fu_busy_rate 0.009638 # FU busy rate (busy events/executed inst) 198system.cpu.iq.int_inst_queue_reads 714724682 # Number of integer instruction queue reads 199system.cpu.iq.int_inst_queue_writes 462639790 # Number of integer instruction queue writes 200system.cpu.iq.int_inst_queue_wakeup_accesses 263265519 # Number of integer instruction queue wakeup accesses 201system.cpu.iq.fp_inst_queue_reads 5304593 # Number of floating instruction queue reads 202system.cpu.iq.fp_inst_queue_writes 4857798 # Number of floating instruction queue writes 203system.cpu.iq.fp_inst_queue_wakeup_accesses 2549095 # Number of floating instruction queue wakeup accesses 204system.cpu.iq.int_alu_accesses 269608691 # Number of integer alu accesses 205system.cpu.iq.fp_alu_accesses 2658038 # Number of floating point alu accesses 206system.cpu.iew.lsq.thread0.forwLoads 18925158 # Number of loads that had data forwarded from stores
| 194system.cpu.iq.FU_type_0::total 270906839 # Type of FU issued 195system.cpu.iq.rate 1.543909 # Inst issue rate 196system.cpu.iq.fu_busy_cnt 2589850 # FU busy when requested 197system.cpu.iq.fu_busy_rate 0.009560 # FU busy rate (busy events/executed inst) 198system.cpu.iq.int_inst_queue_reads 714739567 # Number of integer instruction queue reads 199system.cpu.iq.int_inst_queue_writes 462675137 # Number of integer instruction queue writes 200system.cpu.iq.int_inst_queue_wakeup_accesses 263287653 # Number of integer instruction queue wakeup accesses 201system.cpu.iq.fp_inst_queue_reads 5311974 # Number of floating instruction queue reads 202system.cpu.iq.fp_inst_queue_writes 4876750 # Number of floating instruction queue writes 203system.cpu.iq.fp_inst_queue_wakeup_accesses 2553148 # Number of floating instruction queue wakeup accesses 204system.cpu.iq.int_alu_accesses 269622080 # Number of integer alu accesses 205system.cpu.iq.fp_alu_accesses 2661624 # Number of floating point alu accesses 206system.cpu.iew.lsq.thread0.forwLoads 18915593 # Number of loads that had data forwarded from stores
|
207system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
| 207system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
208system.cpu.iew.lsq.thread0.squashedLoads 33158856 # Number of loads squashed 209system.cpu.iew.lsq.thread0.ignoredResponses 30567 # Number of memory responses ignored because the instruction is squashed 210system.cpu.iew.lsq.thread0.memOrderViolation 304625 # Number of memory ordering violations 211system.cpu.iew.lsq.thread0.squashedStores 12614470 # Number of stores squashed
| 208system.cpu.iew.lsq.thread0.squashedLoads 33186517 # Number of loads squashed 209system.cpu.iew.lsq.thread0.ignoredResponses 30708 # Number of memory responses ignored because the instruction is squashed 210system.cpu.iew.lsq.thread0.memOrderViolation 305892 # Number of memory ordering violations 211system.cpu.iew.lsq.thread0.squashedStores 12610838 # Number of stores squashed
|
212system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 213system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
| 212system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 213system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
214system.cpu.iew.lsq.thread0.rescheduledLoads 47486 # Number of loads that were rescheduled
| 214system.cpu.iew.lsq.thread0.rescheduledLoads 47515 # Number of loads that were rescheduled
|
215system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 216system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
| 215system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 216system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
217system.cpu.iew.iewSquashCycles 16974264 # Number of cycles IEW is squashing 218system.cpu.iew.iewBlockCycles 523635 # Number of cycles IEW is blocking 219system.cpu.iew.iewUnblockCycles 253200 # Number of cycles IEW is unblocking 220system.cpu.iew.iewDispatchedInsts 344523250 # Number of instructions dispatched to IQ 221system.cpu.iew.iewDispSquashedInsts 297274 # Number of squashed instructions skipped by dispatch 222system.cpu.iew.iewDispLoadInsts 89808446 # Number of dispatched load instructions 223system.cpu.iew.iewDispStoreInsts 33130186 # Number of dispatched store instructions 224system.cpu.iew.iewDispNonSpecInsts 1859 # Number of dispatched non-speculative instructions 225system.cpu.iew.iewIQFullEvents 168556 # Number of times the IQ has become full, causing a stall 226system.cpu.iew.iewLSQFullEvents 31575 # Number of times the LSQ has become full, causing a stall 227system.cpu.iew.memOrderViolationEvents 304625 # Number of memory order violations 228system.cpu.iew.predictedTakenIncorrect 1298513 # Number of branches that were predicted taken incorrectly 229system.cpu.iew.predictedNotTakenIncorrect 1028751 # Number of branches that were predicted not taken incorrectly 230system.cpu.iew.branchMispredicts 2327264 # Number of branch mispredicts detected at execute 231system.cpu.iew.iewExecutedInsts 267763849 # Number of executed instructions 232system.cpu.iew.iewExecLoadInsts 67223329 # Number of load instructions executed 233system.cpu.iew.iewExecSquashedInsts 3105192 # Number of squashed instructions skipped in execute
| 217system.cpu.iew.iewSquashCycles 16978490 # Number of cycles IEW is squashing 218system.cpu.iew.iewBlockCycles 517280 # Number of cycles IEW is blocking 219system.cpu.iew.iewUnblockCycles 233874 # Number of cycles IEW is unblocking 220system.cpu.iew.iewDispatchedInsts 344553832 # Number of instructions dispatched to IQ 221system.cpu.iew.iewDispSquashedInsts 297077 # Number of squashed instructions skipped by dispatch 222system.cpu.iew.iewDispLoadInsts 89836107 # Number of dispatched load instructions 223system.cpu.iew.iewDispStoreInsts 33126554 # Number of dispatched store instructions 224system.cpu.iew.iewDispNonSpecInsts 1857 # Number of dispatched non-speculative instructions 225system.cpu.iew.iewIQFullEvents 147591 # Number of times the IQ has become full, causing a stall 226system.cpu.iew.iewLSQFullEvents 33364 # Number of times the LSQ has become full, causing a stall 227system.cpu.iew.memOrderViolationEvents 305892 # Number of memory order violations 228system.cpu.iew.predictedTakenIncorrect 1298592 # Number of branches that were predicted taken incorrectly 229system.cpu.iew.predictedNotTakenIncorrect 1028927 # Number of branches that were predicted not taken incorrectly 230system.cpu.iew.branchMispredicts 2327519 # Number of branch mispredicts detected at execute 231system.cpu.iew.iewExecutedInsts 267790575 # Number of executed instructions 232system.cpu.iew.iewExecLoadInsts 67240366 # Number of load instructions executed 233system.cpu.iew.iewExecSquashedInsts 3116264 # Number of squashed instructions skipped in execute
|
234system.cpu.iew.exec_swp 0 # number of swp insts executed 235system.cpu.iew.exec_nop 0 # number of nop insts executed
| 234system.cpu.iew.exec_swp 0 # number of swp insts executed 235system.cpu.iew.exec_nop 0 # number of nop insts executed
|
236system.cpu.iew.exec_refs 90337843 # number of memory reference insts executed 237system.cpu.iew.exec_branches 14773998 # Number of branches executed 238system.cpu.iew.exec_stores 23114514 # Number of stores executed 239system.cpu.iew.exec_rate 1.525690 # Inst execution rate 240system.cpu.iew.wb_sent 266689649 # cumulative count of insts sent to commit 241system.cpu.iew.wb_count 265814614 # cumulative count of insts written-back 242system.cpu.iew.wb_producers 214459238 # num instructions producing a value 243system.cpu.iew.wb_consumers 504388652 # num instructions consuming a value
| 236system.cpu.iew.exec_refs 90351837 # number of memory reference insts executed 237system.cpu.iew.exec_branches 14775060 # Number of branches executed 238system.cpu.iew.exec_stores 23111471 # Number of stores executed 239system.cpu.iew.exec_rate 1.526150 # Inst execution rate 240system.cpu.iew.wb_sent 266714598 # cumulative count of insts sent to commit 241system.cpu.iew.wb_count 265840801 # cumulative count of insts written-back 242system.cpu.iew.wb_producers 214478617 # num instructions producing a value 243system.cpu.iew.wb_consumers 504376698 # num instructions consuming a value
|
244system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
| 244system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
245system.cpu.iew.wb_rate 1.514583 # insts written-back per cycle 246system.cpu.iew.wb_fanout 0.425186 # average fanout of values written-back
| 245system.cpu.iew.wb_rate 1.515038 # insts written-back per cycle 246system.cpu.iew.wb_fanout 0.425235 # average fanout of values written-back
|
247system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 248system.cpu.commit.commitCommittedInsts 132071227 # The number of committed instructions 249system.cpu.commit.commitCommittedOps 221363017 # The number of committed instructions
| 247system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 248system.cpu.commit.commitCommittedInsts 132071227 # The number of committed instructions 249system.cpu.commit.commitCommittedOps 221363017 # The number of committed instructions
|
250system.cpu.commit.commitSquashedInsts 123271968 # The number of squashed insts skipped by commit
| 250system.cpu.commit.commitSquashedInsts 123301880 # The number of squashed insts skipped by commit
|
251system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards
| 251system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards
|
252system.cpu.commit.branchMispredicts 2209353 # The number of times a branch was mispredicted 253system.cpu.commit.committed_per_cycle::samples 158452156 # Number of insts commited each cycle 254system.cpu.commit.committed_per_cycle::mean 1.397034 # Number of insts commited each cycle 255system.cpu.commit.committed_per_cycle::stdev 1.794480 # Number of insts commited each cycle
| 252system.cpu.commit.branchMispredicts 2209791 # The number of times a branch was mispredicted 253system.cpu.commit.committed_per_cycle::samples 158412747 # Number of insts commited each cycle 254system.cpu.commit.committed_per_cycle::mean 1.397381 # Number of insts commited each cycle 255system.cpu.commit.committed_per_cycle::stdev 1.795092 # Number of insts commited each cycle
|
256system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
| 256system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
257system.cpu.commit.committed_per_cycle::0 54225216 34.22% 34.22% # Number of insts commited each cycle 258system.cpu.commit.committed_per_cycle::1 60443910 38.15% 72.37% # Number of insts commited each cycle 259system.cpu.commit.committed_per_cycle::2 15544008 9.81% 82.18% # Number of insts commited each cycle 260system.cpu.commit.committed_per_cycle::3 12710691 8.02% 90.20% # Number of insts commited each cycle 261system.cpu.commit.committed_per_cycle::4 4546278 2.87% 93.07% # Number of insts commited each cycle 262system.cpu.commit.committed_per_cycle::5 2974927 1.88% 94.95% # Number of insts commited each cycle 263system.cpu.commit.committed_per_cycle::6 2086566 1.32% 96.26% # Number of insts commited each cycle 264system.cpu.commit.committed_per_cycle::7 1244605 0.79% 97.05% # Number of insts commited each cycle 265system.cpu.commit.committed_per_cycle::8 4675955 2.95% 100.00% # Number of insts commited each cycle
| 257system.cpu.commit.committed_per_cycle::0 54206628 34.22% 34.22% # Number of insts commited each cycle 258system.cpu.commit.committed_per_cycle::1 60400758 38.13% 72.35% # Number of insts commited each cycle 259system.cpu.commit.committed_per_cycle::2 15586261 9.84% 82.19% # Number of insts commited each cycle 260system.cpu.commit.committed_per_cycle::3 12707072 8.02% 90.21% # Number of insts commited each cycle 261system.cpu.commit.committed_per_cycle::4 4534557 2.86% 93.07% # Number of insts commited each cycle 262system.cpu.commit.committed_per_cycle::5 2957745 1.87% 94.94% # Number of insts commited each cycle 263system.cpu.commit.committed_per_cycle::6 2082808 1.31% 96.25% # Number of insts commited each cycle 264system.cpu.commit.committed_per_cycle::7 1250624 0.79% 97.04% # Number of insts commited each cycle 265system.cpu.commit.committed_per_cycle::8 4686294 2.96% 100.00% # Number of insts commited each cycle
|
266system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 267system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 268system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
| 266system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 267system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 268system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
269system.cpu.commit.committed_per_cycle::total 158452156 # Number of insts commited each cycle
| 269system.cpu.commit.committed_per_cycle::total 158412747 # Number of insts commited each cycle
|
270system.cpu.commit.committedInsts 132071227 # Number of instructions committed 271system.cpu.commit.committedOps 221363017 # Number of ops (including micro ops) committed 272system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 273system.cpu.commit.refs 77165306 # Number of memory references committed 274system.cpu.commit.loads 56649590 # Number of loads committed 275system.cpu.commit.membars 0 # Number of memory barriers committed 276system.cpu.commit.branches 12326943 # Number of branches committed 277system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. 278system.cpu.commit.int_insts 220339606 # Number of committed integer instructions. 279system.cpu.commit.function_calls 0 # Number of function calls committed.
| 270system.cpu.commit.committedInsts 132071227 # Number of instructions committed 271system.cpu.commit.committedOps 221363017 # Number of ops (including micro ops) committed 272system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 273system.cpu.commit.refs 77165306 # Number of memory references committed 274system.cpu.commit.loads 56649590 # Number of loads committed 275system.cpu.commit.membars 0 # Number of memory barriers committed 276system.cpu.commit.branches 12326943 # Number of branches committed 277system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. 278system.cpu.commit.int_insts 220339606 # Number of committed integer instructions. 279system.cpu.commit.function_calls 0 # Number of function calls committed.
|
280system.cpu.commit.bw_lim_events 4675955 # number cycles where commit BW limit reached
| 280system.cpu.commit.bw_lim_events 4686294 # number cycles where commit BW limit reached
|
281system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
| 281system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
282system.cpu.rob.rob_reads 498411186 # The number of ROB reads 283system.cpu.rob.rob_writes 706281673 # The number of ROB writes 284system.cpu.timesIdled 1684 # Number of times that the entire CPU went into an idle state and unscheduled itself 285system.cpu.idleCycles 77041 # Total number of cycles that the CPU has spent unscheduled due to idling
| 282system.cpu.rob.rob_reads 498391350 # The number of ROB reads 283system.cpu.rob.rob_writes 706346628 # The number of ROB writes 284system.cpu.timesIdled 1678 # Number of times that the entire CPU went into an idle state and unscheduled itself 285system.cpu.idleCycles 76860 # Total number of cycles that the CPU has spent unscheduled due to idling
|
286system.cpu.committedInsts 132071227 # Number of Instructions Simulated 287system.cpu.committedOps 221363017 # Number of Ops (including micro ops) Simulated 288system.cpu.committedInsts_total 132071227 # Number of Instructions Simulated
| 286system.cpu.committedInsts 132071227 # Number of Instructions Simulated 287system.cpu.committedOps 221363017 # Number of Ops (including micro ops) Simulated 288system.cpu.committedInsts_total 132071227 # Number of Instructions Simulated
|
289system.cpu.cpi 1.328855 # CPI: Cycles Per Instruction 290system.cpu.cpi_total 1.328855 # CPI: Total CPI of All Threads 291system.cpu.ipc 0.752528 # IPC: Instructions Per Cycle 292system.cpu.ipc_total 0.752528 # IPC: Total IPC of All Threads 293system.cpu.int_regfile_reads 657510098 # number of integer regfile reads 294system.cpu.int_regfile_writes 365370199 # number of integer regfile writes 295system.cpu.fp_regfile_reads 3509073 # number of floating regfile reads 296system.cpu.fp_regfile_writes 2221147 # number of floating regfile writes 297system.cpu.misc_regfile_reads 139423581 # number of misc regfile reads
| 289system.cpu.cpi 1.328587 # CPI: Cycles Per Instruction 290system.cpu.cpi_total 1.328587 # CPI: Total CPI of All Threads 291system.cpu.ipc 0.752679 # IPC: Instructions Per Cycle 292system.cpu.ipc_total 0.752679 # IPC: Total IPC of All Threads 293system.cpu.int_regfile_reads 657568441 # number of integer regfile reads 294system.cpu.int_regfile_writes 365395599 # number of integer regfile writes 295system.cpu.fp_regfile_reads 3514318 # number of floating regfile reads 296system.cpu.fp_regfile_writes 2225520 # number of floating regfile writes 297system.cpu.misc_regfile_reads 139440665 # number of misc regfile reads
|
298system.cpu.misc_regfile_writes 844 # number of misc regfile writes
| 298system.cpu.misc_regfile_writes 844 # number of misc regfile writes
|
299system.cpu.icache.replacements 5601 # number of replacements 300system.cpu.icache.tagsinuse 1627.936468 # Cycle average of tags in use 301system.cpu.icache.total_refs 25813461 # Total number of references to valid blocks. 302system.cpu.icache.sampled_refs 7571 # Sample count of references to valid blocks. 303system.cpu.icache.avg_refs 3409.518029 # Average number of references to valid blocks.
| 299system.cpu.icache.replacements 5526 # number of replacements 300system.cpu.icache.tagsinuse 1631.257386 # Cycle average of tags in use 301system.cpu.icache.total_refs 25812694 # Total number of references to valid blocks. 302system.cpu.icache.sampled_refs 7496 # Sample count of references to valid blocks. 303system.cpu.icache.avg_refs 3443.529082 # Average number of references to valid blocks.
|
304system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 304system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
305system.cpu.icache.occ_blocks::cpu.inst 1627.936468 # Average occupied blocks per requestor 306system.cpu.icache.occ_percent::cpu.inst 0.794891 # Average percentage of cache occupancy 307system.cpu.icache.occ_percent::total 0.794891 # Average percentage of cache occupancy 308system.cpu.icache.ReadReq_hits::cpu.inst 25813461 # number of ReadReq hits 309system.cpu.icache.ReadReq_hits::total 25813461 # number of ReadReq hits 310system.cpu.icache.demand_hits::cpu.inst 25813461 # number of demand (read+write) hits 311system.cpu.icache.demand_hits::total 25813461 # number of demand (read+write) hits 312system.cpu.icache.overall_hits::cpu.inst 25813461 # number of overall hits 313system.cpu.icache.overall_hits::total 25813461 # number of overall hits 314system.cpu.icache.ReadReq_misses::cpu.inst 9093 # number of ReadReq misses 315system.cpu.icache.ReadReq_misses::total 9093 # number of ReadReq misses 316system.cpu.icache.demand_misses::cpu.inst 9093 # number of demand (read+write) misses 317system.cpu.icache.demand_misses::total 9093 # number of demand (read+write) misses 318system.cpu.icache.overall_misses::cpu.inst 9093 # number of overall misses 319system.cpu.icache.overall_misses::total 9093 # number of overall misses 320system.cpu.icache.ReadReq_miss_latency::cpu.inst 187306000 # number of ReadReq miss cycles 321system.cpu.icache.ReadReq_miss_latency::total 187306000 # number of ReadReq miss cycles 322system.cpu.icache.demand_miss_latency::cpu.inst 187306000 # number of demand (read+write) miss cycles 323system.cpu.icache.demand_miss_latency::total 187306000 # number of demand (read+write) miss cycles 324system.cpu.icache.overall_miss_latency::cpu.inst 187306000 # number of overall miss cycles 325system.cpu.icache.overall_miss_latency::total 187306000 # number of overall miss cycles 326system.cpu.icache.ReadReq_accesses::cpu.inst 25822554 # number of ReadReq accesses(hits+misses) 327system.cpu.icache.ReadReq_accesses::total 25822554 # number of ReadReq accesses(hits+misses) 328system.cpu.icache.demand_accesses::cpu.inst 25822554 # number of demand (read+write) accesses 329system.cpu.icache.demand_accesses::total 25822554 # number of demand (read+write) accesses 330system.cpu.icache.overall_accesses::cpu.inst 25822554 # number of overall (read+write) accesses 331system.cpu.icache.overall_accesses::total 25822554 # number of overall (read+write) accesses 332system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000352 # miss rate for ReadReq accesses 333system.cpu.icache.ReadReq_miss_rate::total 0.000352 # miss rate for ReadReq accesses 334system.cpu.icache.demand_miss_rate::cpu.inst 0.000352 # miss rate for demand accesses 335system.cpu.icache.demand_miss_rate::total 0.000352 # miss rate for demand accesses 336system.cpu.icache.overall_miss_rate::cpu.inst 0.000352 # miss rate for overall accesses 337system.cpu.icache.overall_miss_rate::total 0.000352 # miss rate for overall accesses 338system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20598.922248 # average ReadReq miss latency 339system.cpu.icache.ReadReq_avg_miss_latency::total 20598.922248 # average ReadReq miss latency 340system.cpu.icache.demand_avg_miss_latency::cpu.inst 20598.922248 # average overall miss latency 341system.cpu.icache.demand_avg_miss_latency::total 20598.922248 # average overall miss latency 342system.cpu.icache.overall_avg_miss_latency::cpu.inst 20598.922248 # average overall miss latency 343system.cpu.icache.overall_avg_miss_latency::total 20598.922248 # average overall miss latency
| 305system.cpu.icache.occ_blocks::cpu.inst 1631.257386 # Average occupied blocks per requestor 306system.cpu.icache.occ_percent::cpu.inst 0.796512 # Average percentage of cache occupancy 307system.cpu.icache.occ_percent::total 0.796512 # Average percentage of cache occupancy 308system.cpu.icache.ReadReq_hits::cpu.inst 25812694 # number of ReadReq hits 309system.cpu.icache.ReadReq_hits::total 25812694 # number of ReadReq hits 310system.cpu.icache.demand_hits::cpu.inst 25812694 # number of demand (read+write) hits 311system.cpu.icache.demand_hits::total 25812694 # number of demand (read+write) hits 312system.cpu.icache.overall_hits::cpu.inst 25812694 # number of overall hits 313system.cpu.icache.overall_hits::total 25812694 # number of overall hits 314system.cpu.icache.ReadReq_misses::cpu.inst 8998 # number of ReadReq misses 315system.cpu.icache.ReadReq_misses::total 8998 # number of ReadReq misses 316system.cpu.icache.demand_misses::cpu.inst 8998 # number of demand (read+write) misses 317system.cpu.icache.demand_misses::total 8998 # number of demand (read+write) misses 318system.cpu.icache.overall_misses::cpu.inst 8998 # number of overall misses 319system.cpu.icache.overall_misses::total 8998 # number of overall misses 320system.cpu.icache.ReadReq_miss_latency::cpu.inst 186818500 # number of ReadReq miss cycles 321system.cpu.icache.ReadReq_miss_latency::total 186818500 # number of ReadReq miss cycles 322system.cpu.icache.demand_miss_latency::cpu.inst 186818500 # number of demand (read+write) miss cycles 323system.cpu.icache.demand_miss_latency::total 186818500 # number of demand (read+write) miss cycles 324system.cpu.icache.overall_miss_latency::cpu.inst 186818500 # number of overall miss cycles 325system.cpu.icache.overall_miss_latency::total 186818500 # number of overall miss cycles 326system.cpu.icache.ReadReq_accesses::cpu.inst 25821692 # number of ReadReq accesses(hits+misses) 327system.cpu.icache.ReadReq_accesses::total 25821692 # number of ReadReq accesses(hits+misses) 328system.cpu.icache.demand_accesses::cpu.inst 25821692 # number of demand (read+write) accesses 329system.cpu.icache.demand_accesses::total 25821692 # number of demand (read+write) accesses 330system.cpu.icache.overall_accesses::cpu.inst 25821692 # number of overall (read+write) accesses 331system.cpu.icache.overall_accesses::total 25821692 # number of overall (read+write) accesses 332system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000348 # miss rate for ReadReq accesses 333system.cpu.icache.ReadReq_miss_rate::total 0.000348 # miss rate for ReadReq accesses 334system.cpu.icache.demand_miss_rate::cpu.inst 0.000348 # miss rate for demand accesses 335system.cpu.icache.demand_miss_rate::total 0.000348 # miss rate for demand accesses 336system.cpu.icache.overall_miss_rate::cpu.inst 0.000348 # miss rate for overall accesses 337system.cpu.icache.overall_miss_rate::total 0.000348 # miss rate for overall accesses 338system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20762.224939 # average ReadReq miss latency 339system.cpu.icache.ReadReq_avg_miss_latency::total 20762.224939 # average ReadReq miss latency 340system.cpu.icache.demand_avg_miss_latency::cpu.inst 20762.224939 # average overall miss latency 341system.cpu.icache.demand_avg_miss_latency::total 20762.224939 # average overall miss latency 342system.cpu.icache.overall_avg_miss_latency::cpu.inst 20762.224939 # average overall miss latency 343system.cpu.icache.overall_avg_miss_latency::total 20762.224939 # average overall miss latency
|
344system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 345system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 346system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 347system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 348system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 349system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 350system.cpu.icache.fast_writes 0 # number of fast writes performed 351system.cpu.icache.cache_copies 0 # number of cache copies performed
| 344system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 345system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 346system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 347system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 348system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 349system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 350system.cpu.icache.fast_writes 0 # number of fast writes performed 351system.cpu.icache.cache_copies 0 # number of cache copies performed
|
352system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1367 # number of ReadReq MSHR hits 353system.cpu.icache.ReadReq_mshr_hits::total 1367 # number of ReadReq MSHR hits 354system.cpu.icache.demand_mshr_hits::cpu.inst 1367 # number of demand (read+write) MSHR hits 355system.cpu.icache.demand_mshr_hits::total 1367 # number of demand (read+write) MSHR hits 356system.cpu.icache.overall_mshr_hits::cpu.inst 1367 # number of overall MSHR hits 357system.cpu.icache.overall_mshr_hits::total 1367 # number of overall MSHR hits 358system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7726 # number of ReadReq MSHR misses 359system.cpu.icache.ReadReq_mshr_misses::total 7726 # number of ReadReq MSHR misses 360system.cpu.icache.demand_mshr_misses::cpu.inst 7726 # number of demand (read+write) MSHR misses 361system.cpu.icache.demand_mshr_misses::total 7726 # number of demand (read+write) MSHR misses 362system.cpu.icache.overall_mshr_misses::cpu.inst 7726 # number of overall MSHR misses 363system.cpu.icache.overall_mshr_misses::total 7726 # number of overall MSHR misses 364system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130634500 # number of ReadReq MSHR miss cycles 365system.cpu.icache.ReadReq_mshr_miss_latency::total 130634500 # number of ReadReq MSHR miss cycles 366system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130634500 # number of demand (read+write) MSHR miss cycles 367system.cpu.icache.demand_mshr_miss_latency::total 130634500 # number of demand (read+write) MSHR miss cycles 368system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130634500 # number of overall MSHR miss cycles 369system.cpu.icache.overall_mshr_miss_latency::total 130634500 # number of overall MSHR miss cycles 370system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for ReadReq accesses 371system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000299 # mshr miss rate for ReadReq accesses 372system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for demand accesses 373system.cpu.icache.demand_mshr_miss_rate::total 0.000299 # mshr miss rate for demand accesses 374system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for overall accesses 375system.cpu.icache.overall_mshr_miss_rate::total 0.000299 # mshr miss rate for overall accesses 376system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16908.426094 # average ReadReq mshr miss latency 377system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16908.426094 # average ReadReq mshr miss latency 378system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16908.426094 # average overall mshr miss latency 379system.cpu.icache.demand_avg_mshr_miss_latency::total 16908.426094 # average overall mshr miss latency 380system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16908.426094 # average overall mshr miss latency 381system.cpu.icache.overall_avg_mshr_miss_latency::total 16908.426094 # average overall mshr miss latency
| 352system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1359 # number of ReadReq MSHR hits 353system.cpu.icache.ReadReq_mshr_hits::total 1359 # number of ReadReq MSHR hits 354system.cpu.icache.demand_mshr_hits::cpu.inst 1359 # number of demand (read+write) MSHR hits 355system.cpu.icache.demand_mshr_hits::total 1359 # number of demand (read+write) MSHR hits 356system.cpu.icache.overall_mshr_hits::cpu.inst 1359 # number of overall MSHR hits 357system.cpu.icache.overall_mshr_hits::total 1359 # number of overall MSHR hits 358system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7639 # number of ReadReq MSHR misses 359system.cpu.icache.ReadReq_mshr_misses::total 7639 # number of ReadReq MSHR misses 360system.cpu.icache.demand_mshr_misses::cpu.inst 7639 # number of demand (read+write) MSHR misses 361system.cpu.icache.demand_mshr_misses::total 7639 # number of demand (read+write) MSHR misses 362system.cpu.icache.overall_mshr_misses::cpu.inst 7639 # number of overall MSHR misses 363system.cpu.icache.overall_mshr_misses::total 7639 # number of overall MSHR misses 364system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130438500 # number of ReadReq MSHR miss cycles 365system.cpu.icache.ReadReq_mshr_miss_latency::total 130438500 # number of ReadReq MSHR miss cycles 366system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130438500 # number of demand (read+write) MSHR miss cycles 367system.cpu.icache.demand_mshr_miss_latency::total 130438500 # number of demand (read+write) MSHR miss cycles 368system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130438500 # number of overall MSHR miss cycles 369system.cpu.icache.overall_mshr_miss_latency::total 130438500 # number of overall MSHR miss cycles 370system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000296 # mshr miss rate for ReadReq accesses 371system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000296 # mshr miss rate for ReadReq accesses 372system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000296 # mshr miss rate for demand accesses 373system.cpu.icache.demand_mshr_miss_rate::total 0.000296 # mshr miss rate for demand accesses 374system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000296 # mshr miss rate for overall accesses 375system.cpu.icache.overall_mshr_miss_rate::total 0.000296 # mshr miss rate for overall accesses 376system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17075.337086 # average ReadReq mshr miss latency 377system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17075.337086 # average ReadReq mshr miss latency 378system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17075.337086 # average overall mshr miss latency 379system.cpu.icache.demand_avg_mshr_miss_latency::total 17075.337086 # average overall mshr miss latency 380system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17075.337086 # average overall mshr miss latency 381system.cpu.icache.overall_avg_mshr_miss_latency::total 17075.337086 # average overall mshr miss latency
|
382system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
| 382system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
383system.cpu.dcache.replacements 56 # number of replacements 384system.cpu.dcache.tagsinuse 1426.584624 # Cycle average of tags in use 385system.cpu.dcache.total_refs 68642098 # Total number of references to valid blocks. 386system.cpu.dcache.sampled_refs 1997 # Sample count of references to valid blocks. 387system.cpu.dcache.avg_refs 34372.607912 # Average number of references to valid blocks.
| 383system.cpu.dcache.replacements 57 # number of replacements 384system.cpu.dcache.tagsinuse 1425.887115 # Cycle average of tags in use 385system.cpu.dcache.total_refs 68669194 # Total number of references to valid blocks. 386system.cpu.dcache.sampled_refs 1998 # Sample count of references to valid blocks. 387system.cpu.dcache.avg_refs 34368.965966 # Average number of references to valid blocks.
|
388system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 388system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
389system.cpu.dcache.occ_blocks::cpu.data 1426.584624 # Average occupied blocks per requestor 390system.cpu.dcache.occ_percent::cpu.data 0.348287 # Average percentage of cache occupancy 391system.cpu.dcache.occ_percent::total 0.348287 # Average percentage of cache occupancy 392system.cpu.dcache.ReadReq_hits::cpu.data 48127880 # number of ReadReq hits 393system.cpu.dcache.ReadReq_hits::total 48127880 # number of ReadReq hits 394system.cpu.dcache.WriteReq_hits::cpu.data 20514014 # number of WriteReq hits 395system.cpu.dcache.WriteReq_hits::total 20514014 # number of WriteReq hits 396system.cpu.dcache.demand_hits::cpu.data 68641894 # number of demand (read+write) hits 397system.cpu.dcache.demand_hits::total 68641894 # number of demand (read+write) hits 398system.cpu.dcache.overall_hits::cpu.data 68641894 # number of overall hits 399system.cpu.dcache.overall_hits::total 68641894 # number of overall hits 400system.cpu.dcache.ReadReq_misses::cpu.data 772 # number of ReadReq misses 401system.cpu.dcache.ReadReq_misses::total 772 # number of ReadReq misses 402system.cpu.dcache.WriteReq_misses::cpu.data 1716 # number of WriteReq misses 403system.cpu.dcache.WriteReq_misses::total 1716 # number of WriteReq misses 404system.cpu.dcache.demand_misses::cpu.data 2488 # number of demand (read+write) misses 405system.cpu.dcache.demand_misses::total 2488 # number of demand (read+write) misses 406system.cpu.dcache.overall_misses::cpu.data 2488 # number of overall misses 407system.cpu.dcache.overall_misses::total 2488 # number of overall misses 408system.cpu.dcache.ReadReq_miss_latency::cpu.data 24823500 # number of ReadReq miss cycles 409system.cpu.dcache.ReadReq_miss_latency::total 24823500 # number of ReadReq miss cycles 410system.cpu.dcache.WriteReq_miss_latency::cpu.data 65115000 # number of WriteReq miss cycles 411system.cpu.dcache.WriteReq_miss_latency::total 65115000 # number of WriteReq miss cycles 412system.cpu.dcache.demand_miss_latency::cpu.data 89938500 # number of demand (read+write) miss cycles 413system.cpu.dcache.demand_miss_latency::total 89938500 # number of demand (read+write) miss cycles 414system.cpu.dcache.overall_miss_latency::cpu.data 89938500 # number of overall miss cycles 415system.cpu.dcache.overall_miss_latency::total 89938500 # number of overall miss cycles 416system.cpu.dcache.ReadReq_accesses::cpu.data 48128652 # number of ReadReq accesses(hits+misses) 417system.cpu.dcache.ReadReq_accesses::total 48128652 # number of ReadReq accesses(hits+misses)
| 389system.cpu.dcache.occ_blocks::cpu.data 1425.887115 # Average occupied blocks per requestor 390system.cpu.dcache.occ_percent::cpu.data 0.348117 # Average percentage of cache occupancy 391system.cpu.dcache.occ_percent::total 0.348117 # Average percentage of cache occupancy 392system.cpu.dcache.ReadReq_hits::cpu.data 48154983 # number of ReadReq hits 393system.cpu.dcache.ReadReq_hits::total 48154983 # number of ReadReq hits 394system.cpu.dcache.WriteReq_hits::cpu.data 20514026 # number of WriteReq hits 395system.cpu.dcache.WriteReq_hits::total 20514026 # number of WriteReq hits 396system.cpu.dcache.demand_hits::cpu.data 68669009 # number of demand (read+write) hits 397system.cpu.dcache.demand_hits::total 68669009 # number of demand (read+write) hits 398system.cpu.dcache.overall_hits::cpu.data 68669009 # number of overall hits 399system.cpu.dcache.overall_hits::total 68669009 # number of overall hits 400system.cpu.dcache.ReadReq_misses::cpu.data 768 # number of ReadReq misses 401system.cpu.dcache.ReadReq_misses::total 768 # number of ReadReq misses 402system.cpu.dcache.WriteReq_misses::cpu.data 1704 # number of WriteReq misses 403system.cpu.dcache.WriteReq_misses::total 1704 # number of WriteReq misses 404system.cpu.dcache.demand_misses::cpu.data 2472 # number of demand (read+write) misses 405system.cpu.dcache.demand_misses::total 2472 # number of demand (read+write) misses 406system.cpu.dcache.overall_misses::cpu.data 2472 # number of overall misses 407system.cpu.dcache.overall_misses::total 2472 # number of overall misses 408system.cpu.dcache.ReadReq_miss_latency::cpu.data 24800000 # number of ReadReq miss cycles 409system.cpu.dcache.ReadReq_miss_latency::total 24800000 # number of ReadReq miss cycles 410system.cpu.dcache.WriteReq_miss_latency::cpu.data 64672500 # number of WriteReq miss cycles 411system.cpu.dcache.WriteReq_miss_latency::total 64672500 # number of WriteReq miss cycles 412system.cpu.dcache.demand_miss_latency::cpu.data 89472500 # number of demand (read+write) miss cycles 413system.cpu.dcache.demand_miss_latency::total 89472500 # number of demand (read+write) miss cycles 414system.cpu.dcache.overall_miss_latency::cpu.data 89472500 # number of overall miss cycles 415system.cpu.dcache.overall_miss_latency::total 89472500 # number of overall miss cycles 416system.cpu.dcache.ReadReq_accesses::cpu.data 48155751 # number of ReadReq accesses(hits+misses) 417system.cpu.dcache.ReadReq_accesses::total 48155751 # number of ReadReq accesses(hits+misses)
|
418system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) 419system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses)
| 418system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) 419system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses)
|
420system.cpu.dcache.demand_accesses::cpu.data 68644382 # number of demand (read+write) accesses 421system.cpu.dcache.demand_accesses::total 68644382 # number of demand (read+write) accesses 422system.cpu.dcache.overall_accesses::cpu.data 68644382 # number of overall (read+write) accesses 423system.cpu.dcache.overall_accesses::total 68644382 # number of overall (read+write) accesses
| 420system.cpu.dcache.demand_accesses::cpu.data 68671481 # number of demand (read+write) accesses 421system.cpu.dcache.demand_accesses::total 68671481 # number of demand (read+write) accesses 422system.cpu.dcache.overall_accesses::cpu.data 68671481 # number of overall (read+write) accesses 423system.cpu.dcache.overall_accesses::total 68671481 # number of overall (read+write) accesses
|
424system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000016 # miss rate for ReadReq accesses 425system.cpu.dcache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses
| 424system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000016 # miss rate for ReadReq accesses 425system.cpu.dcache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses
|
426system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses 427system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses
| 426system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses 427system.cpu.dcache.WriteReq_miss_rate::total 0.000083 # miss rate for WriteReq accesses
|
428system.cpu.dcache.demand_miss_rate::cpu.data 0.000036 # miss rate for demand accesses 429system.cpu.dcache.demand_miss_rate::total 0.000036 # miss rate for demand accesses 430system.cpu.dcache.overall_miss_rate::cpu.data 0.000036 # miss rate for overall accesses 431system.cpu.dcache.overall_miss_rate::total 0.000036 # miss rate for overall accesses
| 428system.cpu.dcache.demand_miss_rate::cpu.data 0.000036 # miss rate for demand accesses 429system.cpu.dcache.demand_miss_rate::total 0.000036 # miss rate for demand accesses 430system.cpu.dcache.overall_miss_rate::cpu.data 0.000036 # miss rate for overall accesses 431system.cpu.dcache.overall_miss_rate::total 0.000036 # miss rate for overall accesses
|
432system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32154.792746 # average ReadReq miss latency 433system.cpu.dcache.ReadReq_avg_miss_latency::total 32154.792746 # average ReadReq miss latency 434system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37945.804196 # average WriteReq miss latency 435system.cpu.dcache.WriteReq_avg_miss_latency::total 37945.804196 # average WriteReq miss latency 436system.cpu.dcache.demand_avg_miss_latency::cpu.data 36148.914791 # average overall miss latency 437system.cpu.dcache.demand_avg_miss_latency::total 36148.914791 # average overall miss latency 438system.cpu.dcache.overall_avg_miss_latency::cpu.data 36148.914791 # average overall miss latency 439system.cpu.dcache.overall_avg_miss_latency::total 36148.914791 # average overall miss latency
| 432system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32291.666667 # average ReadReq miss latency 433system.cpu.dcache.ReadReq_avg_miss_latency::total 32291.666667 # average ReadReq miss latency 434system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37953.345070 # average WriteReq miss latency 435system.cpu.dcache.WriteReq_avg_miss_latency::total 37953.345070 # average WriteReq miss latency 436system.cpu.dcache.demand_avg_miss_latency::cpu.data 36194.377023 # average overall miss latency 437system.cpu.dcache.demand_avg_miss_latency::total 36194.377023 # average overall miss latency 438system.cpu.dcache.overall_avg_miss_latency::cpu.data 36194.377023 # average overall miss latency 439system.cpu.dcache.overall_avg_miss_latency::total 36194.377023 # average overall miss latency
|
440system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 441system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 442system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 443system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 444system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 445system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 446system.cpu.dcache.fast_writes 0 # number of fast writes performed 447system.cpu.dcache.cache_copies 0 # number of cache copies performed
| 440system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 441system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 442system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 443system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 444system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 445system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 446system.cpu.dcache.fast_writes 0 # number of fast writes performed 447system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
448system.cpu.dcache.writebacks::writebacks 13 # number of writebacks 449system.cpu.dcache.writebacks::total 13 # number of writebacks 450system.cpu.dcache.ReadReq_mshr_hits::cpu.data 331 # number of ReadReq MSHR hits 451system.cpu.dcache.ReadReq_mshr_hits::total 331 # number of ReadReq MSHR hits
| 448system.cpu.dcache.writebacks::writebacks 14 # number of writebacks 449system.cpu.dcache.writebacks::total 14 # number of writebacks 450system.cpu.dcache.ReadReq_mshr_hits::cpu.data 326 # number of ReadReq MSHR hits 451system.cpu.dcache.ReadReq_mshr_hits::total 326 # number of ReadReq MSHR hits
|
452system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3 # number of WriteReq MSHR hits 453system.cpu.dcache.WriteReq_mshr_hits::total 3 # number of WriteReq MSHR hits
| 452system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3 # number of WriteReq MSHR hits 453system.cpu.dcache.WriteReq_mshr_hits::total 3 # number of WriteReq MSHR hits
|
454system.cpu.dcache.demand_mshr_hits::cpu.data 334 # number of demand (read+write) MSHR hits 455system.cpu.dcache.demand_mshr_hits::total 334 # number of demand (read+write) MSHR hits 456system.cpu.dcache.overall_mshr_hits::cpu.data 334 # number of overall MSHR hits 457system.cpu.dcache.overall_mshr_hits::total 334 # number of overall MSHR hits 458system.cpu.dcache.ReadReq_mshr_misses::cpu.data 441 # number of ReadReq MSHR misses 459system.cpu.dcache.ReadReq_mshr_misses::total 441 # number of ReadReq MSHR misses 460system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1713 # number of WriteReq MSHR misses 461system.cpu.dcache.WriteReq_mshr_misses::total 1713 # number of WriteReq MSHR misses 462system.cpu.dcache.demand_mshr_misses::cpu.data 2154 # number of demand (read+write) MSHR misses 463system.cpu.dcache.demand_mshr_misses::total 2154 # number of demand (read+write) MSHR misses 464system.cpu.dcache.overall_mshr_misses::cpu.data 2154 # number of overall MSHR misses 465system.cpu.dcache.overall_mshr_misses::total 2154 # number of overall MSHR misses 466system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14546500 # number of ReadReq MSHR miss cycles 467system.cpu.dcache.ReadReq_mshr_miss_latency::total 14546500 # number of ReadReq MSHR miss cycles 468system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59868000 # number of WriteReq MSHR miss cycles 469system.cpu.dcache.WriteReq_mshr_miss_latency::total 59868000 # number of WriteReq MSHR miss cycles 470system.cpu.dcache.demand_mshr_miss_latency::cpu.data 74414500 # number of demand (read+write) MSHR miss cycles 471system.cpu.dcache.demand_mshr_miss_latency::total 74414500 # number of demand (read+write) MSHR miss cycles 472system.cpu.dcache.overall_mshr_miss_latency::cpu.data 74414500 # number of overall MSHR miss cycles 473system.cpu.dcache.overall_mshr_miss_latency::total 74414500 # number of overall MSHR miss cycles
| 454system.cpu.dcache.demand_mshr_hits::cpu.data 329 # number of demand (read+write) MSHR hits 455system.cpu.dcache.demand_mshr_hits::total 329 # number of demand (read+write) MSHR hits 456system.cpu.dcache.overall_mshr_hits::cpu.data 329 # number of overall MSHR hits 457system.cpu.dcache.overall_mshr_hits::total 329 # number of overall MSHR hits 458system.cpu.dcache.ReadReq_mshr_misses::cpu.data 442 # number of ReadReq MSHR misses 459system.cpu.dcache.ReadReq_mshr_misses::total 442 # number of ReadReq MSHR misses 460system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1701 # number of WriteReq MSHR misses 461system.cpu.dcache.WriteReq_mshr_misses::total 1701 # number of WriteReq MSHR misses 462system.cpu.dcache.demand_mshr_misses::cpu.data 2143 # number of demand (read+write) MSHR misses 463system.cpu.dcache.demand_mshr_misses::total 2143 # number of demand (read+write) MSHR misses 464system.cpu.dcache.overall_mshr_misses::cpu.data 2143 # number of overall MSHR misses 465system.cpu.dcache.overall_mshr_misses::total 2143 # number of overall MSHR misses 466system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14580500 # number of ReadReq MSHR miss cycles 467system.cpu.dcache.ReadReq_mshr_miss_latency::total 14580500 # number of ReadReq MSHR miss cycles 468system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59464500 # number of WriteReq MSHR miss cycles 469system.cpu.dcache.WriteReq_mshr_miss_latency::total 59464500 # number of WriteReq MSHR miss cycles 470system.cpu.dcache.demand_mshr_miss_latency::cpu.data 74045000 # number of demand (read+write) MSHR miss cycles 471system.cpu.dcache.demand_mshr_miss_latency::total 74045000 # number of demand (read+write) MSHR miss cycles 472system.cpu.dcache.overall_mshr_miss_latency::cpu.data 74045000 # number of overall MSHR miss cycles 473system.cpu.dcache.overall_mshr_miss_latency::total 74045000 # number of overall MSHR miss cycles
|
474system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses 475system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses 476system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000083 # mshr miss rate for WriteReq accesses 477system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000083 # mshr miss rate for WriteReq accesses 478system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for demand accesses 479system.cpu.dcache.demand_mshr_miss_rate::total 0.000031 # mshr miss rate for demand accesses 480system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for overall accesses 481system.cpu.dcache.overall_mshr_miss_rate::total 0.000031 # mshr miss rate for overall accesses
| 474system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses 475system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses 476system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000083 # mshr miss rate for WriteReq accesses 477system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000083 # mshr miss rate for WriteReq accesses 478system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for demand accesses 479system.cpu.dcache.demand_mshr_miss_rate::total 0.000031 # mshr miss rate for demand accesses 480system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for overall accesses 481system.cpu.dcache.overall_mshr_miss_rate::total 0.000031 # mshr miss rate for overall accesses
|
482system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32985.260771 # average ReadReq mshr miss latency 483system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32985.260771 # average ReadReq mshr miss latency 484system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34949.211909 # average WriteReq mshr miss latency 485system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34949.211909 # average WriteReq mshr miss latency 486system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34547.121634 # average overall mshr miss latency 487system.cpu.dcache.demand_avg_mshr_miss_latency::total 34547.121634 # average overall mshr miss latency 488system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34547.121634 # average overall mshr miss latency 489system.cpu.dcache.overall_avg_mshr_miss_latency::total 34547.121634 # average overall mshr miss latency
| 482system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32987.556561 # average ReadReq mshr miss latency 483system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32987.556561 # average ReadReq mshr miss latency 484system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34958.553792 # average WriteReq mshr miss latency 485system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34958.553792 # average WriteReq mshr miss latency 486system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34552.029865 # average overall mshr miss latency 487system.cpu.dcache.demand_avg_mshr_miss_latency::total 34552.029865 # average overall mshr miss latency 488system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34552.029865 # average overall mshr miss latency 489system.cpu.dcache.overall_avg_mshr_miss_latency::total 34552.029865 # average overall mshr miss latency
|
490system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 491system.cpu.l2cache.replacements 0 # number of replacements
| 490system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 491system.cpu.l2cache.replacements 0 # number of replacements
|
492system.cpu.l2cache.tagsinuse 2579.336511 # Cycle average of tags in use 493system.cpu.l2cache.total_refs 4173 # Total number of references to valid blocks. 494system.cpu.l2cache.sampled_refs 3841 # Sample count of references to valid blocks. 495system.cpu.l2cache.avg_refs 1.086436 # Average number of references to valid blocks.
| 492system.cpu.l2cache.tagsinuse 2578.525319 # Cycle average of tags in use 493system.cpu.l2cache.total_refs 4100 # Total number of references to valid blocks. 494system.cpu.l2cache.sampled_refs 3842 # Sample count of references to valid blocks. 495system.cpu.l2cache.avg_refs 1.067153 # Average number of references to valid blocks.
|
496system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 496system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
497system.cpu.l2cache.occ_blocks::writebacks 1.713269 # Average occupied blocks per requestor 498system.cpu.l2cache.occ_blocks::cpu.inst 2279.819240 # Average occupied blocks per requestor 499system.cpu.l2cache.occ_blocks::cpu.data 297.804001 # Average occupied blocks per requestor 500system.cpu.l2cache.occ_percent::writebacks 0.000052 # Average percentage of cache occupancy 501system.cpu.l2cache.occ_percent::cpu.inst 0.069575 # Average percentage of cache occupancy 502system.cpu.l2cache.occ_percent::cpu.data 0.009088 # Average percentage of cache occupancy 503system.cpu.l2cache.occ_percent::total 0.078715 # Average percentage of cache occupancy 504system.cpu.l2cache.ReadReq_hits::cpu.inst 4140 # number of ReadReq hits
| 497system.cpu.l2cache.occ_blocks::writebacks 1.139953 # Average occupied blocks per requestor 498system.cpu.l2cache.occ_blocks::cpu.inst 2280.306781 # Average occupied blocks per requestor 499system.cpu.l2cache.occ_blocks::cpu.data 297.078586 # Average occupied blocks per requestor 500system.cpu.l2cache.occ_percent::writebacks 0.000035 # Average percentage of cache occupancy 501system.cpu.l2cache.occ_percent::cpu.inst 0.069589 # Average percentage of cache occupancy 502system.cpu.l2cache.occ_percent::cpu.data 0.009066 # Average percentage of cache occupancy 503system.cpu.l2cache.occ_percent::total 0.078690 # Average percentage of cache occupancy 504system.cpu.l2cache.ReadReq_hits::cpu.inst 4066 # number of ReadReq hits
|
505system.cpu.l2cache.ReadReq_hits::cpu.data 31 # number of ReadReq hits
| 505system.cpu.l2cache.ReadReq_hits::cpu.data 31 # number of ReadReq hits
|
506system.cpu.l2cache.ReadReq_hits::total 4171 # number of ReadReq hits 507system.cpu.l2cache.Writeback_hits::writebacks 13 # number of Writeback hits 508system.cpu.l2cache.Writeback_hits::total 13 # number of Writeback hits
| 506system.cpu.l2cache.ReadReq_hits::total 4097 # number of ReadReq hits 507system.cpu.l2cache.Writeback_hits::writebacks 14 # number of Writeback hits 508system.cpu.l2cache.Writeback_hits::total 14 # number of Writeback hits
|
509system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits 510system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
| 509system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits 510system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
|
511system.cpu.l2cache.demand_hits::cpu.inst 4140 # number of demand (read+write) hits
| 511system.cpu.l2cache.demand_hits::cpu.inst 4066 # number of demand (read+write) hits
|
512system.cpu.l2cache.demand_hits::cpu.data 39 # number of demand (read+write) hits
| 512system.cpu.l2cache.demand_hits::cpu.data 39 # number of demand (read+write) hits
|
513system.cpu.l2cache.demand_hits::total 4179 # number of demand (read+write) hits 514system.cpu.l2cache.overall_hits::cpu.inst 4140 # number of overall hits
| 513system.cpu.l2cache.demand_hits::total 4105 # number of demand (read+write) hits 514system.cpu.l2cache.overall_hits::cpu.inst 4066 # number of overall hits
|
515system.cpu.l2cache.overall_hits::cpu.data 39 # number of overall hits
| 515system.cpu.l2cache.overall_hits::cpu.data 39 # number of overall hits
|
516system.cpu.l2cache.overall_hits::total 4179 # number of overall hits 517system.cpu.l2cache.ReadReq_misses::cpu.inst 3431 # number of ReadReq misses 518system.cpu.l2cache.ReadReq_misses::cpu.data 409 # number of ReadReq misses
| 516system.cpu.l2cache.overall_hits::total 4105 # number of overall hits 517system.cpu.l2cache.ReadReq_misses::cpu.inst 3430 # number of ReadReq misses 518system.cpu.l2cache.ReadReq_misses::cpu.data 410 # number of ReadReq misses
|
519system.cpu.l2cache.ReadReq_misses::total 3840 # number of ReadReq misses
| 519system.cpu.l2cache.ReadReq_misses::total 3840 # number of ReadReq misses
|
520system.cpu.l2cache.UpgradeReq_misses::cpu.data 155 # number of UpgradeReq misses 521system.cpu.l2cache.UpgradeReq_misses::total 155 # number of UpgradeReq misses
| 520system.cpu.l2cache.UpgradeReq_misses::cpu.data 143 # number of UpgradeReq misses 521system.cpu.l2cache.UpgradeReq_misses::total 143 # number of UpgradeReq misses
|
522system.cpu.l2cache.ReadExReq_misses::cpu.data 1551 # number of ReadExReq misses 523system.cpu.l2cache.ReadExReq_misses::total 1551 # number of ReadExReq misses
| 522system.cpu.l2cache.ReadExReq_misses::cpu.data 1551 # number of ReadExReq misses 523system.cpu.l2cache.ReadExReq_misses::total 1551 # number of ReadExReq misses
|
524system.cpu.l2cache.demand_misses::cpu.inst 3431 # number of demand (read+write) misses 525system.cpu.l2cache.demand_misses::cpu.data 1960 # number of demand (read+write) misses
| 524system.cpu.l2cache.demand_misses::cpu.inst 3430 # number of demand (read+write) misses 525system.cpu.l2cache.demand_misses::cpu.data 1961 # number of demand (read+write) misses
|
526system.cpu.l2cache.demand_misses::total 5391 # number of demand (read+write) misses
| 526system.cpu.l2cache.demand_misses::total 5391 # number of demand (read+write) misses
|
527system.cpu.l2cache.overall_misses::cpu.inst 3431 # number of overall misses 528system.cpu.l2cache.overall_misses::cpu.data 1960 # number of overall misses
| 527system.cpu.l2cache.overall_misses::cpu.inst 3430 # number of overall misses 528system.cpu.l2cache.overall_misses::cpu.data 1961 # number of overall misses
|
529system.cpu.l2cache.overall_misses::total 5391 # number of overall misses
| 529system.cpu.l2cache.overall_misses::total 5391 # number of overall misses
|
530system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 117518500 # number of ReadReq miss cycles 531system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13976500 # number of ReadReq miss cycles 532system.cpu.l2cache.ReadReq_miss_latency::total 131495000 # number of ReadReq miss cycles 533system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 52996000 # number of ReadExReq miss cycles 534system.cpu.l2cache.ReadExReq_miss_latency::total 52996000 # number of ReadExReq miss cycles 535system.cpu.l2cache.demand_miss_latency::cpu.inst 117518500 # number of demand (read+write) miss cycles 536system.cpu.l2cache.demand_miss_latency::cpu.data 66972500 # number of demand (read+write) miss cycles 537system.cpu.l2cache.demand_miss_latency::total 184491000 # number of demand (read+write) miss cycles 538system.cpu.l2cache.overall_miss_latency::cpu.inst 117518500 # number of overall miss cycles 539system.cpu.l2cache.overall_miss_latency::cpu.data 66972500 # number of overall miss cycles 540system.cpu.l2cache.overall_miss_latency::total 184491000 # number of overall miss cycles 541system.cpu.l2cache.ReadReq_accesses::cpu.inst 7571 # number of ReadReq accesses(hits+misses) 542system.cpu.l2cache.ReadReq_accesses::cpu.data 440 # number of ReadReq accesses(hits+misses) 543system.cpu.l2cache.ReadReq_accesses::total 8011 # number of ReadReq accesses(hits+misses) 544system.cpu.l2cache.Writeback_accesses::writebacks 13 # number of Writeback accesses(hits+misses) 545system.cpu.l2cache.Writeback_accesses::total 13 # number of Writeback accesses(hits+misses) 546system.cpu.l2cache.UpgradeReq_accesses::cpu.data 155 # number of UpgradeReq accesses(hits+misses) 547system.cpu.l2cache.UpgradeReq_accesses::total 155 # number of UpgradeReq accesses(hits+misses)
| 530system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 117492500 # number of ReadReq miss cycles 531system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14011500 # number of ReadReq miss cycles 532system.cpu.l2cache.ReadReq_miss_latency::total 131504000 # number of ReadReq miss cycles 533system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 52997000 # number of ReadExReq miss cycles 534system.cpu.l2cache.ReadExReq_miss_latency::total 52997000 # number of ReadExReq miss cycles 535system.cpu.l2cache.demand_miss_latency::cpu.inst 117492500 # number of demand (read+write) miss cycles 536system.cpu.l2cache.demand_miss_latency::cpu.data 67008500 # number of demand (read+write) miss cycles 537system.cpu.l2cache.demand_miss_latency::total 184501000 # number of demand (read+write) miss cycles 538system.cpu.l2cache.overall_miss_latency::cpu.inst 117492500 # number of overall miss cycles 539system.cpu.l2cache.overall_miss_latency::cpu.data 67008500 # number of overall miss cycles 540system.cpu.l2cache.overall_miss_latency::total 184501000 # number of overall miss cycles 541system.cpu.l2cache.ReadReq_accesses::cpu.inst 7496 # number of ReadReq accesses(hits+misses) 542system.cpu.l2cache.ReadReq_accesses::cpu.data 441 # number of ReadReq accesses(hits+misses) 543system.cpu.l2cache.ReadReq_accesses::total 7937 # number of ReadReq accesses(hits+misses) 544system.cpu.l2cache.Writeback_accesses::writebacks 14 # number of Writeback accesses(hits+misses) 545system.cpu.l2cache.Writeback_accesses::total 14 # number of Writeback accesses(hits+misses) 546system.cpu.l2cache.UpgradeReq_accesses::cpu.data 143 # number of UpgradeReq accesses(hits+misses) 547system.cpu.l2cache.UpgradeReq_accesses::total 143 # number of UpgradeReq accesses(hits+misses)
|
548system.cpu.l2cache.ReadExReq_accesses::cpu.data 1559 # number of ReadExReq accesses(hits+misses) 549system.cpu.l2cache.ReadExReq_accesses::total 1559 # number of ReadExReq accesses(hits+misses)
| 548system.cpu.l2cache.ReadExReq_accesses::cpu.data 1559 # number of ReadExReq accesses(hits+misses) 549system.cpu.l2cache.ReadExReq_accesses::total 1559 # number of ReadExReq accesses(hits+misses)
|
550system.cpu.l2cache.demand_accesses::cpu.inst 7571 # number of demand (read+write) accesses 551system.cpu.l2cache.demand_accesses::cpu.data 1999 # number of demand (read+write) accesses 552system.cpu.l2cache.demand_accesses::total 9570 # number of demand (read+write) accesses 553system.cpu.l2cache.overall_accesses::cpu.inst 7571 # number of overall (read+write) accesses 554system.cpu.l2cache.overall_accesses::cpu.data 1999 # number of overall (read+write) accesses 555system.cpu.l2cache.overall_accesses::total 9570 # number of overall (read+write) accesses 556system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.453177 # miss rate for ReadReq accesses 557system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.929545 # miss rate for ReadReq accesses 558system.cpu.l2cache.ReadReq_miss_rate::total 0.479341 # miss rate for ReadReq accesses
| 550system.cpu.l2cache.demand_accesses::cpu.inst 7496 # number of demand (read+write) accesses 551system.cpu.l2cache.demand_accesses::cpu.data 2000 # number of demand (read+write) accesses 552system.cpu.l2cache.demand_accesses::total 9496 # number of demand (read+write) accesses 553system.cpu.l2cache.overall_accesses::cpu.inst 7496 # number of overall (read+write) accesses 554system.cpu.l2cache.overall_accesses::cpu.data 2000 # number of overall (read+write) accesses 555system.cpu.l2cache.overall_accesses::total 9496 # number of overall (read+write) accesses 556system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.457577 # miss rate for ReadReq accesses 557system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.929705 # miss rate for ReadReq accesses 558system.cpu.l2cache.ReadReq_miss_rate::total 0.483810 # miss rate for ReadReq accesses
|
559system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 560system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 561system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994869 # miss rate for ReadExReq accesses 562system.cpu.l2cache.ReadExReq_miss_rate::total 0.994869 # miss rate for ReadExReq accesses
| 559system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 560system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 561system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994869 # miss rate for ReadExReq accesses 562system.cpu.l2cache.ReadExReq_miss_rate::total 0.994869 # miss rate for ReadExReq accesses
|
563system.cpu.l2cache.demand_miss_rate::cpu.inst 0.453177 # miss rate for demand accesses 564system.cpu.l2cache.demand_miss_rate::cpu.data 0.980490 # miss rate for demand accesses 565system.cpu.l2cache.demand_miss_rate::total 0.563323 # miss rate for demand accesses 566system.cpu.l2cache.overall_miss_rate::cpu.inst 0.453177 # miss rate for overall accesses 567system.cpu.l2cache.overall_miss_rate::cpu.data 0.980490 # miss rate for overall accesses 568system.cpu.l2cache.overall_miss_rate::total 0.563323 # miss rate for overall accesses 569system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34251.967356 # average ReadReq miss latency 570system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34172.371638 # average ReadReq miss latency 571system.cpu.l2cache.ReadReq_avg_miss_latency::total 34243.489583 # average ReadReq miss latency 572system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34168.923275 # average ReadExReq miss latency 573system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34168.923275 # average ReadExReq miss latency 574system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34251.967356 # average overall miss latency 575system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34169.642857 # average overall miss latency 576system.cpu.l2cache.demand_avg_miss_latency::total 34222.036728 # average overall miss latency 577system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34251.967356 # average overall miss latency 578system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34169.642857 # average overall miss latency 579system.cpu.l2cache.overall_avg_miss_latency::total 34222.036728 # average overall miss latency
| 563system.cpu.l2cache.demand_miss_rate::cpu.inst 0.457577 # miss rate for demand accesses 564system.cpu.l2cache.demand_miss_rate::cpu.data 0.980500 # miss rate for demand accesses 565system.cpu.l2cache.demand_miss_rate::total 0.567713 # miss rate for demand accesses 566system.cpu.l2cache.overall_miss_rate::cpu.inst 0.457577 # miss rate for overall accesses 567system.cpu.l2cache.overall_miss_rate::cpu.data 0.980500 # miss rate for overall accesses 568system.cpu.l2cache.overall_miss_rate::total 0.567713 # miss rate for overall accesses 569system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34254.373178 # average ReadReq miss latency 570system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34174.390244 # average ReadReq miss latency 571system.cpu.l2cache.ReadReq_avg_miss_latency::total 34245.833333 # average ReadReq miss latency 572system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34169.568021 # average ReadExReq miss latency 573system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34169.568021 # average ReadExReq miss latency 574system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34254.373178 # average overall miss latency 575system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34170.576237 # average overall miss latency 576system.cpu.l2cache.demand_avg_miss_latency::total 34223.891671 # average overall miss latency 577system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34254.373178 # average overall miss latency 578system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34170.576237 # average overall miss latency 579system.cpu.l2cache.overall_avg_miss_latency::total 34223.891671 # average overall miss latency
|
580system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 581system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 582system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 583system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 584system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 585system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 586system.cpu.l2cache.fast_writes 0 # number of fast writes performed 587system.cpu.l2cache.cache_copies 0 # number of cache copies performed
| 580system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 581system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 582system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 583system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 584system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 585system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 586system.cpu.l2cache.fast_writes 0 # number of fast writes performed 587system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
588system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3431 # number of ReadReq MSHR misses 589system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 409 # number of ReadReq MSHR misses
| 588system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3430 # number of ReadReq MSHR misses 589system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 410 # number of ReadReq MSHR misses
|
590system.cpu.l2cache.ReadReq_mshr_misses::total 3840 # number of ReadReq MSHR misses
| 590system.cpu.l2cache.ReadReq_mshr_misses::total 3840 # number of ReadReq MSHR misses
|
591system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 155 # number of UpgradeReq MSHR misses 592system.cpu.l2cache.UpgradeReq_mshr_misses::total 155 # number of UpgradeReq MSHR misses
| 591system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 143 # number of UpgradeReq MSHR misses 592system.cpu.l2cache.UpgradeReq_mshr_misses::total 143 # number of UpgradeReq MSHR misses
|
593system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1551 # number of ReadExReq MSHR misses 594system.cpu.l2cache.ReadExReq_mshr_misses::total 1551 # number of ReadExReq MSHR misses
| 593system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1551 # number of ReadExReq MSHR misses 594system.cpu.l2cache.ReadExReq_mshr_misses::total 1551 # number of ReadExReq MSHR misses
|
595system.cpu.l2cache.demand_mshr_misses::cpu.inst 3431 # number of demand (read+write) MSHR misses 596system.cpu.l2cache.demand_mshr_misses::cpu.data 1960 # number of demand (read+write) MSHR misses
| 595system.cpu.l2cache.demand_mshr_misses::cpu.inst 3430 # number of demand (read+write) MSHR misses 596system.cpu.l2cache.demand_mshr_misses::cpu.data 1961 # number of demand (read+write) MSHR misses
|
597system.cpu.l2cache.demand_mshr_misses::total 5391 # number of demand (read+write) MSHR misses
| 597system.cpu.l2cache.demand_mshr_misses::total 5391 # number of demand (read+write) MSHR misses
|
598system.cpu.l2cache.overall_mshr_misses::cpu.inst 3431 # number of overall MSHR misses 599system.cpu.l2cache.overall_mshr_misses::cpu.data 1960 # number of overall MSHR misses
| 598system.cpu.l2cache.overall_mshr_misses::cpu.inst 3430 # number of overall MSHR misses 599system.cpu.l2cache.overall_mshr_misses::cpu.data 1961 # number of overall MSHR misses
|
600system.cpu.l2cache.overall_mshr_misses::total 5391 # number of overall MSHR misses
| 600system.cpu.l2cache.overall_mshr_misses::total 5391 # number of overall MSHR misses
|
601system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106440500 # number of ReadReq MSHR miss cycles 602system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12676500 # number of ReadReq MSHR miss cycles 603system.cpu.l2cache.ReadReq_mshr_miss_latency::total 119117000 # number of ReadReq MSHR miss cycles 604system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4805000 # number of UpgradeReq MSHR miss cycles 605system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4805000 # number of UpgradeReq MSHR miss cycles
| 601system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106414500 # number of ReadReq MSHR miss cycles 602system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12709500 # number of ReadReq MSHR miss cycles 603system.cpu.l2cache.ReadReq_mshr_miss_latency::total 119124000 # number of ReadReq MSHR miss cycles 604system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4433000 # number of UpgradeReq MSHR miss cycles 605system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4433000 # number of UpgradeReq MSHR miss cycles
|
606system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48110500 # number of ReadExReq MSHR miss cycles 607system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48110500 # number of ReadExReq MSHR miss cycles
| 606system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48110500 # number of ReadExReq MSHR miss cycles 607system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48110500 # number of ReadExReq MSHR miss cycles
|
608system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106440500 # number of demand (read+write) MSHR miss cycles 609system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 60787000 # number of demand (read+write) MSHR miss cycles 610system.cpu.l2cache.demand_mshr_miss_latency::total 167227500 # number of demand (read+write) MSHR miss cycles 611system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106440500 # number of overall MSHR miss cycles 612system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 60787000 # number of overall MSHR miss cycles 613system.cpu.l2cache.overall_mshr_miss_latency::total 167227500 # number of overall MSHR miss cycles 614system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for ReadReq accesses 615system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.929545 # mshr miss rate for ReadReq accesses 616system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.479341 # mshr miss rate for ReadReq accesses
| 608system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106414500 # number of demand (read+write) MSHR miss cycles 609system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 60820000 # number of demand (read+write) MSHR miss cycles 610system.cpu.l2cache.demand_mshr_miss_latency::total 167234500 # number of demand (read+write) MSHR miss cycles 611system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106414500 # number of overall MSHR miss cycles 612system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 60820000 # number of overall MSHR miss cycles 613system.cpu.l2cache.overall_mshr_miss_latency::total 167234500 # number of overall MSHR miss cycles 614system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.457577 # mshr miss rate for ReadReq accesses 615system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.929705 # mshr miss rate for ReadReq accesses 616system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.483810 # mshr miss rate for ReadReq accesses
|
617system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 618system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 619system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994869 # mshr miss rate for ReadExReq accesses 620system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994869 # mshr miss rate for ReadExReq accesses
| 617system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 618system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 619system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994869 # mshr miss rate for ReadExReq accesses 620system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994869 # mshr miss rate for ReadExReq accesses
|
621system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for demand accesses 622system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980490 # mshr miss rate for demand accesses 623system.cpu.l2cache.demand_mshr_miss_rate::total 0.563323 # mshr miss rate for demand accesses 624system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for overall accesses 625system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980490 # mshr miss rate for overall accesses 626system.cpu.l2cache.overall_mshr_miss_rate::total 0.563323 # mshr miss rate for overall accesses 627system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31023.171087 # average ReadReq mshr miss latency 628system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30993.887531 # average ReadReq mshr miss latency 629system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31020.052083 # average ReadReq mshr miss latency
| 621system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.457577 # mshr miss rate for demand accesses 622system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980500 # mshr miss rate for demand accesses 623system.cpu.l2cache.demand_mshr_miss_rate::total 0.567713 # mshr miss rate for demand accesses 624system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.457577 # mshr miss rate for overall accesses 625system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980500 # mshr miss rate for overall accesses 626system.cpu.l2cache.overall_mshr_miss_rate::total 0.567713 # mshr miss rate for overall accesses 627system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31024.635569 # average ReadReq mshr miss latency 628system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30998.780488 # average ReadReq mshr miss latency 629system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31021.875000 # average ReadReq mshr miss latency
|
630system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency 631system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency 632system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31019.019987 # average ReadExReq mshr miss latency 633system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31019.019987 # average ReadExReq mshr miss latency
| 630system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency 631system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency 632system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31019.019987 # average ReadExReq mshr miss latency 633system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31019.019987 # average ReadExReq mshr miss latency
|
634system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31023.171087 # average overall mshr miss latency 635system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31013.775510 # average overall mshr miss latency 636system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31019.755147 # average overall mshr miss latency 637system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31023.171087 # average overall mshr miss latency 638system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31013.775510 # average overall mshr miss latency 639system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31019.755147 # average overall mshr miss latency
| 634system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31024.635569 # average overall mshr miss latency 635system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31014.788373 # average overall mshr miss latency 636system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31021.053608 # average overall mshr miss latency 637system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31024.635569 # average overall mshr miss latency 638system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31014.788373 # average overall mshr miss latency 639system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31021.053608 # average overall mshr miss latency
|
640system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 641 642---------- End Simulation Statistics ----------
| 640system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 641 642---------- End Simulation Statistics ----------
|