| stats.txt (8844:a451e4eda591) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.087728 # Number of seconds simulated 4sim_ticks 87727531000 # Number of ticks simulated 5final_tick 87727531000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.087728 # Number of seconds simulated 4sim_ticks 87727531000 # Number of ticks simulated 5final_tick 87727531000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 101058 # Simulator instruction rate (inst/s) 8host_op_rate 169383 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 67127344 # Simulator tick rate (ticks/s) 10host_mem_usage 229892 # Number of bytes of host memory used 11host_seconds 1306.88 # Real time elapsed on the host | 7host_inst_rate 36137 # Simulator instruction rate (inst/s) 8host_op_rate 60569 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 24003841 # Simulator tick rate (ticks/s) 10host_mem_usage 234992 # Number of bytes of host memory used 11host_seconds 3654.73 # Real time elapsed on the host |
| 12sim_insts 132071227 # Number of instructions simulated 13sim_ops 221363017 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 345792 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 220224 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 5403 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 306 unchanged lines hidden (view full) --- 326system.cpu.icache.overall_miss_rate::cpu.inst 0.000352 # miss rate for overall accesses 327system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20670.001099 # average ReadReq miss latency 328system.cpu.icache.demand_avg_miss_latency::cpu.inst 20670.001099 # average overall miss latency 329system.cpu.icache.overall_avg_miss_latency::cpu.inst 20670.001099 # average overall miss latency 330system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 331system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 332system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 333system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 132071227 # Number of instructions simulated 13sim_ops 221363017 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 345792 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 220224 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 5403 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 306 unchanged lines hidden (view full) --- 326system.cpu.icache.overall_miss_rate::cpu.inst 0.000352 # miss rate for overall accesses 327system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20670.001099 # average ReadReq miss latency 328system.cpu.icache.demand_avg_miss_latency::cpu.inst 20670.001099 # average overall miss latency 329system.cpu.icache.overall_avg_miss_latency::cpu.inst 20670.001099 # average overall miss latency 330system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 331system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 332system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 333system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 334system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 335system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 334system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 335system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 336system.cpu.icache.fast_writes 0 # number of fast writes performed 337system.cpu.icache.cache_copies 0 # number of cache copies performed 338system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1378 # number of ReadReq MSHR hits 339system.cpu.icache.ReadReq_mshr_hits::total 1378 # number of ReadReq MSHR hits 340system.cpu.icache.demand_mshr_hits::cpu.inst 1378 # number of demand (read+write) MSHR hits 341system.cpu.icache.demand_mshr_hits::total 1378 # number of demand (read+write) MSHR hits 342system.cpu.icache.overall_mshr_hits::cpu.inst 1378 # number of overall MSHR hits 343system.cpu.icache.overall_mshr_hits::total 1378 # number of overall MSHR hits --- 64 unchanged lines hidden (view full) --- 408system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32168.627451 # average ReadReq miss latency 409system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37937.024019 # average WriteReq miss latency 410system.cpu.dcache.demand_avg_miss_latency::cpu.data 36151.901294 # average overall miss latency 411system.cpu.dcache.overall_avg_miss_latency::cpu.data 36151.901294 # average overall miss latency 412system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 413system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 414system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 415system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 336system.cpu.icache.fast_writes 0 # number of fast writes performed 337system.cpu.icache.cache_copies 0 # number of cache copies performed 338system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1378 # number of ReadReq MSHR hits 339system.cpu.icache.ReadReq_mshr_hits::total 1378 # number of ReadReq MSHR hits 340system.cpu.icache.demand_mshr_hits::cpu.inst 1378 # number of demand (read+write) MSHR hits 341system.cpu.icache.demand_mshr_hits::total 1378 # number of demand (read+write) MSHR hits 342system.cpu.icache.overall_mshr_hits::cpu.inst 1378 # number of overall MSHR hits 343system.cpu.icache.overall_mshr_hits::total 1378 # number of overall MSHR hits --- 64 unchanged lines hidden (view full) --- 408system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32168.627451 # average ReadReq miss latency 409system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37937.024019 # average WriteReq miss latency 410system.cpu.dcache.demand_avg_miss_latency::cpu.data 36151.901294 # average overall miss latency 411system.cpu.dcache.overall_avg_miss_latency::cpu.data 36151.901294 # average overall miss latency 412system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 413system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 414system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 415system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 416system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 417system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 416system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 417system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 418system.cpu.dcache.fast_writes 0 # number of fast writes performed 419system.cpu.dcache.cache_copies 0 # number of cache copies performed 420system.cpu.dcache.writebacks::writebacks 13 # number of writebacks 421system.cpu.dcache.writebacks::total 13 # number of writebacks 422system.cpu.dcache.ReadReq_mshr_hits::cpu.data 323 # number of ReadReq MSHR hits 423system.cpu.dcache.ReadReq_mshr_hits::total 323 # number of ReadReq MSHR hits 424system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3 # number of WriteReq MSHR hits 425system.cpu.dcache.WriteReq_mshr_hits::total 3 # number of WriteReq MSHR hits --- 105 unchanged lines hidden (view full) --- 531system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34254.577158 # average overall miss latency 532system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34163.863405 # average overall miss latency 533system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34254.577158 # average overall miss latency 534system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34163.863405 # average overall miss latency 535system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 536system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 537system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 538system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 418system.cpu.dcache.fast_writes 0 # number of fast writes performed 419system.cpu.dcache.cache_copies 0 # number of cache copies performed 420system.cpu.dcache.writebacks::writebacks 13 # number of writebacks 421system.cpu.dcache.writebacks::total 13 # number of writebacks 422system.cpu.dcache.ReadReq_mshr_hits::cpu.data 323 # number of ReadReq MSHR hits 423system.cpu.dcache.ReadReq_mshr_hits::total 323 # number of ReadReq MSHR hits 424system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3 # number of WriteReq MSHR hits 425system.cpu.dcache.WriteReq_mshr_hits::total 3 # number of WriteReq MSHR hits --- 105 unchanged lines hidden (view full) --- 531system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34254.577158 # average overall miss latency 532system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34163.863405 # average overall miss latency 533system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34254.577158 # average overall miss latency 534system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34163.863405 # average overall miss latency 535system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 536system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 537system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 538system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 539system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 540system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 539system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 540system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 541system.cpu.l2cache.fast_writes 0 # number of fast writes performed 542system.cpu.l2cache.cache_copies 0 # number of cache copies performed 543system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3441 # number of ReadReq MSHR misses 544system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 411 # number of ReadReq MSHR misses 545system.cpu.l2cache.ReadReq_mshr_misses::total 3852 # number of ReadReq MSHR misses 546system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 146 # number of UpgradeReq MSHR misses 547system.cpu.l2cache.UpgradeReq_mshr_misses::total 146 # number of UpgradeReq MSHR misses 548system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1551 # number of ReadExReq MSHR misses --- 39 unchanged lines hidden --- | 541system.cpu.l2cache.fast_writes 0 # number of fast writes performed 542system.cpu.l2cache.cache_copies 0 # number of cache copies performed 543system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3441 # number of ReadReq MSHR misses 544system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 411 # number of ReadReq MSHR misses 545system.cpu.l2cache.ReadReq_mshr_misses::total 3852 # number of ReadReq MSHR misses 546system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 146 # number of UpgradeReq MSHR misses 547system.cpu.l2cache.UpgradeReq_mshr_misses::total 146 # number of UpgradeReq MSHR misses 548system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1551 # number of ReadExReq MSHR misses --- 39 unchanged lines hidden --- |