Cross Reference: /gem5/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 0.096266 # Number of seconds simulated
4sim_ticks 96266258000 # Number of ticks simulated
5final_tick 96266258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 0.087728 # Number of seconds simulated
4sim_ticks 87727531000 # Number of ticks simulated
5final_tick 87727531000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 89516 # Simulator instruction rate (inst/s)
8host_op_rate 150037 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 65247901 # Simulator tick rate (ticks/s)
10host_mem_usage 229524 # Number of bytes of host memory used
11host_seconds 1475.39 # Real time elapsed on the host

7host_inst_rate 101058 # Simulator instruction rate (inst/s)
8host_op_rate 169383 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 67127344 # Simulator tick rate (ticks/s)
10host_mem_usage 229892 # Number of bytes of host memory used
11host_seconds 1306.88 # Real time elapsed on the host

12sim_insts 132071227 # Number of instructions simulated
13sim_ops 221363017 # Number of ops (including micro ops) simulated

14system.physmem.bytes_read 339712 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 214912 # Number of instructions bytes read from this memory

14system.physmem.bytes_read 345792 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 220224 # Number of instructions bytes read from this memory

16system.physmem.bytes_written 0 # Number of bytes written to this memory

17system.physmem.num_reads 5308 # Number of read requests responded to by this memory

17system.physmem.num_reads 5403 # Number of read requests responded to by this memory

18system.physmem.num_writes 0 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory

20system.physmem.bw_read 3528879 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 2232475 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_total 3528879 # Total bandwidth to/from this memory (bytes/s)

20system.physmem.bw_read 3941659 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 2510318 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_total 3941659 # Total bandwidth to/from this memory (bytes/s)

23system.cpu.workload.num_syscalls 400 # Number of system calls

24system.cpu.numCycles 192532517 # number of cpu cycles simulated

24system.cpu.numCycles 175455063 # number of cpu cycles simulated

25system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
26system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed

27system.cpu.BPredUnit.lookups 25728486 # Number of BP lookups
28system.cpu.BPredUnit.condPredicted 25728486 # Number of conditional branches predicted
29system.cpu.BPredUnit.condIncorrect 2892788 # Number of conditional branches incorrect
30system.cpu.BPredUnit.BTBLookups 23533152 # Number of BTB lookups
31system.cpu.BPredUnit.BTBHits 20839978 # Number of BTB hits

27system.cpu.BPredUnit.lookups 20916443 # Number of BP lookups
28system.cpu.BPredUnit.condPredicted 20916443 # Number of conditional branches predicted
29system.cpu.BPredUnit.condIncorrect 2209285 # Number of conditional branches incorrect
30system.cpu.BPredUnit.BTBLookups 15543482 # Number of BTB lookups
31system.cpu.BPredUnit.BTBHits 13847483 # Number of BTB hits

32system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
33system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
34system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.

35system.cpu.fetch.icacheStallCycles 30657479 # Number of cycles fetch is stalled on an Icache miss
36system.cpu.fetch.Insts 260466955 # Number of instructions fetch has processed
37system.cpu.fetch.Branches 25728486 # Number of branches that fetch encountered
38system.cpu.fetch.predictedBranches 20839978 # Number of branches that fetch has predicted taken
39system.cpu.fetch.Cycles 70644215 # Number of cycles fetch has run and was not squashing or blocked
40system.cpu.fetch.SquashCycles 26785814 # Number of cycles fetch has spent squashing
41system.cpu.fetch.BlockedCycles 67566342 # Number of cycles fetch has spent blocked
42system.cpu.fetch.MiscStallCycles 136 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
43system.cpu.fetch.PendingTrapStallCycles 1120 # Number of stall cycles due to pending traps
44system.cpu.fetch.CacheLines 28758661 # Number of cache lines fetched
45system.cpu.fetch.IcacheSquashes 555177 # Number of outstanding Icache misses that were squashed
46system.cpu.fetch.rateDist::samples 192452166 # Number of instructions fetched each cycle (Total)
47system.cpu.fetch.rateDist::mean 2.262310 # Number of instructions fetched each cycle (Total)
48system.cpu.fetch.rateDist::stdev 3.335029 # Number of instructions fetched each cycle (Total)

35system.cpu.fetch.icacheStallCycles 27331578 # Number of cycles fetch is stalled on an Icache miss
36system.cpu.fetch.Insts 227091825 # Number of instructions fetch has processed
37system.cpu.fetch.Branches 20916443 # Number of branches that fetch encountered
38system.cpu.fetch.predictedBranches 13847483 # Number of branches that fetch has predicted taken
39system.cpu.fetch.Cycles 59872682 # Number of cycles fetch has run and was not squashing or blocked
40system.cpu.fetch.SquashCycles 19479342 # Number of cycles fetch has spent squashing
41system.cpu.fetch.BlockedCycles 71171142 # Number of cycles fetch has spent blocked
42system.cpu.fetch.MiscStallCycles 1142 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
43system.cpu.fetch.PendingTrapStallCycles 9711 # Number of stall cycles due to pending traps
44system.cpu.fetch.CacheLines 25826236 # Number of cache lines fetched
45system.cpu.fetch.IcacheSquashes 465691 # Number of outstanding Icache misses that were squashed
46system.cpu.fetch.rateDist::samples 175377754 # Number of instructions fetched each cycle (Total)
47system.cpu.fetch.rateDist::mean 2.138493 # Number of instructions fetched each cycle (Total)
48system.cpu.fetch.rateDist::stdev 3.301400 # Number of instructions fetched each cycle (Total)

49system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

50system.cpu.fetch.rateDist::0 123644733 64.25% 64.25% # Number of instructions fetched each cycle (Total)
51system.cpu.fetch.rateDist::1 4091160 2.13% 66.37% # Number of instructions fetched each cycle (Total)
52system.cpu.fetch.rateDist::2 3200074 1.66% 68.04% # Number of instructions fetched each cycle (Total)
53system.cpu.fetch.rateDist::3 4567374 2.37% 70.41% # Number of instructions fetched each cycle (Total)
54system.cpu.fetch.rateDist::4 4265123 2.22% 72.63% # Number of instructions fetched each cycle (Total)
55system.cpu.fetch.rateDist::5 4442159 2.31% 74.93% # Number of instructions fetched each cycle (Total)
56system.cpu.fetch.rateDist::6 5459285 2.84% 77.77% # Number of instructions fetched each cycle (Total)
57system.cpu.fetch.rateDist::7 3091960 1.61% 79.38% # Number of instructions fetched each cycle (Total)
58system.cpu.fetch.rateDist::8 39690298 20.62% 100.00% # Number of instructions fetched each cycle (Total)

50system.cpu.fetch.rateDist::0 117181647 66.82% 66.82% # Number of instructions fetched each cycle (Total)
51system.cpu.fetch.rateDist::1 3214918 1.83% 68.65% # Number of instructions fetched each cycle (Total)
52system.cpu.fetch.rateDist::2 2487615 1.42% 70.07% # Number of instructions fetched each cycle (Total)
53system.cpu.fetch.rateDist::3 3152390 1.80% 71.87% # Number of instructions fetched each cycle (Total)
54system.cpu.fetch.rateDist::4 3541045 2.02% 73.88% # Number of instructions fetched each cycle (Total)
55system.cpu.fetch.rateDist::5 3761465 2.14% 76.03% # Number of instructions fetched each cycle (Total)
56system.cpu.fetch.rateDist::6 4534795 2.59% 78.62% # Number of instructions fetched each cycle (Total)
57system.cpu.fetch.rateDist::7 2814480 1.60% 80.22% # Number of instructions fetched each cycle (Total)
58system.cpu.fetch.rateDist::8 34689399 19.78% 100.00% # Number of instructions fetched each cycle (Total)

59system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
60system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
61system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

62system.cpu.fetch.rateDist::total 192452166 # Number of instructions fetched each cycle (Total)
63system.cpu.fetch.branchRate 0.133632 # Number of branch fetches per cycle
64system.cpu.fetch.rate 1.352847 # Number of inst fetches per cycle
65system.cpu.decode.IdleCycles 44411978 # Number of cycles decode is idle
66system.cpu.decode.BlockedCycles 57625858 # Number of cycles decode is blocked
67system.cpu.decode.RunCycles 56973408 # Number of cycles decode is running
68system.cpu.decode.UnblockCycles 9858048 # Number of cycles decode is unblocking
69system.cpu.decode.SquashCycles 23582874 # Number of cycles decode is squashing
70system.cpu.decode.DecodedInsts 423042956 # Number of instructions handled by decode
71system.cpu.rename.SquashCycles 23582874 # Number of cycles rename is squashing
72system.cpu.rename.IdleCycles 52998252 # Number of cycles rename is idle
73system.cpu.rename.BlockCycles 14705836 # Number of cycles rename is blocking
74system.cpu.rename.serializeStallCycles 23082 # count of cycles rename stalled for serializing inst
75system.cpu.rename.RunCycles 57546904 # Number of cycles rename is running
76system.cpu.rename.UnblockCycles 43595218 # Number of cycles rename is unblocking
77system.cpu.rename.RenamedInsts 410638323 # Number of instructions processed by rename
78system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full
79system.cpu.rename.IQFullEvents 18885984 # Number of times rename has blocked due to IQ full
80system.cpu.rename.LSQFullEvents 22330558 # Number of times rename has blocked due to LSQ full
81system.cpu.rename.RenamedOperands 437009036 # Number of destination operands rename has renamed
82system.cpu.rename.RenameLookups 1063910767 # Number of register rename lookups that rename has made
83system.cpu.rename.int_rename_lookups 1053088723 # Number of integer rename lookups
84system.cpu.rename.fp_rename_lookups 10822044 # Number of floating rename lookups

62system.cpu.fetch.rateDist::total 175377754 # Number of instructions fetched each cycle (Total)
63system.cpu.fetch.branchRate 0.119213 # Number of branch fetches per cycle
64system.cpu.fetch.rate 1.294302 # Number of inst fetches per cycle
65system.cpu.decode.IdleCycles 40655078 # Number of cycles decode is idle
66system.cpu.decode.BlockedCycles 60979767 # Number of cycles decode is blocked
67system.cpu.decode.RunCycles 46580847 # Number of cycles decode is running
68system.cpu.decode.UnblockCycles 10170563 # Number of cycles decode is unblocking
69system.cpu.decode.SquashCycles 16991499 # Number of cycles decode is squashing
70system.cpu.decode.DecodedInsts 366154541 # Number of instructions handled by decode
71system.cpu.rename.SquashCycles 16991499 # Number of cycles rename is squashing
72system.cpu.rename.IdleCycles 48551575 # Number of cycles rename is idle
73system.cpu.rename.BlockCycles 16255360 # Number of cycles rename is blocking
74system.cpu.rename.serializeStallCycles 22908 # count of cycles rename stalled for serializing inst
75system.cpu.rename.RunCycles 48159937 # Number of cycles rename is running
76system.cpu.rename.UnblockCycles 45396475 # Number of cycles rename is unblocking
77system.cpu.rename.RenamedInsts 356930622 # Number of instructions processed by rename
78system.cpu.rename.ROBFullEvents 31 # Number of times rename has blocked due to ROB full
79system.cpu.rename.IQFullEvents 20611614 # Number of times rename has blocked due to IQ full
80system.cpu.rename.LSQFullEvents 22556100 # Number of times rename has blocked due to LSQ full
81system.cpu.rename.RenamedOperands 370578330 # Number of destination operands rename has renamed
82system.cpu.rename.RenameLookups 915376002 # Number of register rename lookups that rename has made
83system.cpu.rename.int_rename_lookups 905357204 # Number of integer rename lookups
84system.cpu.rename.fp_rename_lookups 10018798 # Number of floating rename lookups

85system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed

86system.cpu.rename.UndoneMaps 202645627 # Number of HB maps that are undone due to squashing
87system.cpu.rename.serializingInsts 1783 # count of serializing insts renamed
88system.cpu.rename.tempSerializingInsts 1777 # count of temporary serializing insts renamed
89system.cpu.rename.skidInsts 94569707 # count of insts added to the skid buffer
90system.cpu.memDep0.insertedLoads 103994638 # Number of loads inserted to the mem dependence unit.
91system.cpu.memDep0.insertedStores 37171273 # Number of stores inserted to the mem dependence unit.
92system.cpu.memDep0.conflictingLoads 66711674 # Number of conflicting loads.
93system.cpu.memDep0.conflictingStores 21456392 # Number of conflicting stores.
94system.cpu.iq.iqInstsAdded 395555693 # Number of instructions added to the IQ (excludes non-spec)
95system.cpu.iq.iqNonSpecInstsAdded 2683 # Number of non-speculative instructions added to the IQ
96system.cpu.iq.iqInstsIssued 287296212 # Number of instructions issued
97system.cpu.iq.iqSquashedInstsIssued 238230 # Number of squashed instructions issued
98system.cpu.iq.iqSquashedInstsExamined 173600960 # Number of squashed instructions iterated over during squash; mainly for profiling
99system.cpu.iq.iqSquashedOperandsExamined 348497721 # Number of squashed operands that are examined and possibly removed from graph
100system.cpu.iq.iqSquashedNonSpecRemoved 1437 # Number of squashed non-spec instructions that were removed
101system.cpu.iq.issued_per_cycle::samples 192452166 # Number of insts issued each cycle
102system.cpu.iq.issued_per_cycle::mean 1.492819 # Number of insts issued each cycle
103system.cpu.iq.issued_per_cycle::stdev 1.482262 # Number of insts issued each cycle

86system.cpu.rename.UndoneMaps 136214921 # Number of HB maps that are undone due to squashing
87system.cpu.rename.serializingInsts 1884 # count of serializing insts renamed
88system.cpu.rename.tempSerializingInsts 1879 # count of temporary serializing insts renamed
89system.cpu.rename.skidInsts 95075204 # count of insts added to the skid buffer
90system.cpu.memDep0.insertedLoads 89798900 # Number of loads inserted to the mem dependence unit.
91system.cpu.memDep0.insertedStores 33126150 # Number of stores inserted to the mem dependence unit.
92system.cpu.memDep0.conflictingLoads 59105892 # Number of conflicting loads.
93system.cpu.memDep0.conflictingStores 19470251 # Number of conflicting stores.
94system.cpu.iq.iqInstsAdded 344622515 # Number of instructions added to the IQ (excludes non-spec)
95system.cpu.iq.iqNonSpecInstsAdded 7679 # Number of non-speculative instructions added to the IQ
96system.cpu.iq.iqInstsIssued 271009025 # Number of instructions issued
97system.cpu.iq.iqSquashedInstsIssued 252543 # Number of squashed instructions issued
98system.cpu.iq.iqSquashedInstsExamined 122771831 # Number of squashed instructions iterated over during squash; mainly for profiling
99system.cpu.iq.iqSquashedOperandsExamined 234148079 # Number of squashed operands that are examined and possibly removed from graph
100system.cpu.iq.iqSquashedNonSpecRemoved 6433 # Number of squashed non-spec instructions that were removed
101system.cpu.iq.issued_per_cycle::samples 175377754 # Number of insts issued each cycle
102system.cpu.iq.issued_per_cycle::mean 1.545287 # Number of insts issued each cycle
103system.cpu.iq.issued_per_cycle::stdev 1.468253 # Number of insts issued each cycle

104system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

105system.cpu.iq.issued_per_cycle::0 60170871 31.27% 31.27% # Number of insts issued each cycle
106system.cpu.iq.issued_per_cycle::1 53695201 27.90% 59.17% # Number of insts issued each cycle
107system.cpu.iq.issued_per_cycle::2 36000837 18.71% 77.87% # Number of insts issued each cycle
108system.cpu.iq.issued_per_cycle::3 20815986 10.82% 88.69% # Number of insts issued each cycle
109system.cpu.iq.issued_per_cycle::4 13514067 7.02% 95.71% # Number of insts issued each cycle
110system.cpu.iq.issued_per_cycle::5 5325466 2.77% 98.48% # Number of insts issued each cycle
111system.cpu.iq.issued_per_cycle::6 2181156 1.13% 99.61% # Number of insts issued each cycle
112system.cpu.iq.issued_per_cycle::7 607811 0.32% 99.93% # Number of insts issued each cycle
113system.cpu.iq.issued_per_cycle::8 140771 0.07% 100.00% # Number of insts issued each cycle

105system.cpu.iq.issued_per_cycle::0 49123743 28.01% 28.01% # Number of insts issued each cycle
106system.cpu.iq.issued_per_cycle::1 52511910 29.94% 57.95% # Number of insts issued each cycle
107system.cpu.iq.issued_per_cycle::2 34319849 19.57% 77.52% # Number of insts issued each cycle
108system.cpu.iq.issued_per_cycle::3 19020528 10.85% 88.37% # Number of insts issued each cycle
109system.cpu.iq.issued_per_cycle::4 12714994 7.25% 95.62% # Number of insts issued each cycle
110system.cpu.iq.issued_per_cycle::5 4949443 2.82% 98.44% # Number of insts issued each cycle
111system.cpu.iq.issued_per_cycle::6 2083502 1.19% 99.63% # Number of insts issued each cycle
112system.cpu.iq.issued_per_cycle::7 542650 0.31% 99.94% # Number of insts issued each cycle
113system.cpu.iq.issued_per_cycle::8 111135 0.06% 100.00% # Number of insts issued each cycle

114system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
115system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
116system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

117system.cpu.iq.issued_per_cycle::total 192452166 # Number of insts issued each cycle

117system.cpu.iq.issued_per_cycle::total 175377754 # Number of insts issued each cycle

118system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

119system.cpu.iq.fu_full::IntAlu 103783 3.80% 3.80% # attempts to use FU when none available
120system.cpu.iq.fu_full::IntMult 0 0.00% 3.80% # attempts to use FU when none available
121system.cpu.iq.fu_full::IntDiv 0 0.00% 3.80% # attempts to use FU when none available
122system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.80% # attempts to use FU when none available
123system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.80% # attempts to use FU when none available
124system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.80% # attempts to use FU when none available
125system.cpu.iq.fu_full::FloatMult 0 0.00% 3.80% # attempts to use FU when none available
126system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.80% # attempts to use FU when none available
127system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.80% # attempts to use FU when none available
128system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.80% # attempts to use FU when none available
129system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.80% # attempts to use FU when none available
130system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.80% # attempts to use FU when none available
131system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.80% # attempts to use FU when none available
132system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.80% # attempts to use FU when none available
133system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.80% # attempts to use FU when none available
134system.cpu.iq.fu_full::SimdMult 0 0.00% 3.80% # attempts to use FU when none available
135system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.80% # attempts to use FU when none available
136system.cpu.iq.fu_full::SimdShift 0 0.00% 3.80% # attempts to use FU when none available
137system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.80% # attempts to use FU when none available
138system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.80% # attempts to use FU when none available
139system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.80% # attempts to use FU when none available
140system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.80% # attempts to use FU when none available
141system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.80% # attempts to use FU when none available
142system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.80% # attempts to use FU when none available
143system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.80% # attempts to use FU when none available
144system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.80% # attempts to use FU when none available
145system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.80% # attempts to use FU when none available
146system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.80% # attempts to use FU when none available
147system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.80% # attempts to use FU when none available
148system.cpu.iq.fu_full::MemRead 2313613 84.82% 88.62% # attempts to use FU when none available
149system.cpu.iq.fu_full::MemWrite 310319 11.38% 100.00% # attempts to use FU when none available

119system.cpu.iq.fu_full::IntAlu 91290 3.51% 3.51% # attempts to use FU when none available
120system.cpu.iq.fu_full::IntMult 0 0.00% 3.51% # attempts to use FU when none available
121system.cpu.iq.fu_full::IntDiv 0 0.00% 3.51% # attempts to use FU when none available
122system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.51% # attempts to use FU when none available
123system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.51% # attempts to use FU when none available
124system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.51% # attempts to use FU when none available
125system.cpu.iq.fu_full::FloatMult 0 0.00% 3.51% # attempts to use FU when none available
126system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.51% # attempts to use FU when none available
127system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.51% # attempts to use FU when none available
128system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.51% # attempts to use FU when none available
129system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.51% # attempts to use FU when none available
130system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.51% # attempts to use FU when none available
131system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.51% # attempts to use FU when none available
132system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.51% # attempts to use FU when none available
133system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.51% # attempts to use FU when none available
134system.cpu.iq.fu_full::SimdMult 0 0.00% 3.51% # attempts to use FU when none available
135system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.51% # attempts to use FU when none available
136system.cpu.iq.fu_full::SimdShift 0 0.00% 3.51% # attempts to use FU when none available
137system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.51% # attempts to use FU when none available
138system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.51% # attempts to use FU when none available
139system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.51% # attempts to use FU when none available
140system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.51% # attempts to use FU when none available
141system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.51% # attempts to use FU when none available
142system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.51% # attempts to use FU when none available
143system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.51% # attempts to use FU when none available
144system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.51% # attempts to use FU when none available
145system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.51% # attempts to use FU when none available
146system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.51% # attempts to use FU when none available
147system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.51% # attempts to use FU when none available
148system.cpu.iq.fu_full::MemRead 2230006 85.80% 89.31% # attempts to use FU when none available
149system.cpu.iq.fu_full::MemWrite 277845 10.69% 100.00% # attempts to use FU when none available

150system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
151system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available

152system.cpu.iq.FU_type_0::No_OpClass 1202882 0.42% 0.42% # Type of FU issued
153system.cpu.iq.FU_type_0::IntAlu 186701896 64.99% 65.40% # Type of FU issued
154system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.40% # Type of FU issued
155system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.40% # Type of FU issued
156system.cpu.iq.FU_type_0::FloatAdd 1648118 0.57% 65.98% # Type of FU issued
157system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.98% # Type of FU issued
158system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.98% # Type of FU issued
159system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.98% # Type of FU issued
160system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.98% # Type of FU issued
161system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.98% # Type of FU issued
162system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.98% # Type of FU issued
163system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.98% # Type of FU issued
164system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.98% # Type of FU issued
165system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.98% # Type of FU issued
166system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.98% # Type of FU issued
167system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.98% # Type of FU issued
168system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.98% # Type of FU issued
169system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.98% # Type of FU issued
170system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.98% # Type of FU issued
171system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.98% # Type of FU issued
172system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.98% # Type of FU issued
173system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.98% # Type of FU issued
174system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.98% # Type of FU issued
175system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.98% # Type of FU issued
176system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.98% # Type of FU issued
177system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.98% # Type of FU issued
178system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.98% # Type of FU issued
179system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.98% # Type of FU issued
180system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.98% # Type of FU issued
181system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.98% # Type of FU issued
182system.cpu.iq.FU_type_0::MemRead 73212241 25.48% 91.46% # Type of FU issued
183system.cpu.iq.FU_type_0::MemWrite 24531075 8.54% 100.00% # Type of FU issued

152system.cpu.iq.FU_type_0::No_OpClass 1212979 0.45% 0.45% # Type of FU issued
153system.cpu.iq.FU_type_0::IntAlu 176351426 65.07% 65.52% # Type of FU issued
154system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.52% # Type of FU issued
155system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued
156system.cpu.iq.FU_type_0::FloatAdd 1596977 0.59% 66.11% # Type of FU issued
157system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.11% # Type of FU issued
158system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.11% # Type of FU issued
159system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.11% # Type of FU issued
160system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.11% # Type of FU issued
161system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.11% # Type of FU issued
162system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.11% # Type of FU issued
163system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.11% # Type of FU issued
164system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.11% # Type of FU issued
165system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.11% # Type of FU issued
166system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.11% # Type of FU issued
167system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.11% # Type of FU issued
168system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.11% # Type of FU issued
169system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.11% # Type of FU issued
170system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.11% # Type of FU issued
171system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued
172system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.11% # Type of FU issued
173system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued
174system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued
175system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued
176system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued
177system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued
178system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued
179system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued
180system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued
181system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued
182system.cpu.iq.FU_type_0::MemRead 68342169 25.22% 91.33% # Type of FU issued
183system.cpu.iq.FU_type_0::MemWrite 23505474 8.67% 100.00% # Type of FU issued

184system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
185system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

186system.cpu.iq.FU_type_0::total 287296212 # Type of FU issued
187system.cpu.iq.rate 1.492196 # Inst issue rate
188system.cpu.iq.fu_busy_cnt 2727715 # FU busy when requested
189system.cpu.iq.fu_busy_rate 0.009494 # FU busy rate (busy events/executed inst)
190system.cpu.iq.int_inst_queue_reads 764505561 # Number of integer instruction queue reads
191system.cpu.iq.int_inst_queue_writes 564134434 # Number of integer instruction queue writes
192system.cpu.iq.int_inst_queue_wakeup_accesses 277997574 # Number of integer instruction queue wakeup accesses
193system.cpu.iq.fp_inst_queue_reads 5504974 # Number of floating instruction queue reads
194system.cpu.iq.fp_inst_queue_writes 5363501 # Number of floating instruction queue writes
195system.cpu.iq.fp_inst_queue_wakeup_accesses 2644368 # Number of floating instruction queue wakeup accesses
196system.cpu.iq.int_alu_accesses 286052729 # Number of integer alu accesses
197system.cpu.iq.fp_alu_accesses 2768316 # Number of floating point alu accesses
198system.cpu.iew.lsq.thread0.forwLoads 18967849 # Number of loads that had data forwarded from stores

186system.cpu.iq.FU_type_0::total 271009025 # Type of FU issued
187system.cpu.iq.rate 1.544606 # Inst issue rate
188system.cpu.iq.fu_busy_cnt 2599141 # FU busy when requested
189system.cpu.iq.fu_busy_rate 0.009591 # FU busy rate (busy events/executed inst)
190system.cpu.iq.int_inst_queue_reads 714934206 # Number of integer instruction queue reads
191system.cpu.iq.int_inst_queue_writes 462829464 # Number of integer instruction queue writes
192system.cpu.iq.int_inst_queue_wakeup_accesses 263397424 # Number of integer instruction queue wakeup accesses
193system.cpu.iq.fp_inst_queue_reads 5313282 # Number of floating instruction queue reads
194system.cpu.iq.fp_inst_queue_writes 4873666 # Number of floating instruction queue writes
195system.cpu.iq.fp_inst_queue_wakeup_accesses 2553131 # Number of floating instruction queue wakeup accesses
196system.cpu.iq.int_alu_accesses 269732632 # Number of integer alu accesses
197system.cpu.iq.fp_alu_accesses 2662555 # Number of floating point alu accesses
198system.cpu.iew.lsq.thread0.forwLoads 18949841 # Number of loads that had data forwarded from stores

199system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

200system.cpu.iew.lsq.thread0.squashedLoads 47345048 # Number of loads squashed
201system.cpu.iew.lsq.thread0.ignoredResponses 33748 # Number of memory responses ignored because the instruction is squashed
202system.cpu.iew.lsq.thread0.memOrderViolation 344727 # Number of memory ordering violations
203system.cpu.iew.lsq.thread0.squashedStores 16655557 # Number of stores squashed

200system.cpu.iew.lsq.thread0.squashedLoads 33149310 # Number of loads squashed
201system.cpu.iew.lsq.thread0.ignoredResponses 29835 # Number of memory responses ignored because the instruction is squashed
202system.cpu.iew.lsq.thread0.memOrderViolation 306343 # Number of memory ordering violations
203system.cpu.iew.lsq.thread0.squashedStores 12610434 # Number of stores squashed

204system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
205system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding

206system.cpu.iew.lsq.thread0.rescheduledLoads 48770 # Number of loads that were rescheduled

206system.cpu.iew.lsq.thread0.rescheduledLoads 47714 # Number of loads that were rescheduled

207system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
208system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle

209system.cpu.iew.iewSquashCycles 23582874 # Number of cycles IEW is squashing
210system.cpu.iew.iewBlockCycles 506702 # Number of cycles IEW is blocking
211system.cpu.iew.iewUnblockCycles 199063 # Number of cycles IEW is unblocking
212system.cpu.iew.iewDispatchedInsts 395558376 # Number of instructions dispatched to IQ
213system.cpu.iew.iewDispSquashedInsts 136305 # Number of squashed instructions skipped by dispatch
214system.cpu.iew.iewDispLoadInsts 103994638 # Number of dispatched load instructions
215system.cpu.iew.iewDispStoreInsts 37171273 # Number of dispatched store instructions
216system.cpu.iew.iewDispNonSpecInsts 1768 # Number of dispatched non-speculative instructions
217system.cpu.iew.iewIQFullEvents 106766 # Number of times the IQ has become full, causing a stall
218system.cpu.iew.iewLSQFullEvents 14420 # Number of times the LSQ has become full, causing a stall
219system.cpu.iew.memOrderViolationEvents 344727 # Number of memory order violations
220system.cpu.iew.predictedTakenIncorrect 2499729 # Number of branches that were predicted taken incorrectly
221system.cpu.iew.predictedNotTakenIncorrect 593078 # Number of branches that were predicted not taken incorrectly
222system.cpu.iew.branchMispredicts 3092807 # Number of branch mispredicts detected at execute
223system.cpu.iew.iewExecutedInsts 283409034 # Number of executed instructions
224system.cpu.iew.iewExecLoadInsts 71642320 # Number of load instructions executed
225system.cpu.iew.iewExecSquashedInsts 3887178 # Number of squashed instructions skipped in execute

209system.cpu.iew.iewSquashCycles 16991499 # Number of cycles IEW is squashing
210system.cpu.iew.iewBlockCycles 515293 # Number of cycles IEW is blocking
211system.cpu.iew.iewUnblockCycles 247384 # Number of cycles IEW is unblocking
212system.cpu.iew.iewDispatchedInsts 344630194 # Number of instructions dispatched to IQ
213system.cpu.iew.iewDispSquashedInsts 299081 # Number of squashed instructions skipped by dispatch
214system.cpu.iew.iewDispLoadInsts 89798900 # Number of dispatched load instructions
215system.cpu.iew.iewDispStoreInsts 33126150 # Number of dispatched store instructions
216system.cpu.iew.iewDispNonSpecInsts 1841 # Number of dispatched non-speculative instructions
217system.cpu.iew.iewIQFullEvents 161274 # Number of times the IQ has become full, causing a stall
218system.cpu.iew.iewLSQFullEvents 32917 # Number of times the LSQ has become full, causing a stall
219system.cpu.iew.memOrderViolationEvents 306343 # Number of memory order violations
220system.cpu.iew.predictedTakenIncorrect 1299828 # Number of branches that were predicted taken incorrectly
221system.cpu.iew.predictedNotTakenIncorrect 1028827 # Number of branches that were predicted not taken incorrectly
222system.cpu.iew.branchMispredicts 2328655 # Number of branch mispredicts detected at execute
223system.cpu.iew.iewExecutedInsts 267903545 # Number of executed instructions
224system.cpu.iew.iewExecLoadInsts 67266011 # Number of load instructions executed
225system.cpu.iew.iewExecSquashedInsts 3105480 # Number of squashed instructions skipped in execute

226system.cpu.iew.exec_swp 0 # number of swp insts executed
227system.cpu.iew.exec_nop 0 # number of nop insts executed

228system.cpu.iew.exec_refs 95673519 # number of memory reference insts executed
229system.cpu.iew.exec_branches 15642768 # Number of branches executed
230system.cpu.iew.exec_stores 24031199 # Number of stores executed
231system.cpu.iew.exec_rate 1.472006 # Inst execution rate
232system.cpu.iew.wb_sent 281921944 # cumulative count of insts sent to commit
233system.cpu.iew.wb_count 280641942 # cumulative count of insts written-back
234system.cpu.iew.wb_producers 227553614 # num instructions producing a value
235system.cpu.iew.wb_consumers 378165457 # num instructions consuming a value

228system.cpu.iew.exec_refs 90381113 # number of memory reference insts executed
229system.cpu.iew.exec_branches 14784987 # Number of branches executed
230system.cpu.iew.exec_stores 23115102 # Number of stores executed
231system.cpu.iew.exec_rate 1.526907 # Inst execution rate
232system.cpu.iew.wb_sent 266831657 # cumulative count of insts sent to commit
233system.cpu.iew.wb_count 265950555 # cumulative count of insts written-back
234system.cpu.iew.wb_producers 214539100 # num instructions producing a value
235system.cpu.iew.wb_consumers 362277288 # num instructions consuming a value

236system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ

237system.cpu.iew.wb_rate 1.457634 # insts written-back per cycle
238system.cpu.iew.wb_fanout 0.601730 # average fanout of values written-back

237system.cpu.iew.wb_rate 1.515776 # insts written-back per cycle
238system.cpu.iew.wb_fanout 0.592196 # average fanout of values written-back

239system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
240system.cpu.commit.commitCommittedInsts 132071227 # The number of committed instructions
241system.cpu.commit.commitCommittedOps 221363017 # The number of committed instructions

242system.cpu.commit.commitSquashedInsts 174222633 # The number of squashed insts skipped by commit

242system.cpu.commit.commitSquashedInsts 123379420 # The number of squashed insts skipped by commit

243system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards

244system.cpu.commit.branchMispredicts 2892920 # The number of times a branch was mispredicted
245system.cpu.commit.committed_per_cycle::samples 168869292 # Number of insts commited each cycle
246system.cpu.commit.committed_per_cycle::mean 1.310854 # Number of insts commited each cycle
247system.cpu.commit.committed_per_cycle::stdev 1.745147 # Number of insts commited each cycle

244system.cpu.commit.branchMispredicts 2210265 # The number of times a branch was mispredicted
245system.cpu.commit.committed_per_cycle::samples 158386255 # Number of insts commited each cycle
246system.cpu.commit.committed_per_cycle::mean 1.397615 # Number of insts commited each cycle
247system.cpu.commit.committed_per_cycle::stdev 1.796088 # Number of insts commited each cycle

248system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

249system.cpu.commit.committed_per_cycle::0 63124360 37.38% 37.38% # Number of insts commited each cycle
250system.cpu.commit.committed_per_cycle::1 62150025 36.80% 74.18% # Number of insts commited each cycle
251system.cpu.commit.committed_per_cycle::2 15630374 9.26% 83.44% # Number of insts commited each cycle
252system.cpu.commit.committed_per_cycle::3 11975959 7.09% 90.53% # Number of insts commited each cycle
253system.cpu.commit.committed_per_cycle::4 5416595 3.21% 93.74% # Number of insts commited each cycle
254system.cpu.commit.committed_per_cycle::5 2994905 1.77% 95.51% # Number of insts commited each cycle
255system.cpu.commit.committed_per_cycle::6 2021663 1.20% 96.71% # Number of insts commited each cycle
256system.cpu.commit.committed_per_cycle::7 1189804 0.70% 97.41% # Number of insts commited each cycle
257system.cpu.commit.committed_per_cycle::8 4365607 2.59% 100.00% # Number of insts commited each cycle

249system.cpu.commit.committed_per_cycle::0 54200924 34.22% 34.22% # Number of insts commited each cycle
250system.cpu.commit.committed_per_cycle::1 60421756 38.15% 72.37% # Number of insts commited each cycle
251system.cpu.commit.committed_per_cycle::2 15533803 9.81% 82.18% # Number of insts commited each cycle
252system.cpu.commit.committed_per_cycle::3 12711410 8.03% 90.20% # Number of insts commited each cycle
253system.cpu.commit.committed_per_cycle::4 4532649 2.86% 93.06% # Number of insts commited each cycle
254system.cpu.commit.committed_per_cycle::5 2958963 1.87% 94.93% # Number of insts commited each cycle
255system.cpu.commit.committed_per_cycle::6 2077692 1.31% 96.24% # Number of insts commited each cycle
256system.cpu.commit.committed_per_cycle::7 1244602 0.79% 97.03% # Number of insts commited each cycle
257system.cpu.commit.committed_per_cycle::8 4704456 2.97% 100.00% # Number of insts commited each cycle

258system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
259system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
260system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

261system.cpu.commit.committed_per_cycle::total 168869292 # Number of insts commited each cycle

261system.cpu.commit.committed_per_cycle::total 158386255 # Number of insts commited each cycle

262system.cpu.commit.committedInsts 132071227 # Number of instructions committed
263system.cpu.commit.committedOps 221363017 # Number of ops (including micro ops) committed
264system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
265system.cpu.commit.refs 77165306 # Number of memory references committed
266system.cpu.commit.loads 56649590 # Number of loads committed
267system.cpu.commit.membars 0 # Number of memory barriers committed
268system.cpu.commit.branches 12326943 # Number of branches committed
269system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
270system.cpu.commit.int_insts 220339606 # Number of committed integer instructions.
271system.cpu.commit.function_calls 0 # Number of function calls committed.

272system.cpu.commit.bw_lim_events 4365607 # number cycles where commit BW limit reached

272system.cpu.commit.bw_lim_events 4704456 # number cycles where commit BW limit reached

273system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits

274system.cpu.rob.rob_reads 560089335 # The number of ROB reads
275system.cpu.rob.rob_writes 814800236 # The number of ROB writes
276system.cpu.timesIdled 1747 # Number of times that the entire CPU went into an idle state and unscheduled itself
277system.cpu.idleCycles 80351 # Total number of cycles that the CPU has spent unscheduled due to idling

274system.cpu.rob.rob_reads 498424236 # The number of ROB reads
275system.cpu.rob.rob_writes 706514017 # The number of ROB writes
276system.cpu.timesIdled 1681 # Number of times that the entire CPU went into an idle state and unscheduled itself
277system.cpu.idleCycles 77309 # Total number of cycles that the CPU has spent unscheduled due to idling

278system.cpu.committedInsts 132071227 # Number of Instructions Simulated
279system.cpu.committedOps 221363017 # Number of Ops (including micro ops) Simulated
280system.cpu.committedInsts_total 132071227 # Number of Instructions Simulated

281system.cpu.cpi 1.457793 # CPI: Cycles Per Instruction
282system.cpu.cpi_total 1.457793 # CPI: Total CPI of All Threads
283system.cpu.ipc 0.685968 # IPC: Instructions Per Cycle
284system.cpu.ipc_total 0.685968 # IPC: Total IPC of All Threads
285system.cpu.int_regfile_reads 530367480 # number of integer regfile reads
286system.cpu.int_regfile_writes 288604591 # number of integer regfile writes
287system.cpu.fp_regfile_reads 3608788 # number of floating regfile reads
288system.cpu.fp_regfile_writes 2298113 # number of floating regfile writes
289system.cpu.misc_regfile_reads 149639402 # number of misc regfile reads

281system.cpu.cpi 1.328488 # CPI: Cycles Per Instruction
282system.cpu.cpi_total 1.328488 # CPI: Total CPI of All Threads
283system.cpu.ipc 0.752735 # IPC: Instructions Per Cycle
284system.cpu.ipc_total 0.752735 # IPC: Total IPC of All Threads
285system.cpu.int_regfile_reads 511675262 # number of integer regfile reads
286system.cpu.int_regfile_writes 274174484 # number of integer regfile writes
287system.cpu.fp_regfile_reads 3515494 # number of floating regfile reads
288system.cpu.fp_regfile_writes 2227241 # number of floating regfile writes
289system.cpu.misc_regfile_reads 139504609 # number of misc regfile reads

290system.cpu.misc_regfile_writes 844 # number of misc regfile writes

291system.cpu.icache.replacements 4205 # number of replacements
292system.cpu.icache.tagsinuse 1597.649860 # Cycle average of tags in use
293system.cpu.icache.total_refs 28751182 # Total number of references to valid blocks.
294system.cpu.icache.sampled_refs 6167 # Sample count of references to valid blocks.
295system.cpu.icache.avg_refs 4662.101832 # Average number of references to valid blocks.

291system.cpu.icache.replacements 5602 # number of replacements
292system.cpu.icache.tagsinuse 1631.479553 # Cycle average of tags in use
293system.cpu.icache.total_refs 25817139 # Total number of references to valid blocks.
294system.cpu.icache.sampled_refs 7573 # Sample count of references to valid blocks.
295system.cpu.icache.avg_refs 3409.103262 # Average number of references to valid blocks.

296system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

297system.cpu.icache.occ_blocks::cpu.inst 1597.649860 # Average occupied blocks per requestor
298system.cpu.icache.occ_percent::cpu.inst 0.780102 # Average percentage of cache occupancy
299system.cpu.icache.occ_percent::total 0.780102 # Average percentage of cache occupancy
300system.cpu.icache.ReadReq_hits::cpu.inst 28751182 # number of ReadReq hits
301system.cpu.icache.ReadReq_hits::total 28751182 # number of ReadReq hits
302system.cpu.icache.demand_hits::cpu.inst 28751182 # number of demand (read+write) hits
303system.cpu.icache.demand_hits::total 28751182 # number of demand (read+write) hits
304system.cpu.icache.overall_hits::cpu.inst 28751182 # number of overall hits
305system.cpu.icache.overall_hits::total 28751182 # number of overall hits
306system.cpu.icache.ReadReq_misses::cpu.inst 7479 # number of ReadReq misses
307system.cpu.icache.ReadReq_misses::total 7479 # number of ReadReq misses
308system.cpu.icache.demand_misses::cpu.inst 7479 # number of demand (read+write) misses
309system.cpu.icache.demand_misses::total 7479 # number of demand (read+write) misses
310system.cpu.icache.overall_misses::cpu.inst 7479 # number of overall misses
311system.cpu.icache.overall_misses::total 7479 # number of overall misses
312system.cpu.icache.ReadReq_miss_latency::cpu.inst 173725000 # number of ReadReq miss cycles
313system.cpu.icache.ReadReq_miss_latency::total 173725000 # number of ReadReq miss cycles
314system.cpu.icache.demand_miss_latency::cpu.inst 173725000 # number of demand (read+write) miss cycles
315system.cpu.icache.demand_miss_latency::total 173725000 # number of demand (read+write) miss cycles
316system.cpu.icache.overall_miss_latency::cpu.inst 173725000 # number of overall miss cycles
317system.cpu.icache.overall_miss_latency::total 173725000 # number of overall miss cycles
318system.cpu.icache.ReadReq_accesses::cpu.inst 28758661 # number of ReadReq accesses(hits+misses)
319system.cpu.icache.ReadReq_accesses::total 28758661 # number of ReadReq accesses(hits+misses)
320system.cpu.icache.demand_accesses::cpu.inst 28758661 # number of demand (read+write) accesses
321system.cpu.icache.demand_accesses::total 28758661 # number of demand (read+write) accesses
322system.cpu.icache.overall_accesses::cpu.inst 28758661 # number of overall (read+write) accesses
323system.cpu.icache.overall_accesses::total 28758661 # number of overall (read+write) accesses
324system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000260 # miss rate for ReadReq accesses
325system.cpu.icache.demand_miss_rate::cpu.inst 0.000260 # miss rate for demand accesses
326system.cpu.icache.overall_miss_rate::cpu.inst 0.000260 # miss rate for overall accesses
327system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23228.372777 # average ReadReq miss latency
328system.cpu.icache.demand_avg_miss_latency::cpu.inst 23228.372777 # average overall miss latency
329system.cpu.icache.overall_avg_miss_latency::cpu.inst 23228.372777 # average overall miss latency

297system.cpu.icache.occ_blocks::cpu.inst 1631.479553 # Average occupied blocks per requestor
298system.cpu.icache.occ_percent::cpu.inst 0.796621 # Average percentage of cache occupancy
299system.cpu.icache.occ_percent::total 0.796621 # Average percentage of cache occupancy
300system.cpu.icache.ReadReq_hits::cpu.inst 25817139 # number of ReadReq hits
301system.cpu.icache.ReadReq_hits::total 25817139 # number of ReadReq hits
302system.cpu.icache.demand_hits::cpu.inst 25817139 # number of demand (read+write) hits
303system.cpu.icache.demand_hits::total 25817139 # number of demand (read+write) hits
304system.cpu.icache.overall_hits::cpu.inst 25817139 # number of overall hits
305system.cpu.icache.overall_hits::total 25817139 # number of overall hits
306system.cpu.icache.ReadReq_misses::cpu.inst 9097 # number of ReadReq misses
307system.cpu.icache.ReadReq_misses::total 9097 # number of ReadReq misses
308system.cpu.icache.demand_misses::cpu.inst 9097 # number of demand (read+write) misses
309system.cpu.icache.demand_misses::total 9097 # number of demand (read+write) misses
310system.cpu.icache.overall_misses::cpu.inst 9097 # number of overall misses
311system.cpu.icache.overall_misses::total 9097 # number of overall misses
312system.cpu.icache.ReadReq_miss_latency::cpu.inst 188035000 # number of ReadReq miss cycles
313system.cpu.icache.ReadReq_miss_latency::total 188035000 # number of ReadReq miss cycles
314system.cpu.icache.demand_miss_latency::cpu.inst 188035000 # number of demand (read+write) miss cycles
315system.cpu.icache.demand_miss_latency::total 188035000 # number of demand (read+write) miss cycles
316system.cpu.icache.overall_miss_latency::cpu.inst 188035000 # number of overall miss cycles
317system.cpu.icache.overall_miss_latency::total 188035000 # number of overall miss cycles
318system.cpu.icache.ReadReq_accesses::cpu.inst 25826236 # number of ReadReq accesses(hits+misses)
319system.cpu.icache.ReadReq_accesses::total 25826236 # number of ReadReq accesses(hits+misses)
320system.cpu.icache.demand_accesses::cpu.inst 25826236 # number of demand (read+write) accesses
321system.cpu.icache.demand_accesses::total 25826236 # number of demand (read+write) accesses
322system.cpu.icache.overall_accesses::cpu.inst 25826236 # number of overall (read+write) accesses
323system.cpu.icache.overall_accesses::total 25826236 # number of overall (read+write) accesses
324system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000352 # miss rate for ReadReq accesses
325system.cpu.icache.demand_miss_rate::cpu.inst 0.000352 # miss rate for demand accesses
326system.cpu.icache.overall_miss_rate::cpu.inst 0.000352 # miss rate for overall accesses
327system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20670.001099 # average ReadReq miss latency
328system.cpu.icache.demand_avg_miss_latency::cpu.inst 20670.001099 # average overall miss latency
329system.cpu.icache.overall_avg_miss_latency::cpu.inst 20670.001099 # average overall miss latency

330system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
331system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
332system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
333system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
334system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
335system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
336system.cpu.icache.fast_writes 0 # number of fast writes performed
337system.cpu.icache.cache_copies 0 # number of cache copies performed

338system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1119 # number of ReadReq MSHR hits
339system.cpu.icache.ReadReq_mshr_hits::total 1119 # number of ReadReq MSHR hits
340system.cpu.icache.demand_mshr_hits::cpu.inst 1119 # number of demand (read+write) MSHR hits
341system.cpu.icache.demand_mshr_hits::total 1119 # number of demand (read+write) MSHR hits
342system.cpu.icache.overall_mshr_hits::cpu.inst 1119 # number of overall MSHR hits
343system.cpu.icache.overall_mshr_hits::total 1119 # number of overall MSHR hits
344system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6360 # number of ReadReq MSHR misses
345system.cpu.icache.ReadReq_mshr_misses::total 6360 # number of ReadReq MSHR misses
346system.cpu.icache.demand_mshr_misses::cpu.inst 6360 # number of demand (read+write) MSHR misses
347system.cpu.icache.demand_mshr_misses::total 6360 # number of demand (read+write) MSHR misses
348system.cpu.icache.overall_mshr_misses::cpu.inst 6360 # number of overall MSHR misses
349system.cpu.icache.overall_mshr_misses::total 6360 # number of overall MSHR misses
350system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 125233500 # number of ReadReq MSHR miss cycles
351system.cpu.icache.ReadReq_mshr_miss_latency::total 125233500 # number of ReadReq MSHR miss cycles
352system.cpu.icache.demand_mshr_miss_latency::cpu.inst 125233500 # number of demand (read+write) MSHR miss cycles
353system.cpu.icache.demand_mshr_miss_latency::total 125233500 # number of demand (read+write) MSHR miss cycles
354system.cpu.icache.overall_mshr_miss_latency::cpu.inst 125233500 # number of overall MSHR miss cycles
355system.cpu.icache.overall_mshr_miss_latency::total 125233500 # number of overall MSHR miss cycles
356system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000221 # mshr miss rate for ReadReq accesses
357system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000221 # mshr miss rate for demand accesses
358system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000221 # mshr miss rate for overall accesses
359system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19690.801887 # average ReadReq mshr miss latency
360system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19690.801887 # average overall mshr miss latency
361system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19690.801887 # average overall mshr miss latency

338system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1378 # number of ReadReq MSHR hits
339system.cpu.icache.ReadReq_mshr_hits::total 1378 # number of ReadReq MSHR hits
340system.cpu.icache.demand_mshr_hits::cpu.inst 1378 # number of demand (read+write) MSHR hits
341system.cpu.icache.demand_mshr_hits::total 1378 # number of demand (read+write) MSHR hits
342system.cpu.icache.overall_mshr_hits::cpu.inst 1378 # number of overall MSHR hits
343system.cpu.icache.overall_mshr_hits::total 1378 # number of overall MSHR hits
344system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7719 # number of ReadReq MSHR misses
345system.cpu.icache.ReadReq_mshr_misses::total 7719 # number of ReadReq MSHR misses
346system.cpu.icache.demand_mshr_misses::cpu.inst 7719 # number of demand (read+write) MSHR misses
347system.cpu.icache.demand_mshr_misses::total 7719 # number of demand (read+write) MSHR misses
348system.cpu.icache.overall_mshr_misses::cpu.inst 7719 # number of overall MSHR misses
349system.cpu.icache.overall_mshr_misses::total 7719 # number of overall MSHR misses
350system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130954500 # number of ReadReq MSHR miss cycles
351system.cpu.icache.ReadReq_mshr_miss_latency::total 130954500 # number of ReadReq MSHR miss cycles
352system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130954500 # number of demand (read+write) MSHR miss cycles
353system.cpu.icache.demand_mshr_miss_latency::total 130954500 # number of demand (read+write) MSHR miss cycles
354system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130954500 # number of overall MSHR miss cycles
355system.cpu.icache.overall_mshr_miss_latency::total 130954500 # number of overall MSHR miss cycles
356system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for ReadReq accesses
357system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for demand accesses
358system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for overall accesses
359system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16965.215702 # average ReadReq mshr miss latency
360system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16965.215702 # average overall mshr miss latency
361system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16965.215702 # average overall mshr miss latency

362system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate

363system.cpu.dcache.replacements 56 # number of replacements
364system.cpu.dcache.tagsinuse 1415.486536 # Cycle average of tags in use
365system.cpu.dcache.total_refs 72938173 # Total number of references to valid blocks.
366system.cpu.dcache.sampled_refs 1987 # Sample count of references to valid blocks.
367system.cpu.dcache.avg_refs 36707.686462 # Average number of references to valid blocks.

363system.cpu.dcache.replacements 54 # number of replacements
364system.cpu.dcache.tagsinuse 1429.840369 # Cycle average of tags in use
365system.cpu.dcache.total_refs 68659767 # Total number of references to valid blocks.
366system.cpu.dcache.sampled_refs 1998 # Sample count of references to valid blocks.
367system.cpu.dcache.avg_refs 34364.247748 # Average number of references to valid blocks.

368system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

369system.cpu.dcache.occ_blocks::cpu.data 1415.486536 # Average occupied blocks per requestor
370system.cpu.dcache.occ_percent::cpu.data 0.345578 # Average percentage of cache occupancy
371system.cpu.dcache.occ_percent::total 0.345578 # Average percentage of cache occupancy
372system.cpu.dcache.ReadReq_hits::cpu.data 52423955 # number of ReadReq hits
373system.cpu.dcache.ReadReq_hits::total 52423955 # number of ReadReq hits
374system.cpu.dcache.WriteReq_hits::cpu.data 20513973 # number of WriteReq hits
375system.cpu.dcache.WriteReq_hits::total 20513973 # number of WriteReq hits
376system.cpu.dcache.demand_hits::cpu.data 72937928 # number of demand (read+write) hits
377system.cpu.dcache.demand_hits::total 72937928 # number of demand (read+write) hits
378system.cpu.dcache.overall_hits::cpu.data 72937928 # number of overall hits
379system.cpu.dcache.overall_hits::total 72937928 # number of overall hits
380system.cpu.dcache.ReadReq_misses::cpu.data 771 # number of ReadReq misses
381system.cpu.dcache.ReadReq_misses::total 771 # number of ReadReq misses
382system.cpu.dcache.WriteReq_misses::cpu.data 1757 # number of WriteReq misses
383system.cpu.dcache.WriteReq_misses::total 1757 # number of WriteReq misses
384system.cpu.dcache.demand_misses::cpu.data 2528 # number of demand (read+write) misses
385system.cpu.dcache.demand_misses::total 2528 # number of demand (read+write) misses
386system.cpu.dcache.overall_misses::cpu.data 2528 # number of overall misses
387system.cpu.dcache.overall_misses::total 2528 # number of overall misses
388system.cpu.dcache.ReadReq_miss_latency::cpu.data 24605500 # number of ReadReq miss cycles
389system.cpu.dcache.ReadReq_miss_latency::total 24605500 # number of ReadReq miss cycles
390system.cpu.dcache.WriteReq_miss_latency::cpu.data 66582500 # number of WriteReq miss cycles
391system.cpu.dcache.WriteReq_miss_latency::total 66582500 # number of WriteReq miss cycles
392system.cpu.dcache.demand_miss_latency::cpu.data 91188000 # number of demand (read+write) miss cycles
393system.cpu.dcache.demand_miss_latency::total 91188000 # number of demand (read+write) miss cycles
394system.cpu.dcache.overall_miss_latency::cpu.data 91188000 # number of overall miss cycles
395system.cpu.dcache.overall_miss_latency::total 91188000 # number of overall miss cycles
396system.cpu.dcache.ReadReq_accesses::cpu.data 52424726 # number of ReadReq accesses(hits+misses)
397system.cpu.dcache.ReadReq_accesses::total 52424726 # number of ReadReq accesses(hits+misses)

369system.cpu.dcache.occ_blocks::cpu.data 1429.840369 # Average occupied blocks per requestor
370system.cpu.dcache.occ_percent::cpu.data 0.349082 # Average percentage of cache occupancy
371system.cpu.dcache.occ_percent::total 0.349082 # Average percentage of cache occupancy
372system.cpu.dcache.ReadReq_hits::cpu.data 48145557 # number of ReadReq hits
373system.cpu.dcache.ReadReq_hits::total 48145557 # number of ReadReq hits
374system.cpu.dcache.WriteReq_hits::cpu.data 20514023 # number of WriteReq hits
375system.cpu.dcache.WriteReq_hits::total 20514023 # number of WriteReq hits
376system.cpu.dcache.demand_hits::cpu.data 68659580 # number of demand (read+write) hits
377system.cpu.dcache.demand_hits::total 68659580 # number of demand (read+write) hits
378system.cpu.dcache.overall_hits::cpu.data 68659580 # number of overall hits
379system.cpu.dcache.overall_hits::total 68659580 # number of overall hits
380system.cpu.dcache.ReadReq_misses::cpu.data 765 # number of ReadReq misses
381system.cpu.dcache.ReadReq_misses::total 765 # number of ReadReq misses
382system.cpu.dcache.WriteReq_misses::cpu.data 1707 # number of WriteReq misses
383system.cpu.dcache.WriteReq_misses::total 1707 # number of WriteReq misses
384system.cpu.dcache.demand_misses::cpu.data 2472 # number of demand (read+write) misses
385system.cpu.dcache.demand_misses::total 2472 # number of demand (read+write) misses
386system.cpu.dcache.overall_misses::cpu.data 2472 # number of overall misses
387system.cpu.dcache.overall_misses::total 2472 # number of overall misses
388system.cpu.dcache.ReadReq_miss_latency::cpu.data 24609000 # number of ReadReq miss cycles
389system.cpu.dcache.ReadReq_miss_latency::total 24609000 # number of ReadReq miss cycles
390system.cpu.dcache.WriteReq_miss_latency::cpu.data 64758500 # number of WriteReq miss cycles
391system.cpu.dcache.WriteReq_miss_latency::total 64758500 # number of WriteReq miss cycles
392system.cpu.dcache.demand_miss_latency::cpu.data 89367500 # number of demand (read+write) miss cycles
393system.cpu.dcache.demand_miss_latency::total 89367500 # number of demand (read+write) miss cycles
394system.cpu.dcache.overall_miss_latency::cpu.data 89367500 # number of overall miss cycles
395system.cpu.dcache.overall_miss_latency::total 89367500 # number of overall miss cycles
396system.cpu.dcache.ReadReq_accesses::cpu.data 48146322 # number of ReadReq accesses(hits+misses)
397system.cpu.dcache.ReadReq_accesses::total 48146322 # number of ReadReq accesses(hits+misses)

398system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses)
399system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses)

400system.cpu.dcache.demand_accesses::cpu.data 72940456 # number of demand (read+write) accesses
401system.cpu.dcache.demand_accesses::total 72940456 # number of demand (read+write) accesses
402system.cpu.dcache.overall_accesses::cpu.data 72940456 # number of overall (read+write) accesses
403system.cpu.dcache.overall_accesses::total 72940456 # number of overall (read+write) accesses
404system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000015 # miss rate for ReadReq accesses
405system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000086 # miss rate for WriteReq accesses
406system.cpu.dcache.demand_miss_rate::cpu.data 0.000035 # miss rate for demand accesses
407system.cpu.dcache.overall_miss_rate::cpu.data 0.000035 # miss rate for overall accesses
408system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31913.748379 # average ReadReq miss latency
409system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37895.560615 # average WriteReq miss latency
410system.cpu.dcache.demand_avg_miss_latency::cpu.data 36071.202532 # average overall miss latency
411system.cpu.dcache.overall_avg_miss_latency::cpu.data 36071.202532 # average overall miss latency

400system.cpu.dcache.demand_accesses::cpu.data 68662052 # number of demand (read+write) accesses
401system.cpu.dcache.demand_accesses::total 68662052 # number of demand (read+write) accesses
402system.cpu.dcache.overall_accesses::cpu.data 68662052 # number of overall (read+write) accesses
403system.cpu.dcache.overall_accesses::total 68662052 # number of overall (read+write) accesses
404system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000016 # miss rate for ReadReq accesses
405system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses
406system.cpu.dcache.demand_miss_rate::cpu.data 0.000036 # miss rate for demand accesses
407system.cpu.dcache.overall_miss_rate::cpu.data 0.000036 # miss rate for overall accesses
408system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32168.627451 # average ReadReq miss latency
409system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37937.024019 # average WriteReq miss latency
410system.cpu.dcache.demand_avg_miss_latency::cpu.data 36151.901294 # average overall miss latency
411system.cpu.dcache.overall_avg_miss_latency::cpu.data 36151.901294 # average overall miss latency

412system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
413system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
414system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
415system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
416system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
417system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
418system.cpu.dcache.fast_writes 0 # number of fast writes performed
419system.cpu.dcache.cache_copies 0 # number of cache copies performed
420system.cpu.dcache.writebacks::writebacks 13 # number of writebacks
421system.cpu.dcache.writebacks::total 13 # number of writebacks

422system.cpu.dcache.ReadReq_mshr_hits::cpu.data 344 # number of ReadReq MSHR hits
423system.cpu.dcache.ReadReq_mshr_hits::total 344 # number of ReadReq MSHR hits
424system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits
425system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits
426system.cpu.dcache.demand_mshr_hits::cpu.data 346 # number of demand (read+write) MSHR hits
427system.cpu.dcache.demand_mshr_hits::total 346 # number of demand (read+write) MSHR hits
428system.cpu.dcache.overall_mshr_hits::cpu.data 346 # number of overall MSHR hits
429system.cpu.dcache.overall_mshr_hits::total 346 # number of overall MSHR hits
430system.cpu.dcache.ReadReq_mshr_misses::cpu.data 427 # number of ReadReq MSHR misses
431system.cpu.dcache.ReadReq_mshr_misses::total 427 # number of ReadReq MSHR misses
432system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1755 # number of WriteReq MSHR misses
433system.cpu.dcache.WriteReq_mshr_misses::total 1755 # number of WriteReq MSHR misses
434system.cpu.dcache.demand_mshr_misses::cpu.data 2182 # number of demand (read+write) MSHR misses
435system.cpu.dcache.demand_mshr_misses::total 2182 # number of demand (read+write) MSHR misses
436system.cpu.dcache.overall_mshr_misses::cpu.data 2182 # number of overall MSHR misses
437system.cpu.dcache.overall_mshr_misses::total 2182 # number of overall MSHR misses
438system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14039500 # number of ReadReq MSHR miss cycles
439system.cpu.dcache.ReadReq_mshr_miss_latency::total 14039500 # number of ReadReq MSHR miss cycles
440system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61244500 # number of WriteReq MSHR miss cycles
441system.cpu.dcache.WriteReq_mshr_miss_latency::total 61244500 # number of WriteReq MSHR miss cycles
442system.cpu.dcache.demand_mshr_miss_latency::cpu.data 75284000 # number of demand (read+write) MSHR miss cycles
443system.cpu.dcache.demand_mshr_miss_latency::total 75284000 # number of demand (read+write) MSHR miss cycles
444system.cpu.dcache.overall_mshr_miss_latency::cpu.data 75284000 # number of overall MSHR miss cycles
445system.cpu.dcache.overall_mshr_miss_latency::total 75284000 # number of overall MSHR miss cycles
446system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000008 # mshr miss rate for ReadReq accesses
447system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000086 # mshr miss rate for WriteReq accesses
448system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000030 # mshr miss rate for demand accesses
449system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000030 # mshr miss rate for overall accesses
450system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32879.391101 # average ReadReq mshr miss latency
451system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34897.150997 # average WriteReq mshr miss latency
452system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34502.291476 # average overall mshr miss latency
453system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34502.291476 # average overall mshr miss latency

422system.cpu.dcache.ReadReq_mshr_hits::cpu.data 323 # number of ReadReq MSHR hits
423system.cpu.dcache.ReadReq_mshr_hits::total 323 # number of ReadReq MSHR hits
424system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3 # number of WriteReq MSHR hits
425system.cpu.dcache.WriteReq_mshr_hits::total 3 # number of WriteReq MSHR hits
426system.cpu.dcache.demand_mshr_hits::cpu.data 326 # number of demand (read+write) MSHR hits
427system.cpu.dcache.demand_mshr_hits::total 326 # number of demand (read+write) MSHR hits
428system.cpu.dcache.overall_mshr_hits::cpu.data 326 # number of overall MSHR hits
429system.cpu.dcache.overall_mshr_hits::total 326 # number of overall MSHR hits
430system.cpu.dcache.ReadReq_mshr_misses::cpu.data 442 # number of ReadReq MSHR misses
431system.cpu.dcache.ReadReq_mshr_misses::total 442 # number of ReadReq MSHR misses
432system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1704 # number of WriteReq MSHR misses
433system.cpu.dcache.WriteReq_mshr_misses::total 1704 # number of WriteReq MSHR misses
434system.cpu.dcache.demand_mshr_misses::cpu.data 2146 # number of demand (read+write) MSHR misses
435system.cpu.dcache.demand_mshr_misses::total 2146 # number of demand (read+write) MSHR misses
436system.cpu.dcache.overall_mshr_misses::cpu.data 2146 # number of overall MSHR misses
437system.cpu.dcache.overall_mshr_misses::total 2146 # number of overall MSHR misses
438system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14613500 # number of ReadReq MSHR miss cycles
439system.cpu.dcache.ReadReq_mshr_miss_latency::total 14613500 # number of ReadReq MSHR miss cycles
440system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59538000 # number of WriteReq MSHR miss cycles
441system.cpu.dcache.WriteReq_mshr_miss_latency::total 59538000 # number of WriteReq MSHR miss cycles
442system.cpu.dcache.demand_mshr_miss_latency::cpu.data 74151500 # number of demand (read+write) MSHR miss cycles
443system.cpu.dcache.demand_mshr_miss_latency::total 74151500 # number of demand (read+write) MSHR miss cycles
444system.cpu.dcache.overall_mshr_miss_latency::cpu.data 74151500 # number of overall MSHR miss cycles
445system.cpu.dcache.overall_mshr_miss_latency::total 74151500 # number of overall MSHR miss cycles
446system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses
447system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000083 # mshr miss rate for WriteReq accesses
448system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for demand accesses
449system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for overall accesses
450system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33062.217195 # average ReadReq mshr miss latency
451system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34940.140845 # average WriteReq mshr miss latency
452system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34553.355079 # average overall mshr miss latency
453system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34553.355079 # average overall mshr miss latency

454system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
455system.cpu.l2cache.replacements 0 # number of replacements

456system.cpu.l2cache.tagsinuse 2496.824684 # Cycle average of tags in use
457system.cpu.l2cache.total_refs 2842 # Total number of references to valid blocks.
458system.cpu.l2cache.sampled_refs 3755 # Sample count of references to valid blocks.
459system.cpu.l2cache.avg_refs 0.756858 # Average number of references to valid blocks.

456system.cpu.l2cache.tagsinuse 2591.074934 # Cycle average of tags in use
457system.cpu.l2cache.total_refs 4164 # Total number of references to valid blocks.
458system.cpu.l2cache.sampled_refs 3853 # Sample count of references to valid blocks.
459system.cpu.l2cache.avg_refs 1.080716 # Average number of references to valid blocks.

460system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

461system.cpu.l2cache.occ_blocks::writebacks 1.944495 # Average occupied blocks per requestor
462system.cpu.l2cache.occ_blocks::cpu.inst 2209.976363 # Average occupied blocks per requestor
463system.cpu.l2cache.occ_blocks::cpu.data 284.903826 # Average occupied blocks per requestor
464system.cpu.l2cache.occ_percent::writebacks 0.000059 # Average percentage of cache occupancy
465system.cpu.l2cache.occ_percent::cpu.inst 0.067443 # Average percentage of cache occupancy
466system.cpu.l2cache.occ_percent::cpu.data 0.008695 # Average percentage of cache occupancy
467system.cpu.l2cache.occ_percent::total 0.076197 # Average percentage of cache occupancy
468system.cpu.l2cache.ReadReq_hits::cpu.inst 2809 # number of ReadReq hits
469system.cpu.l2cache.ReadReq_hits::cpu.data 31 # number of ReadReq hits
470system.cpu.l2cache.ReadReq_hits::total 2840 # number of ReadReq hits

461system.cpu.l2cache.occ_blocks::writebacks 1.913608 # Average occupied blocks per requestor
462system.cpu.l2cache.occ_blocks::cpu.inst 2287.446518 # Average occupied blocks per requestor
463system.cpu.l2cache.occ_blocks::cpu.data 301.714808 # Average occupied blocks per requestor
464system.cpu.l2cache.occ_percent::writebacks 0.000058 # Average percentage of cache occupancy
465system.cpu.l2cache.occ_percent::cpu.inst 0.069807 # Average percentage of cache occupancy
466system.cpu.l2cache.occ_percent::cpu.data 0.009208 # Average percentage of cache occupancy
467system.cpu.l2cache.occ_percent::total 0.079073 # Average percentage of cache occupancy
468system.cpu.l2cache.ReadReq_hits::cpu.inst 4132 # number of ReadReq hits
469system.cpu.l2cache.ReadReq_hits::cpu.data 30 # number of ReadReq hits
470system.cpu.l2cache.ReadReq_hits::total 4162 # number of ReadReq hits

471system.cpu.l2cache.Writeback_hits::writebacks 13 # number of Writeback hits
472system.cpu.l2cache.Writeback_hits::total 13 # number of Writeback hits
473system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
474system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits

475system.cpu.l2cache.demand_hits::cpu.inst 2809 # number of demand (read+write) hits
476system.cpu.l2cache.demand_hits::cpu.data 39 # number of demand (read+write) hits
477system.cpu.l2cache.demand_hits::total 2848 # number of demand (read+write) hits
478system.cpu.l2cache.overall_hits::cpu.inst 2809 # number of overall hits
479system.cpu.l2cache.overall_hits::cpu.data 39 # number of overall hits
480system.cpu.l2cache.overall_hits::total 2848 # number of overall hits
481system.cpu.l2cache.ReadReq_misses::cpu.inst 3358 # number of ReadReq misses
482system.cpu.l2cache.ReadReq_misses::cpu.data 395 # number of ReadReq misses
483system.cpu.l2cache.ReadReq_misses::total 3753 # number of ReadReq misses
484system.cpu.l2cache.UpgradeReq_misses::cpu.data 193 # number of UpgradeReq misses
485system.cpu.l2cache.UpgradeReq_misses::total 193 # number of UpgradeReq misses
486system.cpu.l2cache.ReadExReq_misses::cpu.data 1555 # number of ReadExReq misses
487system.cpu.l2cache.ReadExReq_misses::total 1555 # number of ReadExReq misses
488system.cpu.l2cache.demand_misses::cpu.inst 3358 # number of demand (read+write) misses
489system.cpu.l2cache.demand_misses::cpu.data 1950 # number of demand (read+write) misses
490system.cpu.l2cache.demand_misses::total 5308 # number of demand (read+write) misses
491system.cpu.l2cache.overall_misses::cpu.inst 3358 # number of overall misses
492system.cpu.l2cache.overall_misses::cpu.data 1950 # number of overall misses
493system.cpu.l2cache.overall_misses::total 5308 # number of overall misses
494system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 115037500 # number of ReadReq miss cycles
495system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13496000 # number of ReadReq miss cycles
496system.cpu.l2cache.ReadReq_miss_latency::total 128533500 # number of ReadReq miss cycles
497system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 53066500 # number of ReadExReq miss cycles
498system.cpu.l2cache.ReadExReq_miss_latency::total 53066500 # number of ReadExReq miss cycles
499system.cpu.l2cache.demand_miss_latency::cpu.inst 115037500 # number of demand (read+write) miss cycles
500system.cpu.l2cache.demand_miss_latency::cpu.data 66562500 # number of demand (read+write) miss cycles
501system.cpu.l2cache.demand_miss_latency::total 181600000 # number of demand (read+write) miss cycles
502system.cpu.l2cache.overall_miss_latency::cpu.inst 115037500 # number of overall miss cycles
503system.cpu.l2cache.overall_miss_latency::cpu.data 66562500 # number of overall miss cycles
504system.cpu.l2cache.overall_miss_latency::total 181600000 # number of overall miss cycles
505system.cpu.l2cache.ReadReq_accesses::cpu.inst 6167 # number of ReadReq accesses(hits+misses)
506system.cpu.l2cache.ReadReq_accesses::cpu.data 426 # number of ReadReq accesses(hits+misses)
507system.cpu.l2cache.ReadReq_accesses::total 6593 # number of ReadReq accesses(hits+misses)

475system.cpu.l2cache.demand_hits::cpu.inst 4132 # number of demand (read+write) hits
476system.cpu.l2cache.demand_hits::cpu.data 38 # number of demand (read+write) hits
477system.cpu.l2cache.demand_hits::total 4170 # number of demand (read+write) hits
478system.cpu.l2cache.overall_hits::cpu.inst 4132 # number of overall hits
479system.cpu.l2cache.overall_hits::cpu.data 38 # number of overall hits
480system.cpu.l2cache.overall_hits::total 4170 # number of overall hits
481system.cpu.l2cache.ReadReq_misses::cpu.inst 3441 # number of ReadReq misses
482system.cpu.l2cache.ReadReq_misses::cpu.data 411 # number of ReadReq misses
483system.cpu.l2cache.ReadReq_misses::total 3852 # number of ReadReq misses
484system.cpu.l2cache.UpgradeReq_misses::cpu.data 146 # number of UpgradeReq misses
485system.cpu.l2cache.UpgradeReq_misses::total 146 # number of UpgradeReq misses
486system.cpu.l2cache.ReadExReq_misses::cpu.data 1551 # number of ReadExReq misses
487system.cpu.l2cache.ReadExReq_misses::total 1551 # number of ReadExReq misses
488system.cpu.l2cache.demand_misses::cpu.inst 3441 # number of demand (read+write) misses
489system.cpu.l2cache.demand_misses::cpu.data 1962 # number of demand (read+write) misses
490system.cpu.l2cache.demand_misses::total 5403 # number of demand (read+write) misses
491system.cpu.l2cache.overall_misses::cpu.inst 3441 # number of overall misses
492system.cpu.l2cache.overall_misses::cpu.data 1962 # number of overall misses
493system.cpu.l2cache.overall_misses::total 5403 # number of overall misses
494system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 117870000 # number of ReadReq miss cycles
495system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14049500 # number of ReadReq miss cycles
496system.cpu.l2cache.ReadReq_miss_latency::total 131919500 # number of ReadReq miss cycles
497system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 52980000 # number of ReadExReq miss cycles
498system.cpu.l2cache.ReadExReq_miss_latency::total 52980000 # number of ReadExReq miss cycles
499system.cpu.l2cache.demand_miss_latency::cpu.inst 117870000 # number of demand (read+write) miss cycles
500system.cpu.l2cache.demand_miss_latency::cpu.data 67029500 # number of demand (read+write) miss cycles
501system.cpu.l2cache.demand_miss_latency::total 184899500 # number of demand (read+write) miss cycles
502system.cpu.l2cache.overall_miss_latency::cpu.inst 117870000 # number of overall miss cycles
503system.cpu.l2cache.overall_miss_latency::cpu.data 67029500 # number of overall miss cycles
504system.cpu.l2cache.overall_miss_latency::total 184899500 # number of overall miss cycles
505system.cpu.l2cache.ReadReq_accesses::cpu.inst 7573 # number of ReadReq accesses(hits+misses)
506system.cpu.l2cache.ReadReq_accesses::cpu.data 441 # number of ReadReq accesses(hits+misses)
507system.cpu.l2cache.ReadReq_accesses::total 8014 # number of ReadReq accesses(hits+misses)

508system.cpu.l2cache.Writeback_accesses::writebacks 13 # number of Writeback accesses(hits+misses)
509system.cpu.l2cache.Writeback_accesses::total 13 # number of Writeback accesses(hits+misses)

510system.cpu.l2cache.UpgradeReq_accesses::cpu.data 193 # number of UpgradeReq accesses(hits+misses)
511system.cpu.l2cache.UpgradeReq_accesses::total 193 # number of UpgradeReq accesses(hits+misses)
512system.cpu.l2cache.ReadExReq_accesses::cpu.data 1563 # number of ReadExReq accesses(hits+misses)
513system.cpu.l2cache.ReadExReq_accesses::total 1563 # number of ReadExReq accesses(hits+misses)
514system.cpu.l2cache.demand_accesses::cpu.inst 6167 # number of demand (read+write) accesses
515system.cpu.l2cache.demand_accesses::cpu.data 1989 # number of demand (read+write) accesses
516system.cpu.l2cache.demand_accesses::total 8156 # number of demand (read+write) accesses
517system.cpu.l2cache.overall_accesses::cpu.inst 6167 # number of overall (read+write) accesses
518system.cpu.l2cache.overall_accesses::cpu.data 1989 # number of overall (read+write) accesses
519system.cpu.l2cache.overall_accesses::total 8156 # number of overall (read+write) accesses
520system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.544511 # miss rate for ReadReq accesses
521system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.927230 # miss rate for ReadReq accesses

510system.cpu.l2cache.UpgradeReq_accesses::cpu.data 146 # number of UpgradeReq accesses(hits+misses)
511system.cpu.l2cache.UpgradeReq_accesses::total 146 # number of UpgradeReq accesses(hits+misses)
512system.cpu.l2cache.ReadExReq_accesses::cpu.data 1559 # number of ReadExReq accesses(hits+misses)
513system.cpu.l2cache.ReadExReq_accesses::total 1559 # number of ReadExReq accesses(hits+misses)
514system.cpu.l2cache.demand_accesses::cpu.inst 7573 # number of demand (read+write) accesses
515system.cpu.l2cache.demand_accesses::cpu.data 2000 # number of demand (read+write) accesses
516system.cpu.l2cache.demand_accesses::total 9573 # number of demand (read+write) accesses
517system.cpu.l2cache.overall_accesses::cpu.inst 7573 # number of overall (read+write) accesses
518system.cpu.l2cache.overall_accesses::cpu.data 2000 # number of overall (read+write) accesses
519system.cpu.l2cache.overall_accesses::total 9573 # number of overall (read+write) accesses
520system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.454377 # miss rate for ReadReq accesses
521system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.931973 # miss rate for ReadReq accesses

522system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses

523system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994882 # miss rate for ReadExReq accesses
524system.cpu.l2cache.demand_miss_rate::cpu.inst 0.544511 # miss rate for demand accesses
525system.cpu.l2cache.demand_miss_rate::cpu.data 0.980392 # miss rate for demand accesses
526system.cpu.l2cache.overall_miss_rate::cpu.inst 0.544511 # miss rate for overall accesses
527system.cpu.l2cache.overall_miss_rate::cpu.data 0.980392 # miss rate for overall accesses
528system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34257.742704 # average ReadReq miss latency
529system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34167.088608 # average ReadReq miss latency
530system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34126.366559 # average ReadExReq miss latency
531system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34257.742704 # average overall miss latency
532system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34134.615385 # average overall miss latency
533system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34257.742704 # average overall miss latency
534system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34134.615385 # average overall miss latency

523system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994869 # miss rate for ReadExReq accesses
524system.cpu.l2cache.demand_miss_rate::cpu.inst 0.454377 # miss rate for demand accesses
525system.cpu.l2cache.demand_miss_rate::cpu.data 0.981000 # miss rate for demand accesses
526system.cpu.l2cache.overall_miss_rate::cpu.inst 0.454377 # miss rate for overall accesses
527system.cpu.l2cache.overall_miss_rate::cpu.data 0.981000 # miss rate for overall accesses
528system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34254.577158 # average ReadReq miss latency
529system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34183.698297 # average ReadReq miss latency
530system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34158.607350 # average ReadExReq miss latency
531system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34254.577158 # average overall miss latency
532system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34163.863405 # average overall miss latency
533system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34254.577158 # average overall miss latency
534system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34163.863405 # average overall miss latency

535system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
536system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
537system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
538system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
539system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
540system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
541system.cpu.l2cache.fast_writes 0 # number of fast writes performed
542system.cpu.l2cache.cache_copies 0 # number of cache copies performed

543system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3358 # number of ReadReq MSHR misses
544system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 395 # number of ReadReq MSHR misses
545system.cpu.l2cache.ReadReq_mshr_misses::total 3753 # number of ReadReq MSHR misses
546system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 193 # number of UpgradeReq MSHR misses
547system.cpu.l2cache.UpgradeReq_mshr_misses::total 193 # number of UpgradeReq MSHR misses
548system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1555 # number of ReadExReq MSHR misses
549system.cpu.l2cache.ReadExReq_mshr_misses::total 1555 # number of ReadExReq MSHR misses
550system.cpu.l2cache.demand_mshr_misses::cpu.inst 3358 # number of demand (read+write) MSHR misses
551system.cpu.l2cache.demand_mshr_misses::cpu.data 1950 # number of demand (read+write) MSHR misses
552system.cpu.l2cache.demand_mshr_misses::total 5308 # number of demand (read+write) MSHR misses
553system.cpu.l2cache.overall_mshr_misses::cpu.inst 3358 # number of overall MSHR misses
554system.cpu.l2cache.overall_mshr_misses::cpu.data 1950 # number of overall MSHR misses
555system.cpu.l2cache.overall_mshr_misses::total 5308 # number of overall MSHR misses
556system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104175500 # number of ReadReq MSHR miss cycles
557system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12238000 # number of ReadReq MSHR miss cycles
558system.cpu.l2cache.ReadReq_mshr_miss_latency::total 116413500 # number of ReadReq MSHR miss cycles
559system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5983000 # number of UpgradeReq MSHR miss cycles
560system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5983000 # number of UpgradeReq MSHR miss cycles
561system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48232500 # number of ReadExReq MSHR miss cycles
562system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48232500 # number of ReadExReq MSHR miss cycles
563system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104175500 # number of demand (read+write) MSHR miss cycles
564system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 60470500 # number of demand (read+write) MSHR miss cycles
565system.cpu.l2cache.demand_mshr_miss_latency::total 164646000 # number of demand (read+write) MSHR miss cycles
566system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104175500 # number of overall MSHR miss cycles
567system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 60470500 # number of overall MSHR miss cycles
568system.cpu.l2cache.overall_mshr_miss_latency::total 164646000 # number of overall MSHR miss cycles
569system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.544511 # mshr miss rate for ReadReq accesses
570system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.927230 # mshr miss rate for ReadReq accesses

543system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3441 # number of ReadReq MSHR misses
544system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 411 # number of ReadReq MSHR misses
545system.cpu.l2cache.ReadReq_mshr_misses::total 3852 # number of ReadReq MSHR misses
546system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 146 # number of UpgradeReq MSHR misses
547system.cpu.l2cache.UpgradeReq_mshr_misses::total 146 # number of UpgradeReq MSHR misses
548system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1551 # number of ReadExReq MSHR misses
549system.cpu.l2cache.ReadExReq_mshr_misses::total 1551 # number of ReadExReq MSHR misses
550system.cpu.l2cache.demand_mshr_misses::cpu.inst 3441 # number of demand (read+write) MSHR misses
551system.cpu.l2cache.demand_mshr_misses::cpu.data 1962 # number of demand (read+write) MSHR misses
552system.cpu.l2cache.demand_mshr_misses::total 5403 # number of demand (read+write) MSHR misses
553system.cpu.l2cache.overall_mshr_misses::cpu.inst 3441 # number of overall MSHR misses
554system.cpu.l2cache.overall_mshr_misses::cpu.data 1962 # number of overall MSHR misses
555system.cpu.l2cache.overall_mshr_misses::total 5403 # number of overall MSHR misses
556system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106751500 # number of ReadReq MSHR miss cycles
557system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12743500 # number of ReadReq MSHR miss cycles
558system.cpu.l2cache.ReadReq_mshr_miss_latency::total 119495000 # number of ReadReq MSHR miss cycles
559system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4526000 # number of UpgradeReq MSHR miss cycles
560system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4526000 # number of UpgradeReq MSHR miss cycles
561system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48112000 # number of ReadExReq MSHR miss cycles
562system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48112000 # number of ReadExReq MSHR miss cycles
563system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106751500 # number of demand (read+write) MSHR miss cycles
564system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 60855500 # number of demand (read+write) MSHR miss cycles
565system.cpu.l2cache.demand_mshr_miss_latency::total 167607000 # number of demand (read+write) MSHR miss cycles
566system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106751500 # number of overall MSHR miss cycles
567system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 60855500 # number of overall MSHR miss cycles
568system.cpu.l2cache.overall_mshr_miss_latency::total 167607000 # number of overall MSHR miss cycles
569system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.454377 # mshr miss rate for ReadReq accesses
570system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.931973 # mshr miss rate for ReadReq accesses

571system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses

572system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994882 # mshr miss rate for ReadExReq accesses
573system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.544511 # mshr miss rate for demand accesses
574system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980392 # mshr miss rate for demand accesses
575system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.544511 # mshr miss rate for overall accesses
576system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980392 # mshr miss rate for overall accesses
577system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31023.079214 # average ReadReq mshr miss latency
578system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30982.278481 # average ReadReq mshr miss latency

572system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994869 # mshr miss rate for ReadExReq accesses
573system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.454377 # mshr miss rate for demand accesses
574system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.981000 # mshr miss rate for demand accesses
575system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.454377 # mshr miss rate for overall accesses
576system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.981000 # mshr miss rate for overall accesses
577system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31023.394362 # average ReadReq mshr miss latency
578system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31006.082725 # average ReadReq mshr miss latency

579system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency

580system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31017.684887 # average ReadExReq mshr miss latency
581system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31023.079214 # average overall mshr miss latency
582system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31010.512821 # average overall mshr miss latency
583system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31023.079214 # average overall mshr miss latency
584system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31010.512821 # average overall mshr miss latency

580system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31019.987105 # average ReadExReq mshr miss latency
581system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31023.394362 # average overall mshr miss latency
582system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31017.074414 # average overall mshr miss latency
583system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31023.394362 # average overall mshr miss latency
584system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31017.074414 # average overall mshr miss latency