| stats.txt (11687:b3d5f0e9e258) | stats.txt (11754:c209cb86278a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.103189 # Number of seconds simulated 4sim_ticks 103189362000 # Number of ticks simulated 5final_tick 103189362000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.103324 # Number of seconds simulated 4sim_ticks 103323995500 # Number of ticks simulated 5final_tick 103323995500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 113263 # Simulator instruction rate (inst/s) 8host_op_rate 189839 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 88494148 # Simulator tick rate (ticks/s) 10host_mem_usage 308956 # Number of bytes of host memory used 11host_seconds 1166.06 # Real time elapsed on the host | 7host_inst_rate 113414 # Simulator instruction rate (inst/s) 8host_op_rate 190092 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 88727502 # Simulator tick rate (ticks/s) 10host_mem_usage 308112 # Number of bytes of host memory used 11host_seconds 1164.51 # Real time elapsed on the host |
| 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221363384 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221363384 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 232704 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 130112 # Number of bytes read from this memory 19system.physmem.bytes_read::total 362816 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 232704 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 232704 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 3636 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 2033 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 5669 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 2255116 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 1260905 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 3516021 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 2255116 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 2255116 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 2255116 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 1260905 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 3516021 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 5669 # Number of read requests accepted | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 232832 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 130880 # Number of bytes read from this memory 19system.physmem.bytes_read::total 363712 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 232832 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 232832 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 3638 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 2045 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 5683 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 2253417 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 1266695 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 3520112 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 2253417 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 2253417 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 2253417 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 1266695 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 3520112 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 5683 # Number of read requests accepted |
| 34system.physmem.writeReqs 0 # Number of write requests accepted | 34system.physmem.writeReqs 0 # Number of write requests accepted |
| 35system.physmem.readBursts 5669 # Number of DRAM read bursts, including those serviced by the write queue | 35system.physmem.readBursts 5683 # Number of DRAM read bursts, including those serviced by the write queue |
| 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 37system.physmem.bytesReadDRAM 362816 # Total number of bytes read from DRAM | 37system.physmem.bytesReadDRAM 363712 # Total number of bytes read from DRAM |
| 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 40system.physmem.bytesReadSys 362816 # Total read bytes from the system interface side | 40system.physmem.bytesReadSys 363712 # Total read bytes from the system interface side |
| 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 45system.physmem.perBankRdBursts::0 309 # Per bank write bursts 46system.physmem.perBankRdBursts::1 384 # Per bank write bursts 47system.physmem.perBankRdBursts::2 476 # Per bank write bursts 48system.physmem.perBankRdBursts::3 363 # Per bank write bursts 49system.physmem.perBankRdBursts::4 357 # Per bank write bursts 50system.physmem.perBankRdBursts::5 335 # Per bank write bursts 51system.physmem.perBankRdBursts::6 419 # Per bank write bursts 52system.physmem.perBankRdBursts::7 395 # Per bank write bursts 53system.physmem.perBankRdBursts::8 387 # Per bank write bursts | 45system.physmem.perBankRdBursts::0 307 # Per bank write bursts 46system.physmem.perBankRdBursts::1 383 # Per bank write bursts 47system.physmem.perBankRdBursts::2 475 # Per bank write bursts 48system.physmem.perBankRdBursts::3 366 # Per bank write bursts 49system.physmem.perBankRdBursts::4 364 # Per bank write bursts 50system.physmem.perBankRdBursts::5 336 # Per bank write bursts 51system.physmem.perBankRdBursts::6 422 # Per bank write bursts 52system.physmem.perBankRdBursts::7 392 # Per bank write bursts 53system.physmem.perBankRdBursts::8 390 # Per bank write bursts |
| 54system.physmem.perBankRdBursts::9 296 # Per bank write bursts | 54system.physmem.perBankRdBursts::9 296 # Per bank write bursts |
| 55system.physmem.perBankRdBursts::10 260 # Per bank write bursts 56system.physmem.perBankRdBursts::11 268 # Per bank write bursts 57system.physmem.perBankRdBursts::12 228 # Per bank write bursts 58system.physmem.perBankRdBursts::13 486 # Per bank write bursts 59system.physmem.perBankRdBursts::14 420 # Per bank write bursts 60system.physmem.perBankRdBursts::15 286 # Per bank write bursts | 55system.physmem.perBankRdBursts::10 255 # Per bank write bursts 56system.physmem.perBankRdBursts::11 273 # Per bank write bursts 57system.physmem.perBankRdBursts::12 229 # Per bank write bursts 58system.physmem.perBankRdBursts::13 485 # Per bank write bursts 59system.physmem.perBankRdBursts::14 425 # Per bank write bursts 60system.physmem.perBankRdBursts::15 285 # Per bank write bursts |
| 61system.physmem.perBankWrBursts::0 0 # Per bank write bursts 62system.physmem.perBankWrBursts::1 0 # Per bank write bursts 63system.physmem.perBankWrBursts::2 0 # Per bank write bursts 64system.physmem.perBankWrBursts::3 0 # Per bank write bursts 65system.physmem.perBankWrBursts::4 0 # Per bank write bursts 66system.physmem.perBankWrBursts::5 0 # Per bank write bursts 67system.physmem.perBankWrBursts::6 0 # Per bank write bursts 68system.physmem.perBankWrBursts::7 0 # Per bank write bursts 69system.physmem.perBankWrBursts::8 0 # Per bank write bursts 70system.physmem.perBankWrBursts::9 0 # Per bank write bursts 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 61system.physmem.perBankWrBursts::0 0 # Per bank write bursts 62system.physmem.perBankWrBursts::1 0 # Per bank write bursts 63system.physmem.perBankWrBursts::2 0 # Per bank write bursts 64system.physmem.perBankWrBursts::3 0 # Per bank write bursts 65system.physmem.perBankWrBursts::4 0 # Per bank write bursts 66system.physmem.perBankWrBursts::5 0 # Per bank write bursts 67system.physmem.perBankWrBursts::6 0 # Per bank write bursts 68system.physmem.perBankWrBursts::7 0 # Per bank write bursts 69system.physmem.perBankWrBursts::8 0 # Per bank write bursts 70system.physmem.perBankWrBursts::9 0 # Per bank write bursts 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 79system.physmem.totGap 103189107000 # Total gap between requests | 79system.physmem.totGap 103323737000 # Total gap between requests |
| 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) | 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 86system.physmem.readPktSize::6 5669 # Read request sizes (log2) | 86system.physmem.readPktSize::6 5683 # Read request sizes (log2) |
| 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) | 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 94system.physmem.rdQLenPdf::0 4455 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::1 978 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 200 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see | 94system.physmem.rdQLenPdf::0 4460 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::1 973 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 211 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 30 # What read queue length does an incoming req see |
| 98system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 76 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 98system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 76 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 190system.physmem.bytesPerActivate::samples 1243 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 291.012068 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 164.006967 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 325.689818 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 565 45.45% 45.45% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 237 19.07% 64.52% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 95 7.64% 72.16% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 65 5.23% 77.39% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 45 3.62% 81.01% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 57 4.59% 85.60% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 29 2.33% 87.93% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 21 1.69% 89.62% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 129 10.38% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 1243 # Bytes accessed per row activation 204system.physmem.totQLat 180648250 # Total ticks spent queuing 205system.physmem.totMemAccLat 286942000 # Total ticks spent from burst creation until serviced by the DRAM 206system.physmem.totBusLat 28345000 # Total ticks spent in databus transfers 207system.physmem.avgQLat 31865.98 # Average queueing delay per DRAM burst | 190system.physmem.bytesPerActivate::samples 1258 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 287.745628 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 162.611559 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 323.712964 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 571 45.39% 45.39% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 250 19.87% 65.26% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 94 7.47% 72.73% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 65 5.17% 77.90% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 43 3.42% 81.32% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 57 4.53% 85.85% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 29 2.31% 88.16% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 22 1.75% 89.90% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 127 10.10% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 1258 # Bytes accessed per row activation 204system.physmem.totQLat 187208250 # Total ticks spent queuing 205system.physmem.totMemAccLat 293764500 # Total ticks spent from burst creation until serviced by the DRAM 206system.physmem.totBusLat 28415000 # Total ticks spent in databus transfers 207system.physmem.avgQLat 32941.80 # Average queueing delay per DRAM burst |
| 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 209system.physmem.avgMemAccLat 50615.98 # Average memory access latency per DRAM burst | 209system.physmem.avgMemAccLat 51691.80 # Average memory access latency per DRAM burst |
| 210system.physmem.avgRdBW 3.52 # Average DRAM read bandwidth in MiByte/s 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 212system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 0.03 # Data bus utilization in percentage 216system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 210system.physmem.avgRdBW 3.52 # Average DRAM read bandwidth in MiByte/s 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 212system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 0.03 # Data bus utilization in percentage 216system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 218system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing | 218system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing |
| 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 220system.physmem.readRowHits 4421 # Number of row buffer hits during reads | 220system.physmem.readRowHits 4417 # Number of row buffer hits during reads |
| 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 222system.physmem.readRowHitRate 77.99 # Row buffer hit rate for reads | 222system.physmem.readRowHitRate 77.72 # Row buffer hit rate for reads |
| 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 224system.physmem.avgGap 18202347.33 # Average gap between requests 225system.physmem.pageHitRate 77.99 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 5333580 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 2823480 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 21691320 # Energy for read commands per rank (pJ) | 224system.physmem.avgGap 18181196.02 # Average gap between requests 225system.physmem.pageHitRate 77.72 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 5404980 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 2853840 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 21741300 # Energy for read commands per rank (pJ) |
| 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) | 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 230system.physmem_0.refreshEnergy 286422240.000000 # Energy for refresh commands per rank (pJ) 231system.physmem_0.actBackEnergy 93806610 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 15765120 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 717579270 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 394813440 # Energy for precharge power-down per rank (pJ) 235system.physmem_0.selfRefreshEnergy 24141432120 # Energy for self refresh per rank (pJ) 236system.physmem_0.totalEnergy 25679671980 # Total energy per rank (pJ) 237system.physmem_0.averagePower 248.859682 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 102941166250 # Total Idle time Per DRAM Rank 239system.physmem_0.memoryStateTime::IDLE 30119500 # Time in different power states 240system.physmem_0.memoryStateTime::REF 121808000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 100340787250 # Time in different power states 242system.physmem_0.memoryStateTime::PRE_PDN 1028168000 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 94814000 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 1573665250 # Time in different power states 245system.physmem_1.actEnergy 3577140 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 1893705 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 18785340 # Energy for read commands per rank (pJ) | 230system.physmem_0.refreshEnergy 298715040.000000 # Energy for refresh commands per rank (pJ) 231system.physmem_0.actBackEnergy 95918460 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 16609440 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 744016440 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 410144160 # Energy for precharge power-down per rank (pJ) 235system.physmem_0.selfRefreshEnergy 24152474700 # Energy for self refresh per rank (pJ) 236system.physmem_0.totalEnergy 25747878360 # Total energy per rank (pJ) 237system.physmem_0.averagePower 249.195533 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 103070096750 # Total Idle time Per DRAM Rank 239system.physmem_0.memoryStateTime::IDLE 32003500 # Time in different power states 240system.physmem_0.memoryStateTime::REF 127050000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 100370697500 # Time in different power states 242system.physmem_0.memoryStateTime::PRE_PDN 1068078250 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 94522250 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 1631644000 # Time in different power states 245system.physmem_1.actEnergy 3634260 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 1920270 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 18835320 # Energy for read commands per rank (pJ) |
| 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) | 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 249system.physmem_1.refreshEnergy 224343600.000000 # Energy for refresh commands per rank (pJ) 250system.physmem_1.actBackEnergy 72770760 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 12467520 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 571365720 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 300199680 # Energy for precharge power-down per rank (pJ) 254system.physmem_1.selfRefreshEnergy 24277951200 # Energy for self refresh per rank (pJ) 255system.physmem_1.totalEnergy 25483354665 # Total energy per rank (pJ) 256system.physmem_1.averagePower 246.957187 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 102997073250 # Total Idle time Per DRAM Rank 258system.physmem_1.memoryStateTime::IDLE 23820000 # Time in different power states 259system.physmem_1.memoryStateTime::REF 95422000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 100962546500 # Time in different power states 261system.physmem_1.memoryStateTime::PRE_PDN 781772000 # Time in different power states 262system.physmem_1.memoryStateTime::ACT 72828000 # Time in different power states 263system.physmem_1.memoryStateTime::ACT_PDN 1252973500 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 40834752 # Number of BP lookups 266system.cpu.branchPred.condPredicted 40834752 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 6720926 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 35301077 # Number of BTB lookups | 249system.physmem_1.refreshEnergy 228031440.000000 # Energy for refresh commands per rank (pJ) 250system.physmem_1.actBackEnergy 73672500 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 12688320 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 586536840 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 299079840 # Energy for precharge power-down per rank (pJ) 254system.physmem_1.selfRefreshEnergy 24303470280 # Energy for self refresh per rank (pJ) 255system.physmem_1.totalEnergy 25527869070 # Total energy per rank (pJ) 256system.physmem_1.averagePower 247.066219 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 103129135750 # Total Idle time Per DRAM Rank 258system.physmem_1.memoryStateTime::IDLE 24348000 # Time in different power states 259system.physmem_1.memoryStateTime::REF 96994000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 101064274500 # Time in different power states 261system.physmem_1.memoryStateTime::PRE_PDN 778849000 # Time in different power states 262system.physmem_1.memoryStateTime::ACT 73295500 # Time in different power states 263system.physmem_1.memoryStateTime::ACT_PDN 1286234500 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 40855234 # Number of BP lookups 266system.cpu.branchPred.condPredicted 40855234 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 6727710 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 35293159 # Number of BTB lookups |
| 269system.cpu.branchPred.BTBHits 0 # Number of BTB hits 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 271system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage | 269system.cpu.branchPred.BTBHits 0 # Number of BTB hits 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 271system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage |
| 272system.cpu.branchPred.usedRAS 3198104 # Number of times the RAS was used to get a target. 273system.cpu.branchPred.RASInCorrect 606453 # Number of incorrect RAS predictions. 274system.cpu.branchPred.indirectLookups 35301077 # Number of indirect predictor lookups. 275system.cpu.branchPred.indirectHits 9875363 # Number of indirect target hits. 276system.cpu.branchPred.indirectMisses 25425714 # Number of indirect misses. 277system.cpu.branchPredindirectMispredicted 5011557 # Number of mispredicted indirect branches. | 272system.cpu.branchPred.usedRAS 3199678 # Number of times the RAS was used to get a target. 273system.cpu.branchPred.RASInCorrect 605841 # Number of incorrect RAS predictions. 274system.cpu.branchPred.indirectLookups 35293159 # Number of indirect predictor lookups. 275system.cpu.branchPred.indirectHits 9878902 # Number of indirect target hits. 276system.cpu.branchPred.indirectMisses 25414257 # Number of indirect misses. 277system.cpu.branchPredindirectMispredicted 5019418 # Number of mispredicted indirect branches. |
| 278system.cpu_clk_domain.clock 500 # Clock period in ticks | 278system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 279system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states | 279system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states |
| 280system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks | 280system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks |
| 281system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states 282system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states | 281system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states 282system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states |
| 283system.cpu.workload.num_syscalls 400 # Number of system calls | 283system.cpu.workload.num_syscalls 400 # Number of system calls |
| 284system.cpu.pwrStateResidencyTicks::ON 103189362000 # Cumulative time (in ticks) in various power states 285system.cpu.numCycles 206378725 # number of cpu cycles simulated | 284system.cpu.pwrStateResidencyTicks::ON 103323995500 # Cumulative time (in ticks) in various power states 285system.cpu.numCycles 206647992 # number of cpu cycles simulated |
| 286system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 287system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 286system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 287system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 288system.cpu.fetch.icacheStallCycles 46270336 # Number of cycles fetch is stalled on an Icache miss 289system.cpu.fetch.Insts 419359791 # Number of instructions fetch has processed 290system.cpu.fetch.Branches 40834752 # Number of branches that fetch encountered 291system.cpu.fetch.predictedBranches 13073467 # Number of branches that fetch has predicted taken 292system.cpu.fetch.Cycles 152339601 # Number of cycles fetch has run and was not squashing or blocked 293system.cpu.fetch.SquashCycles 14895691 # Number of cycles fetch has spent squashing 294system.cpu.fetch.TlbCycles 89 # Number of cycles fetch has spent waiting for tlb 295system.cpu.fetch.MiscStallCycles 5905 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 296system.cpu.fetch.PendingTrapStallCycles 73704 # Number of stall cycles due to pending traps 297system.cpu.fetch.PendingQuiesceStallCycles 808 # Number of stall cycles due to pending quiesce instructions 298system.cpu.fetch.IcacheWaitRetryStallCycles 184 # Number of stall cycles due to full MSHR 299system.cpu.fetch.CacheLines 41191275 # Number of cache lines fetched 300system.cpu.fetch.IcacheSquashes 1518616 # Number of outstanding Icache misses that were squashed 301system.cpu.fetch.ItlbSquashes 6 # Number of outstanding ITLB misses that were squashed 302system.cpu.fetch.rateDist::samples 206138472 # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::mean 3.415591 # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::stdev 3.660484 # Number of instructions fetched each cycle (Total) | 288system.cpu.fetch.icacheStallCycles 46314104 # Number of cycles fetch is stalled on an Icache miss 289system.cpu.fetch.Insts 419677545 # Number of instructions fetch has processed 290system.cpu.fetch.Branches 40855234 # Number of branches that fetch encountered 291system.cpu.fetch.predictedBranches 13078580 # Number of branches that fetch has predicted taken 292system.cpu.fetch.Cycles 152558577 # Number of cycles fetch has run and was not squashing or blocked 293system.cpu.fetch.SquashCycles 14911731 # Number of cycles fetch has spent squashing 294system.cpu.fetch.TlbCycles 146 # Number of cycles fetch has spent waiting for tlb 295system.cpu.fetch.MiscStallCycles 6162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 296system.cpu.fetch.PendingTrapStallCycles 75545 # Number of stall cycles due to pending traps 297system.cpu.fetch.PendingQuiesceStallCycles 535 # Number of stall cycles due to pending quiesce instructions 298system.cpu.fetch.IcacheWaitRetryStallCycles 173 # Number of stall cycles due to full MSHR 299system.cpu.fetch.CacheLines 41227932 # Number of cache lines fetched 300system.cpu.fetch.IcacheSquashes 1521125 # Number of outstanding Icache misses that were squashed 301system.cpu.fetch.ItlbSquashes 10 # Number of outstanding ITLB misses that were squashed 302system.cpu.fetch.rateDist::samples 206411107 # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::mean 3.413574 # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::stdev 3.660203 # Number of instructions fetched each cycle (Total) |
| 305system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 305system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 306system.cpu.fetch.rateDist::0 99063302 48.06% 48.06% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::1 5137465 2.49% 50.55% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::2 5366260 2.60% 53.15% # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::3 5330020 2.59% 55.74% # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::4 6010905 2.92% 58.65% # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::5 5824389 2.83% 61.48% # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::6 5722044 2.78% 64.26% # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::7 4745811 2.30% 66.56% # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::8 68938276 33.44% 100.00% # Number of instructions fetched each cycle (Total) | 306system.cpu.fetch.rateDist::0 99253613 48.09% 48.09% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::1 5140686 2.49% 50.58% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::2 5371591 2.60% 53.18% # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::3 5329252 2.58% 55.76% # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::4 6011005 2.91% 58.67% # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::5 5851603 2.83% 61.51% # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::6 5726027 2.77% 64.28% # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::7 4748810 2.30% 66.58% # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::8 68978520 33.42% 100.00% # Number of instructions fetched each cycle (Total) |
| 315system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 316system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 315system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 316system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 318system.cpu.fetch.rateDist::total 206138472 # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.branchRate 0.197863 # Number of branch fetches per cycle 320system.cpu.fetch.rate 2.031991 # Number of inst fetches per cycle 321system.cpu.decode.IdleCycles 32237214 # Number of cycles decode is idle 322system.cpu.decode.BlockedCycles 86447407 # Number of cycles decode is blocked 323system.cpu.decode.RunCycles 62317142 # Number of cycles decode is running 324system.cpu.decode.UnblockCycles 17688864 # Number of cycles decode is unblocking 325system.cpu.decode.SquashCycles 7447845 # Number of cycles decode is squashing 326system.cpu.decode.DecodedInsts 590237823 # Number of instructions handled by decode 327system.cpu.rename.SquashCycles 7447845 # Number of cycles rename is squashing 328system.cpu.rename.IdleCycles 42013779 # Number of cycles rename is idle 329system.cpu.rename.BlockCycles 46504501 # Number of cycles rename is blocking 330system.cpu.rename.serializeStallCycles 31211 # count of cycles rename stalled for serializing inst 331system.cpu.rename.RunCycles 68811152 # Number of cycles rename is running 332system.cpu.rename.UnblockCycles 41329984 # Number of cycles rename is unblocking 333system.cpu.rename.RenamedInsts 551593859 # Number of instructions processed by rename 334system.cpu.rename.ROBFullEvents 1410 # Number of times rename has blocked due to ROB full 335system.cpu.rename.IQFullEvents 36393589 # Number of times rename has blocked due to IQ full 336system.cpu.rename.LQFullEvents 4822156 # Number of times rename has blocked due to LQ full 337system.cpu.rename.SQFullEvents 169929 # Number of times rename has blocked due to SQ full 338system.cpu.rename.RenamedOperands 628796373 # Number of destination operands rename has renamed 339system.cpu.rename.RenameLookups 1484193525 # Number of register rename lookups that rename has made 340system.cpu.rename.int_rename_lookups 973498992 # Number of integer rename lookups 341system.cpu.rename.fp_rename_lookups 15084169 # Number of floating rename lookups | 318system.cpu.fetch.rateDist::total 206411107 # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.branchRate 0.197704 # Number of branch fetches per cycle 320system.cpu.fetch.rate 2.030881 # Number of inst fetches per cycle 321system.cpu.decode.IdleCycles 32267820 # Number of cycles decode is idle 322system.cpu.decode.BlockedCycles 86650194 # Number of cycles decode is blocked 323system.cpu.decode.RunCycles 62332865 # Number of cycles decode is running 324system.cpu.decode.UnblockCycles 17704363 # Number of cycles decode is unblocking 325system.cpu.decode.SquashCycles 7455865 # Number of cycles decode is squashing 326system.cpu.decode.DecodedInsts 590435256 # Number of instructions handled by decode 327system.cpu.rename.SquashCycles 7455865 # Number of cycles rename is squashing 328system.cpu.rename.IdleCycles 42053837 # Number of cycles rename is idle 329system.cpu.rename.BlockCycles 46607662 # Number of cycles rename is blocking 330system.cpu.rename.serializeStallCycles 29929 # count of cycles rename stalled for serializing inst 331system.cpu.rename.RunCycles 68827187 # Number of cycles rename is running 332system.cpu.rename.UnblockCycles 41436627 # Number of cycles rename is unblocking 333system.cpu.rename.RenamedInsts 551754102 # Number of instructions processed by rename 334system.cpu.rename.ROBFullEvents 1587 # Number of times rename has blocked due to ROB full 335system.cpu.rename.IQFullEvents 36503796 # Number of times rename has blocked due to IQ full 336system.cpu.rename.LQFullEvents 4817365 # Number of times rename has blocked due to LQ full 337system.cpu.rename.SQFullEvents 169314 # Number of times rename has blocked due to SQ full 338system.cpu.rename.RenamedOperands 629088770 # Number of destination operands rename has renamed 339system.cpu.rename.RenameLookups 1485013522 # Number of register rename lookups that rename has made 340system.cpu.rename.int_rename_lookups 974082903 # Number of integer rename lookups 341system.cpu.rename.fp_rename_lookups 15054868 # Number of floating rename lookups |
| 342system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed | 342system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed |
| 343system.cpu.rename.UndoneMaps 369366923 # Number of HB maps that are undone due to squashing 344system.cpu.rename.serializingInsts 2443 # count of serializing insts renamed 345system.cpu.rename.tempSerializingInsts 2459 # count of temporary serializing insts renamed 346system.cpu.rename.skidInsts 89351866 # count of insts added to the skid buffer 347system.cpu.memDep0.insertedLoads 128676829 # Number of loads inserted to the mem dependence unit. 348system.cpu.memDep0.insertedStores 45848779 # Number of stores inserted to the mem dependence unit. 349system.cpu.memDep0.conflictingLoads 77202780 # Number of conflicting loads. 350system.cpu.memDep0.conflictingStores 25186397 # Number of conflicting stores. 351system.cpu.iq.iqInstsAdded 489944627 # Number of instructions added to the IQ (excludes non-spec) 352system.cpu.iq.iqNonSpecInstsAdded 61663 # Number of non-speculative instructions added to the IQ 353system.cpu.iq.iqInstsIssued 338268196 # Number of instructions issued 354system.cpu.iq.iqSquashedInstsIssued 1105632 # Number of squashed instructions issued 355system.cpu.iq.iqSquashedInstsExamined 268642906 # Number of squashed instructions iterated over during squash; mainly for profiling 356system.cpu.iq.iqSquashedOperandsExamined 525336348 # Number of squashed operands that are examined and possibly removed from graph 357system.cpu.iq.iqSquashedNonSpecRemoved 60418 # Number of squashed non-spec instructions that were removed 358system.cpu.iq.issued_per_cycle::samples 206138472 # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::mean 1.640976 # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::stdev 1.805234 # Number of insts issued each cycle | 343system.cpu.rename.UndoneMaps 369659320 # Number of HB maps that are undone due to squashing 344system.cpu.rename.serializingInsts 2323 # count of serializing insts renamed 345system.cpu.rename.tempSerializingInsts 2340 # count of temporary serializing insts renamed 346system.cpu.rename.skidInsts 89508181 # count of insts added to the skid buffer 347system.cpu.memDep0.insertedLoads 128738720 # Number of loads inserted to the mem dependence unit. 348system.cpu.memDep0.insertedStores 45872059 # Number of stores inserted to the mem dependence unit. 349system.cpu.memDep0.conflictingLoads 77414851 # Number of conflicting loads. 350system.cpu.memDep0.conflictingStores 25246681 # Number of conflicting stores. 351system.cpu.iq.iqInstsAdded 490126112 # Number of instructions added to the IQ (excludes non-spec) 352system.cpu.iq.iqNonSpecInstsAdded 61893 # Number of non-speculative instructions added to the IQ 353system.cpu.iq.iqInstsIssued 338153574 # Number of instructions issued 354system.cpu.iq.iqSquashedInstsIssued 1099180 # Number of squashed instructions issued 355system.cpu.iq.iqSquashedInstsExamined 268824621 # Number of squashed instructions iterated over during squash; mainly for profiling 356system.cpu.iq.iqSquashedOperandsExamined 526308720 # Number of squashed operands that are examined and possibly removed from graph 357system.cpu.iq.iqSquashedNonSpecRemoved 60648 # Number of squashed non-spec instructions that were removed 358system.cpu.iq.issued_per_cycle::samples 206411107 # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::mean 1.638253 # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::stdev 1.802953 # Number of insts issued each cycle |
| 361system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 361system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 362system.cpu.iq.issued_per_cycle::0 73134407 35.48% 35.48% # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::1 46607709 22.61% 58.09% # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::2 32815647 15.92% 74.01% # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::3 20883524 10.13% 84.14% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::4 15044203 7.30% 91.44% # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::5 8407546 4.08% 95.51% # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::6 5216740 2.53% 98.05% # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::7 2365929 1.15% 99.19% # Number of insts issued each cycle 370system.cpu.iq.issued_per_cycle::8 1662767 0.81% 100.00% # Number of insts issued each cycle | 362system.cpu.iq.issued_per_cycle::0 73313522 35.52% 35.52% # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::1 46679908 22.62% 58.13% # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::2 32876430 15.93% 74.06% # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::3 20896006 10.12% 84.18% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::4 15048824 7.29% 91.48% # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::5 8392050 4.07% 95.54% # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::6 5201413 2.52% 98.06% # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::7 2354868 1.14% 99.20% # Number of insts issued each cycle 370system.cpu.iq.issued_per_cycle::8 1648086 0.80% 100.00% # Number of insts issued each cycle |
| 371system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 371system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 374system.cpu.iq.issued_per_cycle::total 206138472 # Number of insts issued each cycle | 374system.cpu.iq.issued_per_cycle::total 206411107 # Number of insts issued each cycle |
| 375system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 375system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 376system.cpu.iq.fu_full::IntAlu 759085 19.25% 19.25% # attempts to use FU when none available 377system.cpu.iq.fu_full::IntMult 0 0.00% 19.25% # attempts to use FU when none available 378system.cpu.iq.fu_full::IntDiv 0 0.00% 19.25% # attempts to use FU when none available 379system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.25% # attempts to use FU when none available 380system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.25% # attempts to use FU when none available 381system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.25% # attempts to use FU when none available 382system.cpu.iq.fu_full::FloatMult 0 0.00% 19.25% # attempts to use FU when none available 383system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 19.25% # attempts to use FU when none available 384system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.25% # attempts to use FU when none available 385system.cpu.iq.fu_full::FloatMisc 0 0.00% 19.25% # attempts to use FU when none available 386system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.25% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.25% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.25% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.25% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.25% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.25% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.25% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdMult 0 0.00% 19.25% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.25% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdShift 0 0.00% 19.25% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.25% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.25% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.25% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.25% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.25% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.25% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.25% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.25% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.25% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.25% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.25% # attempts to use FU when none available 407system.cpu.iq.fu_full::MemRead 2706167 68.61% 87.86% # attempts to use FU when none available 408system.cpu.iq.fu_full::MemWrite 429953 10.90% 98.76% # attempts to use FU when none available 409system.cpu.iq.fu_full::FloatMemRead 45275 1.15% 99.91% # attempts to use FU when none available 410system.cpu.iq.fu_full::FloatMemWrite 3569 0.09% 100.00% # attempts to use FU when none available | 376system.cpu.iq.fu_full::IntAlu 756912 19.27% 19.27% # attempts to use FU when none available 377system.cpu.iq.fu_full::IntMult 0 0.00% 19.27% # attempts to use FU when none available 378system.cpu.iq.fu_full::IntDiv 0 0.00% 19.27% # attempts to use FU when none available 379system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.27% # attempts to use FU when none available 380system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.27% # attempts to use FU when none available 381system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.27% # attempts to use FU when none available 382system.cpu.iq.fu_full::FloatMult 0 0.00% 19.27% # attempts to use FU when none available 383system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 19.27% # attempts to use FU when none available 384system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.27% # attempts to use FU when none available 385system.cpu.iq.fu_full::FloatMisc 0 0.00% 19.27% # attempts to use FU when none available 386system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.27% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.27% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.27% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.27% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.27% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.27% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.27% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdMult 0 0.00% 19.27% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.27% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdShift 0 0.00% 19.27% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.27% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.27% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.27% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.27% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.27% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.27% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.27% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.27% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.27% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.27% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.27% # attempts to use FU when none available 407system.cpu.iq.fu_full::MemRead 2690839 68.51% 87.78% # attempts to use FU when none available 408system.cpu.iq.fu_full::MemWrite 431049 10.97% 98.76% # attempts to use FU when none available 409system.cpu.iq.fu_full::FloatMemRead 45501 1.16% 99.91% # attempts to use FU when none available 410system.cpu.iq.fu_full::FloatMemWrite 3340 0.09% 100.00% # attempts to use FU when none available |
| 411system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 412system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 411system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 412system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 413system.cpu.iq.FU_type_0::No_OpClass 1211760 0.36% 0.36% # Type of FU issued 414system.cpu.iq.FU_type_0::IntAlu 216459489 63.99% 64.35% # Type of FU issued 415system.cpu.iq.FU_type_0::IntMult 800418 0.24% 64.59% # Type of FU issued 416system.cpu.iq.FU_type_0::IntDiv 7047773 2.08% 66.67% # Type of FU issued 417system.cpu.iq.FU_type_0::FloatAdd 1809637 0.53% 67.20% # Type of FU issued 418system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.20% # Type of FU issued 419system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.20% # Type of FU issued 420system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.20% # Type of FU issued 421system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.20% # Type of FU issued 422system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.20% # Type of FU issued 423system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.20% # Type of FU issued 424system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.20% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.20% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.20% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.20% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.20% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.20% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.20% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.20% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.20% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.20% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.20% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.20% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.20% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.20% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.20% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.20% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.20% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.20% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.20% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.20% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.20% # Type of FU issued 445system.cpu.iq.FU_type_0::MemRead 82580981 24.41% 91.62% # Type of FU issued 446system.cpu.iq.FU_type_0::MemWrite 26493050 7.83% 99.45% # Type of FU issued 447system.cpu.iq.FU_type_0::FloatMemRead 1734957 0.51% 99.96% # Type of FU issued 448system.cpu.iq.FU_type_0::FloatMemWrite 130131 0.04% 100.00% # Type of FU issued | 413system.cpu.iq.FU_type_0::No_OpClass 1211791 0.36% 0.36% # Type of FU issued 414system.cpu.iq.FU_type_0::IntAlu 216412325 64.00% 64.36% # Type of FU issued 415system.cpu.iq.FU_type_0::IntMult 800256 0.24% 64.59% # Type of FU issued 416system.cpu.iq.FU_type_0::IntDiv 7047583 2.08% 66.68% # Type of FU issued 417system.cpu.iq.FU_type_0::FloatAdd 1802667 0.53% 67.21% # Type of FU issued 418system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.21% # Type of FU issued 419system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.21% # Type of FU issued 420system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.21% # Type of FU issued 421system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.21% # Type of FU issued 422system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.21% # Type of FU issued 423system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.21% # Type of FU issued 424system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.21% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.21% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.21% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.21% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.21% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.21% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.21% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.21% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.21% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.21% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.21% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.21% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.21% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.21% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.21% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.21% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.21% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.21% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.21% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.21% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.21% # Type of FU issued 445system.cpu.iq.FU_type_0::MemRead 82552665 24.41% 91.62% # Type of FU issued 446system.cpu.iq.FU_type_0::MemWrite 26471074 7.83% 99.45% # Type of FU issued 447system.cpu.iq.FU_type_0::FloatMemRead 1726255 0.51% 99.96% # Type of FU issued 448system.cpu.iq.FU_type_0::FloatMemWrite 128958 0.04% 100.00% # Type of FU issued |
| 449system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 450system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 449system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 450system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 451system.cpu.iq.FU_type_0::total 338268196 # Type of FU issued 452system.cpu.iq.rate 1.639065 # Inst issue rate 453system.cpu.iq.fu_busy_cnt 3944049 # FU busy when requested 454system.cpu.iq.fu_busy_rate 0.011660 # FU busy rate (busy events/executed inst) 455system.cpu.iq.int_inst_queue_reads 879529534 # Number of integer instruction queue reads 456system.cpu.iq.int_inst_queue_writes 744046350 # Number of integer instruction queue writes 457system.cpu.iq.int_inst_queue_wakeup_accesses 315909602 # Number of integer instruction queue wakeup accesses 458system.cpu.iq.fp_inst_queue_reads 8195011 # Number of floating instruction queue reads 459system.cpu.iq.fp_inst_queue_writes 15431147 # Number of floating instruction queue writes 460system.cpu.iq.fp_inst_queue_wakeup_accesses 3556535 # Number of floating instruction queue wakeup accesses 461system.cpu.iq.int_alu_accesses 336881361 # Number of integer alu accesses 462system.cpu.iq.fp_alu_accesses 4119124 # Number of floating point alu accesses 463system.cpu.iew.lsq.thread0.forwLoads 18155877 # Number of loads that had data forwarded from stores | 451system.cpu.iq.FU_type_0::total 338153574 # Type of FU issued 452system.cpu.iq.rate 1.636375 # Inst issue rate 453system.cpu.iq.fu_busy_cnt 3927641 # FU busy when requested 454system.cpu.iq.fu_busy_rate 0.011615 # FU busy rate (busy events/executed inst) 455system.cpu.iq.int_inst_queue_reads 879585731 # Number of integer instruction queue reads 456system.cpu.iq.int_inst_queue_writes 744431622 # Number of integer instruction queue writes 457system.cpu.iq.int_inst_queue_wakeup_accesses 315835107 # Number of integer instruction queue wakeup accesses 458system.cpu.iq.fp_inst_queue_reads 8159345 # Number of floating instruction queue reads 459system.cpu.iq.fp_inst_queue_writes 15410519 # Number of floating instruction queue writes 460system.cpu.iq.fp_inst_queue_wakeup_accesses 3544176 # Number of floating instruction queue wakeup accesses 461system.cpu.iq.int_alu_accesses 336768258 # Number of integer alu accesses 462system.cpu.iq.fp_alu_accesses 4101166 # Number of floating point alu accesses 463system.cpu.iew.lsq.thread0.forwLoads 18155454 # Number of loads that had data forwarded from stores |
| 464system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 464system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 465system.cpu.iew.lsq.thread0.squashedLoads 72027242 # Number of loads squashed | 465system.cpu.iew.lsq.thread0.squashedLoads 72089133 # Number of loads squashed |
| 466system.cpu.iew.lsq.thread0.ignoredResponses 55091 # Number of memory responses ignored because the instruction is squashed | 466system.cpu.iew.lsq.thread0.ignoredResponses 55091 # Number of memory responses ignored because the instruction is squashed |
| 467system.cpu.iew.lsq.thread0.memOrderViolation 864575 # Number of memory ordering violations 468system.cpu.iew.lsq.thread0.squashedStores 25333062 # Number of stores squashed | 467system.cpu.iew.lsq.thread0.memOrderViolation 866955 # Number of memory ordering violations 468system.cpu.iew.lsq.thread0.squashedStores 25356342 # Number of stores squashed |
| 469system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 470system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 469system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 470system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 471system.cpu.iew.lsq.thread0.rescheduledLoads 50542 # Number of loads that were rescheduled 472system.cpu.iew.lsq.thread0.cacheBlocked 27 # Number of times an access to memory failed due to the cache being blocked | 471system.cpu.iew.lsq.thread0.rescheduledLoads 50448 # Number of loads that were rescheduled 472system.cpu.iew.lsq.thread0.cacheBlocked 55 # Number of times an access to memory failed due to the cache being blocked |
| 473system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 473system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 474system.cpu.iew.iewSquashCycles 7447845 # Number of cycles IEW is squashing 475system.cpu.iew.iewBlockCycles 35704467 # Number of cycles IEW is blocking 476system.cpu.iew.iewUnblockCycles 582987 # Number of cycles IEW is unblocking 477system.cpu.iew.iewDispatchedInsts 490006290 # Number of instructions dispatched to IQ 478system.cpu.iew.iewDispSquashedInsts 1248239 # Number of squashed instructions skipped by dispatch 479system.cpu.iew.iewDispLoadInsts 128676829 # Number of dispatched load instructions 480system.cpu.iew.iewDispStoreInsts 45848779 # Number of dispatched store instructions 481system.cpu.iew.iewDispNonSpecInsts 22549 # Number of dispatched non-speculative instructions 482system.cpu.iew.iewIQFullEvents 539423 # Number of times the IQ has become full, causing a stall 483system.cpu.iew.iewLSQFullEvents 38394 # Number of times the LSQ has become full, causing a stall 484system.cpu.iew.memOrderViolationEvents 864575 # Number of memory order violations 485system.cpu.iew.predictedTakenIncorrect 1296720 # Number of branches that were predicted taken incorrectly 486system.cpu.iew.predictedNotTakenIncorrect 6850218 # Number of branches that were predicted not taken incorrectly 487system.cpu.iew.branchMispredicts 8146938 # Number of branch mispredicts detected at execute 488system.cpu.iew.iewExecutedInsts 326347367 # Number of executed instructions 489system.cpu.iew.iewExecLoadInsts 80684613 # Number of load instructions executed 490system.cpu.iew.iewExecSquashedInsts 11920829 # Number of squashed instructions skipped in execute | 474system.cpu.iew.iewSquashCycles 7455865 # Number of cycles IEW is squashing 475system.cpu.iew.iewBlockCycles 35715167 # Number of cycles IEW is blocking 476system.cpu.iew.iewUnblockCycles 589866 # Number of cycles IEW is unblocking 477system.cpu.iew.iewDispatchedInsts 490188005 # Number of instructions dispatched to IQ 478system.cpu.iew.iewDispSquashedInsts 1248811 # Number of squashed instructions skipped by dispatch 479system.cpu.iew.iewDispLoadInsts 128738720 # Number of dispatched load instructions 480system.cpu.iew.iewDispStoreInsts 45872059 # Number of dispatched store instructions 481system.cpu.iew.iewDispNonSpecInsts 22561 # Number of dispatched non-speculative instructions 482system.cpu.iew.iewIQFullEvents 546009 # Number of times the IQ has become full, causing a stall 483system.cpu.iew.iewLSQFullEvents 38338 # Number of times the LSQ has become full, causing a stall 484system.cpu.iew.memOrderViolationEvents 866955 # Number of memory order violations 485system.cpu.iew.predictedTakenIncorrect 1295323 # Number of branches that were predicted taken incorrectly 486system.cpu.iew.predictedNotTakenIncorrect 6857589 # Number of branches that were predicted not taken incorrectly 487system.cpu.iew.branchMispredicts 8152912 # Number of branch mispredicts detected at execute 488system.cpu.iew.iewExecutedInsts 326241588 # Number of executed instructions 489system.cpu.iew.iewExecLoadInsts 80652390 # Number of load instructions executed 490system.cpu.iew.iewExecSquashedInsts 11911986 # Number of squashed instructions skipped in execute |
| 491system.cpu.iew.exec_swp 0 # number of swp insts executed 492system.cpu.iew.exec_nop 0 # number of nop insts executed | 491system.cpu.iew.exec_swp 0 # number of swp insts executed 492system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 493system.cpu.iew.exec_refs 106316260 # number of memory reference insts executed 494system.cpu.iew.exec_branches 18920718 # Number of branches executed 495system.cpu.iew.exec_stores 25631647 # Number of stores executed 496system.cpu.iew.exec_rate 1.581303 # Inst execution rate 497system.cpu.iew.wb_sent 322480012 # cumulative count of insts sent to commit 498system.cpu.iew.wb_count 319466137 # cumulative count of insts written-back 499system.cpu.iew.wb_producers 256417161 # num instructions producing a value 500system.cpu.iew.wb_consumers 435540007 # num instructions consuming a value 501system.cpu.iew.wb_rate 1.547961 # insts written-back per cycle 502system.cpu.iew.wb_fanout 0.588734 # average fanout of values written-back 503system.cpu.commit.commitSquashedInsts 268667644 # The number of squashed insts skipped by commit | 493system.cpu.iew.exec_refs 106269865 # number of memory reference insts executed 494system.cpu.iew.exec_branches 18918443 # Number of branches executed 495system.cpu.iew.exec_stores 25617475 # Number of stores executed 496system.cpu.iew.exec_rate 1.578731 # Inst execution rate 497system.cpu.iew.wb_sent 322387752 # cumulative count of insts sent to commit 498system.cpu.iew.wb_count 319379283 # cumulative count of insts written-back 499system.cpu.iew.wb_producers 256328359 # num instructions producing a value 500system.cpu.iew.wb_consumers 435429845 # num instructions consuming a value 501system.cpu.iew.wb_rate 1.545523 # insts written-back per cycle 502system.cpu.iew.wb_fanout 0.588679 # average fanout of values written-back 503system.cpu.commit.commitSquashedInsts 268850223 # The number of squashed insts skipped by commit |
| 504system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards | 504system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards |
| 505system.cpu.commit.branchMispredicts 6725958 # The number of times a branch was mispredicted 506system.cpu.commit.committed_per_cycle::samples 163655626 # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::mean 1.352617 # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::stdev 1.935975 # Number of insts commited each cycle | 505system.cpu.commit.branchMispredicts 6732902 # The number of times a branch was mispredicted 506system.cpu.commit.committed_per_cycle::samples 163914906 # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::mean 1.350477 # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::stdev 1.932475 # Number of insts commited each cycle |
| 509system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 509system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 510system.cpu.commit.committed_per_cycle::0 67077696 40.99% 40.99% # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::1 54856110 33.52% 74.51% # Number of insts commited each cycle 512system.cpu.commit.committed_per_cycle::2 13235317 8.09% 82.59% # Number of insts commited each cycle 513system.cpu.commit.committed_per_cycle::3 10672053 6.52% 89.11% # Number of insts commited each cycle 514system.cpu.commit.committed_per_cycle::4 5439540 3.32% 92.44% # Number of insts commited each cycle 515system.cpu.commit.committed_per_cycle::5 3134329 1.92% 94.35% # Number of insts commited each cycle 516system.cpu.commit.committed_per_cycle::6 1088236 0.66% 95.02% # Number of insts commited each cycle 517system.cpu.commit.committed_per_cycle::7 1157500 0.71% 95.73% # Number of insts commited each cycle 518system.cpu.commit.committed_per_cycle::8 6994845 4.27% 100.00% # Number of insts commited each cycle | 510system.cpu.commit.committed_per_cycle::0 67189595 40.99% 40.99% # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::1 54970007 33.54% 74.53% # Number of insts commited each cycle 512system.cpu.commit.committed_per_cycle::2 13274329 8.10% 82.62% # Number of insts commited each cycle 513system.cpu.commit.committed_per_cycle::3 10696589 6.53% 89.15% # Number of insts commited each cycle 514system.cpu.commit.committed_per_cycle::4 5450081 3.32% 92.48% # Number of insts commited each cycle 515system.cpu.commit.committed_per_cycle::5 3128441 1.91% 94.38% # Number of insts commited each cycle 516system.cpu.commit.committed_per_cycle::6 1086544 0.66% 95.05% # Number of insts commited each cycle 517system.cpu.commit.committed_per_cycle::7 1161401 0.71% 95.76% # Number of insts commited each cycle 518system.cpu.commit.committed_per_cycle::8 6957919 4.24% 100.00% # Number of insts commited each cycle |
| 519system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 519system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 522system.cpu.commit.committed_per_cycle::total 163655626 # Number of insts commited each cycle | 522system.cpu.commit.committed_per_cycle::total 163914906 # Number of insts commited each cycle |
| 523system.cpu.commit.committedInsts 132071192 # Number of instructions committed 524system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed 525system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 526system.cpu.commit.refs 77165304 # Number of memory references committed 527system.cpu.commit.loads 56649587 # Number of loads committed 528system.cpu.commit.membars 0 # Number of memory barriers committed 529system.cpu.commit.branches 12326938 # Number of branches committed 530system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. --- 33 unchanged lines hidden (view full) --- 564system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction 565system.cpu.commit.op_class_0::MemRead 55945136 25.27% 90.41% # Class of committed instruction 566system.cpu.commit.op_class_0::MemWrite 20410230 9.22% 99.63% # Class of committed instruction 567system.cpu.commit.op_class_0::FloatMemRead 704451 0.32% 99.95% # Class of committed instruction 568system.cpu.commit.op_class_0::FloatMemWrite 105487 0.05% 100.00% # Class of committed instruction 569system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 570system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 571system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction | 523system.cpu.commit.committedInsts 132071192 # Number of instructions committed 524system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed 525system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 526system.cpu.commit.refs 77165304 # Number of memory references committed 527system.cpu.commit.loads 56649587 # Number of loads committed 528system.cpu.commit.membars 0 # Number of memory barriers committed 529system.cpu.commit.branches 12326938 # Number of branches committed 530system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. --- 33 unchanged lines hidden (view full) --- 564system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction 565system.cpu.commit.op_class_0::MemRead 55945136 25.27% 90.41% # Class of committed instruction 566system.cpu.commit.op_class_0::MemWrite 20410230 9.22% 99.63% # Class of committed instruction 567system.cpu.commit.op_class_0::FloatMemRead 704451 0.32% 99.95% # Class of committed instruction 568system.cpu.commit.op_class_0::FloatMemWrite 105487 0.05% 100.00% # Class of committed instruction 569system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 570system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 571system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction |
| 572system.cpu.commit.bw_lim_events 6994845 # number cycles where commit BW limit reached 573system.cpu.rob.rob_reads 646691809 # The number of ROB reads 574system.cpu.rob.rob_writes 1022946396 # The number of ROB writes 575system.cpu.timesIdled 2819 # Number of times that the entire CPU went into an idle state and unscheduled itself 576system.cpu.idleCycles 240253 # Total number of cycles that the CPU has spent unscheduled due to idling | 572system.cpu.commit.bw_lim_events 6957919 # number cycles where commit BW limit reached 573system.cpu.rob.rob_reads 647170594 # The number of ROB reads 574system.cpu.rob.rob_writes 1023323556 # The number of ROB writes 575system.cpu.timesIdled 2853 # Number of times that the entire CPU went into an idle state and unscheduled itself 576system.cpu.idleCycles 236885 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 577system.cpu.committedInsts 132071192 # Number of Instructions Simulated 578system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated | 577system.cpu.committedInsts 132071192 # Number of Instructions Simulated 578system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated |
| 579system.cpu.cpi 1.562632 # CPI: Cycles Per Instruction 580system.cpu.cpi_total 1.562632 # CPI: Total CPI of All Threads 581system.cpu.ipc 0.639946 # IPC: Instructions Per Cycle 582system.cpu.ipc_total 0.639946 # IPC: Total IPC of All Threads 583system.cpu.int_regfile_reads 524499390 # number of integer regfile reads 584system.cpu.int_regfile_writes 288922915 # number of integer regfile writes 585system.cpu.fp_regfile_reads 4524370 # number of floating regfile reads 586system.cpu.fp_regfile_writes 3323309 # number of floating regfile writes 587system.cpu.cc_regfile_reads 107020933 # number of cc regfile reads 588system.cpu.cc_regfile_writes 65779043 # number of cc regfile writes 589system.cpu.misc_regfile_reads 176790948 # number of misc regfile reads | 579system.cpu.cpi 1.564671 # CPI: Cycles Per Instruction 580system.cpu.cpi_total 1.564671 # CPI: Total CPI of All Threads 581system.cpu.ipc 0.639112 # IPC: Instructions Per Cycle 582system.cpu.ipc_total 0.639112 # IPC: Total IPC of All Threads 583system.cpu.int_regfile_reads 524350393 # number of integer regfile reads 584system.cpu.int_regfile_writes 288862618 # number of integer regfile writes 585system.cpu.fp_regfile_reads 4510095 # number of floating regfile reads 586system.cpu.fp_regfile_writes 3309705 # number of floating regfile writes 587system.cpu.cc_regfile_reads 106995415 # number of cc regfile reads 588system.cpu.cc_regfile_writes 65768687 # number of cc regfile writes 589system.cpu.misc_regfile_reads 176729824 # number of misc regfile reads |
| 590system.cpu.misc_regfile_writes 1689 # number of misc regfile writes | 590system.cpu.misc_regfile_writes 1689 # number of misc regfile writes |
| 591system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states 592system.cpu.dcache.tags.replacements 81 # number of replacements 593system.cpu.dcache.tags.tagsinuse 1508.634180 # Cycle average of tags in use 594system.cpu.dcache.tags.total_refs 82760913 # Total number of references to valid blocks. 595system.cpu.dcache.tags.sampled_refs 2105 # Sample count of references to valid blocks. 596system.cpu.dcache.tags.avg_refs 39316.348219 # Average number of references to valid blocks. | 591system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states 592system.cpu.dcache.tags.replacements 82 # number of replacements 593system.cpu.dcache.tags.tagsinuse 1514.501359 # Cycle average of tags in use 594system.cpu.dcache.tags.total_refs 82730891 # Total number of references to valid blocks. 595system.cpu.dcache.tags.sampled_refs 2127 # Sample count of references to valid blocks. 596system.cpu.dcache.tags.avg_refs 38895.576399 # Average number of references to valid blocks. |
| 597system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 597system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 598system.cpu.dcache.tags.occ_blocks::cpu.data 1508.634180 # Average occupied blocks per requestor 599system.cpu.dcache.tags.occ_percent::cpu.data 0.368319 # Average percentage of cache occupancy 600system.cpu.dcache.tags.occ_percent::total 0.368319 # Average percentage of cache occupancy 601system.cpu.dcache.tags.occ_task_id_blocks::1024 2024 # Occupied blocks per task id 602system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id | 598system.cpu.dcache.tags.occ_blocks::cpu.data 1514.501359 # Average occupied blocks per requestor 599system.cpu.dcache.tags.occ_percent::cpu.data 0.369751 # Average percentage of cache occupancy 600system.cpu.dcache.tags.occ_percent::total 0.369751 # Average percentage of cache occupancy 601system.cpu.dcache.tags.occ_task_id_blocks::1024 2045 # Occupied blocks per task id 602system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id |
| 603system.cpu.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id | 603system.cpu.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id |
| 604system.cpu.dcache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id 605system.cpu.dcache.tags.age_task_id_blocks_1024::3 423 # Occupied blocks per task id 606system.cpu.dcache.tags.age_task_id_blocks_1024::4 1459 # Occupied blocks per task id 607system.cpu.dcache.tags.occ_task_id_percent::1024 0.494141 # Percentage of cache occupancy per task id 608system.cpu.dcache.tags.tag_accesses 165529197 # Number of tag accesses 609system.cpu.dcache.tags.data_accesses 165529197 # Number of data accesses 610system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states 611system.cpu.dcache.ReadReq_hits::cpu.data 62246604 # number of ReadReq hits 612system.cpu.dcache.ReadReq_hits::total 62246604 # number of ReadReq hits 613system.cpu.dcache.WriteReq_hits::cpu.data 20513664 # number of WriteReq hits 614system.cpu.dcache.WriteReq_hits::total 20513664 # number of WriteReq hits 615system.cpu.dcache.demand_hits::cpu.data 82760268 # number of demand (read+write) hits 616system.cpu.dcache.demand_hits::total 82760268 # number of demand (read+write) hits 617system.cpu.dcache.overall_hits::cpu.data 82760268 # number of overall hits 618system.cpu.dcache.overall_hits::total 82760268 # number of overall hits 619system.cpu.dcache.ReadReq_misses::cpu.data 1211 # number of ReadReq misses 620system.cpu.dcache.ReadReq_misses::total 1211 # number of ReadReq misses 621system.cpu.dcache.WriteReq_misses::cpu.data 2067 # number of WriteReq misses 622system.cpu.dcache.WriteReq_misses::total 2067 # number of WriteReq misses 623system.cpu.dcache.demand_misses::cpu.data 3278 # number of demand (read+write) misses 624system.cpu.dcache.demand_misses::total 3278 # number of demand (read+write) misses 625system.cpu.dcache.overall_misses::cpu.data 3278 # number of overall misses 626system.cpu.dcache.overall_misses::total 3278 # number of overall misses 627system.cpu.dcache.ReadReq_miss_latency::cpu.data 109883500 # number of ReadReq miss cycles 628system.cpu.dcache.ReadReq_miss_latency::total 109883500 # number of ReadReq miss cycles 629system.cpu.dcache.WriteReq_miss_latency::cpu.data 137432000 # number of WriteReq miss cycles 630system.cpu.dcache.WriteReq_miss_latency::total 137432000 # number of WriteReq miss cycles 631system.cpu.dcache.demand_miss_latency::cpu.data 247315500 # number of demand (read+write) miss cycles 632system.cpu.dcache.demand_miss_latency::total 247315500 # number of demand (read+write) miss cycles 633system.cpu.dcache.overall_miss_latency::cpu.data 247315500 # number of overall miss cycles 634system.cpu.dcache.overall_miss_latency::total 247315500 # number of overall miss cycles 635system.cpu.dcache.ReadReq_accesses::cpu.data 62247815 # number of ReadReq accesses(hits+misses) 636system.cpu.dcache.ReadReq_accesses::total 62247815 # number of ReadReq accesses(hits+misses) | 604system.cpu.dcache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id 605system.cpu.dcache.tags.age_task_id_blocks_1024::3 418 # Occupied blocks per task id 606system.cpu.dcache.tags.age_task_id_blocks_1024::4 1470 # Occupied blocks per task id 607system.cpu.dcache.tags.occ_task_id_percent::1024 0.499268 # Percentage of cache occupancy per task id 608system.cpu.dcache.tags.tag_accesses 165469279 # Number of tag accesses 609system.cpu.dcache.tags.data_accesses 165469279 # Number of data accesses 610system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states 611system.cpu.dcache.ReadReq_hits::cpu.data 62216578 # number of ReadReq hits 612system.cpu.dcache.ReadReq_hits::total 62216578 # number of ReadReq hits 613system.cpu.dcache.WriteReq_hits::cpu.data 20513684 # number of WriteReq hits 614system.cpu.dcache.WriteReq_hits::total 20513684 # number of WriteReq hits 615system.cpu.dcache.demand_hits::cpu.data 82730262 # number of demand (read+write) hits 616system.cpu.dcache.demand_hits::total 82730262 # number of demand (read+write) hits 617system.cpu.dcache.overall_hits::cpu.data 82730262 # number of overall hits 618system.cpu.dcache.overall_hits::total 82730262 # number of overall hits 619system.cpu.dcache.ReadReq_misses::cpu.data 1267 # number of ReadReq misses 620system.cpu.dcache.ReadReq_misses::total 1267 # number of ReadReq misses 621system.cpu.dcache.WriteReq_misses::cpu.data 2047 # number of WriteReq misses 622system.cpu.dcache.WriteReq_misses::total 2047 # number of WriteReq misses 623system.cpu.dcache.demand_misses::cpu.data 3314 # number of demand (read+write) misses 624system.cpu.dcache.demand_misses::total 3314 # number of demand (read+write) misses 625system.cpu.dcache.overall_misses::cpu.data 3314 # number of overall misses 626system.cpu.dcache.overall_misses::total 3314 # number of overall misses 627system.cpu.dcache.ReadReq_miss_latency::cpu.data 112642500 # number of ReadReq miss cycles 628system.cpu.dcache.ReadReq_miss_latency::total 112642500 # number of ReadReq miss cycles 629system.cpu.dcache.WriteReq_miss_latency::cpu.data 136500000 # number of WriteReq miss cycles 630system.cpu.dcache.WriteReq_miss_latency::total 136500000 # number of WriteReq miss cycles 631system.cpu.dcache.demand_miss_latency::cpu.data 249142500 # number of demand (read+write) miss cycles 632system.cpu.dcache.demand_miss_latency::total 249142500 # number of demand (read+write) miss cycles 633system.cpu.dcache.overall_miss_latency::cpu.data 249142500 # number of overall miss cycles 634system.cpu.dcache.overall_miss_latency::total 249142500 # number of overall miss cycles 635system.cpu.dcache.ReadReq_accesses::cpu.data 62217845 # number of ReadReq accesses(hits+misses) 636system.cpu.dcache.ReadReq_accesses::total 62217845 # number of ReadReq accesses(hits+misses) |
| 637system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) 638system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) | 637system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) 638system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) |
| 639system.cpu.dcache.demand_accesses::cpu.data 82763546 # number of demand (read+write) accesses 640system.cpu.dcache.demand_accesses::total 82763546 # number of demand (read+write) accesses 641system.cpu.dcache.overall_accesses::cpu.data 82763546 # number of overall (read+write) accesses 642system.cpu.dcache.overall_accesses::total 82763546 # number of overall (read+write) accesses 643system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses 644system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses 645system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000101 # miss rate for WriteReq accesses 646system.cpu.dcache.WriteReq_miss_rate::total 0.000101 # miss rate for WriteReq accesses | 639system.cpu.dcache.demand_accesses::cpu.data 82733576 # number of demand (read+write) accesses 640system.cpu.dcache.demand_accesses::total 82733576 # number of demand (read+write) accesses 641system.cpu.dcache.overall_accesses::cpu.data 82733576 # number of overall (read+write) accesses 642system.cpu.dcache.overall_accesses::total 82733576 # number of overall (read+write) accesses 643system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses 644system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses 645system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000100 # miss rate for WriteReq accesses 646system.cpu.dcache.WriteReq_miss_rate::total 0.000100 # miss rate for WriteReq accesses |
| 647system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses 648system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses 649system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses 650system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses | 647system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses 648system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses 649system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses 650system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses |
| 651system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 90737.819983 # average ReadReq miss latency 652system.cpu.dcache.ReadReq_avg_miss_latency::total 90737.819983 # average ReadReq miss latency 653system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66488.630866 # average WriteReq miss latency 654system.cpu.dcache.WriteReq_avg_miss_latency::total 66488.630866 # average WriteReq miss latency 655system.cpu.dcache.demand_avg_miss_latency::cpu.data 75447.071385 # average overall miss latency 656system.cpu.dcache.demand_avg_miss_latency::total 75447.071385 # average overall miss latency 657system.cpu.dcache.overall_avg_miss_latency::cpu.data 75447.071385 # average overall miss latency 658system.cpu.dcache.overall_avg_miss_latency::total 75447.071385 # average overall miss latency 659system.cpu.dcache.blocked_cycles::no_mshrs 307 # number of cycles access was blocked | 651system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 88904.893449 # average ReadReq miss latency 652system.cpu.dcache.ReadReq_avg_miss_latency::total 88904.893449 # average ReadReq miss latency 653system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66682.950660 # average WriteReq miss latency 654system.cpu.dcache.WriteReq_avg_miss_latency::total 66682.950660 # average WriteReq miss latency 655system.cpu.dcache.demand_avg_miss_latency::cpu.data 75178.786964 # average overall miss latency 656system.cpu.dcache.demand_avg_miss_latency::total 75178.786964 # average overall miss latency 657system.cpu.dcache.overall_avg_miss_latency::cpu.data 75178.786964 # average overall miss latency 658system.cpu.dcache.overall_avg_miss_latency::total 75178.786964 # average overall miss latency 659system.cpu.dcache.blocked_cycles::no_mshrs 331 # number of cycles access was blocked |
| 660system.cpu.dcache.blocked_cycles::no_targets 143 # number of cycles access was blocked 661system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked 662system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked | 660system.cpu.dcache.blocked_cycles::no_targets 143 # number of cycles access was blocked 661system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked 662system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked |
| 663system.cpu.dcache.avg_blocked_cycles::no_mshrs 76.750000 # average number of cycles each access was blocked | 663system.cpu.dcache.avg_blocked_cycles::no_mshrs 82.750000 # average number of cycles each access was blocked |
| 664system.cpu.dcache.avg_blocked_cycles::no_targets 71.500000 # average number of cycles each access was blocked | 664system.cpu.dcache.avg_blocked_cycles::no_targets 71.500000 # average number of cycles each access was blocked |
| 665system.cpu.dcache.writebacks::writebacks 16 # number of writebacks 666system.cpu.dcache.writebacks::total 16 # number of writebacks 667system.cpu.dcache.ReadReq_mshr_hits::cpu.data 626 # number of ReadReq MSHR hits 668system.cpu.dcache.ReadReq_mshr_hits::total 626 # number of ReadReq MSHR hits | 665system.cpu.dcache.writebacks::writebacks 17 # number of writebacks 666system.cpu.dcache.writebacks::total 17 # number of writebacks 667system.cpu.dcache.ReadReq_mshr_hits::cpu.data 658 # number of ReadReq MSHR hits 668system.cpu.dcache.ReadReq_mshr_hits::total 658 # number of ReadReq MSHR hits |
| 669system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6 # number of WriteReq MSHR hits 670system.cpu.dcache.WriteReq_mshr_hits::total 6 # number of WriteReq MSHR hits | 669system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6 # number of WriteReq MSHR hits 670system.cpu.dcache.WriteReq_mshr_hits::total 6 # number of WriteReq MSHR hits |
| 671system.cpu.dcache.demand_mshr_hits::cpu.data 632 # number of demand (read+write) MSHR hits 672system.cpu.dcache.demand_mshr_hits::total 632 # number of demand (read+write) MSHR hits 673system.cpu.dcache.overall_mshr_hits::cpu.data 632 # number of overall MSHR hits 674system.cpu.dcache.overall_mshr_hits::total 632 # number of overall MSHR hits 675system.cpu.dcache.ReadReq_mshr_misses::cpu.data 585 # number of ReadReq MSHR misses 676system.cpu.dcache.ReadReq_mshr_misses::total 585 # number of ReadReq MSHR misses 677system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2061 # number of WriteReq MSHR misses 678system.cpu.dcache.WriteReq_mshr_misses::total 2061 # number of WriteReq MSHR misses 679system.cpu.dcache.demand_mshr_misses::cpu.data 2646 # number of demand (read+write) MSHR misses 680system.cpu.dcache.demand_mshr_misses::total 2646 # number of demand (read+write) MSHR misses 681system.cpu.dcache.overall_mshr_misses::cpu.data 2646 # number of overall MSHR misses 682system.cpu.dcache.overall_mshr_misses::total 2646 # number of overall MSHR misses 683system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67088500 # number of ReadReq MSHR miss cycles 684system.cpu.dcache.ReadReq_mshr_miss_latency::total 67088500 # number of ReadReq MSHR miss cycles 685system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 134984000 # number of WriteReq MSHR miss cycles 686system.cpu.dcache.WriteReq_mshr_miss_latency::total 134984000 # number of WriteReq MSHR miss cycles 687system.cpu.dcache.demand_mshr_miss_latency::cpu.data 202072500 # number of demand (read+write) MSHR miss cycles 688system.cpu.dcache.demand_mshr_miss_latency::total 202072500 # number of demand (read+write) MSHR miss cycles 689system.cpu.dcache.overall_mshr_miss_latency::cpu.data 202072500 # number of overall MSHR miss cycles 690system.cpu.dcache.overall_mshr_miss_latency::total 202072500 # number of overall MSHR miss cycles 691system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses 692system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses 693system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000100 # mshr miss rate for WriteReq accesses 694system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000100 # mshr miss rate for WriteReq accesses | 671system.cpu.dcache.demand_mshr_hits::cpu.data 664 # number of demand (read+write) MSHR hits 672system.cpu.dcache.demand_mshr_hits::total 664 # number of demand (read+write) MSHR hits 673system.cpu.dcache.overall_mshr_hits::cpu.data 664 # number of overall MSHR hits 674system.cpu.dcache.overall_mshr_hits::total 664 # number of overall MSHR hits 675system.cpu.dcache.ReadReq_mshr_misses::cpu.data 609 # number of ReadReq MSHR misses 676system.cpu.dcache.ReadReq_mshr_misses::total 609 # number of ReadReq MSHR misses 677system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2041 # number of WriteReq MSHR misses 678system.cpu.dcache.WriteReq_mshr_misses::total 2041 # number of WriteReq MSHR misses 679system.cpu.dcache.demand_mshr_misses::cpu.data 2650 # number of demand (read+write) MSHR misses 680system.cpu.dcache.demand_mshr_misses::total 2650 # number of demand (read+write) MSHR misses 681system.cpu.dcache.overall_mshr_misses::cpu.data 2650 # number of overall MSHR misses 682system.cpu.dcache.overall_mshr_misses::total 2650 # number of overall MSHR misses 683system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70639000 # number of ReadReq MSHR miss cycles 684system.cpu.dcache.ReadReq_mshr_miss_latency::total 70639000 # number of ReadReq MSHR miss cycles 685system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 134072000 # number of WriteReq MSHR miss cycles 686system.cpu.dcache.WriteReq_mshr_miss_latency::total 134072000 # number of WriteReq MSHR miss cycles 687system.cpu.dcache.demand_mshr_miss_latency::cpu.data 204711000 # number of demand (read+write) MSHR miss cycles 688system.cpu.dcache.demand_mshr_miss_latency::total 204711000 # number of demand (read+write) MSHR miss cycles 689system.cpu.dcache.overall_mshr_miss_latency::cpu.data 204711000 # number of overall MSHR miss cycles 690system.cpu.dcache.overall_mshr_miss_latency::total 204711000 # number of overall MSHR miss cycles 691system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses 692system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses 693system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000099 # mshr miss rate for WriteReq accesses 694system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000099 # mshr miss rate for WriteReq accesses |
| 695system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses 696system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses 697system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses 698system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses | 695system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses 696system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses 697system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses 698system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses |
| 699system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 114681.196581 # average ReadReq mshr miss latency 700system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 114681.196581 # average ReadReq mshr miss latency 701system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65494.420184 # average WriteReq mshr miss latency 702system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65494.420184 # average WriteReq mshr miss latency 703system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76369.047619 # average overall mshr miss latency 704system.cpu.dcache.demand_avg_mshr_miss_latency::total 76369.047619 # average overall mshr miss latency 705system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76369.047619 # average overall mshr miss latency 706system.cpu.dcache.overall_avg_mshr_miss_latency::total 76369.047619 # average overall mshr miss latency 707system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states 708system.cpu.icache.tags.replacements 6530 # number of replacements 709system.cpu.icache.tags.tagsinuse 1674.310192 # Cycle average of tags in use 710system.cpu.icache.tags.total_refs 41178058 # Total number of references to valid blocks. 711system.cpu.icache.tags.sampled_refs 8518 # Sample count of references to valid blocks. 712system.cpu.icache.tags.avg_refs 4834.240197 # Average number of references to valid blocks. | 699system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115991.789819 # average ReadReq mshr miss latency 700system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115991.789819 # average ReadReq mshr miss latency 701system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65689.367957 # average WriteReq mshr miss latency 702system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65689.367957 # average WriteReq mshr miss latency 703system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77249.433962 # average overall mshr miss latency 704system.cpu.dcache.demand_avg_mshr_miss_latency::total 77249.433962 # average overall mshr miss latency 705system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77249.433962 # average overall mshr miss latency 706system.cpu.dcache.overall_avg_mshr_miss_latency::total 77249.433962 # average overall mshr miss latency 707system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states 708system.cpu.icache.tags.replacements 6640 # number of replacements 709system.cpu.icache.tags.tagsinuse 1671.571610 # Cycle average of tags in use 710system.cpu.icache.tags.total_refs 41214631 # Total number of references to valid blocks. 711system.cpu.icache.tags.sampled_refs 8628 # Sample count of references to valid blocks. 712system.cpu.icache.tags.avg_refs 4776.846430 # Average number of references to valid blocks. |
| 713system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 713system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 714system.cpu.icache.tags.occ_blocks::cpu.inst 1674.310192 # Average occupied blocks per requestor 715system.cpu.icache.tags.occ_percent::cpu.inst 0.817534 # Average percentage of cache occupancy 716system.cpu.icache.tags.occ_percent::total 0.817534 # Average percentage of cache occupancy | 714system.cpu.icache.tags.occ_blocks::cpu.inst 1671.571610 # Average occupied blocks per requestor 715system.cpu.icache.tags.occ_percent::cpu.inst 0.816197 # Average percentage of cache occupancy 716system.cpu.icache.tags.occ_percent::total 0.816197 # Average percentage of cache occupancy |
| 717system.cpu.icache.tags.occ_task_id_blocks::1024 1988 # Occupied blocks per task id | 717system.cpu.icache.tags.occ_task_id_blocks::1024 1988 # Occupied blocks per task id |
| 718system.cpu.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id 719system.cpu.icache.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id 720system.cpu.icache.tags.age_task_id_blocks_1024::2 841 # Occupied blocks per task id 721system.cpu.icache.tags.age_task_id_blocks_1024::3 142 # Occupied blocks per task id 722system.cpu.icache.tags.age_task_id_blocks_1024::4 742 # Occupied blocks per task id | 718system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id 719system.cpu.icache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id 720system.cpu.icache.tags.age_task_id_blocks_1024::2 860 # Occupied blocks per task id 721system.cpu.icache.tags.age_task_id_blocks_1024::3 163 # Occupied blocks per task id 722system.cpu.icache.tags.age_task_id_blocks_1024::4 713 # Occupied blocks per task id |
| 723system.cpu.icache.tags.occ_task_id_percent::1024 0.970703 # Percentage of cache occupancy per task id | 723system.cpu.icache.tags.occ_task_id_percent::1024 0.970703 # Percentage of cache occupancy per task id |
| 724system.cpu.icache.tags.tag_accesses 82391597 # Number of tag accesses 725system.cpu.icache.tags.data_accesses 82391597 # Number of data accesses 726system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states 727system.cpu.icache.ReadReq_hits::cpu.inst 41178058 # number of ReadReq hits 728system.cpu.icache.ReadReq_hits::total 41178058 # number of ReadReq hits 729system.cpu.icache.demand_hits::cpu.inst 41178058 # number of demand (read+write) hits 730system.cpu.icache.demand_hits::total 41178058 # number of demand (read+write) hits 731system.cpu.icache.overall_hits::cpu.inst 41178058 # number of overall hits 732system.cpu.icache.overall_hits::total 41178058 # number of overall hits 733system.cpu.icache.ReadReq_misses::cpu.inst 13213 # number of ReadReq misses 734system.cpu.icache.ReadReq_misses::total 13213 # number of ReadReq misses 735system.cpu.icache.demand_misses::cpu.inst 13213 # number of demand (read+write) misses 736system.cpu.icache.demand_misses::total 13213 # number of demand (read+write) misses 737system.cpu.icache.overall_misses::cpu.inst 13213 # number of overall misses 738system.cpu.icache.overall_misses::total 13213 # number of overall misses 739system.cpu.icache.ReadReq_miss_latency::cpu.inst 660957500 # number of ReadReq miss cycles 740system.cpu.icache.ReadReq_miss_latency::total 660957500 # number of ReadReq miss cycles 741system.cpu.icache.demand_miss_latency::cpu.inst 660957500 # number of demand (read+write) miss cycles 742system.cpu.icache.demand_miss_latency::total 660957500 # number of demand (read+write) miss cycles 743system.cpu.icache.overall_miss_latency::cpu.inst 660957500 # number of overall miss cycles 744system.cpu.icache.overall_miss_latency::total 660957500 # number of overall miss cycles 745system.cpu.icache.ReadReq_accesses::cpu.inst 41191271 # number of ReadReq accesses(hits+misses) 746system.cpu.icache.ReadReq_accesses::total 41191271 # number of ReadReq accesses(hits+misses) 747system.cpu.icache.demand_accesses::cpu.inst 41191271 # number of demand (read+write) accesses 748system.cpu.icache.demand_accesses::total 41191271 # number of demand (read+write) accesses 749system.cpu.icache.overall_accesses::cpu.inst 41191271 # number of overall (read+write) accesses 750system.cpu.icache.overall_accesses::total 41191271 # number of overall (read+write) accesses 751system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000321 # miss rate for ReadReq accesses 752system.cpu.icache.ReadReq_miss_rate::total 0.000321 # miss rate for ReadReq accesses 753system.cpu.icache.demand_miss_rate::cpu.inst 0.000321 # miss rate for demand accesses 754system.cpu.icache.demand_miss_rate::total 0.000321 # miss rate for demand accesses 755system.cpu.icache.overall_miss_rate::cpu.inst 0.000321 # miss rate for overall accesses 756system.cpu.icache.overall_miss_rate::total 0.000321 # miss rate for overall accesses 757system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50023.272535 # average ReadReq miss latency 758system.cpu.icache.ReadReq_avg_miss_latency::total 50023.272535 # average ReadReq miss latency 759system.cpu.icache.demand_avg_miss_latency::cpu.inst 50023.272535 # average overall miss latency 760system.cpu.icache.demand_avg_miss_latency::total 50023.272535 # average overall miss latency 761system.cpu.icache.overall_avg_miss_latency::cpu.inst 50023.272535 # average overall miss latency 762system.cpu.icache.overall_avg_miss_latency::total 50023.272535 # average overall miss latency 763system.cpu.icache.blocked_cycles::no_mshrs 1885 # number of cycles access was blocked 764system.cpu.icache.blocked_cycles::no_targets 842 # number of cycles access was blocked 765system.cpu.icache.blocked::no_mshrs 30 # number of cycles access was blocked | 724system.cpu.icache.tags.tag_accesses 82465000 # Number of tag accesses 725system.cpu.icache.tags.data_accesses 82465000 # Number of data accesses 726system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states 727system.cpu.icache.ReadReq_hits::cpu.inst 41214631 # number of ReadReq hits 728system.cpu.icache.ReadReq_hits::total 41214631 # number of ReadReq hits 729system.cpu.icache.demand_hits::cpu.inst 41214631 # number of demand (read+write) hits 730system.cpu.icache.demand_hits::total 41214631 # number of demand (read+write) hits 731system.cpu.icache.overall_hits::cpu.inst 41214631 # number of overall hits 732system.cpu.icache.overall_hits::total 41214631 # number of overall hits 733system.cpu.icache.ReadReq_misses::cpu.inst 13297 # number of ReadReq misses 734system.cpu.icache.ReadReq_misses::total 13297 # number of ReadReq misses 735system.cpu.icache.demand_misses::cpu.inst 13297 # number of demand (read+write) misses 736system.cpu.icache.demand_misses::total 13297 # number of demand (read+write) misses 737system.cpu.icache.overall_misses::cpu.inst 13297 # number of overall misses 738system.cpu.icache.overall_misses::total 13297 # number of overall misses 739system.cpu.icache.ReadReq_miss_latency::cpu.inst 657223000 # number of ReadReq miss cycles 740system.cpu.icache.ReadReq_miss_latency::total 657223000 # number of ReadReq miss cycles 741system.cpu.icache.demand_miss_latency::cpu.inst 657223000 # number of demand (read+write) miss cycles 742system.cpu.icache.demand_miss_latency::total 657223000 # number of demand (read+write) miss cycles 743system.cpu.icache.overall_miss_latency::cpu.inst 657223000 # number of overall miss cycles 744system.cpu.icache.overall_miss_latency::total 657223000 # number of overall miss cycles 745system.cpu.icache.ReadReq_accesses::cpu.inst 41227928 # number of ReadReq accesses(hits+misses) 746system.cpu.icache.ReadReq_accesses::total 41227928 # number of ReadReq accesses(hits+misses) 747system.cpu.icache.demand_accesses::cpu.inst 41227928 # number of demand (read+write) accesses 748system.cpu.icache.demand_accesses::total 41227928 # number of demand (read+write) accesses 749system.cpu.icache.overall_accesses::cpu.inst 41227928 # number of overall (read+write) accesses 750system.cpu.icache.overall_accesses::total 41227928 # number of overall (read+write) accesses 751system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000323 # miss rate for ReadReq accesses 752system.cpu.icache.ReadReq_miss_rate::total 0.000323 # miss rate for ReadReq accesses 753system.cpu.icache.demand_miss_rate::cpu.inst 0.000323 # miss rate for demand accesses 754system.cpu.icache.demand_miss_rate::total 0.000323 # miss rate for demand accesses 755system.cpu.icache.overall_miss_rate::cpu.inst 0.000323 # miss rate for overall accesses 756system.cpu.icache.overall_miss_rate::total 0.000323 # miss rate for overall accesses 757system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49426.411973 # average ReadReq miss latency 758system.cpu.icache.ReadReq_avg_miss_latency::total 49426.411973 # average ReadReq miss latency 759system.cpu.icache.demand_avg_miss_latency::cpu.inst 49426.411973 # average overall miss latency 760system.cpu.icache.demand_avg_miss_latency::total 49426.411973 # average overall miss latency 761system.cpu.icache.overall_avg_miss_latency::cpu.inst 49426.411973 # average overall miss latency 762system.cpu.icache.overall_avg_miss_latency::total 49426.411973 # average overall miss latency 763system.cpu.icache.blocked_cycles::no_mshrs 2020 # number of cycles access was blocked 764system.cpu.icache.blocked_cycles::no_targets 107 # number of cycles access was blocked 765system.cpu.icache.blocked::no_mshrs 32 # number of cycles access was blocked |
| 766system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked | 766system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked |
| 767system.cpu.icache.avg_blocked_cycles::no_mshrs 62.833333 # average number of cycles each access was blocked 768system.cpu.icache.avg_blocked_cycles::no_targets 842 # average number of cycles each access was blocked 769system.cpu.icache.writebacks::writebacks 6530 # number of writebacks 770system.cpu.icache.writebacks::total 6530 # number of writebacks 771system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4157 # number of ReadReq MSHR hits 772system.cpu.icache.ReadReq_mshr_hits::total 4157 # number of ReadReq MSHR hits 773system.cpu.icache.demand_mshr_hits::cpu.inst 4157 # number of demand (read+write) MSHR hits 774system.cpu.icache.demand_mshr_hits::total 4157 # number of demand (read+write) MSHR hits 775system.cpu.icache.overall_mshr_hits::cpu.inst 4157 # number of overall MSHR hits 776system.cpu.icache.overall_mshr_hits::total 4157 # number of overall MSHR hits 777system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9056 # number of ReadReq MSHR misses 778system.cpu.icache.ReadReq_mshr_misses::total 9056 # number of ReadReq MSHR misses 779system.cpu.icache.demand_mshr_misses::cpu.inst 9056 # number of demand (read+write) MSHR misses 780system.cpu.icache.demand_mshr_misses::total 9056 # number of demand (read+write) MSHR misses 781system.cpu.icache.overall_mshr_misses::cpu.inst 9056 # number of overall MSHR misses 782system.cpu.icache.overall_mshr_misses::total 9056 # number of overall MSHR misses 783system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 451350000 # number of ReadReq MSHR miss cycles 784system.cpu.icache.ReadReq_mshr_miss_latency::total 451350000 # number of ReadReq MSHR miss cycles 785system.cpu.icache.demand_mshr_miss_latency::cpu.inst 451350000 # number of demand (read+write) MSHR miss cycles 786system.cpu.icache.demand_mshr_miss_latency::total 451350000 # number of demand (read+write) MSHR miss cycles 787system.cpu.icache.overall_mshr_miss_latency::cpu.inst 451350000 # number of overall MSHR miss cycles 788system.cpu.icache.overall_mshr_miss_latency::total 451350000 # number of overall MSHR miss cycles 789system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000220 # mshr miss rate for ReadReq accesses 790system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000220 # mshr miss rate for ReadReq accesses 791system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000220 # mshr miss rate for demand accesses 792system.cpu.icache.demand_mshr_miss_rate::total 0.000220 # mshr miss rate for demand accesses 793system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000220 # mshr miss rate for overall accesses 794system.cpu.icache.overall_mshr_miss_rate::total 0.000220 # mshr miss rate for overall accesses 795system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49839.885159 # average ReadReq mshr miss latency 796system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49839.885159 # average ReadReq mshr miss latency 797system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49839.885159 # average overall mshr miss latency 798system.cpu.icache.demand_avg_mshr_miss_latency::total 49839.885159 # average overall mshr miss latency 799system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49839.885159 # average overall mshr miss latency 800system.cpu.icache.overall_avg_mshr_miss_latency::total 49839.885159 # average overall mshr miss latency 801system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states | 767system.cpu.icache.avg_blocked_cycles::no_mshrs 63.125000 # average number of cycles each access was blocked 768system.cpu.icache.avg_blocked_cycles::no_targets 107 # average number of cycles each access was blocked 769system.cpu.icache.writebacks::writebacks 6640 # number of writebacks 770system.cpu.icache.writebacks::total 6640 # number of writebacks 771system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4152 # number of ReadReq MSHR hits 772system.cpu.icache.ReadReq_mshr_hits::total 4152 # number of ReadReq MSHR hits 773system.cpu.icache.demand_mshr_hits::cpu.inst 4152 # number of demand (read+write) MSHR hits 774system.cpu.icache.demand_mshr_hits::total 4152 # number of demand (read+write) MSHR hits 775system.cpu.icache.overall_mshr_hits::cpu.inst 4152 # number of overall MSHR hits 776system.cpu.icache.overall_mshr_hits::total 4152 # number of overall MSHR hits 777system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9145 # number of ReadReq MSHR misses 778system.cpu.icache.ReadReq_mshr_misses::total 9145 # number of ReadReq MSHR misses 779system.cpu.icache.demand_mshr_misses::cpu.inst 9145 # number of demand (read+write) MSHR misses 780system.cpu.icache.demand_mshr_misses::total 9145 # number of demand (read+write) MSHR misses 781system.cpu.icache.overall_mshr_misses::cpu.inst 9145 # number of overall MSHR misses 782system.cpu.icache.overall_mshr_misses::total 9145 # number of overall MSHR misses 783system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 457240000 # number of ReadReq MSHR miss cycles 784system.cpu.icache.ReadReq_mshr_miss_latency::total 457240000 # number of ReadReq MSHR miss cycles 785system.cpu.icache.demand_mshr_miss_latency::cpu.inst 457240000 # number of demand (read+write) MSHR miss cycles 786system.cpu.icache.demand_mshr_miss_latency::total 457240000 # number of demand (read+write) MSHR miss cycles 787system.cpu.icache.overall_mshr_miss_latency::cpu.inst 457240000 # number of overall MSHR miss cycles 788system.cpu.icache.overall_mshr_miss_latency::total 457240000 # number of overall MSHR miss cycles 789system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000222 # mshr miss rate for ReadReq accesses 790system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000222 # mshr miss rate for ReadReq accesses 791system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000222 # mshr miss rate for demand accesses 792system.cpu.icache.demand_mshr_miss_rate::total 0.000222 # mshr miss rate for demand accesses 793system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000222 # mshr miss rate for overall accesses 794system.cpu.icache.overall_mshr_miss_rate::total 0.000222 # mshr miss rate for overall accesses 795system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49998.906506 # average ReadReq mshr miss latency 796system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49998.906506 # average ReadReq mshr miss latency 797system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49998.906506 # average overall mshr miss latency 798system.cpu.icache.demand_avg_mshr_miss_latency::total 49998.906506 # average overall mshr miss latency 799system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49998.906506 # average overall mshr miss latency 800system.cpu.icache.overall_avg_mshr_miss_latency::total 49998.906506 # average overall mshr miss latency 801system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states |
| 802system.cpu.l2cache.tags.replacements 0 # number of replacements | 802system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 803system.cpu.l2cache.tags.tagsinuse 3894.223765 # Cycle average of tags in use 804system.cpu.l2cache.tags.total_refs 12041 # Total number of references to valid blocks. 805system.cpu.l2cache.tags.sampled_refs 5669 # Sample count of references to valid blocks. 806system.cpu.l2cache.tags.avg_refs 2.124008 # Average number of references to valid blocks. | 803system.cpu.l2cache.tags.tagsinuse 3890.572014 # Cycle average of tags in use 804system.cpu.l2cache.tags.total_refs 12247 # Total number of references to valid blocks. 805system.cpu.l2cache.tags.sampled_refs 5683 # Sample count of references to valid blocks. 806system.cpu.l2cache.tags.avg_refs 2.155024 # Average number of references to valid blocks. |
| 807system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 807system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 808system.cpu.l2cache.tags.occ_blocks::cpu.inst 2411.748228 # Average occupied blocks per requestor 809system.cpu.l2cache.tags.occ_blocks::cpu.data 1482.475537 # Average occupied blocks per requestor 810system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073601 # Average percentage of cache occupancy 811system.cpu.l2cache.tags.occ_percent::cpu.data 0.045242 # Average percentage of cache occupancy 812system.cpu.l2cache.tags.occ_percent::total 0.118842 # Average percentage of cache occupancy 813system.cpu.l2cache.tags.occ_task_id_blocks::1024 5669 # Occupied blocks per task id 814system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id 815system.cpu.l2cache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id 816system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1008 # Occupied blocks per task id 817system.cpu.l2cache.tags.age_task_id_blocks_1024::3 525 # Occupied blocks per task id 818system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3930 # Occupied blocks per task id 819system.cpu.l2cache.tags.occ_task_id_percent::1024 0.173004 # Percentage of cache occupancy per task id 820system.cpu.l2cache.tags.tag_accesses 147349 # Number of tag accesses 821system.cpu.l2cache.tags.data_accesses 147349 # Number of data accesses 822system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states 823system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits 824system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits 825system.cpu.l2cache.WritebackClean_hits::writebacks 6476 # number of WritebackClean hits 826system.cpu.l2cache.WritebackClean_hits::total 6476 # number of WritebackClean hits 827system.cpu.l2cache.UpgradeReq_hits::cpu.data 541 # number of UpgradeReq hits 828system.cpu.l2cache.UpgradeReq_hits::total 541 # number of UpgradeReq hits | 808system.cpu.l2cache.tags.occ_blocks::cpu.inst 2409.860843 # Average occupied blocks per requestor 809system.cpu.l2cache.tags.occ_blocks::cpu.data 1480.711171 # Average occupied blocks per requestor 810system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073543 # Average percentage of cache occupancy 811system.cpu.l2cache.tags.occ_percent::cpu.data 0.045188 # Average percentage of cache occupancy 812system.cpu.l2cache.tags.occ_percent::total 0.118731 # Average percentage of cache occupancy 813system.cpu.l2cache.tags.occ_task_id_blocks::1024 5683 # Occupied blocks per task id 814system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 815system.cpu.l2cache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id 816system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1019 # Occupied blocks per task id 817system.cpu.l2cache.tags.age_task_id_blocks_1024::3 527 # Occupied blocks per task id 818system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3926 # Occupied blocks per task id 819system.cpu.l2cache.tags.occ_task_id_percent::1024 0.173431 # Percentage of cache occupancy per task id 820system.cpu.l2cache.tags.tag_accesses 149123 # Number of tag accesses 821system.cpu.l2cache.tags.data_accesses 149123 # Number of data accesses 822system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states 823system.cpu.l2cache.WritebackDirty_hits::writebacks 17 # number of WritebackDirty hits 824system.cpu.l2cache.WritebackDirty_hits::total 17 # number of WritebackDirty hits 825system.cpu.l2cache.WritebackClean_hits::writebacks 6583 # number of WritebackClean hits 826system.cpu.l2cache.WritebackClean_hits::total 6583 # number of WritebackClean hits 827system.cpu.l2cache.UpgradeReq_hits::cpu.data 523 # number of UpgradeReq hits 828system.cpu.l2cache.UpgradeReq_hits::total 523 # number of UpgradeReq hits |
| 829system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # number of ReadExReq hits 830system.cpu.l2cache.ReadExReq_hits::total 7 # number of ReadExReq hits | 829system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # number of ReadExReq hits 830system.cpu.l2cache.ReadExReq_hits::total 7 # number of ReadExReq hits |
| 831system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4877 # number of ReadCleanReq hits 832system.cpu.l2cache.ReadCleanReq_hits::total 4877 # number of ReadCleanReq hits 833system.cpu.l2cache.ReadSharedReq_hits::cpu.data 65 # number of ReadSharedReq hits 834system.cpu.l2cache.ReadSharedReq_hits::total 65 # number of ReadSharedReq hits 835system.cpu.l2cache.demand_hits::cpu.inst 4877 # number of demand (read+write) hits 836system.cpu.l2cache.demand_hits::cpu.data 72 # number of demand (read+write) hits 837system.cpu.l2cache.demand_hits::total 4949 # number of demand (read+write) hits 838system.cpu.l2cache.overall_hits::cpu.inst 4877 # number of overall hits 839system.cpu.l2cache.overall_hits::cpu.data 72 # number of overall hits 840system.cpu.l2cache.overall_hits::total 4949 # number of overall hits 841system.cpu.l2cache.ReadExReq_misses::cpu.data 1515 # number of ReadExReq misses 842system.cpu.l2cache.ReadExReq_misses::total 1515 # number of ReadExReq misses 843system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3636 # number of ReadCleanReq misses 844system.cpu.l2cache.ReadCleanReq_misses::total 3636 # number of ReadCleanReq misses 845system.cpu.l2cache.ReadSharedReq_misses::cpu.data 518 # number of ReadSharedReq misses 846system.cpu.l2cache.ReadSharedReq_misses::total 518 # number of ReadSharedReq misses 847system.cpu.l2cache.demand_misses::cpu.inst 3636 # number of demand (read+write) misses 848system.cpu.l2cache.demand_misses::cpu.data 2033 # number of demand (read+write) misses 849system.cpu.l2cache.demand_misses::total 5669 # number of demand (read+write) misses 850system.cpu.l2cache.overall_misses::cpu.inst 3636 # number of overall misses 851system.cpu.l2cache.overall_misses::cpu.data 2033 # number of overall misses 852system.cpu.l2cache.overall_misses::total 5669 # number of overall misses 853system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 125752500 # number of ReadExReq miss cycles 854system.cpu.l2cache.ReadExReq_miss_latency::total 125752500 # number of ReadExReq miss cycles 855system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 385523500 # number of ReadCleanReq miss cycles 856system.cpu.l2cache.ReadCleanReq_miss_latency::total 385523500 # number of ReadCleanReq miss cycles 857system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 65306000 # number of ReadSharedReq miss cycles 858system.cpu.l2cache.ReadSharedReq_miss_latency::total 65306000 # number of ReadSharedReq miss cycles 859system.cpu.l2cache.demand_miss_latency::cpu.inst 385523500 # number of demand (read+write) miss cycles 860system.cpu.l2cache.demand_miss_latency::cpu.data 191058500 # number of demand (read+write) miss cycles 861system.cpu.l2cache.demand_miss_latency::total 576582000 # number of demand (read+write) miss cycles 862system.cpu.l2cache.overall_miss_latency::cpu.inst 385523500 # number of overall miss cycles 863system.cpu.l2cache.overall_miss_latency::cpu.data 191058500 # number of overall miss cycles 864system.cpu.l2cache.overall_miss_latency::total 576582000 # number of overall miss cycles 865system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses) 866system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses) 867system.cpu.l2cache.WritebackClean_accesses::writebacks 6476 # number of WritebackClean accesses(hits+misses) 868system.cpu.l2cache.WritebackClean_accesses::total 6476 # number of WritebackClean accesses(hits+misses) 869system.cpu.l2cache.UpgradeReq_accesses::cpu.data 541 # number of UpgradeReq accesses(hits+misses) 870system.cpu.l2cache.UpgradeReq_accesses::total 541 # number of UpgradeReq accesses(hits+misses) 871system.cpu.l2cache.ReadExReq_accesses::cpu.data 1522 # number of ReadExReq accesses(hits+misses) 872system.cpu.l2cache.ReadExReq_accesses::total 1522 # number of ReadExReq accesses(hits+misses) 873system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8513 # number of ReadCleanReq accesses(hits+misses) 874system.cpu.l2cache.ReadCleanReq_accesses::total 8513 # number of ReadCleanReq accesses(hits+misses) 875system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 583 # number of ReadSharedReq accesses(hits+misses) 876system.cpu.l2cache.ReadSharedReq_accesses::total 583 # number of ReadSharedReq accesses(hits+misses) 877system.cpu.l2cache.demand_accesses::cpu.inst 8513 # number of demand (read+write) accesses 878system.cpu.l2cache.demand_accesses::cpu.data 2105 # number of demand (read+write) accesses 879system.cpu.l2cache.demand_accesses::total 10618 # number of demand (read+write) accesses 880system.cpu.l2cache.overall_accesses::cpu.inst 8513 # number of overall (read+write) accesses 881system.cpu.l2cache.overall_accesses::cpu.data 2105 # number of overall (read+write) accesses 882system.cpu.l2cache.overall_accesses::total 10618 # number of overall (read+write) accesses 883system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995401 # miss rate for ReadExReq accesses 884system.cpu.l2cache.ReadExReq_miss_rate::total 0.995401 # miss rate for ReadExReq accesses 885system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.427111 # miss rate for ReadCleanReq accesses 886system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.427111 # miss rate for ReadCleanReq accesses 887system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.888508 # miss rate for ReadSharedReq accesses 888system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.888508 # miss rate for ReadSharedReq accesses 889system.cpu.l2cache.demand_miss_rate::cpu.inst 0.427111 # miss rate for demand accesses 890system.cpu.l2cache.demand_miss_rate::cpu.data 0.965796 # miss rate for demand accesses 891system.cpu.l2cache.demand_miss_rate::total 0.533905 # miss rate for demand accesses 892system.cpu.l2cache.overall_miss_rate::cpu.inst 0.427111 # miss rate for overall accesses 893system.cpu.l2cache.overall_miss_rate::cpu.data 0.965796 # miss rate for overall accesses 894system.cpu.l2cache.overall_miss_rate::total 0.533905 # miss rate for overall accesses 895system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83004.950495 # average ReadExReq miss latency 896system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83004.950495 # average ReadExReq miss latency 897system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 106029.565457 # average ReadCleanReq miss latency 898system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 106029.565457 # average ReadCleanReq miss latency 899system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 126073.359073 # average ReadSharedReq miss latency 900system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 126073.359073 # average ReadSharedReq miss latency 901system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 106029.565457 # average overall miss latency 902system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93978.603050 # average overall miss latency 903system.cpu.l2cache.demand_avg_miss_latency::total 101707.884989 # average overall miss latency 904system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 106029.565457 # average overall miss latency 905system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93978.603050 # average overall miss latency 906system.cpu.l2cache.overall_avg_miss_latency::total 101707.884989 # average overall miss latency | 831system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4982 # number of ReadCleanReq hits 832system.cpu.l2cache.ReadCleanReq_hits::total 4982 # number of ReadCleanReq hits 833system.cpu.l2cache.ReadSharedReq_hits::cpu.data 75 # number of ReadSharedReq hits 834system.cpu.l2cache.ReadSharedReq_hits::total 75 # number of ReadSharedReq hits 835system.cpu.l2cache.demand_hits::cpu.inst 4982 # number of demand (read+write) hits 836system.cpu.l2cache.demand_hits::cpu.data 82 # number of demand (read+write) hits 837system.cpu.l2cache.demand_hits::total 5064 # number of demand (read+write) hits 838system.cpu.l2cache.overall_hits::cpu.inst 4982 # number of overall hits 839system.cpu.l2cache.overall_hits::cpu.data 82 # number of overall hits 840system.cpu.l2cache.overall_hits::total 5064 # number of overall hits 841system.cpu.l2cache.ReadExReq_misses::cpu.data 1513 # number of ReadExReq misses 842system.cpu.l2cache.ReadExReq_misses::total 1513 # number of ReadExReq misses 843system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3638 # number of ReadCleanReq misses 844system.cpu.l2cache.ReadCleanReq_misses::total 3638 # number of ReadCleanReq misses 845system.cpu.l2cache.ReadSharedReq_misses::cpu.data 532 # number of ReadSharedReq misses 846system.cpu.l2cache.ReadSharedReq_misses::total 532 # number of ReadSharedReq misses 847system.cpu.l2cache.demand_misses::cpu.inst 3638 # number of demand (read+write) misses 848system.cpu.l2cache.demand_misses::cpu.data 2045 # number of demand (read+write) misses 849system.cpu.l2cache.demand_misses::total 5683 # number of demand (read+write) misses 850system.cpu.l2cache.overall_misses::cpu.inst 3638 # number of overall misses 851system.cpu.l2cache.overall_misses::cpu.data 2045 # number of overall misses 852system.cpu.l2cache.overall_misses::total 5683 # number of overall misses 853system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 125080500 # number of ReadExReq miss cycles 854system.cpu.l2cache.ReadExReq_miss_latency::total 125080500 # number of ReadExReq miss cycles 855system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 390212000 # number of ReadCleanReq miss cycles 856system.cpu.l2cache.ReadCleanReq_miss_latency::total 390212000 # number of ReadCleanReq miss cycles 857system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 68692500 # number of ReadSharedReq miss cycles 858system.cpu.l2cache.ReadSharedReq_miss_latency::total 68692500 # number of ReadSharedReq miss cycles 859system.cpu.l2cache.demand_miss_latency::cpu.inst 390212000 # number of demand (read+write) miss cycles 860system.cpu.l2cache.demand_miss_latency::cpu.data 193773000 # number of demand (read+write) miss cycles 861system.cpu.l2cache.demand_miss_latency::total 583985000 # number of demand (read+write) miss cycles 862system.cpu.l2cache.overall_miss_latency::cpu.inst 390212000 # number of overall miss cycles 863system.cpu.l2cache.overall_miss_latency::cpu.data 193773000 # number of overall miss cycles 864system.cpu.l2cache.overall_miss_latency::total 583985000 # number of overall miss cycles 865system.cpu.l2cache.WritebackDirty_accesses::writebacks 17 # number of WritebackDirty accesses(hits+misses) 866system.cpu.l2cache.WritebackDirty_accesses::total 17 # number of WritebackDirty accesses(hits+misses) 867system.cpu.l2cache.WritebackClean_accesses::writebacks 6583 # number of WritebackClean accesses(hits+misses) 868system.cpu.l2cache.WritebackClean_accesses::total 6583 # number of WritebackClean accesses(hits+misses) 869system.cpu.l2cache.UpgradeReq_accesses::cpu.data 523 # number of UpgradeReq accesses(hits+misses) 870system.cpu.l2cache.UpgradeReq_accesses::total 523 # number of UpgradeReq accesses(hits+misses) 871system.cpu.l2cache.ReadExReq_accesses::cpu.data 1520 # number of ReadExReq accesses(hits+misses) 872system.cpu.l2cache.ReadExReq_accesses::total 1520 # number of ReadExReq accesses(hits+misses) 873system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8620 # number of ReadCleanReq accesses(hits+misses) 874system.cpu.l2cache.ReadCleanReq_accesses::total 8620 # number of ReadCleanReq accesses(hits+misses) 875system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 607 # number of ReadSharedReq accesses(hits+misses) 876system.cpu.l2cache.ReadSharedReq_accesses::total 607 # number of ReadSharedReq accesses(hits+misses) 877system.cpu.l2cache.demand_accesses::cpu.inst 8620 # number of demand (read+write) accesses 878system.cpu.l2cache.demand_accesses::cpu.data 2127 # number of demand (read+write) accesses 879system.cpu.l2cache.demand_accesses::total 10747 # number of demand (read+write) accesses 880system.cpu.l2cache.overall_accesses::cpu.inst 8620 # number of overall (read+write) accesses 881system.cpu.l2cache.overall_accesses::cpu.data 2127 # number of overall (read+write) accesses 882system.cpu.l2cache.overall_accesses::total 10747 # number of overall (read+write) accesses 883system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995395 # miss rate for ReadExReq accesses 884system.cpu.l2cache.ReadExReq_miss_rate::total 0.995395 # miss rate for ReadExReq accesses 885system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.422042 # miss rate for ReadCleanReq accesses 886system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.422042 # miss rate for ReadCleanReq accesses 887system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.876442 # miss rate for ReadSharedReq accesses 888system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.876442 # miss rate for ReadSharedReq accesses 889system.cpu.l2cache.demand_miss_rate::cpu.inst 0.422042 # miss rate for demand accesses 890system.cpu.l2cache.demand_miss_rate::cpu.data 0.961448 # miss rate for demand accesses 891system.cpu.l2cache.demand_miss_rate::total 0.528799 # miss rate for demand accesses 892system.cpu.l2cache.overall_miss_rate::cpu.inst 0.422042 # miss rate for overall accesses 893system.cpu.l2cache.overall_miss_rate::cpu.data 0.961448 # miss rate for overall accesses 894system.cpu.l2cache.overall_miss_rate::total 0.528799 # miss rate for overall accesses 895system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82670.522141 # average ReadExReq miss latency 896system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82670.522141 # average ReadExReq miss latency 897system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 107260.032985 # average ReadCleanReq miss latency 898system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 107260.032985 # average ReadCleanReq miss latency 899system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 129121.240602 # average ReadSharedReq miss latency 900system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 129121.240602 # average ReadSharedReq miss latency 901system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 107260.032985 # average overall miss latency 902system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94754.523227 # average overall miss latency 903system.cpu.l2cache.demand_avg_miss_latency::total 102759.985923 # average overall miss latency 904system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 107260.032985 # average overall miss latency 905system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94754.523227 # average overall miss latency 906system.cpu.l2cache.overall_avg_miss_latency::total 102759.985923 # average overall miss latency |
| 907system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 908system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 909system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 910system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 911system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 912system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 907system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 908system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 909system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 910system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 911system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 912system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 913system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1515 # number of ReadExReq MSHR misses 914system.cpu.l2cache.ReadExReq_mshr_misses::total 1515 # number of ReadExReq MSHR misses 915system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3636 # number of ReadCleanReq MSHR misses 916system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3636 # number of ReadCleanReq MSHR misses 917system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 518 # number of ReadSharedReq MSHR misses 918system.cpu.l2cache.ReadSharedReq_mshr_misses::total 518 # number of ReadSharedReq MSHR misses 919system.cpu.l2cache.demand_mshr_misses::cpu.inst 3636 # number of demand (read+write) MSHR misses 920system.cpu.l2cache.demand_mshr_misses::cpu.data 2033 # number of demand (read+write) MSHR misses 921system.cpu.l2cache.demand_mshr_misses::total 5669 # number of demand (read+write) MSHR misses 922system.cpu.l2cache.overall_mshr_misses::cpu.inst 3636 # number of overall MSHR misses 923system.cpu.l2cache.overall_mshr_misses::cpu.data 2033 # number of overall MSHR misses 924system.cpu.l2cache.overall_mshr_misses::total 5669 # number of overall MSHR misses 925system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 110602500 # number of ReadExReq MSHR miss cycles 926system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 110602500 # number of ReadExReq MSHR miss cycles 927system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 349163500 # number of ReadCleanReq MSHR miss cycles 928system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 349163500 # number of ReadCleanReq MSHR miss cycles 929system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 60126000 # number of ReadSharedReq MSHR miss cycles 930system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 60126000 # number of ReadSharedReq MSHR miss cycles 931system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 349163500 # number of demand (read+write) MSHR miss cycles 932system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 170728500 # number of demand (read+write) MSHR miss cycles 933system.cpu.l2cache.demand_mshr_miss_latency::total 519892000 # number of demand (read+write) MSHR miss cycles 934system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 349163500 # number of overall MSHR miss cycles 935system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 170728500 # number of overall MSHR miss cycles 936system.cpu.l2cache.overall_mshr_miss_latency::total 519892000 # number of overall MSHR miss cycles 937system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995401 # mshr miss rate for ReadExReq accesses 938system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995401 # mshr miss rate for ReadExReq accesses 939system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.427111 # mshr miss rate for ReadCleanReq accesses 940system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.427111 # mshr miss rate for ReadCleanReq accesses 941system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.888508 # mshr miss rate for ReadSharedReq accesses 942system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.888508 # mshr miss rate for ReadSharedReq accesses 943system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.427111 # mshr miss rate for demand accesses 944system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.965796 # mshr miss rate for demand accesses 945system.cpu.l2cache.demand_mshr_miss_rate::total 0.533905 # mshr miss rate for demand accesses 946system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.427111 # mshr miss rate for overall accesses 947system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.965796 # mshr miss rate for overall accesses 948system.cpu.l2cache.overall_mshr_miss_rate::total 0.533905 # mshr miss rate for overall accesses 949system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73004.950495 # average ReadExReq mshr miss latency 950system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73004.950495 # average ReadExReq mshr miss latency 951system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 96029.565457 # average ReadCleanReq mshr miss latency 952system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 96029.565457 # average ReadCleanReq mshr miss latency 953system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 116073.359073 # average ReadSharedReq mshr miss latency 954system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 116073.359073 # average ReadSharedReq mshr miss latency 955system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 96029.565457 # average overall mshr miss latency 956system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83978.603050 # average overall mshr miss latency 957system.cpu.l2cache.demand_avg_mshr_miss_latency::total 91707.884989 # average overall mshr miss latency 958system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 96029.565457 # average overall mshr miss latency 959system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83978.603050 # average overall mshr miss latency 960system.cpu.l2cache.overall_avg_mshr_miss_latency::total 91707.884989 # average overall mshr miss latency 961system.cpu.toL2Bus.snoop_filter.tot_requests 18313 # Total number of requests made to the snoop filter. 962system.cpu.toL2Bus.snoop_filter.hit_single_requests 7194 # Number of requests hitting in the snoop filter with a single holder of the requested data. 963system.cpu.toL2Bus.snoop_filter.hit_multi_requests 597 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. | 913system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1513 # number of ReadExReq MSHR misses 914system.cpu.l2cache.ReadExReq_mshr_misses::total 1513 # number of ReadExReq MSHR misses 915system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3638 # number of ReadCleanReq MSHR misses 916system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3638 # number of ReadCleanReq MSHR misses 917system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 532 # number of ReadSharedReq MSHR misses 918system.cpu.l2cache.ReadSharedReq_mshr_misses::total 532 # number of ReadSharedReq MSHR misses 919system.cpu.l2cache.demand_mshr_misses::cpu.inst 3638 # number of demand (read+write) MSHR misses 920system.cpu.l2cache.demand_mshr_misses::cpu.data 2045 # number of demand (read+write) MSHR misses 921system.cpu.l2cache.demand_mshr_misses::total 5683 # number of demand (read+write) MSHR misses 922system.cpu.l2cache.overall_mshr_misses::cpu.inst 3638 # number of overall MSHR misses 923system.cpu.l2cache.overall_mshr_misses::cpu.data 2045 # number of overall MSHR misses 924system.cpu.l2cache.overall_mshr_misses::total 5683 # number of overall MSHR misses 925system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 109950500 # number of ReadExReq MSHR miss cycles 926system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 109950500 # number of ReadExReq MSHR miss cycles 927system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 353832000 # number of ReadCleanReq MSHR miss cycles 928system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 353832000 # number of ReadCleanReq MSHR miss cycles 929system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 63372500 # number of ReadSharedReq MSHR miss cycles 930system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 63372500 # number of ReadSharedReq MSHR miss cycles 931system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 353832000 # number of demand (read+write) MSHR miss cycles 932system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 173323000 # number of demand (read+write) MSHR miss cycles 933system.cpu.l2cache.demand_mshr_miss_latency::total 527155000 # number of demand (read+write) MSHR miss cycles 934system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 353832000 # number of overall MSHR miss cycles 935system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 173323000 # number of overall MSHR miss cycles 936system.cpu.l2cache.overall_mshr_miss_latency::total 527155000 # number of overall MSHR miss cycles 937system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995395 # mshr miss rate for ReadExReq accesses 938system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995395 # mshr miss rate for ReadExReq accesses 939system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.422042 # mshr miss rate for ReadCleanReq accesses 940system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.422042 # mshr miss rate for ReadCleanReq accesses 941system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.876442 # mshr miss rate for ReadSharedReq accesses 942system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.876442 # mshr miss rate for ReadSharedReq accesses 943system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.422042 # mshr miss rate for demand accesses 944system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.961448 # mshr miss rate for demand accesses 945system.cpu.l2cache.demand_mshr_miss_rate::total 0.528799 # mshr miss rate for demand accesses 946system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.422042 # mshr miss rate for overall accesses 947system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.961448 # mshr miss rate for overall accesses 948system.cpu.l2cache.overall_mshr_miss_rate::total 0.528799 # mshr miss rate for overall accesses 949system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72670.522141 # average ReadExReq mshr miss latency 950system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72670.522141 # average ReadExReq mshr miss latency 951system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97260.032985 # average ReadCleanReq mshr miss latency 952system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97260.032985 # average ReadCleanReq mshr miss latency 953system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 119121.240602 # average ReadSharedReq mshr miss latency 954system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 119121.240602 # average ReadSharedReq mshr miss latency 955system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97260.032985 # average overall mshr miss latency 956system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84754.523227 # average overall mshr miss latency 957system.cpu.l2cache.demand_avg_mshr_miss_latency::total 92759.985923 # average overall mshr miss latency 958system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97260.032985 # average overall mshr miss latency 959system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84754.523227 # average overall mshr miss latency 960system.cpu.l2cache.overall_avg_mshr_miss_latency::total 92759.985923 # average overall mshr miss latency 961system.cpu.toL2Bus.snoop_filter.tot_requests 18517 # Total number of requests made to the snoop filter. 962system.cpu.toL2Bus.snoop_filter.hit_single_requests 6823 # Number of requests hitting in the snoop filter with a single holder of the requested data. 963system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1046 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 964system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 965system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 966system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 964system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 965system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 966system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 967system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states 968system.cpu.toL2Bus.trans_dist::ReadResp 9638 # Transaction distribution 969system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution 970system.cpu.toL2Bus.trans_dist::WritebackClean 6530 # Transaction distribution | 967system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states 968system.cpu.toL2Bus.trans_dist::ReadResp 9751 # Transaction distribution 969system.cpu.toL2Bus.trans_dist::WritebackDirty 17 # Transaction distribution 970system.cpu.toL2Bus.trans_dist::WritebackClean 6640 # Transaction distribution |
| 971system.cpu.toL2Bus.trans_dist::CleanEvict 65 # Transaction distribution | 971system.cpu.toL2Bus.trans_dist::CleanEvict 65 # Transaction distribution |
| 972system.cpu.toL2Bus.trans_dist::UpgradeReq 541 # Transaction distribution 973system.cpu.toL2Bus.trans_dist::UpgradeResp 541 # Transaction distribution 974system.cpu.toL2Bus.trans_dist::ReadExReq 1522 # Transaction distribution 975system.cpu.toL2Bus.trans_dist::ReadExResp 1522 # Transaction distribution 976system.cpu.toL2Bus.trans_dist::ReadCleanReq 9056 # Transaction distribution 977system.cpu.toL2Bus.trans_dist::ReadSharedReq 583 # Transaction distribution 978system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24098 # Packet count per connected master and slave (bytes) 979system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5373 # Packet count per connected master and slave (bytes) 980system.cpu.toL2Bus.pkt_count::total 29471 # Packet count per connected master and slave (bytes) 981system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 962688 # Cumulative packet size per connected master and slave (bytes) 982system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 135744 # Cumulative packet size per connected master and slave (bytes) 983system.cpu.toL2Bus.pkt_size::total 1098432 # Cumulative packet size per connected master and slave (bytes) 984system.cpu.toL2Bus.snoops 543 # Total snoops (count) 985system.cpu.toL2Bus.snoopTraffic 34752 # Total snoop traffic (bytes) 986system.cpu.toL2Bus.snoop_fanout::samples 11702 # Request fanout histogram 987system.cpu.toL2Bus.snoop_fanout::mean 0.100496 # Request fanout histogram 988system.cpu.toL2Bus.snoop_fanout::stdev 0.300673 # Request fanout histogram | 972system.cpu.toL2Bus.trans_dist::UpgradeReq 523 # Transaction distribution 973system.cpu.toL2Bus.trans_dist::UpgradeResp 523 # Transaction distribution 974system.cpu.toL2Bus.trans_dist::ReadExReq 1520 # Transaction distribution 975system.cpu.toL2Bus.trans_dist::ReadExResp 1520 # Transaction distribution 976system.cpu.toL2Bus.trans_dist::ReadCleanReq 9145 # Transaction distribution 977system.cpu.toL2Bus.trans_dist::ReadSharedReq 607 # Transaction distribution 978system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24404 # Packet count per connected master and slave (bytes) 979system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5382 # Packet count per connected master and slave (bytes) 980system.cpu.toL2Bus.pkt_count::total 29786 # Packet count per connected master and slave (bytes) 981system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 976576 # Cumulative packet size per connected master and slave (bytes) 982system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 137216 # Cumulative packet size per connected master and slave (bytes) 983system.cpu.toL2Bus.pkt_size::total 1113792 # Cumulative packet size per connected master and slave (bytes) 984system.cpu.toL2Bus.snoops 525 # Total snoops (count) 985system.cpu.toL2Bus.snoopTraffic 33600 # Total snoop traffic (bytes) 986system.cpu.toL2Bus.snoop_fanout::samples 11795 # Request fanout histogram 987system.cpu.toL2Bus.snoop_fanout::mean 0.096651 # Request fanout histogram 988system.cpu.toL2Bus.snoop_fanout::stdev 0.295495 # Request fanout histogram |
| 989system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 989system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 990system.cpu.toL2Bus.snoop_fanout::0 10526 89.95% 89.95% # Request fanout histogram 991system.cpu.toL2Bus.snoop_fanout::1 1176 10.05% 100.00% # Request fanout histogram | 990system.cpu.toL2Bus.snoop_fanout::0 10655 90.33% 90.33% # Request fanout histogram 991system.cpu.toL2Bus.snoop_fanout::1 1140 9.67% 100.00% # Request fanout histogram |
| 992system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 993system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 994system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 995system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 992system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 993system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 994system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 995system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 996system.cpu.toL2Bus.snoop_fanout::total 11702 # Request fanout histogram 997system.cpu.toL2Bus.reqLayer0.occupancy 15702500 # Layer occupancy (ticks) | 996system.cpu.toL2Bus.snoop_fanout::total 11795 # Request fanout histogram 997system.cpu.toL2Bus.reqLayer0.occupancy 15915500 # Layer occupancy (ticks) |
| 998system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 998system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 999system.cpu.toL2Bus.respLayer0.occupancy 13582500 # Layer occupancy (ticks) | 999system.cpu.toL2Bus.respLayer0.occupancy 13716000 # Layer occupancy (ticks) |
| 1000system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 1000system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1001system.cpu.toL2Bus.respLayer1.occupancy 3428499 # Layer occupancy (ticks) | 1001system.cpu.toL2Bus.respLayer1.occupancy 3452000 # Layer occupancy (ticks) |
| 1002system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1002system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1003system.membus.snoop_filter.tot_requests 5669 # Total number of requests made to the snoop filter. | 1003system.membus.snoop_filter.tot_requests 5683 # Total number of requests made to the snoop filter. |
| 1004system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1005system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1006system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1007system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1008system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1004system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1005system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1006system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1007system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1008system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1009system.membus.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states 1010system.membus.trans_dist::ReadResp 4154 # Transaction distribution 1011system.membus.trans_dist::ReadExReq 1515 # Transaction distribution 1012system.membus.trans_dist::ReadExResp 1515 # Transaction distribution 1013system.membus.trans_dist::ReadSharedReq 4154 # Transaction distribution 1014system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11338 # Packet count per connected master and slave (bytes) 1015system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11338 # Packet count per connected master and slave (bytes) 1016system.membus.pkt_count::total 11338 # Packet count per connected master and slave (bytes) 1017system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 362816 # Cumulative packet size per connected master and slave (bytes) 1018system.membus.pkt_size_system.cpu.l2cache.mem_side::total 362816 # Cumulative packet size per connected master and slave (bytes) 1019system.membus.pkt_size::total 362816 # Cumulative packet size per connected master and slave (bytes) | 1009system.membus.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states 1010system.membus.trans_dist::ReadResp 4170 # Transaction distribution 1011system.membus.trans_dist::ReadExReq 1513 # Transaction distribution 1012system.membus.trans_dist::ReadExResp 1513 # Transaction distribution 1013system.membus.trans_dist::ReadSharedReq 4170 # Transaction distribution 1014system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11366 # Packet count per connected master and slave (bytes) 1015system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11366 # Packet count per connected master and slave (bytes) 1016system.membus.pkt_count::total 11366 # Packet count per connected master and slave (bytes) 1017system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 363712 # Cumulative packet size per connected master and slave (bytes) 1018system.membus.pkt_size_system.cpu.l2cache.mem_side::total 363712 # Cumulative packet size per connected master and slave (bytes) 1019system.membus.pkt_size::total 363712 # Cumulative packet size per connected master and slave (bytes) |
| 1020system.membus.snoops 0 # Total snoops (count) 1021system.membus.snoopTraffic 0 # Total snoop traffic (bytes) | 1020system.membus.snoops 0 # Total snoops (count) 1021system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 1022system.membus.snoop_fanout::samples 5669 # Request fanout histogram | 1022system.membus.snoop_fanout::samples 5683 # Request fanout histogram |
| 1023system.membus.snoop_fanout::mean 0 # Request fanout histogram 1024system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1025system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1023system.membus.snoop_fanout::mean 0 # Request fanout histogram 1024system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1025system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1026system.membus.snoop_fanout::0 5669 100.00% 100.00% # Request fanout histogram | 1026system.membus.snoop_fanout::0 5683 100.00% 100.00% # Request fanout histogram |
| 1027system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1028system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1029system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1030system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 1027system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1028system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1029system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1030system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 1031system.membus.snoop_fanout::total 5669 # Request fanout histogram 1032system.membus.reqLayer0.occupancy 7048500 # Layer occupancy (ticks) | 1031system.membus.snoop_fanout::total 5683 # Request fanout histogram 1032system.membus.reqLayer0.occupancy 6909500 # Layer occupancy (ticks) |
| 1033system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1033system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1034system.membus.respLayer1.occupancy 30047500 # Layer occupancy (ticks) | 1034system.membus.respLayer1.occupancy 30126750 # Layer occupancy (ticks) |
| 1035system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 1036 1037---------- End Simulation Statistics ---------- | 1035system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 1036 1037---------- End Simulation Statistics ---------- |