| stats.txt (11606:6b749761c398) | stats.txt (11680:b4d943429dc6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.103278 # Number of seconds simulated 4sim_ticks 103278421500 # Number of ticks simulated 5final_tick 103278421500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.103189 # Number of seconds simulated 4sim_ticks 103189362000 # Number of ticks simulated 5final_tick 103189362000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 68420 # Simulator instruction rate (inst/s) 8host_op_rate 114678 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 53503682 # Simulator tick rate (ticks/s) 10host_mem_usage 309068 # Number of bytes of host memory used 11host_seconds 1930.31 # Real time elapsed on the host | 7host_inst_rate 73255 # Simulator instruction rate (inst/s) 8host_op_rate 122783 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 57235650 # Simulator tick rate (ticks/s) 10host_mem_usage 306480 # Number of bytes of host memory used 11host_seconds 1802.89 # Real time elapsed on the host |
| 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221363384 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221363384 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 232192 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 130496 # Number of bytes read from this memory 19system.physmem.bytes_read::total 362688 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 232192 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 232192 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 3628 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 2039 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 5667 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 2248214 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 1263536 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 3511750 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 2248214 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 2248214 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 2248214 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 1263536 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 3511750 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 5668 # Number of read requests accepted | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 232704 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 130112 # Number of bytes read from this memory 19system.physmem.bytes_read::total 362816 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 232704 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 232704 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 3636 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 2033 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 5669 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 2255116 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 1260905 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 3516021 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 2255116 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 2255116 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 2255116 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 1260905 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 3516021 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 5669 # Number of read requests accepted |
| 34system.physmem.writeReqs 0 # Number of write requests accepted | 34system.physmem.writeReqs 0 # Number of write requests accepted |
| 35system.physmem.readBursts 5668 # Number of DRAM read bursts, including those serviced by the write queue | 35system.physmem.readBursts 5669 # Number of DRAM read bursts, including those serviced by the write queue |
| 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 37system.physmem.bytesReadDRAM 362752 # Total number of bytes read from DRAM | 37system.physmem.bytesReadDRAM 362816 # Total number of bytes read from DRAM |
| 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 40system.physmem.bytesReadSys 362752 # Total read bytes from the system interface side | 40system.physmem.bytesReadSys 362816 # Total read bytes from the system interface side |
| 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 45system.physmem.perBankRdBursts::0 314 # Per bank write bursts 46system.physmem.perBankRdBursts::1 385 # Per bank write bursts 47system.physmem.perBankRdBursts::2 471 # Per bank write bursts 48system.physmem.perBankRdBursts::3 359 # Per bank write bursts 49system.physmem.perBankRdBursts::4 360 # Per bank write bursts 50system.physmem.perBankRdBursts::5 334 # Per bank write bursts 51system.physmem.perBankRdBursts::6 420 # Per bank write bursts 52system.physmem.perBankRdBursts::7 393 # Per bank write bursts 53system.physmem.perBankRdBursts::8 389 # Per bank write bursts | 45system.physmem.perBankRdBursts::0 309 # Per bank write bursts 46system.physmem.perBankRdBursts::1 384 # Per bank write bursts 47system.physmem.perBankRdBursts::2 476 # Per bank write bursts 48system.physmem.perBankRdBursts::3 363 # Per bank write bursts 49system.physmem.perBankRdBursts::4 357 # Per bank write bursts 50system.physmem.perBankRdBursts::5 335 # Per bank write bursts 51system.physmem.perBankRdBursts::6 419 # Per bank write bursts 52system.physmem.perBankRdBursts::7 395 # Per bank write bursts 53system.physmem.perBankRdBursts::8 387 # Per bank write bursts |
| 54system.physmem.perBankRdBursts::9 296 # Per bank write bursts | 54system.physmem.perBankRdBursts::9 296 # Per bank write bursts |
| 55system.physmem.perBankRdBursts::10 257 # Per bank write bursts 56system.physmem.perBankRdBursts::11 272 # Per bank write bursts 57system.physmem.perBankRdBursts::12 232 # Per bank write bursts 58system.physmem.perBankRdBursts::13 487 # Per bank write bursts 59system.physmem.perBankRdBursts::14 416 # Per bank write bursts 60system.physmem.perBankRdBursts::15 283 # Per bank write bursts | 55system.physmem.perBankRdBursts::10 260 # Per bank write bursts 56system.physmem.perBankRdBursts::11 268 # Per bank write bursts 57system.physmem.perBankRdBursts::12 228 # Per bank write bursts 58system.physmem.perBankRdBursts::13 486 # Per bank write bursts 59system.physmem.perBankRdBursts::14 420 # Per bank write bursts 60system.physmem.perBankRdBursts::15 286 # Per bank write bursts |
| 61system.physmem.perBankWrBursts::0 0 # Per bank write bursts 62system.physmem.perBankWrBursts::1 0 # Per bank write bursts 63system.physmem.perBankWrBursts::2 0 # Per bank write bursts 64system.physmem.perBankWrBursts::3 0 # Per bank write bursts 65system.physmem.perBankWrBursts::4 0 # Per bank write bursts 66system.physmem.perBankWrBursts::5 0 # Per bank write bursts 67system.physmem.perBankWrBursts::6 0 # Per bank write bursts 68system.physmem.perBankWrBursts::7 0 # Per bank write bursts 69system.physmem.perBankWrBursts::8 0 # Per bank write bursts 70system.physmem.perBankWrBursts::9 0 # Per bank write bursts 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 61system.physmem.perBankWrBursts::0 0 # Per bank write bursts 62system.physmem.perBankWrBursts::1 0 # Per bank write bursts 63system.physmem.perBankWrBursts::2 0 # Per bank write bursts 64system.physmem.perBankWrBursts::3 0 # Per bank write bursts 65system.physmem.perBankWrBursts::4 0 # Per bank write bursts 66system.physmem.perBankWrBursts::5 0 # Per bank write bursts 67system.physmem.perBankWrBursts::6 0 # Per bank write bursts 68system.physmem.perBankWrBursts::7 0 # Per bank write bursts 69system.physmem.perBankWrBursts::8 0 # Per bank write bursts 70system.physmem.perBankWrBursts::9 0 # Per bank write bursts 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 79system.physmem.totGap 103278386000 # Total gap between requests | 79system.physmem.totGap 103189107000 # Total gap between requests |
| 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) | 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 86system.physmem.readPktSize::6 5668 # Read request sizes (log2) | 86system.physmem.readPktSize::6 5669 # Read request sizes (log2) |
| 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) | 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 94system.physmem.rdQLenPdf::0 4530 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::1 947 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 166 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see | 94system.physmem.rdQLenPdf::0 4455 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::1 978 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 200 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see |
| 99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 75 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 75 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 190system.physmem.bytesPerActivate::samples 1276 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 283.335423 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 163.570090 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 315.354372 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 562 44.04% 44.04% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 260 20.38% 64.42% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 126 9.87% 74.29% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 65 5.09% 79.39% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 38 2.98% 82.37% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 52 4.08% 86.44% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 32 2.51% 88.95% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 25 1.96% 90.91% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 116 9.09% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 1276 # Bytes accessed per row activation 204system.physmem.totQLat 44968750 # Total ticks spent queuing 205system.physmem.totMemAccLat 151243750 # Total ticks spent from burst creation until serviced by the DRAM 206system.physmem.totBusLat 28340000 # Total ticks spent in databus transfers 207system.physmem.avgQLat 7933.79 # Average queueing delay per DRAM burst | 190system.physmem.bytesPerActivate::samples 1243 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 291.012068 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 164.006967 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 325.689818 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 565 45.45% 45.45% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 237 19.07% 64.52% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 95 7.64% 72.16% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 65 5.23% 77.39% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 45 3.62% 81.01% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 57 4.59% 85.60% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 29 2.33% 87.93% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 21 1.69% 89.62% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 129 10.38% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 1243 # Bytes accessed per row activation 204system.physmem.totQLat 180648250 # Total ticks spent queuing 205system.physmem.totMemAccLat 286942000 # Total ticks spent from burst creation until serviced by the DRAM 206system.physmem.totBusLat 28345000 # Total ticks spent in databus transfers 207system.physmem.avgQLat 31865.98 # Average queueing delay per DRAM burst |
| 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 209system.physmem.avgMemAccLat 26683.79 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 3.51 # Average DRAM read bandwidth in MiByte/s | 209system.physmem.avgMemAccLat 50615.98 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 3.52 # Average DRAM read bandwidth in MiByte/s |
| 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 212system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s | 212system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s |
| 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 0.03 # Data bus utilization in percentage 216system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 0.03 # Data bus utilization in percentage 216system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 218system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing | 218system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing |
| 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 220system.physmem.readRowHits 4387 # Number of row buffer hits during reads | 220system.physmem.readRowHits 4421 # Number of row buffer hits during reads |
| 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 222system.physmem.readRowHitRate 77.40 # Row buffer hit rate for reads | 222system.physmem.readRowHitRate 77.99 # Row buffer hit rate for reads |
| 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 224system.physmem.avgGap 18221310.16 # Average gap between requests 225system.physmem.pageHitRate 77.40 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 5677560 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 3097875 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 23649600 # Energy for read commands per rank (pJ) | 224system.physmem.avgGap 18202347.33 # Average gap between requests 225system.physmem.pageHitRate 77.99 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 5333580 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 2823480 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 21691320 # Energy for read commands per rank (pJ) |
| 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) | 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 230system.physmem_0.refreshEnergy 6745539840 # Energy for refresh commands per rank (pJ) 231system.physmem_0.actBackEnergy 3123252585 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 59226559500 # Energy for precharge background per rank (pJ) 233system.physmem_0.totalEnergy 69127776960 # Total energy per rank (pJ) 234system.physmem_0.averagePower 669.342795 # Core power per rank (mW) 235system.physmem_0.memoryStateTime::IDLE 98524507750 # Time in different power states 236system.physmem_0.memoryStateTime::REF 3448640000 # Time in different power states 237system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 238system.physmem_0.memoryStateTime::ACT 1303957250 # Time in different power states 239system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 240system.physmem_1.actEnergy 3969000 # Energy for activate commands per rank (pJ) 241system.physmem_1.preEnergy 2165625 # Energy for precharge commands per rank (pJ) 242system.physmem_1.readEnergy 20412600 # Energy for read commands per rank (pJ) | 230system.physmem_0.refreshEnergy 286422240.000000 # Energy for refresh commands per rank (pJ) 231system.physmem_0.actBackEnergy 93806610 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 15765120 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 717579270 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 394813440 # Energy for precharge power-down per rank (pJ) 235system.physmem_0.selfRefreshEnergy 24141432120 # Energy for self refresh per rank (pJ) 236system.physmem_0.totalEnergy 25679671980 # Total energy per rank (pJ) 237system.physmem_0.averagePower 248.859682 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 102941166250 # Total Idle time Per DRAM Rank 239system.physmem_0.memoryStateTime::IDLE 30119500 # Time in different power states 240system.physmem_0.memoryStateTime::REF 121808000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 100340787250 # Time in different power states 242system.physmem_0.memoryStateTime::PRE_PDN 1028168000 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 94814000 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 1573665250 # Time in different power states 245system.physmem_1.actEnergy 3577140 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 1893705 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 18785340 # Energy for read commands per rank (pJ) |
| 243system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) | 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 244system.physmem_1.refreshEnergy 6745539840 # Energy for refresh commands per rank (pJ) 245system.physmem_1.actBackEnergy 3000772125 # Energy for active background per rank (pJ) 246system.physmem_1.preBackEnergy 59333991750 # Energy for precharge background per rank (pJ) 247system.physmem_1.totalEnergy 69106850940 # Total energy per rank (pJ) 248system.physmem_1.averagePower 669.140248 # Core power per rank (mW) 249system.physmem_1.memoryStateTime::IDLE 98704275500 # Time in different power states 250system.physmem_1.memoryStateTime::REF 3448640000 # Time in different power states 251system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 252system.physmem_1.memoryStateTime::ACT 1124404000 # Time in different power states 253system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 254system.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states 255system.cpu.branchPred.lookups 40909998 # Number of BP lookups 256system.cpu.branchPred.condPredicted 40909998 # Number of conditional branches predicted 257system.cpu.branchPred.condIncorrect 6747980 # Number of conditional branches incorrect 258system.cpu.branchPred.BTBLookups 35338690 # Number of BTB lookups | 249system.physmem_1.refreshEnergy 224343600.000000 # Energy for refresh commands per rank (pJ) 250system.physmem_1.actBackEnergy 72770760 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 12467520 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 571365720 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 300199680 # Energy for precharge power-down per rank (pJ) 254system.physmem_1.selfRefreshEnergy 24277951200 # Energy for self refresh per rank (pJ) 255system.physmem_1.totalEnergy 25483354665 # Total energy per rank (pJ) 256system.physmem_1.averagePower 246.957187 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 102997073250 # Total Idle time Per DRAM Rank 258system.physmem_1.memoryStateTime::IDLE 23820000 # Time in different power states 259system.physmem_1.memoryStateTime::REF 95422000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 100962546500 # Time in different power states 261system.physmem_1.memoryStateTime::PRE_PDN 781772000 # Time in different power states 262system.physmem_1.memoryStateTime::ACT 72828000 # Time in different power states 263system.physmem_1.memoryStateTime::ACT_PDN 1252973500 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 40834752 # Number of BP lookups 266system.cpu.branchPred.condPredicted 40834752 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 6720926 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 35301077 # Number of BTB lookups |
| 259system.cpu.branchPred.BTBHits 0 # Number of BTB hits 260system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 261system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage | 269system.cpu.branchPred.BTBHits 0 # Number of BTB hits 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 271system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage |
| 262system.cpu.branchPred.usedRAS 3198330 # Number of times the RAS was used to get a target. 263system.cpu.branchPred.RASInCorrect 606499 # Number of incorrect RAS predictions. 264system.cpu.branchPred.indirectLookups 35338690 # Number of indirect predictor lookups. 265system.cpu.branchPred.indirectHits 9879284 # Number of indirect target hits. 266system.cpu.branchPred.indirectMisses 25459406 # Number of indirect misses. 267system.cpu.branchPredindirectMispredicted 5040736 # Number of mispredicted indirect branches. | 272system.cpu.branchPred.usedRAS 3198104 # Number of times the RAS was used to get a target. 273system.cpu.branchPred.RASInCorrect 606453 # Number of incorrect RAS predictions. 274system.cpu.branchPred.indirectLookups 35301077 # Number of indirect predictor lookups. 275system.cpu.branchPred.indirectHits 9875363 # Number of indirect target hits. 276system.cpu.branchPred.indirectMisses 25425714 # Number of indirect misses. 277system.cpu.branchPredindirectMispredicted 5011557 # Number of mispredicted indirect branches. |
| 268system.cpu_clk_domain.clock 500 # Clock period in ticks | 278system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 269system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states | 279system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states |
| 270system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks | 280system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks |
| 271system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states 272system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states | 281system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states 282system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states |
| 273system.cpu.workload.num_syscalls 400 # Number of system calls | 283system.cpu.workload.num_syscalls 400 # Number of system calls |
| 274system.cpu.pwrStateResidencyTicks::ON 103278421500 # Cumulative time (in ticks) in various power states 275system.cpu.numCycles 206556844 # number of cpu cycles simulated | 284system.cpu.pwrStateResidencyTicks::ON 103189362000 # Cumulative time (in ticks) in various power states 285system.cpu.numCycles 206378725 # number of cpu cycles simulated |
| 276system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 277system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 286system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 287system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 278system.cpu.fetch.icacheStallCycles 46378865 # Number of cycles fetch is stalled on an Icache miss 279system.cpu.fetch.Insts 420308215 # Number of instructions fetch has processed 280system.cpu.fetch.Branches 40909998 # Number of branches that fetch encountered 281system.cpu.fetch.predictedBranches 13077614 # Number of branches that fetch has predicted taken 282system.cpu.fetch.Cycles 152415438 # Number of cycles fetch has run and was not squashing or blocked 283system.cpu.fetch.SquashCycles 14966481 # Number of cycles fetch has spent squashing 284system.cpu.fetch.TlbCycles 135 # Number of cycles fetch has spent waiting for tlb 285system.cpu.fetch.MiscStallCycles 5953 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 286system.cpu.fetch.PendingTrapStallCycles 72789 # Number of stall cycles due to pending traps 287system.cpu.fetch.PendingQuiesceStallCycles 564 # Number of stall cycles due to pending quiesce instructions 288system.cpu.fetch.IcacheWaitRetryStallCycles 110 # Number of stall cycles due to full MSHR 289system.cpu.fetch.CacheLines 41283191 # Number of cache lines fetched 290system.cpu.fetch.IcacheSquashes 1528436 # Number of outstanding Icache misses that were squashed 291system.cpu.fetch.ItlbSquashes 4 # Number of outstanding ITLB misses that were squashed 292system.cpu.fetch.rateDist::samples 206357094 # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::mean 3.419964 # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.rateDist::stdev 3.660932 # Number of instructions fetched each cycle (Total) | 288system.cpu.fetch.icacheStallCycles 46270336 # Number of cycles fetch is stalled on an Icache miss 289system.cpu.fetch.Insts 419359791 # Number of instructions fetch has processed 290system.cpu.fetch.Branches 40834752 # Number of branches that fetch encountered 291system.cpu.fetch.predictedBranches 13073467 # Number of branches that fetch has predicted taken 292system.cpu.fetch.Cycles 152339601 # Number of cycles fetch has run and was not squashing or blocked 293system.cpu.fetch.SquashCycles 14895691 # Number of cycles fetch has spent squashing 294system.cpu.fetch.TlbCycles 89 # Number of cycles fetch has spent waiting for tlb 295system.cpu.fetch.MiscStallCycles 5905 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 296system.cpu.fetch.PendingTrapStallCycles 73704 # Number of stall cycles due to pending traps 297system.cpu.fetch.PendingQuiesceStallCycles 808 # Number of stall cycles due to pending quiesce instructions 298system.cpu.fetch.IcacheWaitRetryStallCycles 184 # Number of stall cycles due to full MSHR 299system.cpu.fetch.CacheLines 41191275 # Number of cache lines fetched 300system.cpu.fetch.IcacheSquashes 1518616 # Number of outstanding Icache misses that were squashed 301system.cpu.fetch.ItlbSquashes 6 # Number of outstanding ITLB misses that were squashed 302system.cpu.fetch.rateDist::samples 206138472 # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::mean 3.415591 # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::stdev 3.660484 # Number of instructions fetched each cycle (Total) |
| 295system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 305system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 296system.cpu.fetch.rateDist::0 99044157 48.00% 48.00% # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::1 5139433 2.49% 50.49% # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.rateDist::2 5380650 2.61% 53.09% # Number of instructions fetched each cycle (Total) 299system.cpu.fetch.rateDist::3 5336666 2.59% 55.68% # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.rateDist::4 6016483 2.92% 58.60% # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::5 5851353 2.84% 61.43% # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::6 5736237 2.78% 64.21% # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::7 4733991 2.29% 66.51% # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::8 69118124 33.49% 100.00% # Number of instructions fetched each cycle (Total) | 306system.cpu.fetch.rateDist::0 99063302 48.06% 48.06% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::1 5137465 2.49% 50.55% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::2 5366260 2.60% 53.15% # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::3 5330020 2.59% 55.74% # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::4 6010905 2.92% 58.65% # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::5 5824389 2.83% 61.48% # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::6 5722044 2.78% 64.26% # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::7 4745811 2.30% 66.56% # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::8 68938276 33.44% 100.00% # Number of instructions fetched each cycle (Total) |
| 305system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 315system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 316system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 308system.cpu.fetch.rateDist::total 206357094 # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.branchRate 0.198057 # Number of branch fetches per cycle 310system.cpu.fetch.rate 2.034831 # Number of inst fetches per cycle 311system.cpu.decode.IdleCycles 32325248 # Number of cycles decode is idle 312system.cpu.decode.BlockedCycles 86371056 # Number of cycles decode is blocked 313system.cpu.decode.RunCycles 62511253 # Number of cycles decode is running 314system.cpu.decode.UnblockCycles 17666297 # Number of cycles decode is unblocking 315system.cpu.decode.SquashCycles 7483240 # Number of cycles decode is squashing 316system.cpu.decode.DecodedInsts 591444337 # Number of instructions handled by decode 317system.cpu.rename.SquashCycles 7483240 # Number of cycles rename is squashing 318system.cpu.rename.IdleCycles 42110583 # Number of cycles rename is idle 319system.cpu.rename.BlockCycles 46566289 # Number of cycles rename is blocking 320system.cpu.rename.serializeStallCycles 29410 # count of cycles rename stalled for serializing inst 321system.cpu.rename.RunCycles 68967744 # Number of cycles rename is running 322system.cpu.rename.UnblockCycles 41199828 # Number of cycles rename is unblocking 323system.cpu.rename.RenamedInsts 552624215 # Number of instructions processed by rename 324system.cpu.rename.ROBFullEvents 1533 # Number of times rename has blocked due to ROB full 325system.cpu.rename.IQFullEvents 36277086 # Number of times rename has blocked due to IQ full 326system.cpu.rename.LQFullEvents 4842177 # Number of times rename has blocked due to LQ full 327system.cpu.rename.SQFullEvents 151976 # Number of times rename has blocked due to SQ full 328system.cpu.rename.RenamedOperands 630066400 # Number of destination operands rename has renamed 329system.cpu.rename.RenameLookups 1487530571 # Number of register rename lookups that rename has made 330system.cpu.rename.int_rename_lookups 975657611 # Number of integer rename lookups 331system.cpu.rename.fp_rename_lookups 15077279 # Number of floating rename lookups | 318system.cpu.fetch.rateDist::total 206138472 # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.branchRate 0.197863 # Number of branch fetches per cycle 320system.cpu.fetch.rate 2.031991 # Number of inst fetches per cycle 321system.cpu.decode.IdleCycles 32237214 # Number of cycles decode is idle 322system.cpu.decode.BlockedCycles 86447407 # Number of cycles decode is blocked 323system.cpu.decode.RunCycles 62317142 # Number of cycles decode is running 324system.cpu.decode.UnblockCycles 17688864 # Number of cycles decode is unblocking 325system.cpu.decode.SquashCycles 7447845 # Number of cycles decode is squashing 326system.cpu.decode.DecodedInsts 590237823 # Number of instructions handled by decode 327system.cpu.rename.SquashCycles 7447845 # Number of cycles rename is squashing 328system.cpu.rename.IdleCycles 42013779 # Number of cycles rename is idle 329system.cpu.rename.BlockCycles 46504501 # Number of cycles rename is blocking 330system.cpu.rename.serializeStallCycles 31211 # count of cycles rename stalled for serializing inst 331system.cpu.rename.RunCycles 68811152 # Number of cycles rename is running 332system.cpu.rename.UnblockCycles 41329984 # Number of cycles rename is unblocking 333system.cpu.rename.RenamedInsts 551593859 # Number of instructions processed by rename 334system.cpu.rename.ROBFullEvents 1410 # Number of times rename has blocked due to ROB full 335system.cpu.rename.IQFullEvents 36393589 # Number of times rename has blocked due to IQ full 336system.cpu.rename.LQFullEvents 4822156 # Number of times rename has blocked due to LQ full 337system.cpu.rename.SQFullEvents 169929 # Number of times rename has blocked due to SQ full 338system.cpu.rename.RenamedOperands 628796373 # Number of destination operands rename has renamed 339system.cpu.rename.RenameLookups 1484193525 # Number of register rename lookups that rename has made 340system.cpu.rename.int_rename_lookups 973498992 # Number of integer rename lookups 341system.cpu.rename.fp_rename_lookups 15084169 # Number of floating rename lookups |
| 332system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed | 342system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed |
| 333system.cpu.rename.UndoneMaps 370636950 # Number of HB maps that are undone due to squashing 334system.cpu.rename.serializingInsts 2363 # count of serializing insts renamed 335system.cpu.rename.tempSerializingInsts 2376 # count of temporary serializing insts renamed 336system.cpu.rename.skidInsts 89140950 # count of insts added to the skid buffer 337system.cpu.memDep0.insertedLoads 128894590 # Number of loads inserted to the mem dependence unit. 338system.cpu.memDep0.insertedStores 45939948 # Number of stores inserted to the mem dependence unit. 339system.cpu.memDep0.conflictingLoads 77227738 # Number of conflicting loads. 340system.cpu.memDep0.conflictingStores 25186602 # Number of conflicting stores. 341system.cpu.iq.iqInstsAdded 490698604 # Number of instructions added to the IQ (excludes non-spec) 342system.cpu.iq.iqNonSpecInstsAdded 59973 # Number of non-speculative instructions added to the IQ 343system.cpu.iq.iqInstsIssued 338566221 # Number of instructions issued 344system.cpu.iq.iqSquashedInstsIssued 1098463 # Number of squashed instructions issued 345system.cpu.iq.iqSquashedInstsExamined 269395193 # Number of squashed instructions iterated over during squash; mainly for profiling 346system.cpu.iq.iqSquashedOperandsExamined 527209931 # Number of squashed operands that are examined and possibly removed from graph 347system.cpu.iq.iqSquashedNonSpecRemoved 58728 # Number of squashed non-spec instructions that were removed 348system.cpu.iq.issued_per_cycle::samples 206357094 # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::mean 1.640681 # Number of insts issued each cycle 350system.cpu.iq.issued_per_cycle::stdev 1.805896 # Number of insts issued each cycle | 343system.cpu.rename.UndoneMaps 369366923 # Number of HB maps that are undone due to squashing 344system.cpu.rename.serializingInsts 2443 # count of serializing insts renamed 345system.cpu.rename.tempSerializingInsts 2459 # count of temporary serializing insts renamed 346system.cpu.rename.skidInsts 89351866 # count of insts added to the skid buffer 347system.cpu.memDep0.insertedLoads 128676829 # Number of loads inserted to the mem dependence unit. 348system.cpu.memDep0.insertedStores 45848779 # Number of stores inserted to the mem dependence unit. 349system.cpu.memDep0.conflictingLoads 77202780 # Number of conflicting loads. 350system.cpu.memDep0.conflictingStores 25186397 # Number of conflicting stores. 351system.cpu.iq.iqInstsAdded 489944627 # Number of instructions added to the IQ (excludes non-spec) 352system.cpu.iq.iqNonSpecInstsAdded 61663 # Number of non-speculative instructions added to the IQ 353system.cpu.iq.iqInstsIssued 338268196 # Number of instructions issued 354system.cpu.iq.iqSquashedInstsIssued 1105632 # Number of squashed instructions issued 355system.cpu.iq.iqSquashedInstsExamined 268642906 # Number of squashed instructions iterated over during squash; mainly for profiling 356system.cpu.iq.iqSquashedOperandsExamined 525336348 # Number of squashed operands that are examined and possibly removed from graph 357system.cpu.iq.iqSquashedNonSpecRemoved 60418 # Number of squashed non-spec instructions that were removed 358system.cpu.iq.issued_per_cycle::samples 206138472 # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::mean 1.640976 # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::stdev 1.805234 # Number of insts issued each cycle |
| 351system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 361system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 352system.cpu.iq.issued_per_cycle::0 73312584 35.53% 35.53% # Number of insts issued each cycle 353system.cpu.iq.issued_per_cycle::1 46573584 22.57% 58.10% # Number of insts issued each cycle 354system.cpu.iq.issued_per_cycle::2 32816576 15.90% 74.00% # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::3 20907210 10.13% 84.13% # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::4 15065478 7.30% 91.43% # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::5 8412685 4.08% 95.51% # Number of insts issued each cycle 358system.cpu.iq.issued_per_cycle::6 5234413 2.54% 98.04% # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::7 2370472 1.15% 99.19% # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::8 1664092 0.81% 100.00% # Number of insts issued each cycle | 362system.cpu.iq.issued_per_cycle::0 73134407 35.48% 35.48% # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::1 46607709 22.61% 58.09% # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::2 32815647 15.92% 74.01% # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::3 20883524 10.13% 84.14% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::4 15044203 7.30% 91.44% # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::5 8407546 4.08% 95.51% # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::6 5216740 2.53% 98.05% # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::7 2365929 1.15% 99.19% # Number of insts issued each cycle 370system.cpu.iq.issued_per_cycle::8 1662767 0.81% 100.00% # Number of insts issued each cycle |
| 361system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 371system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 364system.cpu.iq.issued_per_cycle::total 206357094 # Number of insts issued each cycle | 374system.cpu.iq.issued_per_cycle::total 206138472 # Number of insts issued each cycle |
| 365system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 375system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 366system.cpu.iq.fu_full::IntAlu 762770 19.47% 19.47% # attempts to use FU when none available 367system.cpu.iq.fu_full::IntMult 0 0.00% 19.47% # attempts to use FU when none available 368system.cpu.iq.fu_full::IntDiv 0 0.00% 19.47% # attempts to use FU when none available 369system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.47% # attempts to use FU when none available 370system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.47% # attempts to use FU when none available 371system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.47% # attempts to use FU when none available 372system.cpu.iq.fu_full::FloatMult 0 0.00% 19.47% # attempts to use FU when none available 373system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.47% # attempts to use FU when none available 374system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.47% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.47% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.47% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.47% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.47% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.47% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.47% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdMult 0 0.00% 19.47% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.47% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdShift 0 0.00% 19.47% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.47% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.47% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.47% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.47% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.47% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.47% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.47% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.47% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.47% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.47% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.47% # attempts to use FU when none available 395system.cpu.iq.fu_full::MemRead 2718793 69.40% 88.87% # attempts to use FU when none available 396system.cpu.iq.fu_full::MemWrite 436106 11.13% 100.00% # attempts to use FU when none available | 376system.cpu.iq.fu_full::IntAlu 759085 19.35% 19.35% # attempts to use FU when none available 377system.cpu.iq.fu_full::IntMult 0 0.00% 19.35% # attempts to use FU when none available 378system.cpu.iq.fu_full::IntDiv 0 0.00% 19.35% # attempts to use FU when none available 379system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.35% # attempts to use FU when none available 380system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.35% # attempts to use FU when none available 381system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.35% # attempts to use FU when none available 382system.cpu.iq.fu_full::FloatMult 0 0.00% 19.35% # attempts to use FU when none available 383system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.35% # attempts to use FU when none available 384system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.35% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.35% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.35% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.35% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.35% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.35% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.35% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdMult 0 0.00% 19.35% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.35% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdShift 0 0.00% 19.35% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.35% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.35% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.35% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.35% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.35% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.35% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.35% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.35% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.35% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.35% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.35% # attempts to use FU when none available 405system.cpu.iq.fu_full::MemRead 2731626 69.64% 88.99% # attempts to use FU when none available 406system.cpu.iq.fu_full::MemWrite 432034 11.01% 100.00% # attempts to use FU when none available |
| 397system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 398system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 407system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 408system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 399system.cpu.iq.FU_type_0::No_OpClass 1211777 0.36% 0.36% # Type of FU issued 400system.cpu.iq.FU_type_0::IntAlu 216613901 63.98% 64.34% # Type of FU issued 401system.cpu.iq.FU_type_0::IntMult 799985 0.24% 64.57% # Type of FU issued 402system.cpu.iq.FU_type_0::IntDiv 7047582 2.08% 66.66% # Type of FU issued 403system.cpu.iq.FU_type_0::FloatAdd 1810682 0.53% 67.19% # Type of FU issued 404system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.19% # Type of FU issued 405system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.19% # Type of FU issued 406system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.19% # Type of FU issued 407system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.19% # Type of FU issued 408system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.19% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.19% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.19% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.19% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.19% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.19% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.19% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.19% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.19% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.19% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.19% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.19% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.19% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.19% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.19% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.19% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.19% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.19% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.19% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.19% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.19% # Type of FU issued 429system.cpu.iq.FU_type_0::MemRead 84424015 24.94% 92.13% # Type of FU issued 430system.cpu.iq.FU_type_0::MemWrite 26658279 7.87% 100.00% # Type of FU issued | 409system.cpu.iq.FU_type_0::No_OpClass 1211760 0.36% 0.36% # Type of FU issued 410system.cpu.iq.FU_type_0::IntAlu 216459489 63.99% 64.35% # Type of FU issued 411system.cpu.iq.FU_type_0::IntMult 800418 0.24% 64.59% # Type of FU issued 412system.cpu.iq.FU_type_0::IntDiv 7047773 2.08% 66.67% # Type of FU issued 413system.cpu.iq.FU_type_0::FloatAdd 1809637 0.53% 67.20% # Type of FU issued 414system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.20% # Type of FU issued 415system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.20% # Type of FU issued 416system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.20% # Type of FU issued 417system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.20% # Type of FU issued 418system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.20% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.20% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.20% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.20% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.20% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.20% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.20% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.20% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.20% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.20% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.20% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.20% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.20% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.20% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.20% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.20% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.20% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.20% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.20% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.20% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.20% # Type of FU issued 439system.cpu.iq.FU_type_0::MemRead 84315938 24.93% 92.13% # Type of FU issued 440system.cpu.iq.FU_type_0::MemWrite 26623181 7.87% 100.00% # Type of FU issued |
| 431system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 432system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 441system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 442system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 433system.cpu.iq.FU_type_0::total 338566221 # Type of FU issued 434system.cpu.iq.rate 1.639095 # Inst issue rate 435system.cpu.iq.fu_busy_cnt 3917669 # FU busy when requested 436system.cpu.iq.fu_busy_rate 0.011571 # FU busy rate (busy events/executed inst) 437system.cpu.iq.int_inst_queue_reads 880328489 # Number of integer instruction queue reads 438system.cpu.iq.int_inst_queue_writes 745561228 # Number of integer instruction queue writes 439system.cpu.iq.int_inst_queue_wakeup_accesses 316131833 # Number of integer instruction queue wakeup accesses 440system.cpu.iq.fp_inst_queue_reads 8177179 # Number of floating instruction queue reads 441system.cpu.iq.fp_inst_queue_writes 15427221 # Number of floating instruction queue writes 442system.cpu.iq.fp_inst_queue_wakeup_accesses 3556889 # Number of floating instruction queue wakeup accesses 443system.cpu.iq.int_alu_accesses 337169115 # Number of integer alu accesses 444system.cpu.iq.fp_alu_accesses 4102998 # Number of floating point alu accesses 445system.cpu.iew.lsq.thread0.forwLoads 18179072 # Number of loads that had data forwarded from stores | 443system.cpu.iq.FU_type_0::total 338268196 # Type of FU issued 444system.cpu.iq.rate 1.639065 # Inst issue rate 445system.cpu.iq.fu_busy_cnt 3922745 # FU busy when requested 446system.cpu.iq.fu_busy_rate 0.011597 # FU busy rate (busy events/executed inst) 447system.cpu.iq.int_inst_queue_reads 879521716 # Number of integer instruction queue reads 448system.cpu.iq.int_inst_queue_writes 744046350 # Number of integer instruction queue writes 449system.cpu.iq.int_inst_queue_wakeup_accesses 315909602 # Number of integer instruction queue wakeup accesses 450system.cpu.iq.fp_inst_queue_reads 8181525 # Number of floating instruction queue reads 451system.cpu.iq.fp_inst_queue_writes 15431147 # Number of floating instruction queue writes 452system.cpu.iq.fp_inst_queue_wakeup_accesses 3556535 # Number of floating instruction queue wakeup accesses 453system.cpu.iq.int_alu_accesses 336873543 # Number of integer alu accesses 454system.cpu.iq.fp_alu_accesses 4105638 # Number of floating point alu accesses 455system.cpu.iew.lsq.thread0.forwLoads 18155877 # Number of loads that had data forwarded from stores |
| 446system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 456system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 447system.cpu.iew.lsq.thread0.squashedLoads 72245003 # Number of loads squashed 448system.cpu.iew.lsq.thread0.ignoredResponses 55572 # Number of memory responses ignored because the instruction is squashed 449system.cpu.iew.lsq.thread0.memOrderViolation 872144 # Number of memory ordering violations 450system.cpu.iew.lsq.thread0.squashedStores 25424231 # Number of stores squashed | 457system.cpu.iew.lsq.thread0.squashedLoads 72027242 # Number of loads squashed 458system.cpu.iew.lsq.thread0.ignoredResponses 55091 # Number of memory responses ignored because the instruction is squashed 459system.cpu.iew.lsq.thread0.memOrderViolation 864575 # Number of memory ordering violations 460system.cpu.iew.lsq.thread0.squashedStores 25333062 # Number of stores squashed |
| 451system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 452system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 461system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 462system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 453system.cpu.iew.lsq.thread0.rescheduledLoads 50651 # Number of loads that were rescheduled 454system.cpu.iew.lsq.thread0.cacheBlocked 53 # Number of times an access to memory failed due to the cache being blocked | 463system.cpu.iew.lsq.thread0.rescheduledLoads 50542 # Number of loads that were rescheduled 464system.cpu.iew.lsq.thread0.cacheBlocked 27 # Number of times an access to memory failed due to the cache being blocked |
| 455system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 465system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 456system.cpu.iew.iewSquashCycles 7483240 # Number of cycles IEW is squashing 457system.cpu.iew.iewBlockCycles 35798970 # Number of cycles IEW is blocking 458system.cpu.iew.iewUnblockCycles 583606 # Number of cycles IEW is unblocking 459system.cpu.iew.iewDispatchedInsts 490758577 # Number of instructions dispatched to IQ 460system.cpu.iew.iewDispSquashedInsts 1261619 # Number of squashed instructions skipped by dispatch 461system.cpu.iew.iewDispLoadInsts 128894590 # Number of dispatched load instructions 462system.cpu.iew.iewDispStoreInsts 45939948 # Number of dispatched store instructions 463system.cpu.iew.iewDispNonSpecInsts 21909 # Number of dispatched non-speculative instructions 464system.cpu.iew.iewIQFullEvents 539997 # Number of times the IQ has become full, causing a stall 465system.cpu.iew.iewLSQFullEvents 37637 # Number of times the LSQ has become full, causing a stall 466system.cpu.iew.memOrderViolationEvents 872144 # Number of memory order violations 467system.cpu.iew.predictedTakenIncorrect 1294345 # Number of branches that were predicted taken incorrectly 468system.cpu.iew.predictedNotTakenIncorrect 6884684 # Number of branches that were predicted not taken incorrectly 469system.cpu.iew.branchMispredicts 8179029 # Number of branch mispredicts detected at execute 470system.cpu.iew.iewExecutedInsts 326602378 # Number of executed instructions 471system.cpu.iew.iewExecLoadInsts 80777118 # Number of load instructions executed 472system.cpu.iew.iewExecSquashedInsts 11963843 # Number of squashed instructions skipped in execute | 466system.cpu.iew.iewSquashCycles 7447845 # Number of cycles IEW is squashing 467system.cpu.iew.iewBlockCycles 35704467 # Number of cycles IEW is blocking 468system.cpu.iew.iewUnblockCycles 582987 # Number of cycles IEW is unblocking 469system.cpu.iew.iewDispatchedInsts 490006290 # Number of instructions dispatched to IQ 470system.cpu.iew.iewDispSquashedInsts 1248239 # Number of squashed instructions skipped by dispatch 471system.cpu.iew.iewDispLoadInsts 128676829 # Number of dispatched load instructions 472system.cpu.iew.iewDispStoreInsts 45848779 # Number of dispatched store instructions 473system.cpu.iew.iewDispNonSpecInsts 22549 # Number of dispatched non-speculative instructions 474system.cpu.iew.iewIQFullEvents 539423 # Number of times the IQ has become full, causing a stall 475system.cpu.iew.iewLSQFullEvents 38394 # Number of times the LSQ has become full, causing a stall 476system.cpu.iew.memOrderViolationEvents 864575 # Number of memory order violations 477system.cpu.iew.predictedTakenIncorrect 1296720 # Number of branches that were predicted taken incorrectly 478system.cpu.iew.predictedNotTakenIncorrect 6850218 # Number of branches that were predicted not taken incorrectly 479system.cpu.iew.branchMispredicts 8146938 # Number of branch mispredicts detected at execute 480system.cpu.iew.iewExecutedInsts 326347367 # Number of executed instructions 481system.cpu.iew.iewExecLoadInsts 80684613 # Number of load instructions executed 482system.cpu.iew.iewExecSquashedInsts 11920829 # Number of squashed instructions skipped in execute |
| 473system.cpu.iew.exec_swp 0 # number of swp insts executed 474system.cpu.iew.exec_nop 0 # number of nop insts executed | 483system.cpu.iew.exec_swp 0 # number of swp insts executed 484system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 475system.cpu.iew.exec_refs 106442155 # number of memory reference insts executed 476system.cpu.iew.exec_branches 18940356 # Number of branches executed 477system.cpu.iew.exec_stores 25665037 # Number of stores executed 478system.cpu.iew.exec_rate 1.581174 # Inst execution rate 479system.cpu.iew.wb_sent 322715986 # cumulative count of insts sent to commit 480system.cpu.iew.wb_count 319688722 # cumulative count of insts written-back 481system.cpu.iew.wb_producers 256576217 # num instructions producing a value 482system.cpu.iew.wb_consumers 435723594 # num instructions consuming a value 483system.cpu.iew.wb_rate 1.547703 # insts written-back per cycle 484system.cpu.iew.wb_fanout 0.588851 # average fanout of values written-back 485system.cpu.commit.commitSquashedInsts 269420821 # The number of squashed insts skipped by commit | 485system.cpu.iew.exec_refs 106316260 # number of memory reference insts executed 486system.cpu.iew.exec_branches 18920718 # Number of branches executed 487system.cpu.iew.exec_stores 25631647 # Number of stores executed 488system.cpu.iew.exec_rate 1.581303 # Inst execution rate 489system.cpu.iew.wb_sent 322480012 # cumulative count of insts sent to commit 490system.cpu.iew.wb_count 319466137 # cumulative count of insts written-back 491system.cpu.iew.wb_producers 256417161 # num instructions producing a value 492system.cpu.iew.wb_consumers 435540007 # num instructions consuming a value 493system.cpu.iew.wb_rate 1.547961 # insts written-back per cycle 494system.cpu.iew.wb_fanout 0.588734 # average fanout of values written-back 495system.cpu.commit.commitSquashedInsts 268667644 # The number of squashed insts skipped by commit |
| 486system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards | 496system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards |
| 487system.cpu.commit.branchMispredicts 6753005 # The number of times a branch was mispredicted 488system.cpu.commit.committed_per_cycle::samples 163742250 # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::mean 1.351901 # Number of insts commited each cycle 490system.cpu.commit.committed_per_cycle::stdev 1.936120 # Number of insts commited each cycle | 497system.cpu.commit.branchMispredicts 6725958 # The number of times a branch was mispredicted 498system.cpu.commit.committed_per_cycle::samples 163655626 # Number of insts commited each cycle 499system.cpu.commit.committed_per_cycle::mean 1.352617 # Number of insts commited each cycle 500system.cpu.commit.committed_per_cycle::stdev 1.935975 # Number of insts commited each cycle |
| 491system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 501system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 492system.cpu.commit.committed_per_cycle::0 67180478 41.03% 41.03% # Number of insts commited each cycle 493system.cpu.commit.committed_per_cycle::1 54846489 33.50% 74.52% # Number of insts commited each cycle 494system.cpu.commit.committed_per_cycle::2 13227508 8.08% 82.60% # Number of insts commited each cycle 495system.cpu.commit.committed_per_cycle::3 10675855 6.52% 89.12% # Number of insts commited each cycle 496system.cpu.commit.committed_per_cycle::4 5434961 3.32% 92.44% # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::5 3126709 1.91% 94.35% # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::6 1096647 0.67% 95.02% # Number of insts commited each cycle 499system.cpu.commit.committed_per_cycle::7 1147781 0.70% 95.72% # Number of insts commited each cycle 500system.cpu.commit.committed_per_cycle::8 7005822 4.28% 100.00% # Number of insts commited each cycle | 502system.cpu.commit.committed_per_cycle::0 67077696 40.99% 40.99% # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::1 54856110 33.52% 74.51% # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::2 13235317 8.09% 82.59% # Number of insts commited each cycle 505system.cpu.commit.committed_per_cycle::3 10672053 6.52% 89.11% # Number of insts commited each cycle 506system.cpu.commit.committed_per_cycle::4 5439540 3.32% 92.44% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::5 3134329 1.92% 94.35% # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::6 1088236 0.66% 95.02% # Number of insts commited each cycle 509system.cpu.commit.committed_per_cycle::7 1157500 0.71% 95.73% # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::8 6994845 4.27% 100.00% # Number of insts commited each cycle |
| 501system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 511system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 512system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 513system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 504system.cpu.commit.committed_per_cycle::total 163742250 # Number of insts commited each cycle | 514system.cpu.commit.committed_per_cycle::total 163655626 # Number of insts commited each cycle |
| 505system.cpu.commit.committedInsts 132071192 # Number of instructions committed 506system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed 507system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 508system.cpu.commit.refs 77165304 # Number of memory references committed 509system.cpu.commit.loads 56649587 # Number of loads committed 510system.cpu.commit.membars 0 # Number of memory barriers committed 511system.cpu.commit.branches 12326938 # Number of branches committed 512system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 542system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction 543system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction 544system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction 545system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction 546system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction 547system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 548system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 549system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction | 515system.cpu.commit.committedInsts 132071192 # Number of instructions committed 516system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed 517system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 518system.cpu.commit.refs 77165304 # Number of memory references committed 519system.cpu.commit.loads 56649587 # Number of loads committed 520system.cpu.commit.membars 0 # Number of memory barriers committed 521system.cpu.commit.branches 12326938 # Number of branches committed 522system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 552system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction 553system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction 554system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction 555system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction 556system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction 557system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 558system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 559system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction |
| 550system.cpu.commit.bw_lim_events 7005822 # number cycles where commit BW limit reached 551system.cpu.rob.rob_reads 647520633 # The number of ROB reads 552system.cpu.rob.rob_writes 1024585644 # The number of ROB writes 553system.cpu.timesIdled 2803 # Number of times that the entire CPU went into an idle state and unscheduled itself 554system.cpu.idleCycles 199750 # Total number of cycles that the CPU has spent unscheduled due to idling | 560system.cpu.commit.bw_lim_events 6994845 # number cycles where commit BW limit reached 561system.cpu.rob.rob_reads 646691809 # The number of ROB reads 562system.cpu.rob.rob_writes 1022946396 # The number of ROB writes 563system.cpu.timesIdled 2819 # Number of times that the entire CPU went into an idle state and unscheduled itself 564system.cpu.idleCycles 240253 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 555system.cpu.committedInsts 132071192 # Number of Instructions Simulated 556system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated | 565system.cpu.committedInsts 132071192 # Number of Instructions Simulated 566system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated |
| 557system.cpu.cpi 1.563981 # CPI: Cycles Per Instruction 558system.cpu.cpi_total 1.563981 # CPI: Total CPI of All Threads 559system.cpu.ipc 0.639394 # IPC: Instructions Per Cycle 560system.cpu.ipc_total 0.639394 # IPC: Total IPC of All Threads 561system.cpu.int_regfile_reads 524858514 # number of integer regfile reads 562system.cpu.int_regfile_writes 289109549 # number of integer regfile writes 563system.cpu.fp_regfile_reads 4527972 # number of floating regfile reads 564system.cpu.fp_regfile_writes 3322072 # number of floating regfile writes 565system.cpu.cc_regfile_reads 107078976 # number of cc regfile reads 566system.cpu.cc_regfile_writes 65816113 # number of cc regfile writes 567system.cpu.misc_regfile_reads 177007720 # number of misc regfile reads | 567system.cpu.cpi 1.562632 # CPI: Cycles Per Instruction 568system.cpu.cpi_total 1.562632 # CPI: Total CPI of All Threads 569system.cpu.ipc 0.639946 # IPC: Instructions Per Cycle 570system.cpu.ipc_total 0.639946 # IPC: Total IPC of All Threads 571system.cpu.int_regfile_reads 524499390 # number of integer regfile reads 572system.cpu.int_regfile_writes 288922915 # number of integer regfile writes 573system.cpu.fp_regfile_reads 4524370 # number of floating regfile reads 574system.cpu.fp_regfile_writes 3323309 # number of floating regfile writes 575system.cpu.cc_regfile_reads 107020933 # number of cc regfile reads 576system.cpu.cc_regfile_writes 65779043 # number of cc regfile writes 577system.cpu.misc_regfile_reads 176790948 # number of misc regfile reads |
| 568system.cpu.misc_regfile_writes 1689 # number of misc regfile writes | 578system.cpu.misc_regfile_writes 1689 # number of misc regfile writes |
| 569system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states 570system.cpu.dcache.tags.replacements 77 # number of replacements 571system.cpu.dcache.tags.tagsinuse 1524.395872 # Cycle average of tags in use 572system.cpu.dcache.tags.total_refs 82831685 # Total number of references to valid blocks. 573system.cpu.dcache.tags.sampled_refs 2117 # Sample count of references to valid blocks. 574system.cpu.dcache.tags.avg_refs 39126.917808 # Average number of references to valid blocks. | 579system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states 580system.cpu.dcache.tags.replacements 81 # number of replacements 581system.cpu.dcache.tags.tagsinuse 1508.634180 # Cycle average of tags in use 582system.cpu.dcache.tags.total_refs 82760913 # Total number of references to valid blocks. 583system.cpu.dcache.tags.sampled_refs 2105 # Sample count of references to valid blocks. 584system.cpu.dcache.tags.avg_refs 39316.348219 # Average number of references to valid blocks. |
| 575system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 585system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 576system.cpu.dcache.tags.occ_blocks::cpu.data 1524.395872 # Average occupied blocks per requestor 577system.cpu.dcache.tags.occ_percent::cpu.data 0.372167 # Average percentage of cache occupancy 578system.cpu.dcache.tags.occ_percent::total 0.372167 # Average percentage of cache occupancy 579system.cpu.dcache.tags.occ_task_id_blocks::1024 2040 # Occupied blocks per task id 580system.cpu.dcache.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id 581system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id 582system.cpu.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id 583system.cpu.dcache.tags.age_task_id_blocks_1024::3 411 # Occupied blocks per task id 584system.cpu.dcache.tags.age_task_id_blocks_1024::4 1479 # Occupied blocks per task id 585system.cpu.dcache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id 586system.cpu.dcache.tags.tag_accesses 165670739 # Number of tag accesses 587system.cpu.dcache.tags.data_accesses 165670739 # Number of data accesses 588system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states 589system.cpu.dcache.ReadReq_hits::cpu.data 62317357 # number of ReadReq hits 590system.cpu.dcache.ReadReq_hits::total 62317357 # number of ReadReq hits 591system.cpu.dcache.WriteReq_hits::cpu.data 20513773 # number of WriteReq hits 592system.cpu.dcache.WriteReq_hits::total 20513773 # number of WriteReq hits 593system.cpu.dcache.demand_hits::cpu.data 82831130 # number of demand (read+write) hits 594system.cpu.dcache.demand_hits::total 82831130 # number of demand (read+write) hits 595system.cpu.dcache.overall_hits::cpu.data 82831130 # number of overall hits 596system.cpu.dcache.overall_hits::total 82831130 # number of overall hits 597system.cpu.dcache.ReadReq_misses::cpu.data 1223 # number of ReadReq misses 598system.cpu.dcache.ReadReq_misses::total 1223 # number of ReadReq misses 599system.cpu.dcache.WriteReq_misses::cpu.data 1958 # number of WriteReq misses 600system.cpu.dcache.WriteReq_misses::total 1958 # number of WriteReq misses 601system.cpu.dcache.demand_misses::cpu.data 3181 # number of demand (read+write) misses 602system.cpu.dcache.demand_misses::total 3181 # number of demand (read+write) misses 603system.cpu.dcache.overall_misses::cpu.data 3181 # number of overall misses 604system.cpu.dcache.overall_misses::total 3181 # number of overall misses 605system.cpu.dcache.ReadReq_miss_latency::cpu.data 77985000 # number of ReadReq miss cycles 606system.cpu.dcache.ReadReq_miss_latency::total 77985000 # number of ReadReq miss cycles 607system.cpu.dcache.WriteReq_miss_latency::cpu.data 124974000 # number of WriteReq miss cycles 608system.cpu.dcache.WriteReq_miss_latency::total 124974000 # number of WriteReq miss cycles 609system.cpu.dcache.demand_miss_latency::cpu.data 202959000 # number of demand (read+write) miss cycles 610system.cpu.dcache.demand_miss_latency::total 202959000 # number of demand (read+write) miss cycles 611system.cpu.dcache.overall_miss_latency::cpu.data 202959000 # number of overall miss cycles 612system.cpu.dcache.overall_miss_latency::total 202959000 # number of overall miss cycles 613system.cpu.dcache.ReadReq_accesses::cpu.data 62318580 # number of ReadReq accesses(hits+misses) 614system.cpu.dcache.ReadReq_accesses::total 62318580 # number of ReadReq accesses(hits+misses) | 586system.cpu.dcache.tags.occ_blocks::cpu.data 1508.634180 # Average occupied blocks per requestor 587system.cpu.dcache.tags.occ_percent::cpu.data 0.368319 # Average percentage of cache occupancy 588system.cpu.dcache.tags.occ_percent::total 0.368319 # Average percentage of cache occupancy 589system.cpu.dcache.tags.occ_task_id_blocks::1024 2024 # Occupied blocks per task id 590system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id 591system.cpu.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id 592system.cpu.dcache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id 593system.cpu.dcache.tags.age_task_id_blocks_1024::3 423 # Occupied blocks per task id 594system.cpu.dcache.tags.age_task_id_blocks_1024::4 1459 # Occupied blocks per task id 595system.cpu.dcache.tags.occ_task_id_percent::1024 0.494141 # Percentage of cache occupancy per task id 596system.cpu.dcache.tags.tag_accesses 165529197 # Number of tag accesses 597system.cpu.dcache.tags.data_accesses 165529197 # Number of data accesses 598system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states 599system.cpu.dcache.ReadReq_hits::cpu.data 62246604 # number of ReadReq hits 600system.cpu.dcache.ReadReq_hits::total 62246604 # number of ReadReq hits 601system.cpu.dcache.WriteReq_hits::cpu.data 20513664 # number of WriteReq hits 602system.cpu.dcache.WriteReq_hits::total 20513664 # number of WriteReq hits 603system.cpu.dcache.demand_hits::cpu.data 82760268 # number of demand (read+write) hits 604system.cpu.dcache.demand_hits::total 82760268 # number of demand (read+write) hits 605system.cpu.dcache.overall_hits::cpu.data 82760268 # number of overall hits 606system.cpu.dcache.overall_hits::total 82760268 # number of overall hits 607system.cpu.dcache.ReadReq_misses::cpu.data 1211 # number of ReadReq misses 608system.cpu.dcache.ReadReq_misses::total 1211 # number of ReadReq misses 609system.cpu.dcache.WriteReq_misses::cpu.data 2067 # number of WriteReq misses 610system.cpu.dcache.WriteReq_misses::total 2067 # number of WriteReq misses 611system.cpu.dcache.demand_misses::cpu.data 3278 # number of demand (read+write) misses 612system.cpu.dcache.demand_misses::total 3278 # number of demand (read+write) misses 613system.cpu.dcache.overall_misses::cpu.data 3278 # number of overall misses 614system.cpu.dcache.overall_misses::total 3278 # number of overall misses 615system.cpu.dcache.ReadReq_miss_latency::cpu.data 109883500 # number of ReadReq miss cycles 616system.cpu.dcache.ReadReq_miss_latency::total 109883500 # number of ReadReq miss cycles 617system.cpu.dcache.WriteReq_miss_latency::cpu.data 137432000 # number of WriteReq miss cycles 618system.cpu.dcache.WriteReq_miss_latency::total 137432000 # number of WriteReq miss cycles 619system.cpu.dcache.demand_miss_latency::cpu.data 247315500 # number of demand (read+write) miss cycles 620system.cpu.dcache.demand_miss_latency::total 247315500 # number of demand (read+write) miss cycles 621system.cpu.dcache.overall_miss_latency::cpu.data 247315500 # number of overall miss cycles 622system.cpu.dcache.overall_miss_latency::total 247315500 # number of overall miss cycles 623system.cpu.dcache.ReadReq_accesses::cpu.data 62247815 # number of ReadReq accesses(hits+misses) 624system.cpu.dcache.ReadReq_accesses::total 62247815 # number of ReadReq accesses(hits+misses) |
| 615system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) 616system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) | 625system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) 626system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) |
| 617system.cpu.dcache.demand_accesses::cpu.data 82834311 # number of demand (read+write) accesses 618system.cpu.dcache.demand_accesses::total 82834311 # number of demand (read+write) accesses 619system.cpu.dcache.overall_accesses::cpu.data 82834311 # number of overall (read+write) accesses 620system.cpu.dcache.overall_accesses::total 82834311 # number of overall (read+write) accesses 621system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses 622system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses 623system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000095 # miss rate for WriteReq accesses 624system.cpu.dcache.WriteReq_miss_rate::total 0.000095 # miss rate for WriteReq accesses 625system.cpu.dcache.demand_miss_rate::cpu.data 0.000038 # miss rate for demand accesses 626system.cpu.dcache.demand_miss_rate::total 0.000038 # miss rate for demand accesses 627system.cpu.dcache.overall_miss_rate::cpu.data 0.000038 # miss rate for overall accesses 628system.cpu.dcache.overall_miss_rate::total 0.000038 # miss rate for overall accesses 629system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63765.331153 # average ReadReq miss latency 630system.cpu.dcache.ReadReq_avg_miss_latency::total 63765.331153 # average ReadReq miss latency 631system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63827.374872 # average WriteReq miss latency 632system.cpu.dcache.WriteReq_avg_miss_latency::total 63827.374872 # average WriteReq miss latency 633system.cpu.dcache.demand_avg_miss_latency::cpu.data 63803.520905 # average overall miss latency 634system.cpu.dcache.demand_avg_miss_latency::total 63803.520905 # average overall miss latency 635system.cpu.dcache.overall_avg_miss_latency::cpu.data 63803.520905 # average overall miss latency 636system.cpu.dcache.overall_avg_miss_latency::total 63803.520905 # average overall miss latency 637system.cpu.dcache.blocked_cycles::no_mshrs 403 # number of cycles access was blocked 638system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked 639system.cpu.dcache.blocked::no_mshrs 9 # number of cycles access was blocked | 627system.cpu.dcache.demand_accesses::cpu.data 82763546 # number of demand (read+write) accesses 628system.cpu.dcache.demand_accesses::total 82763546 # number of demand (read+write) accesses 629system.cpu.dcache.overall_accesses::cpu.data 82763546 # number of overall (read+write) accesses 630system.cpu.dcache.overall_accesses::total 82763546 # number of overall (read+write) accesses 631system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses 632system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses 633system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000101 # miss rate for WriteReq accesses 634system.cpu.dcache.WriteReq_miss_rate::total 0.000101 # miss rate for WriteReq accesses 635system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses 636system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses 637system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses 638system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses 639system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 90737.819983 # average ReadReq miss latency 640system.cpu.dcache.ReadReq_avg_miss_latency::total 90737.819983 # average ReadReq miss latency 641system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66488.630866 # average WriteReq miss latency 642system.cpu.dcache.WriteReq_avg_miss_latency::total 66488.630866 # average WriteReq miss latency 643system.cpu.dcache.demand_avg_miss_latency::cpu.data 75447.071385 # average overall miss latency 644system.cpu.dcache.demand_avg_miss_latency::total 75447.071385 # average overall miss latency 645system.cpu.dcache.overall_avg_miss_latency::cpu.data 75447.071385 # average overall miss latency 646system.cpu.dcache.overall_avg_miss_latency::total 75447.071385 # average overall miss latency 647system.cpu.dcache.blocked_cycles::no_mshrs 307 # number of cycles access was blocked 648system.cpu.dcache.blocked_cycles::no_targets 143 # number of cycles access was blocked 649system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked |
| 640system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked | 650system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked |
| 641system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.777778 # average number of cycles each access was blocked 642system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked | 651system.cpu.dcache.avg_blocked_cycles::no_mshrs 76.750000 # average number of cycles each access was blocked 652system.cpu.dcache.avg_blocked_cycles::no_targets 71.500000 # average number of cycles each access was blocked |
| 643system.cpu.dcache.writebacks::writebacks 16 # number of writebacks 644system.cpu.dcache.writebacks::total 16 # number of writebacks | 653system.cpu.dcache.writebacks::writebacks 16 # number of writebacks 654system.cpu.dcache.writebacks::total 16 # number of writebacks |
| 645system.cpu.dcache.ReadReq_mshr_hits::cpu.data 622 # number of ReadReq MSHR hits 646system.cpu.dcache.ReadReq_mshr_hits::total 622 # number of ReadReq MSHR hits 647system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8 # number of WriteReq MSHR hits 648system.cpu.dcache.WriteReq_mshr_hits::total 8 # number of WriteReq MSHR hits 649system.cpu.dcache.demand_mshr_hits::cpu.data 630 # number of demand (read+write) MSHR hits 650system.cpu.dcache.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits 651system.cpu.dcache.overall_mshr_hits::cpu.data 630 # number of overall MSHR hits 652system.cpu.dcache.overall_mshr_hits::total 630 # number of overall MSHR hits 653system.cpu.dcache.ReadReq_mshr_misses::cpu.data 601 # number of ReadReq MSHR misses 654system.cpu.dcache.ReadReq_mshr_misses::total 601 # number of ReadReq MSHR misses 655system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1950 # number of WriteReq MSHR misses 656system.cpu.dcache.WriteReq_mshr_misses::total 1950 # number of WriteReq MSHR misses 657system.cpu.dcache.demand_mshr_misses::cpu.data 2551 # number of demand (read+write) MSHR misses 658system.cpu.dcache.demand_mshr_misses::total 2551 # number of demand (read+write) MSHR misses 659system.cpu.dcache.overall_mshr_misses::cpu.data 2551 # number of overall MSHR misses 660system.cpu.dcache.overall_mshr_misses::total 2551 # number of overall MSHR misses 661system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47286500 # number of ReadReq MSHR miss cycles 662system.cpu.dcache.ReadReq_mshr_miss_latency::total 47286500 # number of ReadReq MSHR miss cycles 663system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 122663000 # number of WriteReq MSHR miss cycles 664system.cpu.dcache.WriteReq_mshr_miss_latency::total 122663000 # number of WriteReq MSHR miss cycles 665system.cpu.dcache.demand_mshr_miss_latency::cpu.data 169949500 # number of demand (read+write) MSHR miss cycles 666system.cpu.dcache.demand_mshr_miss_latency::total 169949500 # number of demand (read+write) MSHR miss cycles 667system.cpu.dcache.overall_mshr_miss_latency::cpu.data 169949500 # number of overall MSHR miss cycles 668system.cpu.dcache.overall_mshr_miss_latency::total 169949500 # number of overall MSHR miss cycles 669system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses 670system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses 671system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000095 # mshr miss rate for WriteReq accesses 672system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000095 # mshr miss rate for WriteReq accesses 673system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for demand accesses 674system.cpu.dcache.demand_mshr_miss_rate::total 0.000031 # mshr miss rate for demand accesses 675system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for overall accesses 676system.cpu.dcache.overall_mshr_miss_rate::total 0.000031 # mshr miss rate for overall accesses 677system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78679.700499 # average ReadReq mshr miss latency 678system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78679.700499 # average ReadReq mshr miss latency 679system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62904.102564 # average WriteReq mshr miss latency 680system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62904.102564 # average WriteReq mshr miss latency 681system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66620.736966 # average overall mshr miss latency 682system.cpu.dcache.demand_avg_mshr_miss_latency::total 66620.736966 # average overall mshr miss latency 683system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66620.736966 # average overall mshr miss latency 684system.cpu.dcache.overall_avg_mshr_miss_latency::total 66620.736966 # average overall mshr miss latency 685system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states 686system.cpu.icache.tags.replacements 6489 # number of replacements 687system.cpu.icache.tags.tagsinuse 1681.757073 # Cycle average of tags in use 688system.cpu.icache.tags.total_refs 41270224 # Total number of references to valid blocks. 689system.cpu.icache.tags.sampled_refs 8478 # Sample count of references to valid blocks. 690system.cpu.icache.tags.avg_refs 4867.919792 # Average number of references to valid blocks. | 655system.cpu.dcache.ReadReq_mshr_hits::cpu.data 626 # number of ReadReq MSHR hits 656system.cpu.dcache.ReadReq_mshr_hits::total 626 # number of ReadReq MSHR hits 657system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6 # number of WriteReq MSHR hits 658system.cpu.dcache.WriteReq_mshr_hits::total 6 # number of WriteReq MSHR hits 659system.cpu.dcache.demand_mshr_hits::cpu.data 632 # number of demand (read+write) MSHR hits 660system.cpu.dcache.demand_mshr_hits::total 632 # number of demand (read+write) MSHR hits 661system.cpu.dcache.overall_mshr_hits::cpu.data 632 # number of overall MSHR hits 662system.cpu.dcache.overall_mshr_hits::total 632 # number of overall MSHR hits 663system.cpu.dcache.ReadReq_mshr_misses::cpu.data 585 # number of ReadReq MSHR misses 664system.cpu.dcache.ReadReq_mshr_misses::total 585 # number of ReadReq MSHR misses 665system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2061 # number of WriteReq MSHR misses 666system.cpu.dcache.WriteReq_mshr_misses::total 2061 # number of WriteReq MSHR misses 667system.cpu.dcache.demand_mshr_misses::cpu.data 2646 # number of demand (read+write) MSHR misses 668system.cpu.dcache.demand_mshr_misses::total 2646 # number of demand (read+write) MSHR misses 669system.cpu.dcache.overall_mshr_misses::cpu.data 2646 # number of overall MSHR misses 670system.cpu.dcache.overall_mshr_misses::total 2646 # number of overall MSHR misses 671system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67088500 # number of ReadReq MSHR miss cycles 672system.cpu.dcache.ReadReq_mshr_miss_latency::total 67088500 # number of ReadReq MSHR miss cycles 673system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 134984000 # number of WriteReq MSHR miss cycles 674system.cpu.dcache.WriteReq_mshr_miss_latency::total 134984000 # number of WriteReq MSHR miss cycles 675system.cpu.dcache.demand_mshr_miss_latency::cpu.data 202072500 # number of demand (read+write) MSHR miss cycles 676system.cpu.dcache.demand_mshr_miss_latency::total 202072500 # number of demand (read+write) MSHR miss cycles 677system.cpu.dcache.overall_mshr_miss_latency::cpu.data 202072500 # number of overall MSHR miss cycles 678system.cpu.dcache.overall_mshr_miss_latency::total 202072500 # number of overall MSHR miss cycles 679system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses 680system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses 681system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000100 # mshr miss rate for WriteReq accesses 682system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000100 # mshr miss rate for WriteReq accesses 683system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses 684system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses 685system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses 686system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses 687system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 114681.196581 # average ReadReq mshr miss latency 688system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 114681.196581 # average ReadReq mshr miss latency 689system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65494.420184 # average WriteReq mshr miss latency 690system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65494.420184 # average WriteReq mshr miss latency 691system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76369.047619 # average overall mshr miss latency 692system.cpu.dcache.demand_avg_mshr_miss_latency::total 76369.047619 # average overall mshr miss latency 693system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76369.047619 # average overall mshr miss latency 694system.cpu.dcache.overall_avg_mshr_miss_latency::total 76369.047619 # average overall mshr miss latency 695system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states 696system.cpu.icache.tags.replacements 6530 # number of replacements 697system.cpu.icache.tags.tagsinuse 1674.310192 # Cycle average of tags in use 698system.cpu.icache.tags.total_refs 41178058 # Total number of references to valid blocks. 699system.cpu.icache.tags.sampled_refs 8518 # Sample count of references to valid blocks. 700system.cpu.icache.tags.avg_refs 4834.240197 # Average number of references to valid blocks. |
| 691system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 701system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 692system.cpu.icache.tags.occ_blocks::cpu.inst 1681.757073 # Average occupied blocks per requestor 693system.cpu.icache.tags.occ_percent::cpu.inst 0.821170 # Average percentage of cache occupancy 694system.cpu.icache.tags.occ_percent::total 0.821170 # Average percentage of cache occupancy 695system.cpu.icache.tags.occ_task_id_blocks::1024 1989 # Occupied blocks per task id 696system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id 697system.cpu.icache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id 698system.cpu.icache.tags.age_task_id_blocks_1024::2 832 # Occupied blocks per task id 699system.cpu.icache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id 700system.cpu.icache.tags.age_task_id_blocks_1024::4 747 # Occupied blocks per task id 701system.cpu.icache.tags.occ_task_id_percent::1024 0.971191 # Percentage of cache occupancy per task id 702system.cpu.icache.tags.tag_accesses 82575282 # Number of tag accesses 703system.cpu.icache.tags.data_accesses 82575282 # Number of data accesses 704system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states 705system.cpu.icache.ReadReq_hits::cpu.inst 41270227 # number of ReadReq hits 706system.cpu.icache.ReadReq_hits::total 41270227 # number of ReadReq hits 707system.cpu.icache.demand_hits::cpu.inst 41270227 # number of demand (read+write) hits 708system.cpu.icache.demand_hits::total 41270227 # number of demand (read+write) hits 709system.cpu.icache.overall_hits::cpu.inst 41270227 # number of overall hits 710system.cpu.icache.overall_hits::total 41270227 # number of overall hits 711system.cpu.icache.ReadReq_misses::cpu.inst 12961 # number of ReadReq misses 712system.cpu.icache.ReadReq_misses::total 12961 # number of ReadReq misses 713system.cpu.icache.demand_misses::cpu.inst 12961 # number of demand (read+write) misses 714system.cpu.icache.demand_misses::total 12961 # number of demand (read+write) misses 715system.cpu.icache.overall_misses::cpu.inst 12961 # number of overall misses 716system.cpu.icache.overall_misses::total 12961 # number of overall misses 717system.cpu.icache.ReadReq_miss_latency::cpu.inst 483569000 # number of ReadReq miss cycles 718system.cpu.icache.ReadReq_miss_latency::total 483569000 # number of ReadReq miss cycles 719system.cpu.icache.demand_miss_latency::cpu.inst 483569000 # number of demand (read+write) miss cycles 720system.cpu.icache.demand_miss_latency::total 483569000 # number of demand (read+write) miss cycles 721system.cpu.icache.overall_miss_latency::cpu.inst 483569000 # number of overall miss cycles 722system.cpu.icache.overall_miss_latency::total 483569000 # number of overall miss cycles 723system.cpu.icache.ReadReq_accesses::cpu.inst 41283188 # number of ReadReq accesses(hits+misses) 724system.cpu.icache.ReadReq_accesses::total 41283188 # number of ReadReq accesses(hits+misses) 725system.cpu.icache.demand_accesses::cpu.inst 41283188 # number of demand (read+write) accesses 726system.cpu.icache.demand_accesses::total 41283188 # number of demand (read+write) accesses 727system.cpu.icache.overall_accesses::cpu.inst 41283188 # number of overall (read+write) accesses 728system.cpu.icache.overall_accesses::total 41283188 # number of overall (read+write) accesses 729system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000314 # miss rate for ReadReq accesses 730system.cpu.icache.ReadReq_miss_rate::total 0.000314 # miss rate for ReadReq accesses 731system.cpu.icache.demand_miss_rate::cpu.inst 0.000314 # miss rate for demand accesses 732system.cpu.icache.demand_miss_rate::total 0.000314 # miss rate for demand accesses 733system.cpu.icache.overall_miss_rate::cpu.inst 0.000314 # miss rate for overall accesses 734system.cpu.icache.overall_miss_rate::total 0.000314 # miss rate for overall accesses 735system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37309.544017 # average ReadReq miss latency 736system.cpu.icache.ReadReq_avg_miss_latency::total 37309.544017 # average ReadReq miss latency 737system.cpu.icache.demand_avg_miss_latency::cpu.inst 37309.544017 # average overall miss latency 738system.cpu.icache.demand_avg_miss_latency::total 37309.544017 # average overall miss latency 739system.cpu.icache.overall_avg_miss_latency::cpu.inst 37309.544017 # average overall miss latency 740system.cpu.icache.overall_avg_miss_latency::total 37309.544017 # average overall miss latency 741system.cpu.icache.blocked_cycles::no_mshrs 1349 # number of cycles access was blocked 742system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 743system.cpu.icache.blocked::no_mshrs 25 # number of cycles access was blocked 744system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 745system.cpu.icache.avg_blocked_cycles::no_mshrs 53.960000 # average number of cycles each access was blocked 746system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 747system.cpu.icache.writebacks::writebacks 6489 # number of writebacks 748system.cpu.icache.writebacks::total 6489 # number of writebacks 749system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4054 # number of ReadReq MSHR hits 750system.cpu.icache.ReadReq_mshr_hits::total 4054 # number of ReadReq MSHR hits 751system.cpu.icache.demand_mshr_hits::cpu.inst 4054 # number of demand (read+write) MSHR hits 752system.cpu.icache.demand_mshr_hits::total 4054 # number of demand (read+write) MSHR hits 753system.cpu.icache.overall_mshr_hits::cpu.inst 4054 # number of overall MSHR hits 754system.cpu.icache.overall_mshr_hits::total 4054 # number of overall MSHR hits 755system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8907 # number of ReadReq MSHR misses 756system.cpu.icache.ReadReq_mshr_misses::total 8907 # number of ReadReq MSHR misses 757system.cpu.icache.demand_mshr_misses::cpu.inst 8907 # number of demand (read+write) MSHR misses 758system.cpu.icache.demand_mshr_misses::total 8907 # number of demand (read+write) MSHR misses 759system.cpu.icache.overall_mshr_misses::cpu.inst 8907 # number of overall MSHR misses 760system.cpu.icache.overall_mshr_misses::total 8907 # number of overall MSHR misses 761system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 345609000 # number of ReadReq MSHR miss cycles 762system.cpu.icache.ReadReq_mshr_miss_latency::total 345609000 # number of ReadReq MSHR miss cycles 763system.cpu.icache.demand_mshr_miss_latency::cpu.inst 345609000 # number of demand (read+write) MSHR miss cycles 764system.cpu.icache.demand_mshr_miss_latency::total 345609000 # number of demand (read+write) MSHR miss cycles 765system.cpu.icache.overall_mshr_miss_latency::cpu.inst 345609000 # number of overall MSHR miss cycles 766system.cpu.icache.overall_mshr_miss_latency::total 345609000 # number of overall MSHR miss cycles 767system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000216 # mshr miss rate for ReadReq accesses 768system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000216 # mshr miss rate for ReadReq accesses 769system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000216 # mshr miss rate for demand accesses 770system.cpu.icache.demand_mshr_miss_rate::total 0.000216 # mshr miss rate for demand accesses 771system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000216 # mshr miss rate for overall accesses 772system.cpu.icache.overall_mshr_miss_rate::total 0.000216 # mshr miss rate for overall accesses 773system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38801.953520 # average ReadReq mshr miss latency 774system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38801.953520 # average ReadReq mshr miss latency 775system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38801.953520 # average overall mshr miss latency 776system.cpu.icache.demand_avg_mshr_miss_latency::total 38801.953520 # average overall mshr miss latency 777system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38801.953520 # average overall mshr miss latency 778system.cpu.icache.overall_avg_mshr_miss_latency::total 38801.953520 # average overall mshr miss latency 779system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states | 702system.cpu.icache.tags.occ_blocks::cpu.inst 1674.310192 # Average occupied blocks per requestor 703system.cpu.icache.tags.occ_percent::cpu.inst 0.817534 # Average percentage of cache occupancy 704system.cpu.icache.tags.occ_percent::total 0.817534 # Average percentage of cache occupancy 705system.cpu.icache.tags.occ_task_id_blocks::1024 1988 # Occupied blocks per task id 706system.cpu.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id 707system.cpu.icache.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id 708system.cpu.icache.tags.age_task_id_blocks_1024::2 841 # Occupied blocks per task id 709system.cpu.icache.tags.age_task_id_blocks_1024::3 142 # Occupied blocks per task id 710system.cpu.icache.tags.age_task_id_blocks_1024::4 742 # Occupied blocks per task id 711system.cpu.icache.tags.occ_task_id_percent::1024 0.970703 # Percentage of cache occupancy per task id 712system.cpu.icache.tags.tag_accesses 82391597 # Number of tag accesses 713system.cpu.icache.tags.data_accesses 82391597 # Number of data accesses 714system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states 715system.cpu.icache.ReadReq_hits::cpu.inst 41178058 # number of ReadReq hits 716system.cpu.icache.ReadReq_hits::total 41178058 # number of ReadReq hits 717system.cpu.icache.demand_hits::cpu.inst 41178058 # number of demand (read+write) hits 718system.cpu.icache.demand_hits::total 41178058 # number of demand (read+write) hits 719system.cpu.icache.overall_hits::cpu.inst 41178058 # number of overall hits 720system.cpu.icache.overall_hits::total 41178058 # number of overall hits 721system.cpu.icache.ReadReq_misses::cpu.inst 13213 # number of ReadReq misses 722system.cpu.icache.ReadReq_misses::total 13213 # number of ReadReq misses 723system.cpu.icache.demand_misses::cpu.inst 13213 # number of demand (read+write) misses 724system.cpu.icache.demand_misses::total 13213 # number of demand (read+write) misses 725system.cpu.icache.overall_misses::cpu.inst 13213 # number of overall misses 726system.cpu.icache.overall_misses::total 13213 # number of overall misses 727system.cpu.icache.ReadReq_miss_latency::cpu.inst 660957500 # number of ReadReq miss cycles 728system.cpu.icache.ReadReq_miss_latency::total 660957500 # number of ReadReq miss cycles 729system.cpu.icache.demand_miss_latency::cpu.inst 660957500 # number of demand (read+write) miss cycles 730system.cpu.icache.demand_miss_latency::total 660957500 # number of demand (read+write) miss cycles 731system.cpu.icache.overall_miss_latency::cpu.inst 660957500 # number of overall miss cycles 732system.cpu.icache.overall_miss_latency::total 660957500 # number of overall miss cycles 733system.cpu.icache.ReadReq_accesses::cpu.inst 41191271 # number of ReadReq accesses(hits+misses) 734system.cpu.icache.ReadReq_accesses::total 41191271 # number of ReadReq accesses(hits+misses) 735system.cpu.icache.demand_accesses::cpu.inst 41191271 # number of demand (read+write) accesses 736system.cpu.icache.demand_accesses::total 41191271 # number of demand (read+write) accesses 737system.cpu.icache.overall_accesses::cpu.inst 41191271 # number of overall (read+write) accesses 738system.cpu.icache.overall_accesses::total 41191271 # number of overall (read+write) accesses 739system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000321 # miss rate for ReadReq accesses 740system.cpu.icache.ReadReq_miss_rate::total 0.000321 # miss rate for ReadReq accesses 741system.cpu.icache.demand_miss_rate::cpu.inst 0.000321 # miss rate for demand accesses 742system.cpu.icache.demand_miss_rate::total 0.000321 # miss rate for demand accesses 743system.cpu.icache.overall_miss_rate::cpu.inst 0.000321 # miss rate for overall accesses 744system.cpu.icache.overall_miss_rate::total 0.000321 # miss rate for overall accesses 745system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50023.272535 # average ReadReq miss latency 746system.cpu.icache.ReadReq_avg_miss_latency::total 50023.272535 # average ReadReq miss latency 747system.cpu.icache.demand_avg_miss_latency::cpu.inst 50023.272535 # average overall miss latency 748system.cpu.icache.demand_avg_miss_latency::total 50023.272535 # average overall miss latency 749system.cpu.icache.overall_avg_miss_latency::cpu.inst 50023.272535 # average overall miss latency 750system.cpu.icache.overall_avg_miss_latency::total 50023.272535 # average overall miss latency 751system.cpu.icache.blocked_cycles::no_mshrs 1885 # number of cycles access was blocked 752system.cpu.icache.blocked_cycles::no_targets 842 # number of cycles access was blocked 753system.cpu.icache.blocked::no_mshrs 30 # number of cycles access was blocked 754system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 755system.cpu.icache.avg_blocked_cycles::no_mshrs 62.833333 # average number of cycles each access was blocked 756system.cpu.icache.avg_blocked_cycles::no_targets 842 # average number of cycles each access was blocked 757system.cpu.icache.writebacks::writebacks 6530 # number of writebacks 758system.cpu.icache.writebacks::total 6530 # number of writebacks 759system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4157 # number of ReadReq MSHR hits 760system.cpu.icache.ReadReq_mshr_hits::total 4157 # number of ReadReq MSHR hits 761system.cpu.icache.demand_mshr_hits::cpu.inst 4157 # number of demand (read+write) MSHR hits 762system.cpu.icache.demand_mshr_hits::total 4157 # number of demand (read+write) MSHR hits 763system.cpu.icache.overall_mshr_hits::cpu.inst 4157 # number of overall MSHR hits 764system.cpu.icache.overall_mshr_hits::total 4157 # number of overall MSHR hits 765system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9056 # number of ReadReq MSHR misses 766system.cpu.icache.ReadReq_mshr_misses::total 9056 # number of ReadReq MSHR misses 767system.cpu.icache.demand_mshr_misses::cpu.inst 9056 # number of demand (read+write) MSHR misses 768system.cpu.icache.demand_mshr_misses::total 9056 # number of demand (read+write) MSHR misses 769system.cpu.icache.overall_mshr_misses::cpu.inst 9056 # number of overall MSHR misses 770system.cpu.icache.overall_mshr_misses::total 9056 # number of overall MSHR misses 771system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 451350000 # number of ReadReq MSHR miss cycles 772system.cpu.icache.ReadReq_mshr_miss_latency::total 451350000 # number of ReadReq MSHR miss cycles 773system.cpu.icache.demand_mshr_miss_latency::cpu.inst 451350000 # number of demand (read+write) MSHR miss cycles 774system.cpu.icache.demand_mshr_miss_latency::total 451350000 # number of demand (read+write) MSHR miss cycles 775system.cpu.icache.overall_mshr_miss_latency::cpu.inst 451350000 # number of overall MSHR miss cycles 776system.cpu.icache.overall_mshr_miss_latency::total 451350000 # number of overall MSHR miss cycles 777system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000220 # mshr miss rate for ReadReq accesses 778system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000220 # mshr miss rate for ReadReq accesses 779system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000220 # mshr miss rate for demand accesses 780system.cpu.icache.demand_mshr_miss_rate::total 0.000220 # mshr miss rate for demand accesses 781system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000220 # mshr miss rate for overall accesses 782system.cpu.icache.overall_mshr_miss_rate::total 0.000220 # mshr miss rate for overall accesses 783system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49839.885159 # average ReadReq mshr miss latency 784system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49839.885159 # average ReadReq mshr miss latency 785system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49839.885159 # average overall mshr miss latency 786system.cpu.icache.demand_avg_mshr_miss_latency::total 49839.885159 # average overall mshr miss latency 787system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49839.885159 # average overall mshr miss latency 788system.cpu.icache.overall_avg_mshr_miss_latency::total 49839.885159 # average overall mshr miss latency 789system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states |
| 780system.cpu.l2cache.tags.replacements 0 # number of replacements | 790system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 781system.cpu.l2cache.tags.tagsinuse 3906.658043 # Cycle average of tags in use 782system.cpu.l2cache.tags.total_refs 11874 # Total number of references to valid blocks. 783system.cpu.l2cache.tags.sampled_refs 5667 # Sample count of references to valid blocks. 784system.cpu.l2cache.tags.avg_refs 2.095289 # Average number of references to valid blocks. | 791system.cpu.l2cache.tags.tagsinuse 3894.223765 # Cycle average of tags in use 792system.cpu.l2cache.tags.total_refs 12041 # Total number of references to valid blocks. 793system.cpu.l2cache.tags.sampled_refs 5669 # Sample count of references to valid blocks. 794system.cpu.l2cache.tags.avg_refs 2.124008 # Average number of references to valid blocks. |
| 785system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 795system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 786system.cpu.l2cache.tags.occ_blocks::cpu.inst 2417.494362 # Average occupied blocks per requestor 787system.cpu.l2cache.tags.occ_blocks::cpu.data 1489.163681 # Average occupied blocks per requestor 788system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073776 # Average percentage of cache occupancy 789system.cpu.l2cache.tags.occ_percent::cpu.data 0.045446 # Average percentage of cache occupancy 790system.cpu.l2cache.tags.occ_percent::total 0.119222 # Average percentage of cache occupancy 791system.cpu.l2cache.tags.occ_task_id_blocks::1024 5667 # Occupied blocks per task id | 796system.cpu.l2cache.tags.occ_blocks::cpu.inst 2411.748228 # Average occupied blocks per requestor 797system.cpu.l2cache.tags.occ_blocks::cpu.data 1482.475537 # Average occupied blocks per requestor 798system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073601 # Average percentage of cache occupancy 799system.cpu.l2cache.tags.occ_percent::cpu.data 0.045242 # Average percentage of cache occupancy 800system.cpu.l2cache.tags.occ_percent::total 0.118842 # Average percentage of cache occupancy 801system.cpu.l2cache.tags.occ_task_id_blocks::1024 5669 # Occupied blocks per task id |
| 792system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id | 802system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id |
| 793system.cpu.l2cache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id | 803system.cpu.l2cache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id |
| 794system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1008 # Occupied blocks per task id | 804system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1008 # Occupied blocks per task id |
| 795system.cpu.l2cache.tags.age_task_id_blocks_1024::3 510 # Occupied blocks per task id 796system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3942 # Occupied blocks per task id 797system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172943 # Percentage of cache occupancy per task id 798system.cpu.l2cache.tags.tag_accesses 146003 # Number of tag accesses 799system.cpu.l2cache.tags.data_accesses 146003 # Number of data accesses 800system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states | 805system.cpu.l2cache.tags.age_task_id_blocks_1024::3 525 # Occupied blocks per task id 806system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3930 # Occupied blocks per task id 807system.cpu.l2cache.tags.occ_task_id_percent::1024 0.173004 # Percentage of cache occupancy per task id 808system.cpu.l2cache.tags.tag_accesses 147349 # Number of tag accesses 809system.cpu.l2cache.tags.data_accesses 147349 # Number of data accesses 810system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states |
| 801system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits 802system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits | 811system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits 812system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits |
| 803system.cpu.l2cache.WritebackClean_hits::writebacks 6443 # number of WritebackClean hits 804system.cpu.l2cache.WritebackClean_hits::total 6443 # number of WritebackClean hits 805system.cpu.l2cache.UpgradeReq_hits::cpu.data 433 # number of UpgradeReq hits 806system.cpu.l2cache.UpgradeReq_hits::total 433 # number of UpgradeReq hits | 813system.cpu.l2cache.WritebackClean_hits::writebacks 6476 # number of WritebackClean hits 814system.cpu.l2cache.WritebackClean_hits::total 6476 # number of WritebackClean hits 815system.cpu.l2cache.UpgradeReq_hits::cpu.data 541 # number of UpgradeReq hits 816system.cpu.l2cache.UpgradeReq_hits::total 541 # number of UpgradeReq hits |
| 807system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # number of ReadExReq hits 808system.cpu.l2cache.ReadExReq_hits::total 7 # number of ReadExReq hits | 817system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # number of ReadExReq hits 818system.cpu.l2cache.ReadExReq_hits::total 7 # number of ReadExReq hits |
| 809system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4846 # number of ReadCleanReq hits 810system.cpu.l2cache.ReadCleanReq_hits::total 4846 # number of ReadCleanReq hits 811system.cpu.l2cache.ReadSharedReq_hits::cpu.data 71 # number of ReadSharedReq hits 812system.cpu.l2cache.ReadSharedReq_hits::total 71 # number of ReadSharedReq hits 813system.cpu.l2cache.demand_hits::cpu.inst 4846 # number of demand (read+write) hits 814system.cpu.l2cache.demand_hits::cpu.data 78 # number of demand (read+write) hits 815system.cpu.l2cache.demand_hits::total 4924 # number of demand (read+write) hits 816system.cpu.l2cache.overall_hits::cpu.inst 4846 # number of overall hits 817system.cpu.l2cache.overall_hits::cpu.data 78 # number of overall hits 818system.cpu.l2cache.overall_hits::total 4924 # number of overall hits 819system.cpu.l2cache.ReadExReq_misses::cpu.data 1512 # number of ReadExReq misses 820system.cpu.l2cache.ReadExReq_misses::total 1512 # number of ReadExReq misses 821system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3628 # number of ReadCleanReq misses 822system.cpu.l2cache.ReadCleanReq_misses::total 3628 # number of ReadCleanReq misses 823system.cpu.l2cache.ReadSharedReq_misses::cpu.data 528 # number of ReadSharedReq misses 824system.cpu.l2cache.ReadSharedReq_misses::total 528 # number of ReadSharedReq misses 825system.cpu.l2cache.demand_misses::cpu.inst 3628 # number of demand (read+write) misses 826system.cpu.l2cache.demand_misses::cpu.data 2040 # number of demand (read+write) misses 827system.cpu.l2cache.demand_misses::total 5668 # number of demand (read+write) misses 828system.cpu.l2cache.overall_misses::cpu.inst 3628 # number of overall misses 829system.cpu.l2cache.overall_misses::cpu.data 2040 # number of overall misses 830system.cpu.l2cache.overall_misses::total 5668 # number of overall misses 831system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 114827000 # number of ReadExReq miss cycles 832system.cpu.l2cache.ReadExReq_miss_latency::total 114827000 # number of ReadExReq miss cycles 833system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 280498500 # number of ReadCleanReq miss cycles 834system.cpu.l2cache.ReadCleanReq_miss_latency::total 280498500 # number of ReadCleanReq miss cycles 835system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 45425000 # number of ReadSharedReq miss cycles 836system.cpu.l2cache.ReadSharedReq_miss_latency::total 45425000 # number of ReadSharedReq miss cycles 837system.cpu.l2cache.demand_miss_latency::cpu.inst 280498500 # number of demand (read+write) miss cycles 838system.cpu.l2cache.demand_miss_latency::cpu.data 160252000 # number of demand (read+write) miss cycles 839system.cpu.l2cache.demand_miss_latency::total 440750500 # number of demand (read+write) miss cycles 840system.cpu.l2cache.overall_miss_latency::cpu.inst 280498500 # number of overall miss cycles 841system.cpu.l2cache.overall_miss_latency::cpu.data 160252000 # number of overall miss cycles 842system.cpu.l2cache.overall_miss_latency::total 440750500 # number of overall miss cycles | 819system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4877 # number of ReadCleanReq hits 820system.cpu.l2cache.ReadCleanReq_hits::total 4877 # number of ReadCleanReq hits 821system.cpu.l2cache.ReadSharedReq_hits::cpu.data 65 # number of ReadSharedReq hits 822system.cpu.l2cache.ReadSharedReq_hits::total 65 # number of ReadSharedReq hits 823system.cpu.l2cache.demand_hits::cpu.inst 4877 # number of demand (read+write) hits 824system.cpu.l2cache.demand_hits::cpu.data 72 # number of demand (read+write) hits 825system.cpu.l2cache.demand_hits::total 4949 # number of demand (read+write) hits 826system.cpu.l2cache.overall_hits::cpu.inst 4877 # number of overall hits 827system.cpu.l2cache.overall_hits::cpu.data 72 # number of overall hits 828system.cpu.l2cache.overall_hits::total 4949 # number of overall hits 829system.cpu.l2cache.ReadExReq_misses::cpu.data 1515 # number of ReadExReq misses 830system.cpu.l2cache.ReadExReq_misses::total 1515 # number of ReadExReq misses 831system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3636 # number of ReadCleanReq misses 832system.cpu.l2cache.ReadCleanReq_misses::total 3636 # number of ReadCleanReq misses 833system.cpu.l2cache.ReadSharedReq_misses::cpu.data 518 # number of ReadSharedReq misses 834system.cpu.l2cache.ReadSharedReq_misses::total 518 # number of ReadSharedReq misses 835system.cpu.l2cache.demand_misses::cpu.inst 3636 # number of demand (read+write) misses 836system.cpu.l2cache.demand_misses::cpu.data 2033 # number of demand (read+write) misses 837system.cpu.l2cache.demand_misses::total 5669 # number of demand (read+write) misses 838system.cpu.l2cache.overall_misses::cpu.inst 3636 # number of overall misses 839system.cpu.l2cache.overall_misses::cpu.data 2033 # number of overall misses 840system.cpu.l2cache.overall_misses::total 5669 # number of overall misses 841system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 125752500 # number of ReadExReq miss cycles 842system.cpu.l2cache.ReadExReq_miss_latency::total 125752500 # number of ReadExReq miss cycles 843system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 385523500 # number of ReadCleanReq miss cycles 844system.cpu.l2cache.ReadCleanReq_miss_latency::total 385523500 # number of ReadCleanReq miss cycles 845system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 65306000 # number of ReadSharedReq miss cycles 846system.cpu.l2cache.ReadSharedReq_miss_latency::total 65306000 # number of ReadSharedReq miss cycles 847system.cpu.l2cache.demand_miss_latency::cpu.inst 385523500 # number of demand (read+write) miss cycles 848system.cpu.l2cache.demand_miss_latency::cpu.data 191058500 # number of demand (read+write) miss cycles 849system.cpu.l2cache.demand_miss_latency::total 576582000 # number of demand (read+write) miss cycles 850system.cpu.l2cache.overall_miss_latency::cpu.inst 385523500 # number of overall miss cycles 851system.cpu.l2cache.overall_miss_latency::cpu.data 191058500 # number of overall miss cycles 852system.cpu.l2cache.overall_miss_latency::total 576582000 # number of overall miss cycles |
| 843system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses) 844system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses) | 853system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses) 854system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses) |
| 845system.cpu.l2cache.WritebackClean_accesses::writebacks 6443 # number of WritebackClean accesses(hits+misses) 846system.cpu.l2cache.WritebackClean_accesses::total 6443 # number of WritebackClean accesses(hits+misses) 847system.cpu.l2cache.UpgradeReq_accesses::cpu.data 433 # number of UpgradeReq accesses(hits+misses) 848system.cpu.l2cache.UpgradeReq_accesses::total 433 # number of UpgradeReq accesses(hits+misses) 849system.cpu.l2cache.ReadExReq_accesses::cpu.data 1519 # number of ReadExReq accesses(hits+misses) 850system.cpu.l2cache.ReadExReq_accesses::total 1519 # number of ReadExReq accesses(hits+misses) 851system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8474 # number of ReadCleanReq accesses(hits+misses) 852system.cpu.l2cache.ReadCleanReq_accesses::total 8474 # number of ReadCleanReq accesses(hits+misses) 853system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 599 # number of ReadSharedReq accesses(hits+misses) 854system.cpu.l2cache.ReadSharedReq_accesses::total 599 # number of ReadSharedReq accesses(hits+misses) 855system.cpu.l2cache.demand_accesses::cpu.inst 8474 # number of demand (read+write) accesses 856system.cpu.l2cache.demand_accesses::cpu.data 2118 # number of demand (read+write) accesses 857system.cpu.l2cache.demand_accesses::total 10592 # number of demand (read+write) accesses 858system.cpu.l2cache.overall_accesses::cpu.inst 8474 # number of overall (read+write) accesses 859system.cpu.l2cache.overall_accesses::cpu.data 2118 # number of overall (read+write) accesses 860system.cpu.l2cache.overall_accesses::total 10592 # number of overall (read+write) accesses 861system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995392 # miss rate for ReadExReq accesses 862system.cpu.l2cache.ReadExReq_miss_rate::total 0.995392 # miss rate for ReadExReq accesses 863system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.428133 # miss rate for ReadCleanReq accesses 864system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.428133 # miss rate for ReadCleanReq accesses 865system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.881469 # miss rate for ReadSharedReq accesses 866system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.881469 # miss rate for ReadSharedReq accesses 867system.cpu.l2cache.demand_miss_rate::cpu.inst 0.428133 # miss rate for demand accesses 868system.cpu.l2cache.demand_miss_rate::cpu.data 0.963173 # miss rate for demand accesses 869system.cpu.l2cache.demand_miss_rate::total 0.535121 # miss rate for demand accesses 870system.cpu.l2cache.overall_miss_rate::cpu.inst 0.428133 # miss rate for overall accesses 871system.cpu.l2cache.overall_miss_rate::cpu.data 0.963173 # miss rate for overall accesses 872system.cpu.l2cache.overall_miss_rate::total 0.535121 # miss rate for overall accesses 873system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75943.783069 # average ReadExReq miss latency 874system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75943.783069 # average ReadExReq miss latency 875system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77314.911797 # average ReadCleanReq miss latency 876system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77314.911797 # average ReadCleanReq miss latency 877system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86032.196970 # average ReadSharedReq miss latency 878system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86032.196970 # average ReadSharedReq miss latency 879system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77314.911797 # average overall miss latency 880system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78554.901961 # average overall miss latency 881system.cpu.l2cache.demand_avg_miss_latency::total 77761.203246 # average overall miss latency 882system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77314.911797 # average overall miss latency 883system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78554.901961 # average overall miss latency 884system.cpu.l2cache.overall_avg_miss_latency::total 77761.203246 # average overall miss latency | 855system.cpu.l2cache.WritebackClean_accesses::writebacks 6476 # number of WritebackClean accesses(hits+misses) 856system.cpu.l2cache.WritebackClean_accesses::total 6476 # number of WritebackClean accesses(hits+misses) 857system.cpu.l2cache.UpgradeReq_accesses::cpu.data 541 # number of UpgradeReq accesses(hits+misses) 858system.cpu.l2cache.UpgradeReq_accesses::total 541 # number of UpgradeReq accesses(hits+misses) 859system.cpu.l2cache.ReadExReq_accesses::cpu.data 1522 # number of ReadExReq accesses(hits+misses) 860system.cpu.l2cache.ReadExReq_accesses::total 1522 # number of ReadExReq accesses(hits+misses) 861system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8513 # number of ReadCleanReq accesses(hits+misses) 862system.cpu.l2cache.ReadCleanReq_accesses::total 8513 # number of ReadCleanReq accesses(hits+misses) 863system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 583 # number of ReadSharedReq accesses(hits+misses) 864system.cpu.l2cache.ReadSharedReq_accesses::total 583 # number of ReadSharedReq accesses(hits+misses) 865system.cpu.l2cache.demand_accesses::cpu.inst 8513 # number of demand (read+write) accesses 866system.cpu.l2cache.demand_accesses::cpu.data 2105 # number of demand (read+write) accesses 867system.cpu.l2cache.demand_accesses::total 10618 # number of demand (read+write) accesses 868system.cpu.l2cache.overall_accesses::cpu.inst 8513 # number of overall (read+write) accesses 869system.cpu.l2cache.overall_accesses::cpu.data 2105 # number of overall (read+write) accesses 870system.cpu.l2cache.overall_accesses::total 10618 # number of overall (read+write) accesses 871system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995401 # miss rate for ReadExReq accesses 872system.cpu.l2cache.ReadExReq_miss_rate::total 0.995401 # miss rate for ReadExReq accesses 873system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.427111 # miss rate for ReadCleanReq accesses 874system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.427111 # miss rate for ReadCleanReq accesses 875system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.888508 # miss rate for ReadSharedReq accesses 876system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.888508 # miss rate for ReadSharedReq accesses 877system.cpu.l2cache.demand_miss_rate::cpu.inst 0.427111 # miss rate for demand accesses 878system.cpu.l2cache.demand_miss_rate::cpu.data 0.965796 # miss rate for demand accesses 879system.cpu.l2cache.demand_miss_rate::total 0.533905 # miss rate for demand accesses 880system.cpu.l2cache.overall_miss_rate::cpu.inst 0.427111 # miss rate for overall accesses 881system.cpu.l2cache.overall_miss_rate::cpu.data 0.965796 # miss rate for overall accesses 882system.cpu.l2cache.overall_miss_rate::total 0.533905 # miss rate for overall accesses 883system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83004.950495 # average ReadExReq miss latency 884system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83004.950495 # average ReadExReq miss latency 885system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 106029.565457 # average ReadCleanReq miss latency 886system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 106029.565457 # average ReadCleanReq miss latency 887system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 126073.359073 # average ReadSharedReq miss latency 888system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 126073.359073 # average ReadSharedReq miss latency 889system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 106029.565457 # average overall miss latency 890system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93978.603050 # average overall miss latency 891system.cpu.l2cache.demand_avg_miss_latency::total 101707.884989 # average overall miss latency 892system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 106029.565457 # average overall miss latency 893system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93978.603050 # average overall miss latency 894system.cpu.l2cache.overall_avg_miss_latency::total 101707.884989 # average overall miss latency |
| 885system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 886system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 887system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 888system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 889system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 890system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 895system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 896system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 897system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 898system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 899system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 900system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 891system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1512 # number of ReadExReq MSHR misses 892system.cpu.l2cache.ReadExReq_mshr_misses::total 1512 # number of ReadExReq MSHR misses 893system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3628 # number of ReadCleanReq MSHR misses 894system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3628 # number of ReadCleanReq MSHR misses 895system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 528 # number of ReadSharedReq MSHR misses 896system.cpu.l2cache.ReadSharedReq_mshr_misses::total 528 # number of ReadSharedReq MSHR misses 897system.cpu.l2cache.demand_mshr_misses::cpu.inst 3628 # number of demand (read+write) MSHR misses 898system.cpu.l2cache.demand_mshr_misses::cpu.data 2040 # number of demand (read+write) MSHR misses 899system.cpu.l2cache.demand_mshr_misses::total 5668 # number of demand (read+write) MSHR misses 900system.cpu.l2cache.overall_mshr_misses::cpu.inst 3628 # number of overall MSHR misses 901system.cpu.l2cache.overall_mshr_misses::cpu.data 2040 # number of overall MSHR misses 902system.cpu.l2cache.overall_mshr_misses::total 5668 # number of overall MSHR misses 903system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 99707000 # number of ReadExReq MSHR miss cycles 904system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 99707000 # number of ReadExReq MSHR miss cycles 905system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 244218500 # number of ReadCleanReq MSHR miss cycles 906system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 244218500 # number of ReadCleanReq MSHR miss cycles 907system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 40155000 # number of ReadSharedReq MSHR miss cycles 908system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 40155000 # number of ReadSharedReq MSHR miss cycles 909system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 244218500 # number of demand (read+write) MSHR miss cycles 910system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 139862000 # number of demand (read+write) MSHR miss cycles 911system.cpu.l2cache.demand_mshr_miss_latency::total 384080500 # number of demand (read+write) MSHR miss cycles 912system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 244218500 # number of overall MSHR miss cycles 913system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 139862000 # number of overall MSHR miss cycles 914system.cpu.l2cache.overall_mshr_miss_latency::total 384080500 # number of overall MSHR miss cycles 915system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995392 # mshr miss rate for ReadExReq accesses 916system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995392 # mshr miss rate for ReadExReq accesses 917system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.428133 # mshr miss rate for ReadCleanReq accesses 918system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.428133 # mshr miss rate for ReadCleanReq accesses 919system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.881469 # mshr miss rate for ReadSharedReq accesses 920system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.881469 # mshr miss rate for ReadSharedReq accesses 921system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.428133 # mshr miss rate for demand accesses 922system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963173 # mshr miss rate for demand accesses 923system.cpu.l2cache.demand_mshr_miss_rate::total 0.535121 # mshr miss rate for demand accesses 924system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.428133 # mshr miss rate for overall accesses 925system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963173 # mshr miss rate for overall accesses 926system.cpu.l2cache.overall_mshr_miss_rate::total 0.535121 # mshr miss rate for overall accesses 927system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65943.783069 # average ReadExReq mshr miss latency 928system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65943.783069 # average ReadExReq mshr miss latency 929system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67314.911797 # average ReadCleanReq mshr miss latency 930system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67314.911797 # average ReadCleanReq mshr miss latency 931system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76051.136364 # average ReadSharedReq mshr miss latency 932system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76051.136364 # average ReadSharedReq mshr miss latency 933system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67314.911797 # average overall mshr miss latency 934system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68559.803922 # average overall mshr miss latency 935system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67762.967537 # average overall mshr miss latency 936system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67314.911797 # average overall mshr miss latency 937system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68559.803922 # average overall mshr miss latency 938system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67762.967537 # average overall mshr miss latency 939system.cpu.toL2Bus.snoop_filter.tot_requests 18024 # Total number of requests made to the snoop filter. 940system.cpu.toL2Bus.snoop_filter.hit_single_requests 7043 # Number of requests hitting in the snoop filter with a single holder of the requested data. 941system.cpu.toL2Bus.snoop_filter.hit_multi_requests 478 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. | 901system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1515 # number of ReadExReq MSHR misses 902system.cpu.l2cache.ReadExReq_mshr_misses::total 1515 # number of ReadExReq MSHR misses 903system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3636 # number of ReadCleanReq MSHR misses 904system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3636 # number of ReadCleanReq MSHR misses 905system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 518 # number of ReadSharedReq MSHR misses 906system.cpu.l2cache.ReadSharedReq_mshr_misses::total 518 # number of ReadSharedReq MSHR misses 907system.cpu.l2cache.demand_mshr_misses::cpu.inst 3636 # number of demand (read+write) MSHR misses 908system.cpu.l2cache.demand_mshr_misses::cpu.data 2033 # number of demand (read+write) MSHR misses 909system.cpu.l2cache.demand_mshr_misses::total 5669 # number of demand (read+write) MSHR misses 910system.cpu.l2cache.overall_mshr_misses::cpu.inst 3636 # number of overall MSHR misses 911system.cpu.l2cache.overall_mshr_misses::cpu.data 2033 # number of overall MSHR misses 912system.cpu.l2cache.overall_mshr_misses::total 5669 # number of overall MSHR misses 913system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 110602500 # number of ReadExReq MSHR miss cycles 914system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 110602500 # number of ReadExReq MSHR miss cycles 915system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 349163500 # number of ReadCleanReq MSHR miss cycles 916system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 349163500 # number of ReadCleanReq MSHR miss cycles 917system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 60126000 # number of ReadSharedReq MSHR miss cycles 918system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 60126000 # number of ReadSharedReq MSHR miss cycles 919system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 349163500 # number of demand (read+write) MSHR miss cycles 920system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 170728500 # number of demand (read+write) MSHR miss cycles 921system.cpu.l2cache.demand_mshr_miss_latency::total 519892000 # number of demand (read+write) MSHR miss cycles 922system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 349163500 # number of overall MSHR miss cycles 923system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 170728500 # number of overall MSHR miss cycles 924system.cpu.l2cache.overall_mshr_miss_latency::total 519892000 # number of overall MSHR miss cycles 925system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995401 # mshr miss rate for ReadExReq accesses 926system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995401 # mshr miss rate for ReadExReq accesses 927system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.427111 # mshr miss rate for ReadCleanReq accesses 928system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.427111 # mshr miss rate for ReadCleanReq accesses 929system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.888508 # mshr miss rate for ReadSharedReq accesses 930system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.888508 # mshr miss rate for ReadSharedReq accesses 931system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.427111 # mshr miss rate for demand accesses 932system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.965796 # mshr miss rate for demand accesses 933system.cpu.l2cache.demand_mshr_miss_rate::total 0.533905 # mshr miss rate for demand accesses 934system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.427111 # mshr miss rate for overall accesses 935system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.965796 # mshr miss rate for overall accesses 936system.cpu.l2cache.overall_mshr_miss_rate::total 0.533905 # mshr miss rate for overall accesses 937system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73004.950495 # average ReadExReq mshr miss latency 938system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73004.950495 # average ReadExReq mshr miss latency 939system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 96029.565457 # average ReadCleanReq mshr miss latency 940system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 96029.565457 # average ReadCleanReq mshr miss latency 941system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 116073.359073 # average ReadSharedReq mshr miss latency 942system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 116073.359073 # average ReadSharedReq mshr miss latency 943system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 96029.565457 # average overall mshr miss latency 944system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83978.603050 # average overall mshr miss latency 945system.cpu.l2cache.demand_avg_mshr_miss_latency::total 91707.884989 # average overall mshr miss latency 946system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 96029.565457 # average overall mshr miss latency 947system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83978.603050 # average overall mshr miss latency 948system.cpu.l2cache.overall_avg_mshr_miss_latency::total 91707.884989 # average overall mshr miss latency 949system.cpu.toL2Bus.snoop_filter.tot_requests 18313 # Total number of requests made to the snoop filter. 950system.cpu.toL2Bus.snoop_filter.hit_single_requests 7194 # Number of requests hitting in the snoop filter with a single holder of the requested data. 951system.cpu.toL2Bus.snoop_filter.hit_multi_requests 597 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 942system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 943system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 944system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 952system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 953system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 954system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 945system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states 946system.cpu.toL2Bus.trans_dist::ReadResp 9504 # Transaction distribution | 955system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states 956system.cpu.toL2Bus.trans_dist::ReadResp 9638 # Transaction distribution |
| 947system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution | 957system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution |
| 948system.cpu.toL2Bus.trans_dist::WritebackClean 6489 # Transaction distribution 949system.cpu.toL2Bus.trans_dist::CleanEvict 61 # Transaction distribution 950system.cpu.toL2Bus.trans_dist::UpgradeReq 433 # Transaction distribution 951system.cpu.toL2Bus.trans_dist::UpgradeResp 433 # Transaction distribution 952system.cpu.toL2Bus.trans_dist::ReadExReq 1519 # Transaction distribution 953system.cpu.toL2Bus.trans_dist::ReadExResp 1519 # Transaction distribution 954system.cpu.toL2Bus.trans_dist::ReadCleanReq 8907 # Transaction distribution 955system.cpu.toL2Bus.trans_dist::ReadSharedReq 599 # Transaction distribution 956system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23869 # Packet count per connected master and slave (bytes) 957system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5178 # Packet count per connected master and slave (bytes) 958system.cpu.toL2Bus.pkt_count::total 29047 # Packet count per connected master and slave (bytes) 959system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 957568 # Cumulative packet size per connected master and slave (bytes) 960system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 136512 # Cumulative packet size per connected master and slave (bytes) 961system.cpu.toL2Bus.pkt_size::total 1094080 # Cumulative packet size per connected master and slave (bytes) 962system.cpu.toL2Bus.snoops 433 # Total snoops (count) 963system.cpu.toL2Bus.snoopTraffic 27712 # Total snoop traffic (bytes) 964system.cpu.toL2Bus.snoop_fanout::samples 11458 # Request fanout histogram 965system.cpu.toL2Bus.snoop_fanout::mean 0.082912 # Request fanout histogram 966system.cpu.toL2Bus.snoop_fanout::stdev 0.275760 # Request fanout histogram | 958system.cpu.toL2Bus.trans_dist::WritebackClean 6530 # Transaction distribution 959system.cpu.toL2Bus.trans_dist::CleanEvict 65 # Transaction distribution 960system.cpu.toL2Bus.trans_dist::UpgradeReq 541 # Transaction distribution 961system.cpu.toL2Bus.trans_dist::UpgradeResp 541 # Transaction distribution 962system.cpu.toL2Bus.trans_dist::ReadExReq 1522 # Transaction distribution 963system.cpu.toL2Bus.trans_dist::ReadExResp 1522 # Transaction distribution 964system.cpu.toL2Bus.trans_dist::ReadCleanReq 9056 # Transaction distribution 965system.cpu.toL2Bus.trans_dist::ReadSharedReq 583 # Transaction distribution 966system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24098 # Packet count per connected master and slave (bytes) 967system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5373 # Packet count per connected master and slave (bytes) 968system.cpu.toL2Bus.pkt_count::total 29471 # Packet count per connected master and slave (bytes) 969system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 962688 # Cumulative packet size per connected master and slave (bytes) 970system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 135744 # Cumulative packet size per connected master and slave (bytes) 971system.cpu.toL2Bus.pkt_size::total 1098432 # Cumulative packet size per connected master and slave (bytes) 972system.cpu.toL2Bus.snoops 543 # Total snoops (count) 973system.cpu.toL2Bus.snoopTraffic 34752 # Total snoop traffic (bytes) 974system.cpu.toL2Bus.snoop_fanout::samples 11702 # Request fanout histogram 975system.cpu.toL2Bus.snoop_fanout::mean 0.100496 # Request fanout histogram 976system.cpu.toL2Bus.snoop_fanout::stdev 0.300673 # Request fanout histogram |
| 967system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 977system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 968system.cpu.toL2Bus.snoop_fanout::0 10508 91.71% 91.71% # Request fanout histogram 969system.cpu.toL2Bus.snoop_fanout::1 950 8.29% 100.00% # Request fanout histogram | 978system.cpu.toL2Bus.snoop_fanout::0 10526 89.95% 89.95% # Request fanout histogram 979system.cpu.toL2Bus.snoop_fanout::1 1176 10.05% 100.00% # Request fanout histogram |
| 970system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 971system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 972system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 973system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 980system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 981system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 982system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 983system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 974system.cpu.toL2Bus.snoop_fanout::total 11458 # Request fanout histogram 975system.cpu.toL2Bus.reqLayer0.occupancy 15517998 # Layer occupancy (ticks) | 984system.cpu.toL2Bus.snoop_fanout::total 11702 # Request fanout histogram 985system.cpu.toL2Bus.reqLayer0.occupancy 15702500 # Layer occupancy (ticks) |
| 976system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 986system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 977system.cpu.toL2Bus.respLayer0.occupancy 13359000 # Layer occupancy (ticks) | 987system.cpu.toL2Bus.respLayer0.occupancy 13582500 # Layer occupancy (ticks) |
| 978system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 988system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 979system.cpu.toL2Bus.respLayer1.occupancy 3392501 # Layer occupancy (ticks) | 989system.cpu.toL2Bus.respLayer1.occupancy 3428499 # Layer occupancy (ticks) |
| 980system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 990system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 981system.membus.snoop_filter.tot_requests 5668 # Total number of requests made to the snoop filter. | 991system.membus.snoop_filter.tot_requests 5669 # Total number of requests made to the snoop filter. |
| 982system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 983system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 984system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 985system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 986system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 992system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 993system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 994system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 995system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 996system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 987system.membus.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states 988system.membus.trans_dist::ReadResp 4155 # Transaction distribution 989system.membus.trans_dist::ReadExReq 1512 # Transaction distribution 990system.membus.trans_dist::ReadExResp 1512 # Transaction distribution 991system.membus.trans_dist::ReadSharedReq 4156 # Transaction distribution 992system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11335 # Packet count per connected master and slave (bytes) 993system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11335 # Packet count per connected master and slave (bytes) 994system.membus.pkt_count::total 11335 # Packet count per connected master and slave (bytes) 995system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 362688 # Cumulative packet size per connected master and slave (bytes) 996system.membus.pkt_size_system.cpu.l2cache.mem_side::total 362688 # Cumulative packet size per connected master and slave (bytes) 997system.membus.pkt_size::total 362688 # Cumulative packet size per connected master and slave (bytes) | 997system.membus.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states 998system.membus.trans_dist::ReadResp 4154 # Transaction distribution 999system.membus.trans_dist::ReadExReq 1515 # Transaction distribution 1000system.membus.trans_dist::ReadExResp 1515 # Transaction distribution 1001system.membus.trans_dist::ReadSharedReq 4154 # Transaction distribution 1002system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11338 # Packet count per connected master and slave (bytes) 1003system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11338 # Packet count per connected master and slave (bytes) 1004system.membus.pkt_count::total 11338 # Packet count per connected master and slave (bytes) 1005system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 362816 # Cumulative packet size per connected master and slave (bytes) 1006system.membus.pkt_size_system.cpu.l2cache.mem_side::total 362816 # Cumulative packet size per connected master and slave (bytes) 1007system.membus.pkt_size::total 362816 # Cumulative packet size per connected master and slave (bytes) |
| 998system.membus.snoops 0 # Total snoops (count) 999system.membus.snoopTraffic 0 # Total snoop traffic (bytes) | 1008system.membus.snoops 0 # Total snoops (count) 1009system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 1000system.membus.snoop_fanout::samples 5668 # Request fanout histogram | 1010system.membus.snoop_fanout::samples 5669 # Request fanout histogram |
| 1001system.membus.snoop_fanout::mean 0 # Request fanout histogram 1002system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1003system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1011system.membus.snoop_fanout::mean 0 # Request fanout histogram 1012system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1013system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1004system.membus.snoop_fanout::0 5668 100.00% 100.00% # Request fanout histogram | 1014system.membus.snoop_fanout::0 5669 100.00% 100.00% # Request fanout histogram |
| 1005system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1006system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1007system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1008system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 1015system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1016system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1017system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1018system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 1009system.membus.snoop_fanout::total 5668 # Request fanout histogram 1010system.membus.reqLayer0.occupancy 7074000 # Layer occupancy (ticks) | 1019system.membus.snoop_fanout::total 5669 # Request fanout histogram 1020system.membus.reqLayer0.occupancy 7048500 # Layer occupancy (ticks) |
| 1011system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1021system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1012system.membus.respLayer1.occupancy 30060000 # Layer occupancy (ticks) | 1022system.membus.respLayer1.occupancy 30047500 # Layer occupancy (ticks) |
| 1013system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 1014 1015---------- End Simulation Statistics ---------- | 1023system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 1024 1025---------- End Simulation Statistics ---------- |