| stats.txt (11507:be6065c1d8d2) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.103324 # Number of seconds simulated 4sim_ticks 103324153500 # Number of ticks simulated 5final_tick 103324153500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.103324 # Number of seconds simulated 4sim_ticks 103324153500 # Number of ticks simulated 5final_tick 103324153500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 48808 # Simulator instruction rate (inst/s) 8host_op_rate 81806 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 38183996 # Simulator tick rate (ticks/s) 10host_mem_usage 302208 # Number of bytes of host memory used 11host_seconds 2705.95 # Real time elapsed on the host | 7host_inst_rate 98344 # Simulator instruction rate (inst/s) 8host_op_rate 164833 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 76937982 # Simulator tick rate (ticks/s) 10host_mem_usage 350904 # Number of bytes of host memory used 11host_seconds 1342.95 # Real time elapsed on the host |
| 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221363384 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221363384 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.inst 231488 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 130496 # Number of bytes read from this memory 18system.physmem.bytes_read::total 361984 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 231488 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 231488 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 3617 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 2039 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 5656 # Number of read requests responded to by this memory --- 221 unchanged lines hidden (view full) --- 245system.physmem_1.preBackEnergy 59393774250 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 69133507095 # Total energy per rank (pJ) 247system.physmem_1.averagePower 669.095685 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 98803806250 # Time in different power states 249system.physmem_1.memoryStateTime::REF 3450200000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 1069805000 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.physmem.bytes_read::cpu.inst 231488 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 130496 # Number of bytes read from this memory 19system.physmem.bytes_read::total 361984 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 231488 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 231488 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 3617 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 2039 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 5656 # Number of read requests responded to by this memory --- 221 unchanged lines hidden (view full) --- 246system.physmem_1.preBackEnergy 59393774250 # Energy for precharge background per rank (pJ) 247system.physmem_1.totalEnergy 69133507095 # Total energy per rank (pJ) 248system.physmem_1.averagePower 669.095685 # Core power per rank (mW) 249system.physmem_1.memoryStateTime::IDLE 98803806250 # Time in different power states 250system.physmem_1.memoryStateTime::REF 3450200000 # Time in different power states 251system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 252system.physmem_1.memoryStateTime::ACT 1069805000 # Time in different power states 253system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 254system.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states |
|
| 253system.cpu.branchPred.lookups 40908032 # Number of BP lookups 254system.cpu.branchPred.condPredicted 40908032 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 6741329 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 35316490 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 0 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 3206071 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 604531 # Number of incorrect RAS predictions. 262system.cpu.branchPred.indirectLookups 35316490 # Number of indirect predictor lookups. 263system.cpu.branchPred.indirectHits 9869044 # Number of indirect target hits. 264system.cpu.branchPred.indirectMisses 25447446 # Number of indirect misses. 265system.cpu.branchPredindirectMispredicted 5035252 # Number of mispredicted indirect branches. 266system.cpu_clk_domain.clock 500 # Clock period in ticks | 255system.cpu.branchPred.lookups 40908032 # Number of BP lookups 256system.cpu.branchPred.condPredicted 40908032 # Number of conditional branches predicted 257system.cpu.branchPred.condIncorrect 6741329 # Number of conditional branches incorrect 258system.cpu.branchPred.BTBLookups 35316490 # Number of BTB lookups 259system.cpu.branchPred.BTBHits 0 # Number of BTB hits 260system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 261system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 262system.cpu.branchPred.usedRAS 3206071 # Number of times the RAS was used to get a target. 263system.cpu.branchPred.RASInCorrect 604531 # Number of incorrect RAS predictions. 264system.cpu.branchPred.indirectLookups 35316490 # Number of indirect predictor lookups. 265system.cpu.branchPred.indirectHits 9869044 # Number of indirect target hits. 266system.cpu.branchPred.indirectMisses 25447446 # Number of indirect misses. 267system.cpu.branchPredindirectMispredicted 5035252 # Number of mispredicted indirect branches. 268system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 269system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states |
|
| 267system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks | 270system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks |
| 271system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states 272system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states |
|
| 268system.cpu.workload.num_syscalls 400 # Number of system calls | 273system.cpu.workload.num_syscalls 400 # Number of system calls |
| 274system.cpu.pwrStateResidencyTicks::ON 103324153500 # Cumulative time (in ticks) in various power states |
|
| 269system.cpu.numCycles 206648308 # number of cpu cycles simulated 270system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 271system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 272system.cpu.fetch.icacheStallCycles 46351281 # Number of cycles fetch is stalled on an Icache miss 273system.cpu.fetch.Insts 420030465 # Number of instructions fetch has processed 274system.cpu.fetch.Branches 40908032 # Number of branches that fetch encountered 275system.cpu.fetch.predictedBranches 13075115 # Number of branches that fetch has predicted taken 276system.cpu.fetch.Cycles 152558958 # Number of cycles fetch has run and was not squashing or blocked --- 278 unchanged lines hidden (view full) --- 555system.cpu.int_regfile_reads 524516370 # number of integer regfile reads 556system.cpu.int_regfile_writes 289029189 # number of integer regfile writes 557system.cpu.fp_regfile_reads 4536413 # number of floating regfile reads 558system.cpu.fp_regfile_writes 3331836 # number of floating regfile writes 559system.cpu.cc_regfile_reads 107017358 # number of cc regfile reads 560system.cpu.cc_regfile_writes 65774990 # number of cc regfile writes 561system.cpu.misc_regfile_reads 176892429 # number of misc regfile reads 562system.cpu.misc_regfile_writes 1689 # number of misc regfile writes | 275system.cpu.numCycles 206648308 # number of cpu cycles simulated 276system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 277system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 278system.cpu.fetch.icacheStallCycles 46351281 # Number of cycles fetch is stalled on an Icache miss 279system.cpu.fetch.Insts 420030465 # Number of instructions fetch has processed 280system.cpu.fetch.Branches 40908032 # Number of branches that fetch encountered 281system.cpu.fetch.predictedBranches 13075115 # Number of branches that fetch has predicted taken 282system.cpu.fetch.Cycles 152558958 # Number of cycles fetch has run and was not squashing or blocked --- 278 unchanged lines hidden (view full) --- 561system.cpu.int_regfile_reads 524516370 # number of integer regfile reads 562system.cpu.int_regfile_writes 289029189 # number of integer regfile writes 563system.cpu.fp_regfile_reads 4536413 # number of floating regfile reads 564system.cpu.fp_regfile_writes 3331836 # number of floating regfile writes 565system.cpu.cc_regfile_reads 107017358 # number of cc regfile reads 566system.cpu.cc_regfile_writes 65774990 # number of cc regfile writes 567system.cpu.misc_regfile_reads 176892429 # number of misc regfile reads 568system.cpu.misc_regfile_writes 1689 # number of misc regfile writes |
| 569system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states |
|
| 563system.cpu.dcache.tags.replacements 72 # number of replacements 564system.cpu.dcache.tags.tagsinuse 1525.498489 # Cycle average of tags in use 565system.cpu.dcache.tags.total_refs 82766316 # Total number of references to valid blocks. 566system.cpu.dcache.tags.sampled_refs 2113 # Sample count of references to valid blocks. 567system.cpu.dcache.tags.avg_refs 39170.050166 # Average number of references to valid blocks. 568system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 569system.cpu.dcache.tags.occ_blocks::cpu.data 1525.498489 # Average occupied blocks per requestor 570system.cpu.dcache.tags.occ_percent::cpu.data 0.372436 # Average percentage of cache occupancy 571system.cpu.dcache.tags.occ_percent::total 0.372436 # Average percentage of cache occupancy 572system.cpu.dcache.tags.occ_task_id_blocks::1024 2041 # Occupied blocks per task id 573system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id 574system.cpu.dcache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id 575system.cpu.dcache.tags.age_task_id_blocks_1024::2 101 # Occupied blocks per task id 576system.cpu.dcache.tags.age_task_id_blocks_1024::3 409 # Occupied blocks per task id 577system.cpu.dcache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id 578system.cpu.dcache.tags.occ_task_id_percent::1024 0.498291 # Percentage of cache occupancy per task id 579system.cpu.dcache.tags.tag_accesses 165539971 # Number of tag accesses 580system.cpu.dcache.tags.data_accesses 165539971 # Number of data accesses | 570system.cpu.dcache.tags.replacements 72 # number of replacements 571system.cpu.dcache.tags.tagsinuse 1525.498489 # Cycle average of tags in use 572system.cpu.dcache.tags.total_refs 82766316 # Total number of references to valid blocks. 573system.cpu.dcache.tags.sampled_refs 2113 # Sample count of references to valid blocks. 574system.cpu.dcache.tags.avg_refs 39170.050166 # Average number of references to valid blocks. 575system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 576system.cpu.dcache.tags.occ_blocks::cpu.data 1525.498489 # Average occupied blocks per requestor 577system.cpu.dcache.tags.occ_percent::cpu.data 0.372436 # Average percentage of cache occupancy 578system.cpu.dcache.tags.occ_percent::total 0.372436 # Average percentage of cache occupancy 579system.cpu.dcache.tags.occ_task_id_blocks::1024 2041 # Occupied blocks per task id 580system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id 581system.cpu.dcache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id 582system.cpu.dcache.tags.age_task_id_blocks_1024::2 101 # Occupied blocks per task id 583system.cpu.dcache.tags.age_task_id_blocks_1024::3 409 # Occupied blocks per task id 584system.cpu.dcache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id 585system.cpu.dcache.tags.occ_task_id_percent::1024 0.498291 # Percentage of cache occupancy per task id 586system.cpu.dcache.tags.tag_accesses 165539971 # Number of tag accesses 587system.cpu.dcache.tags.data_accesses 165539971 # Number of data accesses |
| 588system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states |
|
| 581system.cpu.dcache.ReadReq_hits::cpu.data 62251936 # number of ReadReq hits 582system.cpu.dcache.ReadReq_hits::total 62251936 # number of ReadReq hits 583system.cpu.dcache.WriteReq_hits::cpu.data 20513707 # number of WriteReq hits 584system.cpu.dcache.WriteReq_hits::total 20513707 # number of WriteReq hits 585system.cpu.dcache.demand_hits::cpu.data 82765643 # number of demand (read+write) hits 586system.cpu.dcache.demand_hits::total 82765643 # number of demand (read+write) hits 587system.cpu.dcache.overall_hits::cpu.data 82765643 # number of overall hits 588system.cpu.dcache.overall_hits::total 82765643 # number of overall hits --- 80 unchanged lines hidden (view full) --- 669system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79384.359401 # average ReadReq mshr miss latency 670system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79384.359401 # average ReadReq mshr miss latency 671system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64271.938523 # average WriteReq mshr miss latency 672system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64271.938523 # average WriteReq mshr miss latency 673system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67741.214668 # average overall mshr miss latency 674system.cpu.dcache.demand_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency 675system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67741.214668 # average overall mshr miss latency 676system.cpu.dcache.overall_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency | 589system.cpu.dcache.ReadReq_hits::cpu.data 62251936 # number of ReadReq hits 590system.cpu.dcache.ReadReq_hits::total 62251936 # number of ReadReq hits 591system.cpu.dcache.WriteReq_hits::cpu.data 20513707 # number of WriteReq hits 592system.cpu.dcache.WriteReq_hits::total 20513707 # number of WriteReq hits 593system.cpu.dcache.demand_hits::cpu.data 82765643 # number of demand (read+write) hits 594system.cpu.dcache.demand_hits::total 82765643 # number of demand (read+write) hits 595system.cpu.dcache.overall_hits::cpu.data 82765643 # number of overall hits 596system.cpu.dcache.overall_hits::total 82765643 # number of overall hits --- 80 unchanged lines hidden (view full) --- 677system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79384.359401 # average ReadReq mshr miss latency 678system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79384.359401 # average ReadReq mshr miss latency 679system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64271.938523 # average WriteReq mshr miss latency 680system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64271.938523 # average WriteReq mshr miss latency 681system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67741.214668 # average overall mshr miss latency 682system.cpu.dcache.demand_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency 683system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67741.214668 # average overall mshr miss latency 684system.cpu.dcache.overall_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency |
| 685system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states |
|
| 677system.cpu.icache.tags.replacements 6515 # number of replacements 678system.cpu.icache.tags.tagsinuse 1663.291735 # Cycle average of tags in use 679system.cpu.icache.tags.total_refs 41248897 # Total number of references to valid blocks. 680system.cpu.icache.tags.sampled_refs 8499 # Sample count of references to valid blocks. 681system.cpu.icache.tags.avg_refs 4853.382398 # Average number of references to valid blocks. 682system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 683system.cpu.icache.tags.occ_blocks::cpu.inst 1663.291735 # Average occupied blocks per requestor 684system.cpu.icache.tags.occ_percent::cpu.inst 0.812154 # Average percentage of cache occupancy 685system.cpu.icache.tags.occ_percent::total 0.812154 # Average percentage of cache occupancy 686system.cpu.icache.tags.occ_task_id_blocks::1024 1984 # Occupied blocks per task id 687system.cpu.icache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id 688system.cpu.icache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id 689system.cpu.icache.tags.age_task_id_blocks_1024::2 845 # Occupied blocks per task id 690system.cpu.icache.tags.age_task_id_blocks_1024::3 155 # Occupied blocks per task id 691system.cpu.icache.tags.age_task_id_blocks_1024::4 736 # Occupied blocks per task id 692system.cpu.icache.tags.occ_task_id_percent::1024 0.968750 # Percentage of cache occupancy per task id 693system.cpu.icache.tags.tag_accesses 82532972 # Number of tag accesses 694system.cpu.icache.tags.data_accesses 82532972 # Number of data accesses | 686system.cpu.icache.tags.replacements 6515 # number of replacements 687system.cpu.icache.tags.tagsinuse 1663.291735 # Cycle average of tags in use 688system.cpu.icache.tags.total_refs 41248897 # Total number of references to valid blocks. 689system.cpu.icache.tags.sampled_refs 8499 # Sample count of references to valid blocks. 690system.cpu.icache.tags.avg_refs 4853.382398 # Average number of references to valid blocks. 691system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 692system.cpu.icache.tags.occ_blocks::cpu.inst 1663.291735 # Average occupied blocks per requestor 693system.cpu.icache.tags.occ_percent::cpu.inst 0.812154 # Average percentage of cache occupancy 694system.cpu.icache.tags.occ_percent::total 0.812154 # Average percentage of cache occupancy 695system.cpu.icache.tags.occ_task_id_blocks::1024 1984 # Occupied blocks per task id 696system.cpu.icache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id 697system.cpu.icache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id 698system.cpu.icache.tags.age_task_id_blocks_1024::2 845 # Occupied blocks per task id 699system.cpu.icache.tags.age_task_id_blocks_1024::3 155 # Occupied blocks per task id 700system.cpu.icache.tags.age_task_id_blocks_1024::4 736 # Occupied blocks per task id 701system.cpu.icache.tags.occ_task_id_percent::1024 0.968750 # Percentage of cache occupancy per task id 702system.cpu.icache.tags.tag_accesses 82532972 # Number of tag accesses 703system.cpu.icache.tags.data_accesses 82532972 # Number of data accesses |
| 704system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states |
|
| 695system.cpu.icache.ReadReq_hits::cpu.inst 41248897 # number of ReadReq hits 696system.cpu.icache.ReadReq_hits::total 41248897 # number of ReadReq hits 697system.cpu.icache.demand_hits::cpu.inst 41248897 # number of demand (read+write) hits 698system.cpu.icache.demand_hits::total 41248897 # number of demand (read+write) hits 699system.cpu.icache.overall_hits::cpu.inst 41248897 # number of overall hits 700system.cpu.icache.overall_hits::total 41248897 # number of overall hits 701system.cpu.icache.ReadReq_misses::cpu.inst 13089 # number of ReadReq misses 702system.cpu.icache.ReadReq_misses::total 13089 # number of ReadReq misses --- 58 unchanged lines hidden (view full) --- 761system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for overall accesses 762system.cpu.icache.overall_mshr_miss_rate::total 0.000218 # mshr miss rate for overall accesses 763system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37852.238640 # average ReadReq mshr miss latency 764system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37852.238640 # average ReadReq mshr miss latency 765system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37852.238640 # average overall mshr miss latency 766system.cpu.icache.demand_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency 767system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37852.238640 # average overall mshr miss latency 768system.cpu.icache.overall_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency | 705system.cpu.icache.ReadReq_hits::cpu.inst 41248897 # number of ReadReq hits 706system.cpu.icache.ReadReq_hits::total 41248897 # number of ReadReq hits 707system.cpu.icache.demand_hits::cpu.inst 41248897 # number of demand (read+write) hits 708system.cpu.icache.demand_hits::total 41248897 # number of demand (read+write) hits 709system.cpu.icache.overall_hits::cpu.inst 41248897 # number of overall hits 710system.cpu.icache.overall_hits::total 41248897 # number of overall hits 711system.cpu.icache.ReadReq_misses::cpu.inst 13089 # number of ReadReq misses 712system.cpu.icache.ReadReq_misses::total 13089 # number of ReadReq misses --- 58 unchanged lines hidden (view full) --- 771system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for overall accesses 772system.cpu.icache.overall_mshr_miss_rate::total 0.000218 # mshr miss rate for overall accesses 773system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37852.238640 # average ReadReq mshr miss latency 774system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37852.238640 # average ReadReq mshr miss latency 775system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37852.238640 # average overall mshr miss latency 776system.cpu.icache.demand_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency 777system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37852.238640 # average overall mshr miss latency 778system.cpu.icache.overall_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency |
| 779system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states |
|
| 769system.cpu.l2cache.tags.replacements 0 # number of replacements 770system.cpu.l2cache.tags.tagsinuse 2796.844278 # Cycle average of tags in use 771system.cpu.l2cache.tags.total_refs 11471 # Total number of references to valid blocks. 772system.cpu.l2cache.tags.sampled_refs 4155 # Sample count of references to valid blocks. 773system.cpu.l2cache.tags.avg_refs 2.760770 # Average number of references to valid blocks. 774system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 775system.cpu.l2cache.tags.occ_blocks::writebacks 4.971138 # Average occupied blocks per requestor 776system.cpu.l2cache.tags.occ_blocks::cpu.inst 2402.103394 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 783system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 784system.cpu.l2cache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id 785system.cpu.l2cache.tags.age_task_id_blocks_1024::2 992 # Occupied blocks per task id 786system.cpu.l2cache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id 787system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2824 # Occupied blocks per task id 788system.cpu.l2cache.tags.occ_task_id_percent::1024 0.126801 # Percentage of cache occupancy per task id 789system.cpu.l2cache.tags.tag_accesses 146881 # Number of tag accesses 790system.cpu.l2cache.tags.data_accesses 146881 # Number of data accesses | 780system.cpu.l2cache.tags.replacements 0 # number of replacements 781system.cpu.l2cache.tags.tagsinuse 2796.844278 # Cycle average of tags in use 782system.cpu.l2cache.tags.total_refs 11471 # Total number of references to valid blocks. 783system.cpu.l2cache.tags.sampled_refs 4155 # Sample count of references to valid blocks. 784system.cpu.l2cache.tags.avg_refs 2.760770 # Average number of references to valid blocks. 785system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 786system.cpu.l2cache.tags.occ_blocks::writebacks 4.971138 # Average occupied blocks per requestor 787system.cpu.l2cache.tags.occ_blocks::cpu.inst 2402.103394 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 794system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 795system.cpu.l2cache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id 796system.cpu.l2cache.tags.age_task_id_blocks_1024::2 992 # Occupied blocks per task id 797system.cpu.l2cache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id 798system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2824 # Occupied blocks per task id 799system.cpu.l2cache.tags.occ_task_id_percent::1024 0.126801 # Percentage of cache occupancy per task id 800system.cpu.l2cache.tags.tag_accesses 146881 # Number of tag accesses 801system.cpu.l2cache.tags.data_accesses 146881 # Number of data accesses |
| 802system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states |
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| 791system.cpu.l2cache.WritebackDirty_hits::writebacks 18 # number of WritebackDirty hits 792system.cpu.l2cache.WritebackDirty_hits::total 18 # number of WritebackDirty hits 793system.cpu.l2cache.WritebackClean_hits::writebacks 6469 # number of WritebackClean hits 794system.cpu.l2cache.WritebackClean_hits::total 6469 # number of WritebackClean hits 795system.cpu.l2cache.UpgradeReq_hits::cpu.data 5 # number of UpgradeReq hits 796system.cpu.l2cache.UpgradeReq_hits::total 5 # number of UpgradeReq hits 797system.cpu.l2cache.ReadExReq_hits::cpu.data 6 # number of ReadExReq hits 798system.cpu.l2cache.ReadExReq_hits::total 6 # number of ReadExReq hits --- 140 unchanged lines hidden (view full) --- 939system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67493.379107 # average overall mshr miss latency 940system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66562.411598 # average overall mshr miss latency 941system.cpu.toL2Bus.snoop_filter.tot_requests 18206 # Total number of requests made to the snoop filter. 942system.cpu.toL2Bus.snoop_filter.hit_single_requests 7138 # Number of requests hitting in the snoop filter with a single holder of the requested data. 943system.cpu.toL2Bus.snoop_filter.hit_multi_requests 549 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 944system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 945system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 946system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 803system.cpu.l2cache.WritebackDirty_hits::writebacks 18 # number of WritebackDirty hits 804system.cpu.l2cache.WritebackDirty_hits::total 18 # number of WritebackDirty hits 805system.cpu.l2cache.WritebackClean_hits::writebacks 6469 # number of WritebackClean hits 806system.cpu.l2cache.WritebackClean_hits::total 6469 # number of WritebackClean hits 807system.cpu.l2cache.UpgradeReq_hits::cpu.data 5 # number of UpgradeReq hits 808system.cpu.l2cache.UpgradeReq_hits::total 5 # number of UpgradeReq hits 809system.cpu.l2cache.ReadExReq_hits::cpu.data 6 # number of ReadExReq hits 810system.cpu.l2cache.ReadExReq_hits::total 6 # number of ReadExReq hits --- 140 unchanged lines hidden (view full) --- 951system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67493.379107 # average overall mshr miss latency 952system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66562.411598 # average overall mshr miss latency 953system.cpu.toL2Bus.snoop_filter.tot_requests 18206 # Total number of requests made to the snoop filter. 954system.cpu.toL2Bus.snoop_filter.hit_single_requests 7138 # Number of requests hitting in the snoop filter with a single holder of the requested data. 955system.cpu.toL2Bus.snoop_filter.hit_multi_requests 549 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 956system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 957system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 958system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 959system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states |
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| 947system.cpu.toL2Bus.trans_dist::ReadResp 9600 # Transaction distribution 948system.cpu.toL2Bus.trans_dist::WritebackDirty 18 # Transaction distribution 949system.cpu.toL2Bus.trans_dist::WritebackClean 6515 # Transaction distribution 950system.cpu.toL2Bus.trans_dist::CleanEvict 54 # Transaction distribution 951system.cpu.toL2Bus.trans_dist::UpgradeReq 505 # Transaction distribution 952system.cpu.toL2Bus.trans_dist::UpgradeResp 505 # Transaction distribution 953system.cpu.toL2Bus.trans_dist::ReadExReq 1513 # Transaction distribution 954system.cpu.toL2Bus.trans_dist::ReadExResp 1513 # Transaction distribution --- 18 unchanged lines hidden (view full) --- 973system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 974system.cpu.toL2Bus.snoop_fanout::total 11619 # Request fanout histogram 975system.cpu.toL2Bus.reqLayer0.occupancy 15636499 # Layer occupancy (ticks) 976system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 977system.cpu.toL2Bus.respLayer0.occupancy 13500000 # Layer occupancy (ticks) 978system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 979system.cpu.toL2Bus.respLayer1.occupancy 3422499 # Layer occupancy (ticks) 980system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 960system.cpu.toL2Bus.trans_dist::ReadResp 9600 # Transaction distribution 961system.cpu.toL2Bus.trans_dist::WritebackDirty 18 # Transaction distribution 962system.cpu.toL2Bus.trans_dist::WritebackClean 6515 # Transaction distribution 963system.cpu.toL2Bus.trans_dist::CleanEvict 54 # Transaction distribution 964system.cpu.toL2Bus.trans_dist::UpgradeReq 505 # Transaction distribution 965system.cpu.toL2Bus.trans_dist::UpgradeResp 505 # Transaction distribution 966system.cpu.toL2Bus.trans_dist::ReadExReq 1513 # Transaction distribution 967system.cpu.toL2Bus.trans_dist::ReadExResp 1513 # Transaction distribution --- 18 unchanged lines hidden (view full) --- 986system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 987system.cpu.toL2Bus.snoop_fanout::total 11619 # Request fanout histogram 988system.cpu.toL2Bus.reqLayer0.occupancy 15636499 # Layer occupancy (ticks) 989system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 990system.cpu.toL2Bus.respLayer0.occupancy 13500000 # Layer occupancy (ticks) 991system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 992system.cpu.toL2Bus.respLayer1.occupancy 3422499 # Layer occupancy (ticks) 993system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 994system.membus.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states |
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| 981system.membus.trans_dist::ReadResp 4149 # Transaction distribution 982system.membus.trans_dist::UpgradeReq 500 # Transaction distribution 983system.membus.trans_dist::ReadExReq 1507 # Transaction distribution 984system.membus.trans_dist::ReadExResp 1507 # Transaction distribution 985system.membus.trans_dist::ReadSharedReq 4149 # Transaction distribution 986system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11812 # Packet count per connected master and slave (bytes) 987system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11812 # Packet count per connected master and slave (bytes) 988system.membus.pkt_count::total 11812 # Packet count per connected master and slave (bytes) --- 20 unchanged lines hidden --- | 995system.membus.trans_dist::ReadResp 4149 # Transaction distribution 996system.membus.trans_dist::UpgradeReq 500 # Transaction distribution 997system.membus.trans_dist::ReadExReq 1507 # Transaction distribution 998system.membus.trans_dist::ReadExResp 1507 # Transaction distribution 999system.membus.trans_dist::ReadSharedReq 4149 # Transaction distribution 1000system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11812 # Packet count per connected master and slave (bytes) 1001system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11812 # Packet count per connected master and slave (bytes) 1002system.membus.pkt_count::total 11812 # Packet count per connected master and slave (bytes) --- 20 unchanged lines hidden --- |