Cross Reference: /gem5/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt

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stats.txt (11456:c0fb4435b80f)	stats.txt (11502:e273e86a873d)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.103324 # Number of seconds simulated 4sim_ticks 103324153500 # Number of ticks simulated 5final_tick 103324153500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 75581 # Simulator instruction rate (inst/s) 8host_op_rate 126680 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 59129521 # Simulator tick rate (ticks/s) 10host_mem_usage 307596 # Number of bytes of host memory used 11host_seconds 1747.42 # Real time elapsed on the host 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221363384 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 231488 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 130496 # Number of bytes read from this memory 18system.physmem.bytes_read::total 361984 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 231488 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 231488 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 3617 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 2039 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 5656 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 2240405 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 1262977 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 3503382 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 2240405 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 2240405 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 2240405 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 1262977 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 3503382 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 5656 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 5656 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 361984 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 361984 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 310 # Per bank write bursts 45system.physmem.perBankRdBursts::1 382 # Per bank write bursts 46system.physmem.perBankRdBursts::2 476 # Per bank write bursts 47system.physmem.perBankRdBursts::3 358 # Per bank write bursts 48system.physmem.perBankRdBursts::4 362 # Per bank write bursts 49system.physmem.perBankRdBursts::5 335 # Per bank write bursts 50system.physmem.perBankRdBursts::6 419 # Per bank write bursts 51system.physmem.perBankRdBursts::7 385 # Per bank write bursts 52system.physmem.perBankRdBursts::8 389 # Per bank write bursts 53system.physmem.perBankRdBursts::9 295 # Per bank write bursts 54system.physmem.perBankRdBursts::10 260 # Per bank write bursts 55system.physmem.perBankRdBursts::11 270 # Per bank write bursts 56system.physmem.perBankRdBursts::12 228 # Per bank write bursts 57system.physmem.perBankRdBursts::13 484 # Per bank write bursts 58system.physmem.perBankRdBursts::14 420 # Per bank write bursts 59system.physmem.perBankRdBursts::15 283 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 103323899000 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 5656 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 4508 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 949 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 169 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 1264 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 286.278481 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 164.439317 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 318.670037 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 554 43.83% 43.83% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 264 20.89% 64.72% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 105 8.31% 73.02% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 69 5.46% 78.48% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 45 3.56% 82.04% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 57 4.51% 86.55% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 28 2.22% 88.77% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 17 1.34% 90.11% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 125 9.89% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 1264 # Bytes accessed per row activation 203system.physmem.totQLat 43672750 # Total ticks spent queuing 204system.physmem.totMemAccLat 149722750 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 28280000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 7721.49 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 26471.49 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 3.50 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 3.50 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.03 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 4391 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 77.63 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 18268016.09 # Average gap between requests 224system.physmem.pageHitRate 77.63 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 5624640 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 3069000 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 23610600 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 6748591200 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 3147948405 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 59232949500 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 69161793345 # Total energy per rank (pJ) 233system.physmem_0.averagePower 669.369133 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 98535205500 # Time in different power states 235system.physmem_0.memoryStateTime::REF 3450200000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 237system.physmem_0.memoryStateTime::ACT 1338454000 # Time in different power states 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.physmem_1.actEnergy 3931200 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 2145000 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 20490600 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 6748591200 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 2964574845 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 59393774250 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 69133507095 # Total energy per rank (pJ) 247system.physmem_1.averagePower 669.095685 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 98803806250 # Time in different power states 249system.physmem_1.memoryStateTime::REF 3450200000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 1069805000 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.cpu.branchPred.lookups 40908032 # Number of BP lookups 254system.cpu.branchPred.condPredicted 40908032 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 6741329 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 35316490 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 0 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 3206071 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 604531 # Number of incorrect RAS predictions. 262system.cpu.branchPred.indirectLookups 35316490 # Number of indirect predictor lookups. 263system.cpu.branchPred.indirectHits 9869044 # Number of indirect target hits. 264system.cpu.branchPred.indirectMisses 25447446 # Number of indirect misses. 265system.cpu.branchPredindirectMispredicted 5035252 # Number of mispredicted indirect branches. 266system.cpu_clk_domain.clock 500 # Clock period in ticks 267system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 268system.cpu.workload.num_syscalls 400 # Number of system calls 269system.cpu.numCycles 206648308 # number of cpu cycles simulated 270system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 271system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 272system.cpu.fetch.icacheStallCycles 46351281 # Number of cycles fetch is stalled on an Icache miss 273system.cpu.fetch.Insts 420030465 # Number of instructions fetch has processed 274system.cpu.fetch.Branches 40908032 # Number of branches that fetch encountered 275system.cpu.fetch.predictedBranches 13075115 # Number of branches that fetch has predicted taken 276system.cpu.fetch.Cycles 152558958 # Number of cycles fetch has run and was not squashing or blocked 277system.cpu.fetch.SquashCycles 14935189 # Number of cycles fetch has spent squashing 278system.cpu.fetch.TlbCycles 126 # Number of cycles fetch has spent waiting for tlb 279system.cpu.fetch.MiscStallCycles 5881 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 280system.cpu.fetch.PendingTrapStallCycles 68758 # Number of stall cycles due to pending traps 281system.cpu.fetch.PendingQuiesceStallCycles 764 # Number of stall cycles due to pending quiesce instructions 282system.cpu.fetch.IcacheWaitRetryStallCycles 179 # Number of stall cycles due to full MSHR 283system.cpu.fetch.CacheLines 41261989 # Number of cache lines fetched 284system.cpu.fetch.IcacheSquashes 1525874 # Number of outstanding Icache misses that were squashed 285system.cpu.fetch.ItlbSquashes 8 # Number of outstanding ITLB misses that were squashed 286system.cpu.fetch.rateDist::samples 206453541 # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::mean 3.416062 # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::stdev 3.660543 # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::0 99211398 48.06% 48.06% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::1 5135847 2.49% 50.54% # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::2 5374620 2.60% 53.15% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::3 5328555 2.58% 55.73% # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.rateDist::4 6013612 2.91% 58.64% # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.rateDist::5 5856529 2.84% 61.48% # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::6 5733209 2.78% 64.25% # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::7 4747222 2.30% 66.55% # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.rateDist::8 69052549 33.45% 100.00% # Number of instructions fetched each cycle (Total) 299system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::total 206453541 # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.branchRate 0.197960 # Number of branch fetches per cycle 304system.cpu.fetch.rate 2.032586 # Number of inst fetches per cycle 305system.cpu.decode.IdleCycles 32305475 # Number of cycles decode is idle 306system.cpu.decode.BlockedCycles 86547165 # Number of cycles decode is blocked 307system.cpu.decode.RunCycles 62440790 # Number of cycles decode is running 308system.cpu.decode.UnblockCycles 17692517 # Number of cycles decode is unblocking 309system.cpu.decode.SquashCycles 7467594 # Number of cycles decode is squashing 310system.cpu.decode.DecodedInsts 591140753 # Number of instructions handled by decode 311system.cpu.rename.SquashCycles 7467594 # Number of cycles rename is squashing 312system.cpu.rename.IdleCycles 42099614 # Number of cycles rename is idle 313system.cpu.rename.BlockCycles 46622929 # Number of cycles rename is blocking 314system.cpu.rename.serializeStallCycles 29580 # count of cycles rename stalled for serializing inst 315system.cpu.rename.RunCycles 68917298 # Number of cycles rename is running 316system.cpu.rename.UnblockCycles 41316526 # Number of cycles rename is unblocking 317system.cpu.rename.RenamedInsts 552365156 # Number of instructions processed by rename 318system.cpu.rename.ROBFullEvents 1615 # Number of times rename has blocked due to ROB full 319system.cpu.rename.IQFullEvents 36415427 # Number of times rename has blocked due to IQ full 320system.cpu.rename.LQFullEvents 4818042 # Number of times rename has blocked due to LQ full 321system.cpu.rename.SQFullEvents 146051 # Number of times rename has blocked due to SQ full 322system.cpu.rename.RenamedOperands 629691896 # Number of destination operands rename has renamed 323system.cpu.rename.RenameLookups 1486514399 # Number of register rename lookups that rename has made 324system.cpu.rename.int_rename_lookups 974943820 # Number of integer rename lookups 325system.cpu.rename.fp_rename_lookups 15152274 # Number of floating rename lookups 326system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed 327system.cpu.rename.UndoneMaps 370262446 # Number of HB maps that are undone due to squashing 328system.cpu.rename.serializingInsts 2381 # count of serializing insts renamed 329system.cpu.rename.tempSerializingInsts 2386 # count of temporary serializing insts renamed 330system.cpu.rename.skidInsts 89347483 # count of insts added to the skid buffer 331system.cpu.memDep0.insertedLoads 128815998 # Number of loads inserted to the mem dependence unit. 332system.cpu.memDep0.insertedStores 45923960 # Number of stores inserted to the mem dependence unit. 333system.cpu.memDep0.conflictingLoads 77358410 # Number of conflicting loads. 334system.cpu.memDep0.conflictingStores 25275137 # Number of conflicting stores. 335system.cpu.iq.iqInstsAdded 490566423 # Number of instructions added to the IQ (excludes non-spec) 336system.cpu.iq.iqNonSpecInstsAdded 62065 # Number of non-speculative instructions added to the IQ 337system.cpu.iq.iqInstsIssued 338414549 # Number of instructions issued 338system.cpu.iq.iqSquashedInstsIssued 1099553 # Number of squashed instructions issued 339system.cpu.iq.iqSquashedInstsExamined 269265104 # Number of squashed instructions iterated over during squash; mainly for profiling 340system.cpu.iq.iqSquashedOperandsExamined 527048763 # Number of squashed operands that are examined and possibly removed from graph 341system.cpu.iq.iqSquashedNonSpecRemoved 60820 # Number of squashed non-spec instructions that were removed 342system.cpu.iq.issued_per_cycle::samples 206453541 # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::mean 1.639180 # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::stdev 1.804126 # Number of insts issued each cycle 345system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::0 73345677 35.53% 35.53% # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::1 46646037 22.59% 58.12% # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::2 32854801 15.91% 74.03% # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::3 20905072 10.13% 84.16% # Number of insts issued each cycle 350system.cpu.iq.issued_per_cycle::4 15063521 7.30% 91.46% # Number of insts issued each cycle 351system.cpu.iq.issued_per_cycle::5 8409386 4.07% 95.53% # Number of insts issued each cycle 352system.cpu.iq.issued_per_cycle::6 5213188 2.53% 98.05% # Number of insts issued each cycle 353system.cpu.iq.issued_per_cycle::7 2363320 1.14% 99.20% # Number of insts issued each cycle 354system.cpu.iq.issued_per_cycle::8 1652539 0.80% 100.00% # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 358system.cpu.iq.issued_per_cycle::total 206453541 # Number of insts issued each cycle 359system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 360system.cpu.iq.fu_full::IntAlu 758238 19.31% 19.31% # attempts to use FU when none available 361system.cpu.iq.fu_full::IntMult 0 0.00% 19.31% # attempts to use FU when none available 362system.cpu.iq.fu_full::IntDiv 0 0.00% 19.31% # attempts to use FU when none available 363system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.31% # attempts to use FU when none available 364system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.31% # attempts to use FU when none available 365system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.31% # attempts to use FU when none available 366system.cpu.iq.fu_full::FloatMult 0 0.00% 19.31% # attempts to use FU when none available 367system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.31% # attempts to use FU when none available 368system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.31% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.31% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.31% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.31% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.31% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.31% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.31% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdMult 0 0.00% 19.31% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.31% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdShift 0 0.00% 19.31% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.31% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.31% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.31% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.31% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.31% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.31% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.31% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.31% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.31% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.31% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.31% # attempts to use FU when none available 389system.cpu.iq.fu_full::MemRead 2733075 69.60% 88.91% # attempts to use FU when none available 390system.cpu.iq.fu_full::MemWrite 435620 11.09% 100.00% # attempts to use FU when none available 391system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 392system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 393system.cpu.iq.FU_type_0::No_OpClass 1211810 0.36% 0.36% # Type of FU issued 394system.cpu.iq.FU_type_0::IntAlu 216608884 64.01% 64.37% # Type of FU issued 395system.cpu.iq.FU_type_0::IntMult 799973 0.24% 64.60% # Type of FU issued 396system.cpu.iq.FU_type_0::IntDiv 7048329 2.08% 66.68% # Type of FU issued 397system.cpu.iq.FU_type_0::FloatAdd 1813849 0.54% 67.22% # Type of FU issued 398system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.22% # Type of FU issued 399system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.22% # Type of FU issued 400system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.22% # Type of FU issued 401system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.22% # Type of FU issued 402system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.22% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.22% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.22% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.22% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.22% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.22% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.22% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.22% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.22% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.22% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.22% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.22% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.22% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.22% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.22% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.22% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.22% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.22% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.22% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.22% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.22% # Type of FU issued 423system.cpu.iq.FU_type_0::MemRead 84312637 24.91% 92.13% # Type of FU issued 424system.cpu.iq.FU_type_0::MemWrite 26619067 7.87% 100.00% # Type of FU issued 425system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 426system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 427system.cpu.iq.FU_type_0::total 338414549 # Type of FU issued 428system.cpu.iq.rate 1.637635 # Inst issue rate 429system.cpu.iq.fu_busy_cnt 3926933 # FU busy when requested 430system.cpu.iq.fu_busy_rate 0.011604 # FU busy rate (busy events/executed inst) 431system.cpu.iq.int_inst_queue_reads 880106724 # Number of integer instruction queue reads 432system.cpu.iq.int_inst_queue_writes 745207821 # Number of integer instruction queue writes 433system.cpu.iq.int_inst_queue_wakeup_accesses 316030450 # Number of integer instruction queue wakeup accesses 434system.cpu.iq.fp_inst_queue_reads 8202401 # Number of floating instruction queue reads 435system.cpu.iq.fp_inst_queue_writes 15512263 # Number of floating instruction queue writes 436system.cpu.iq.fp_inst_queue_wakeup_accesses 3567674 # Number of floating instruction queue wakeup accesses 437system.cpu.iq.int_alu_accesses 337013730 # Number of integer alu accesses 438system.cpu.iq.fp_alu_accesses 4115942 # Number of floating point alu accesses 439system.cpu.iew.lsq.thread0.forwLoads 18154732 # Number of loads that had data forwarded from stores 440system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 441system.cpu.iew.lsq.thread0.squashedLoads 72166411 # Number of loads squashed 442system.cpu.iew.lsq.thread0.ignoredResponses 54986 # Number of memory responses ignored because the instruction is squashed 443system.cpu.iew.lsq.thread0.memOrderViolation 863760 # Number of memory ordering violations 444system.cpu.iew.lsq.thread0.squashedStores 25408243 # Number of stores squashed 445system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 446system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 447system.cpu.iew.lsq.thread0.rescheduledLoads 50543 # Number of loads that were rescheduled 448system.cpu.iew.lsq.thread0.cacheBlocked 53 # Number of times an access to memory failed due to the cache being blocked 449system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 450system.cpu.iew.iewSquashCycles 7467594 # Number of cycles IEW is squashing 451system.cpu.iew.iewBlockCycles 35770303 # Number of cycles IEW is blocking 452system.cpu.iew.iewUnblockCycles 592137 # Number of cycles IEW is unblocking 453system.cpu.iew.iewDispatchedInsts 490628488 # Number of instructions dispatched to IQ 454system.cpu.iew.iewDispSquashedInsts 1259959 # Number of squashed instructions skipped by dispatch 455system.cpu.iew.iewDispLoadInsts 128815998 # Number of dispatched load instructions 456system.cpu.iew.iewDispStoreInsts 45923960 # Number of dispatched store instructions 457system.cpu.iew.iewDispNonSpecInsts 22654 # Number of dispatched non-speculative instructions 458system.cpu.iew.iewIQFullEvents 545800 # Number of times the IQ has become full, causing a stall 459system.cpu.iew.iewLSQFullEvents 38626 # Number of times the LSQ has become full, causing a stall 460system.cpu.iew.memOrderViolationEvents 863760 # Number of memory order violations 461system.cpu.iew.predictedTakenIncorrect 1294864 # Number of branches that were predicted taken incorrectly 462system.cpu.iew.predictedNotTakenIncorrect 6880130 # Number of branches that were predicted not taken incorrectly 463system.cpu.iew.branchMispredicts 8174994 # Number of branch mispredicts detected at execute 464system.cpu.iew.iewExecutedInsts 326485130 # Number of executed instructions 465system.cpu.iew.iewExecLoadInsts 80685795 # Number of load instructions executed 466system.cpu.iew.iewExecSquashedInsts 11929419 # Number of squashed instructions skipped in execute 467system.cpu.iew.exec_swp 0 # number of swp insts executed 468system.cpu.iew.exec_nop 0 # number of nop insts executed 469system.cpu.iew.exec_refs 106318426 # number of memory reference insts executed 470system.cpu.iew.exec_branches 18939296 # Number of branches executed 471system.cpu.iew.exec_stores 25632631 # Number of stores executed 472system.cpu.iew.exec_rate 1.579907 # Inst execution rate 473system.cpu.iew.wb_sent 322610085 # cumulative count of insts sent to commit 474system.cpu.iew.wb_count 319598124 # cumulative count of insts written-back 475system.cpu.iew.wb_producers 256503247 # num instructions producing a value 476system.cpu.iew.wb_consumers 435667509 # num instructions consuming a value 477system.cpu.iew.wb_rate 1.546580 # insts written-back per cycle 478system.cpu.iew.wb_fanout 0.588759 # average fanout of values written-back 479system.cpu.commit.commitSquashedInsts 269290512 # The number of squashed insts skipped by commit 480system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards 481system.cpu.commit.branchMispredicts 6746174 # The number of times a branch was mispredicted 482system.cpu.commit.committed_per_cycle::samples 163890954 # Number of insts commited each cycle 483system.cpu.commit.committed_per_cycle::mean 1.350675 # Number of insts commited each cycle 484system.cpu.commit.committed_per_cycle::stdev 1.933271 # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::0 67206524 41.01% 41.01% # Number of insts commited each cycle 487system.cpu.commit.committed_per_cycle::1 54940140 33.52% 74.53% # Number of insts commited each cycle 488system.cpu.commit.committed_per_cycle::2 13261155 8.09% 82.62% # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::3 10687834 6.52% 89.14% # Number of insts commited each cycle 490system.cpu.commit.committed_per_cycle::4 5446779 3.32% 92.47% # Number of insts commited each cycle 491system.cpu.commit.committed_per_cycle::5 3132108 1.91% 94.38% # Number of insts commited each cycle 492system.cpu.commit.committed_per_cycle::6 1092307 0.67% 95.04% # Number of insts commited each cycle 493system.cpu.commit.committed_per_cycle::7 1156922 0.71% 95.75% # Number of insts commited each cycle 494system.cpu.commit.committed_per_cycle::8 6967185 4.25% 100.00% # Number of insts commited each cycle 495system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 496system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::total 163890954 # Number of insts commited each cycle 499system.cpu.commit.committedInsts 132071192 # Number of instructions committed 500system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed 501system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 502system.cpu.commit.refs 77165304 # Number of memory references committed 503system.cpu.commit.loads 56649587 # Number of loads committed 504system.cpu.commit.membars 0 # Number of memory barriers committed 505system.cpu.commit.branches 12326938 # Number of branches committed 506system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. 507system.cpu.commit.int_insts 219019985 # Number of committed integer instructions. 508system.cpu.commit.function_calls 797818 # Number of function calls committed. 509system.cpu.commit.op_class_0::No_OpClass 1176721 0.53% 0.53% # Class of committed instruction 510system.cpu.commit.op_class_0::IntAlu 134111832 60.58% 61.12% # Class of committed instruction 511system.cpu.commit.op_class_0::IntMult 772953 0.35% 61.47% # Class of committed instruction 512system.cpu.commit.op_class_0::IntDiv 7031501 3.18% 64.64% # Class of committed instruction 513system.cpu.commit.op_class_0::FloatAdd 1105073 0.50% 65.14% # Class of committed instruction 514system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.14% # Class of committed instruction 515system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.14% # Class of committed instruction 516system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.14% # Class of committed instruction 517system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.14% # Class of committed instruction 518system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.14% # Class of committed instruction 519system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.14% # Class of committed instruction 520system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.14% # Class of committed instruction 521system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.14% # Class of committed instruction 522system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.14% # Class of committed instruction 523system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.14% # Class of committed instruction 524system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.14% # Class of committed instruction 525system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.14% # Class of committed instruction 526system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.14% # Class of committed instruction 527system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.14% # Class of committed instruction 528system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.14% # Class of committed instruction 529system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.14% # Class of committed instruction 530system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.14% # Class of committed instruction 531system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.14% # Class of committed instruction 532system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.14% # Class of committed instruction 533system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.14% # Class of committed instruction 534system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.14% # Class of committed instruction 535system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.14% # Class of committed instruction 536system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction 537system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction 538system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction 539system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction 540system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction 541system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 542system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 543system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction 544system.cpu.commit.bw_lim_events 6967185 # number cycles where commit BW limit reached 545system.cpu.rob.rob_reads 647577665 # The number of ROB reads 546system.cpu.rob.rob_writes 1024269930 # The number of ROB writes 547system.cpu.timesIdled 2819 # Number of times that the entire CPU went into an idle state and unscheduled itself 548system.cpu.idleCycles 194767 # Total number of cycles that the CPU has spent unscheduled due to idling 549system.cpu.committedInsts 132071192 # Number of Instructions Simulated 550system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated 551system.cpu.cpi 1.564674 # CPI: Cycles Per Instruction 552system.cpu.cpi_total 1.564674 # CPI: Total CPI of All Threads 553system.cpu.ipc 0.639111 # IPC: Instructions Per Cycle 554system.cpu.ipc_total 0.639111 # IPC: Total IPC of All Threads 555system.cpu.int_regfile_reads 524516370 # number of integer regfile reads 556system.cpu.int_regfile_writes 289029189 # number of integer regfile writes 557system.cpu.fp_regfile_reads 4536413 # number of floating regfile reads 558system.cpu.fp_regfile_writes 3331836 # number of floating regfile writes 559system.cpu.cc_regfile_reads 107017358 # number of cc regfile reads 560system.cpu.cc_regfile_writes 65774990 # number of cc regfile writes 561system.cpu.misc_regfile_reads 176892429 # number of misc regfile reads 562system.cpu.misc_regfile_writes 1689 # number of misc regfile writes 563system.cpu.dcache.tags.replacements 72 # number of replacements 564system.cpu.dcache.tags.tagsinuse 1525.498489 # Cycle average of tags in use 565system.cpu.dcache.tags.total_refs 82766316 # Total number of references to valid blocks. 566system.cpu.dcache.tags.sampled_refs 2113 # Sample count of references to valid blocks. 567system.cpu.dcache.tags.avg_refs 39170.050166 # Average number of references to valid blocks. 568system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 569system.cpu.dcache.tags.occ_blocks::cpu.data 1525.498489 # Average occupied blocks per requestor 570system.cpu.dcache.tags.occ_percent::cpu.data 0.372436 # Average percentage of cache occupancy 571system.cpu.dcache.tags.occ_percent::total 0.372436 # Average percentage of cache occupancy 572system.cpu.dcache.tags.occ_task_id_blocks::1024 2041 # Occupied blocks per task id 573system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id 574system.cpu.dcache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id 575system.cpu.dcache.tags.age_task_id_blocks_1024::2 101 # Occupied blocks per task id 576system.cpu.dcache.tags.age_task_id_blocks_1024::3 409 # Occupied blocks per task id 577system.cpu.dcache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id 578system.cpu.dcache.tags.occ_task_id_percent::1024 0.498291 # Percentage of cache occupancy per task id 579system.cpu.dcache.tags.tag_accesses 165539971 # Number of tag accesses 580system.cpu.dcache.tags.data_accesses 165539971 # Number of data accesses 581system.cpu.dcache.ReadReq_hits::cpu.data 62251936 # number of ReadReq hits 582system.cpu.dcache.ReadReq_hits::total 62251936 # number of ReadReq hits 583system.cpu.dcache.WriteReq_hits::cpu.data 20513707 # number of WriteReq hits 584system.cpu.dcache.WriteReq_hits::total 20513707 # number of WriteReq hits 585system.cpu.dcache.demand_hits::cpu.data 82765643 # number of demand (read+write) hits 586system.cpu.dcache.demand_hits::total 82765643 # number of demand (read+write) hits 587system.cpu.dcache.overall_hits::cpu.data 82765643 # number of overall hits 588system.cpu.dcache.overall_hits::total 82765643 # number of overall hits 589system.cpu.dcache.ReadReq_misses::cpu.data 1262 # number of ReadReq misses 590system.cpu.dcache.ReadReq_misses::total 1262 # number of ReadReq misses 591system.cpu.dcache.WriteReq_misses::cpu.data 2024 # number of WriteReq misses 592system.cpu.dcache.WriteReq_misses::total 2024 # number of WriteReq misses 593system.cpu.dcache.demand_misses::cpu.data 3286 # number of demand (read+write) misses 594system.cpu.dcache.demand_misses::total 3286 # number of demand (read+write) misses 595system.cpu.dcache.overall_misses::cpu.data 3286 # number of overall misses 596system.cpu.dcache.overall_misses::total 3286 # number of overall misses 597system.cpu.dcache.ReadReq_miss_latency::cpu.data 84231000 # number of ReadReq miss cycles 598system.cpu.dcache.ReadReq_miss_latency::total 84231000 # number of ReadReq miss cycles 599system.cpu.dcache.WriteReq_miss_latency::cpu.data 131983500 # number of WriteReq miss cycles 600system.cpu.dcache.WriteReq_miss_latency::total 131983500 # number of WriteReq miss cycles 601system.cpu.dcache.demand_miss_latency::cpu.data 216214500 # number of demand (read+write) miss cycles 602system.cpu.dcache.demand_miss_latency::total 216214500 # number of demand (read+write) miss cycles 603system.cpu.dcache.overall_miss_latency::cpu.data 216214500 # number of overall miss cycles 604system.cpu.dcache.overall_miss_latency::total 216214500 # number of overall miss cycles 605system.cpu.dcache.ReadReq_accesses::cpu.data 62253198 # number of ReadReq accesses(hits+misses) 606system.cpu.dcache.ReadReq_accesses::total 62253198 # number of ReadReq accesses(hits+misses) 607system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) 608system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) 609system.cpu.dcache.demand_accesses::cpu.data 82768929 # number of demand (read+write) accesses 610system.cpu.dcache.demand_accesses::total 82768929 # number of demand (read+write) accesses 611system.cpu.dcache.overall_accesses::cpu.data 82768929 # number of overall (read+write) accesses 612system.cpu.dcache.overall_accesses::total 82768929 # number of overall (read+write) accesses 613system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses 614system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses 615system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000099 # miss rate for WriteReq accesses 616system.cpu.dcache.WriteReq_miss_rate::total 0.000099 # miss rate for WriteReq accesses 617system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses 618system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses 619system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses 620system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses 621system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66744.057052 # average ReadReq miss latency 622system.cpu.dcache.ReadReq_avg_miss_latency::total 66744.057052 # average ReadReq miss latency 623system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65209.239130 # average WriteReq miss latency 624system.cpu.dcache.WriteReq_avg_miss_latency::total 65209.239130 # average WriteReq miss latency 625system.cpu.dcache.demand_avg_miss_latency::cpu.data 65798.691418 # average overall miss latency 626system.cpu.dcache.demand_avg_miss_latency::total 65798.691418 # average overall miss latency 627system.cpu.dcache.overall_avg_miss_latency::cpu.data 65798.691418 # average overall miss latency 628system.cpu.dcache.overall_avg_miss_latency::total 65798.691418 # average overall miss latency 629system.cpu.dcache.blocked_cycles::no_mshrs 369 # number of cycles access was blocked 630system.cpu.dcache.blocked_cycles::no_targets 73 # number of cycles access was blocked 631system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked 632system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked 633system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.125000 # average number of cycles each access was blocked 634system.cpu.dcache.avg_blocked_cycles::no_targets 36.500000 # average number of cycles each access was blocked 635system.cpu.dcache.writebacks::writebacks 18 # number of writebacks 636system.cpu.dcache.writebacks::total 18 # number of writebacks 637system.cpu.dcache.ReadReq_mshr_hits::cpu.data 661 # number of ReadReq MSHR hits 638system.cpu.dcache.ReadReq_mshr_hits::total 661 # number of ReadReq MSHR hits 639system.cpu.dcache.WriteReq_mshr_hits::cpu.data 7 # number of WriteReq MSHR hits 640system.cpu.dcache.WriteReq_mshr_hits::total 7 # number of WriteReq MSHR hits 641system.cpu.dcache.demand_mshr_hits::cpu.data 668 # number of demand (read+write) MSHR hits 642system.cpu.dcache.demand_mshr_hits::total 668 # number of demand (read+write) MSHR hits 643system.cpu.dcache.overall_mshr_hits::cpu.data 668 # number of overall MSHR hits 644system.cpu.dcache.overall_mshr_hits::total 668 # number of overall MSHR hits 645system.cpu.dcache.ReadReq_mshr_misses::cpu.data 601 # number of ReadReq MSHR misses 646system.cpu.dcache.ReadReq_mshr_misses::total 601 # number of ReadReq MSHR misses 647system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2017 # number of WriteReq MSHR misses 648system.cpu.dcache.WriteReq_mshr_misses::total 2017 # number of WriteReq MSHR misses 649system.cpu.dcache.demand_mshr_misses::cpu.data 2618 # number of demand (read+write) MSHR misses 650system.cpu.dcache.demand_mshr_misses::total 2618 # number of demand (read+write) MSHR misses 651system.cpu.dcache.overall_mshr_misses::cpu.data 2618 # number of overall MSHR misses 652system.cpu.dcache.overall_mshr_misses::total 2618 # number of overall MSHR misses 653system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47710000 # number of ReadReq MSHR miss cycles 654system.cpu.dcache.ReadReq_mshr_miss_latency::total 47710000 # number of ReadReq MSHR miss cycles 655system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 129636500 # number of WriteReq MSHR miss cycles 656system.cpu.dcache.WriteReq_mshr_miss_latency::total 129636500 # number of WriteReq MSHR miss cycles 657system.cpu.dcache.demand_mshr_miss_latency::cpu.data 177346500 # number of demand (read+write) MSHR miss cycles 658system.cpu.dcache.demand_mshr_miss_latency::total 177346500 # number of demand (read+write) MSHR miss cycles 659system.cpu.dcache.overall_mshr_miss_latency::cpu.data 177346500 # number of overall MSHR miss cycles 660system.cpu.dcache.overall_mshr_miss_latency::total 177346500 # number of overall MSHR miss cycles 661system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses 662system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses 663system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000098 # mshr miss rate for WriteReq accesses 664system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000098 # mshr miss rate for WriteReq accesses 665system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses 666system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses 667system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses 668system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses 669system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79384.359401 # average ReadReq mshr miss latency 670system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79384.359401 # average ReadReq mshr miss latency 671system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64271.938523 # average WriteReq mshr miss latency 672system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64271.938523 # average WriteReq mshr miss latency 673system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67741.214668 # average overall mshr miss latency 674system.cpu.dcache.demand_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency 675system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67741.214668 # average overall mshr miss latency 676system.cpu.dcache.overall_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency 677system.cpu.icache.tags.replacements 6515 # number of replacements 678system.cpu.icache.tags.tagsinuse 1663.291735 # Cycle average of tags in use 679system.cpu.icache.tags.total_refs 41248897 # Total number of references to valid blocks. 680system.cpu.icache.tags.sampled_refs 8499 # Sample count of references to valid blocks. 681system.cpu.icache.tags.avg_refs 4853.382398 # Average number of references to valid blocks. 682system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 683system.cpu.icache.tags.occ_blocks::cpu.inst 1663.291735 # Average occupied blocks per requestor 684system.cpu.icache.tags.occ_percent::cpu.inst 0.812154 # Average percentage of cache occupancy 685system.cpu.icache.tags.occ_percent::total 0.812154 # Average percentage of cache occupancy 686system.cpu.icache.tags.occ_task_id_blocks::1024 1984 # Occupied blocks per task id 687system.cpu.icache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id 688system.cpu.icache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id 689system.cpu.icache.tags.age_task_id_blocks_1024::2 845 # Occupied blocks per task id 690system.cpu.icache.tags.age_task_id_blocks_1024::3 155 # Occupied blocks per task id 691system.cpu.icache.tags.age_task_id_blocks_1024::4 736 # Occupied blocks per task id 692system.cpu.icache.tags.occ_task_id_percent::1024 0.968750 # Percentage of cache occupancy per task id 693system.cpu.icache.tags.tag_accesses 82532972 # Number of tag accesses 694system.cpu.icache.tags.data_accesses 82532972 # Number of data accesses 695system.cpu.icache.ReadReq_hits::cpu.inst 41248897 # number of ReadReq hits 696system.cpu.icache.ReadReq_hits::total 41248897 # number of ReadReq hits 697system.cpu.icache.demand_hits::cpu.inst 41248897 # number of demand (read+write) hits 698system.cpu.icache.demand_hits::total 41248897 # number of demand (read+write) hits 699system.cpu.icache.overall_hits::cpu.inst 41248897 # number of overall hits 700system.cpu.icache.overall_hits::total 41248897 # number of overall hits 701system.cpu.icache.ReadReq_misses::cpu.inst 13089 # number of ReadReq misses 702system.cpu.icache.ReadReq_misses::total 13089 # number of ReadReq misses 703system.cpu.icache.demand_misses::cpu.inst 13089 # number of demand (read+write) misses 704system.cpu.icache.demand_misses::total 13089 # number of demand (read+write) misses 705system.cpu.icache.overall_misses::cpu.inst 13089 # number of overall misses 706system.cpu.icache.overall_misses::total 13089 # number of overall misses 707system.cpu.icache.ReadReq_miss_latency::cpu.inst 485791000 # number of ReadReq miss cycles 708system.cpu.icache.ReadReq_miss_latency::total 485791000 # number of ReadReq miss cycles 709system.cpu.icache.demand_miss_latency::cpu.inst 485791000 # number of demand (read+write) miss cycles 710system.cpu.icache.demand_miss_latency::total 485791000 # number of demand (read+write) miss cycles 711system.cpu.icache.overall_miss_latency::cpu.inst 485791000 # number of overall miss cycles 712system.cpu.icache.overall_miss_latency::total 485791000 # number of overall miss cycles 713system.cpu.icache.ReadReq_accesses::cpu.inst 41261986 # number of ReadReq accesses(hits+misses) 714system.cpu.icache.ReadReq_accesses::total 41261986 # number of ReadReq accesses(hits+misses) 715system.cpu.icache.demand_accesses::cpu.inst 41261986 # number of demand (read+write) accesses 716system.cpu.icache.demand_accesses::total 41261986 # number of demand (read+write) accesses 717system.cpu.icache.overall_accesses::cpu.inst 41261986 # number of overall (read+write) accesses 718system.cpu.icache.overall_accesses::total 41261986 # number of overall (read+write) accesses 719system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000317 # miss rate for ReadReq accesses 720system.cpu.icache.ReadReq_miss_rate::total 0.000317 # miss rate for ReadReq accesses 721system.cpu.icache.demand_miss_rate::cpu.inst 0.000317 # miss rate for demand accesses 722system.cpu.icache.demand_miss_rate::total 0.000317 # miss rate for demand accesses 723system.cpu.icache.overall_miss_rate::cpu.inst 0.000317 # miss rate for overall accesses 724system.cpu.icache.overall_miss_rate::total 0.000317 # miss rate for overall accesses 725system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37114.447246 # average ReadReq miss latency 726system.cpu.icache.ReadReq_avg_miss_latency::total 37114.447246 # average ReadReq miss latency 727system.cpu.icache.demand_avg_miss_latency::cpu.inst 37114.447246 # average overall miss latency 728system.cpu.icache.demand_avg_miss_latency::total 37114.447246 # average overall miss latency 729system.cpu.icache.overall_avg_miss_latency::cpu.inst 37114.447246 # average overall miss latency 730system.cpu.icache.overall_avg_miss_latency::total 37114.447246 # average overall miss latency 731system.cpu.icache.blocked_cycles::no_mshrs 2090 # number of cycles access was blocked 732system.cpu.icache.blocked_cycles::no_targets 305 # number of cycles access was blocked 733system.cpu.icache.blocked::no_mshrs 30 # number of cycles access was blocked 734system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 735system.cpu.icache.avg_blocked_cycles::no_mshrs 69.666667 # average number of cycles each access was blocked 736system.cpu.icache.avg_blocked_cycles::no_targets 305 # average number of cycles each access was blocked 737system.cpu.icache.writebacks::writebacks 6515 # number of writebacks 738system.cpu.icache.writebacks::total 6515 # number of writebacks 739system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4088 # number of ReadReq MSHR hits 740system.cpu.icache.ReadReq_mshr_hits::total 4088 # number of ReadReq MSHR hits 741system.cpu.icache.demand_mshr_hits::cpu.inst 4088 # number of demand (read+write) MSHR hits 742system.cpu.icache.demand_mshr_hits::total 4088 # number of demand (read+write) MSHR hits 743system.cpu.icache.overall_mshr_hits::cpu.inst 4088 # number of overall MSHR hits 744system.cpu.icache.overall_mshr_hits::total 4088 # number of overall MSHR hits 745system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9001 # number of ReadReq MSHR misses 746system.cpu.icache.ReadReq_mshr_misses::total 9001 # number of ReadReq MSHR misses 747system.cpu.icache.demand_mshr_misses::cpu.inst 9001 # number of demand (read+write) MSHR misses 748system.cpu.icache.demand_mshr_misses::total 9001 # number of demand (read+write) MSHR misses 749system.cpu.icache.overall_mshr_misses::cpu.inst 9001 # number of overall MSHR misses 750system.cpu.icache.overall_mshr_misses::total 9001 # number of overall MSHR misses 751system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 340708000 # number of ReadReq MSHR miss cycles 752system.cpu.icache.ReadReq_mshr_miss_latency::total 340708000 # number of ReadReq MSHR miss cycles 753system.cpu.icache.demand_mshr_miss_latency::cpu.inst 340708000 # number of demand (read+write) MSHR miss cycles 754system.cpu.icache.demand_mshr_miss_latency::total 340708000 # number of demand (read+write) MSHR miss cycles 755system.cpu.icache.overall_mshr_miss_latency::cpu.inst 340708000 # number of overall MSHR miss cycles 756system.cpu.icache.overall_mshr_miss_latency::total 340708000 # number of overall MSHR miss cycles 757system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for ReadReq accesses 758system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000218 # mshr miss rate for ReadReq accesses 759system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for demand accesses 760system.cpu.icache.demand_mshr_miss_rate::total 0.000218 # mshr miss rate for demand accesses 761system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for overall accesses 762system.cpu.icache.overall_mshr_miss_rate::total 0.000218 # mshr miss rate for overall accesses 763system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37852.238640 # average ReadReq mshr miss latency 764system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37852.238640 # average ReadReq mshr miss latency 765system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37852.238640 # average overall mshr miss latency 766system.cpu.icache.demand_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency 767system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37852.238640 # average overall mshr miss latency 768system.cpu.icache.overall_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency 769system.cpu.l2cache.tags.replacements 0 # number of replacements 770system.cpu.l2cache.tags.tagsinuse 2796.844278 # Cycle average of tags in use 771system.cpu.l2cache.tags.total_refs 11471 # Total number of references to valid blocks. 772system.cpu.l2cache.tags.sampled_refs 4155 # Sample count of references to valid blocks. 773system.cpu.l2cache.tags.avg_refs 2.760770 # Average number of references to valid blocks. 774system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 775system.cpu.l2cache.tags.occ_blocks::writebacks 4.971138 # Average occupied blocks per requestor 776system.cpu.l2cache.tags.occ_blocks::cpu.inst 2402.103394 # Average occupied blocks per requestor 777system.cpu.l2cache.tags.occ_blocks::cpu.data 389.769746 # Average occupied blocks per requestor 778system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy 779system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073306 # Average percentage of cache occupancy 780system.cpu.l2cache.tags.occ_percent::cpu.data 0.011895 # Average percentage of cache occupancy 781system.cpu.l2cache.tags.occ_percent::total 0.085353 # Average percentage of cache occupancy 782system.cpu.l2cache.tags.occ_task_id_blocks::1024 4155 # Occupied blocks per task id 783system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 784system.cpu.l2cache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id 785system.cpu.l2cache.tags.age_task_id_blocks_1024::2 992 # Occupied blocks per task id 786system.cpu.l2cache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id 787system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2824 # Occupied blocks per task id 788system.cpu.l2cache.tags.occ_task_id_percent::1024 0.126801 # Percentage of cache occupancy per task id 789system.cpu.l2cache.tags.tag_accesses 146881 # Number of tag accesses 790system.cpu.l2cache.tags.data_accesses 146881 # Number of data accesses 791system.cpu.l2cache.WritebackDirty_hits::writebacks 18 # number of WritebackDirty hits 792system.cpu.l2cache.WritebackDirty_hits::total 18 # number of WritebackDirty hits 793system.cpu.l2cache.WritebackClean_hits::writebacks 6469 # number of WritebackClean hits 794system.cpu.l2cache.WritebackClean_hits::total 6469 # number of WritebackClean hits 795system.cpu.l2cache.UpgradeReq_hits::cpu.data 5 # number of UpgradeReq hits 796system.cpu.l2cache.UpgradeReq_hits::total 5 # number of UpgradeReq hits 797system.cpu.l2cache.ReadExReq_hits::cpu.data 6 # number of ReadExReq hits 798system.cpu.l2cache.ReadExReq_hits::total 6 # number of ReadExReq hits 799system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4877 # number of ReadCleanReq hits 800system.cpu.l2cache.ReadCleanReq_hits::total 4877 # number of ReadCleanReq hits 801system.cpu.l2cache.ReadSharedReq_hits::cpu.data 68 # number of ReadSharedReq hits 802system.cpu.l2cache.ReadSharedReq_hits::total 68 # number of ReadSharedReq hits 803system.cpu.l2cache.demand_hits::cpu.inst 4877 # number of demand (read+write) hits 804system.cpu.l2cache.demand_hits::cpu.data 74 # number of demand (read+write) hits 805system.cpu.l2cache.demand_hits::total 4951 # number of demand (read+write) hits 806system.cpu.l2cache.overall_hits::cpu.inst 4877 # number of overall hits 807system.cpu.l2cache.overall_hits::cpu.data 74 # number of overall hits 808system.cpu.l2cache.overall_hits::total 4951 # number of overall hits 809system.cpu.l2cache.UpgradeReq_misses::cpu.data 500 # number of UpgradeReq misses 810system.cpu.l2cache.UpgradeReq_misses::total 500 # number of UpgradeReq misses 811system.cpu.l2cache.ReadExReq_misses::cpu.data 1507 # number of ReadExReq misses 812system.cpu.l2cache.ReadExReq_misses::total 1507 # number of ReadExReq misses 813system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3617 # number of ReadCleanReq misses 814system.cpu.l2cache.ReadCleanReq_misses::total 3617 # number of ReadCleanReq misses 815system.cpu.l2cache.ReadSharedReq_misses::cpu.data 532 # number of ReadSharedReq misses 816system.cpu.l2cache.ReadSharedReq_misses::total 532 # number of ReadSharedReq misses 817system.cpu.l2cache.demand_misses::cpu.inst 3617 # number of demand (read+write) misses 818system.cpu.l2cache.demand_misses::cpu.data 2039 # number of demand (read+write) misses 819system.cpu.l2cache.demand_misses::total 5656 # number of demand (read+write) misses 820system.cpu.l2cache.overall_misses::cpu.inst 3617 # number of overall misses 821system.cpu.l2cache.overall_misses::cpu.data 2039 # number of overall misses 822system.cpu.l2cache.overall_misses::total 5656 # number of overall misses 823system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 112056000 # number of ReadExReq miss cycles 824system.cpu.l2cache.ReadExReq_miss_latency::total 112056000 # number of ReadExReq miss cycles 825system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 275028000 # number of ReadCleanReq miss cycles 826system.cpu.l2cache.ReadCleanReq_miss_latency::total 275028000 # number of ReadCleanReq miss cycles 827system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 45953000 # number of ReadSharedReq miss cycles 828system.cpu.l2cache.ReadSharedReq_miss_latency::total 45953000 # number of ReadSharedReq miss cycles 829system.cpu.l2cache.demand_miss_latency::cpu.inst 275028000 # number of demand (read+write) miss cycles 830system.cpu.l2cache.demand_miss_latency::cpu.data 158009000 # number of demand (read+write) miss cycles 831system.cpu.l2cache.demand_miss_latency::total 433037000 # number of demand (read+write) miss cycles 832system.cpu.l2cache.overall_miss_latency::cpu.inst 275028000 # number of overall miss cycles 833system.cpu.l2cache.overall_miss_latency::cpu.data 158009000 # number of overall miss cycles 834system.cpu.l2cache.overall_miss_latency::total 433037000 # number of overall miss cycles 835system.cpu.l2cache.WritebackDirty_accesses::writebacks 18 # number of WritebackDirty accesses(hits+misses) 836system.cpu.l2cache.WritebackDirty_accesses::total 18 # number of WritebackDirty accesses(hits+misses) 837system.cpu.l2cache.WritebackClean_accesses::writebacks 6469 # number of WritebackClean accesses(hits+misses) 838system.cpu.l2cache.WritebackClean_accesses::total 6469 # number of WritebackClean accesses(hits+misses) 839system.cpu.l2cache.UpgradeReq_accesses::cpu.data 505 # number of UpgradeReq accesses(hits+misses) 840system.cpu.l2cache.UpgradeReq_accesses::total 505 # number of UpgradeReq accesses(hits+misses) 841system.cpu.l2cache.ReadExReq_accesses::cpu.data 1513 # number of ReadExReq accesses(hits+misses) 842system.cpu.l2cache.ReadExReq_accesses::total 1513 # number of ReadExReq accesses(hits+misses) 843system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8494 # number of ReadCleanReq accesses(hits+misses) 844system.cpu.l2cache.ReadCleanReq_accesses::total 8494 # number of ReadCleanReq accesses(hits+misses) 845system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 600 # number of ReadSharedReq accesses(hits+misses) 846system.cpu.l2cache.ReadSharedReq_accesses::total 600 # number of ReadSharedReq accesses(hits+misses) 847system.cpu.l2cache.demand_accesses::cpu.inst 8494 # number of demand (read+write) accesses 848system.cpu.l2cache.demand_accesses::cpu.data 2113 # number of demand (read+write) accesses 849system.cpu.l2cache.demand_accesses::total 10607 # number of demand (read+write) accesses 850system.cpu.l2cache.overall_accesses::cpu.inst 8494 # number of overall (read+write) accesses 851system.cpu.l2cache.overall_accesses::cpu.data 2113 # number of overall (read+write) accesses 852system.cpu.l2cache.overall_accesses::total 10607 # number of overall (read+write) accesses 853system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990099 # miss rate for UpgradeReq accesses 854system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990099 # miss rate for UpgradeReq accesses 855system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996034 # miss rate for ReadExReq accesses 856system.cpu.l2cache.ReadExReq_miss_rate::total 0.996034 # miss rate for ReadExReq accesses 857system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.425830 # miss rate for ReadCleanReq accesses 858system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.425830 # miss rate for ReadCleanReq accesses 859system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.886667 # miss rate for ReadSharedReq accesses 860system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.886667 # miss rate for ReadSharedReq accesses 861system.cpu.l2cache.demand_miss_rate::cpu.inst 0.425830 # miss rate for demand accesses 862system.cpu.l2cache.demand_miss_rate::cpu.data 0.964979 # miss rate for demand accesses 863system.cpu.l2cache.demand_miss_rate::total 0.533233 # miss rate for demand accesses 864system.cpu.l2cache.overall_miss_rate::cpu.inst 0.425830 # miss rate for overall accesses 865system.cpu.l2cache.overall_miss_rate::cpu.data 0.964979 # miss rate for overall accesses 866system.cpu.l2cache.overall_miss_rate::total 0.533233 # miss rate for overall accesses 867system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74357.000664 # average ReadExReq miss latency 868system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74357.000664 # average ReadExReq miss latency 869system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76037.600221 # average ReadCleanReq miss latency 870system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76037.600221 # average ReadCleanReq miss latency 871system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86377.819549 # average ReadSharedReq miss latency 872system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86377.819549 # average ReadSharedReq miss latency 873system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76037.600221 # average overall miss latency 874system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77493.379107 # average overall miss latency 875system.cpu.l2cache.demand_avg_miss_latency::total 76562.411598 # average overall miss latency 876system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76037.600221 # average overall miss latency 877system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77493.379107 # average overall miss latency 878system.cpu.l2cache.overall_avg_miss_latency::total 76562.411598 # average overall miss latency 879system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 880system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 881system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 882system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 883system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 884system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 885system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 500 # number of UpgradeReq MSHR misses 886system.cpu.l2cache.UpgradeReq_mshr_misses::total 500 # number of UpgradeReq MSHR misses 887system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1507 # number of ReadExReq MSHR misses 888system.cpu.l2cache.ReadExReq_mshr_misses::total 1507 # number of ReadExReq MSHR misses 889system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3617 # number of ReadCleanReq MSHR misses 890system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3617 # number of ReadCleanReq MSHR misses 891system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 532 # number of ReadSharedReq MSHR misses 892system.cpu.l2cache.ReadSharedReq_mshr_misses::total 532 # number of ReadSharedReq MSHR misses 893system.cpu.l2cache.demand_mshr_misses::cpu.inst 3617 # number of demand (read+write) MSHR misses 894system.cpu.l2cache.demand_mshr_misses::cpu.data 2039 # number of demand (read+write) MSHR misses 895system.cpu.l2cache.demand_mshr_misses::total 5656 # number of demand (read+write) MSHR misses 896system.cpu.l2cache.overall_mshr_misses::cpu.inst 3617 # number of overall MSHR misses 897system.cpu.l2cache.overall_mshr_misses::cpu.data 2039 # number of overall MSHR misses 898system.cpu.l2cache.overall_mshr_misses::total 5656 # number of overall MSHR misses 899system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 9503500 # number of UpgradeReq MSHR miss cycles 900system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 9503500 # number of UpgradeReq MSHR miss cycles 901system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 96986000 # number of ReadExReq MSHR miss cycles 902system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 96986000 # number of ReadExReq MSHR miss cycles 903system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 238858000 # number of ReadCleanReq MSHR miss cycles 904system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 238858000 # number of ReadCleanReq MSHR miss cycles 905system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 40633000 # number of ReadSharedReq MSHR miss cycles 906system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 40633000 # number of ReadSharedReq MSHR miss cycles 907system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 238858000 # number of demand (read+write) MSHR miss cycles 908system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137619000 # number of demand (read+write) MSHR miss cycles 909system.cpu.l2cache.demand_mshr_miss_latency::total 376477000 # number of demand (read+write) MSHR miss cycles 910system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 238858000 # number of overall MSHR miss cycles 911system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137619000 # number of overall MSHR miss cycles 912system.cpu.l2cache.overall_mshr_miss_latency::total 376477000 # number of overall MSHR miss cycles 913system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990099 # mshr miss rate for UpgradeReq accesses 914system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990099 # mshr miss rate for UpgradeReq accesses 915system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996034 # mshr miss rate for ReadExReq accesses 916system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996034 # mshr miss rate for ReadExReq accesses 917system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.425830 # mshr miss rate for ReadCleanReq accesses 918system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.425830 # mshr miss rate for ReadCleanReq accesses 919system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.886667 # mshr miss rate for ReadSharedReq accesses 920system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.886667 # mshr miss rate for ReadSharedReq accesses 921system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.425830 # mshr miss rate for demand accesses 922system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964979 # mshr miss rate for demand accesses 923system.cpu.l2cache.demand_mshr_miss_rate::total 0.533233 # mshr miss rate for demand accesses 924system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.425830 # mshr miss rate for overall accesses 925system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964979 # mshr miss rate for overall accesses 926system.cpu.l2cache.overall_mshr_miss_rate::total 0.533233 # mshr miss rate for overall accesses 927system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19007 # average UpgradeReq mshr miss latency 928system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19007 # average UpgradeReq mshr miss latency 929system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64357.000664 # average ReadExReq mshr miss latency 930system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64357.000664 # average ReadExReq mshr miss latency 931system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66037.600221 # average ReadCleanReq mshr miss latency 932system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66037.600221 # average ReadCleanReq mshr miss latency 933system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76377.819549 # average ReadSharedReq mshr miss latency 934system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76377.819549 # average ReadSharedReq mshr miss latency 935system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66037.600221 # average overall mshr miss latency 936system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67493.379107 # average overall mshr miss latency 937system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66562.411598 # average overall mshr miss latency 938system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66037.600221 # average overall mshr miss latency 939system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67493.379107 # average overall mshr miss latency 940system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66562.411598 # average overall mshr miss latency 941system.cpu.toL2Bus.snoop_filter.tot_requests 18206 # Total number of requests made to the snoop filter. 942system.cpu.toL2Bus.snoop_filter.hit_single_requests 7138 # Number of requests hitting in the snoop filter with a single holder of the requested data. 943system.cpu.toL2Bus.snoop_filter.hit_multi_requests 549 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 944system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 945system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 946system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 947system.cpu.toL2Bus.trans_dist::ReadResp 9600 # Transaction distribution 948system.cpu.toL2Bus.trans_dist::WritebackDirty 18 # Transaction distribution 949system.cpu.toL2Bus.trans_dist::WritebackClean 6515 # Transaction distribution 950system.cpu.toL2Bus.trans_dist::CleanEvict 54 # Transaction distribution 951system.cpu.toL2Bus.trans_dist::UpgradeReq 505 # Transaction distribution 952system.cpu.toL2Bus.trans_dist::UpgradeResp 505 # Transaction distribution 953system.cpu.toL2Bus.trans_dist::ReadExReq 1513 # Transaction distribution 954system.cpu.toL2Bus.trans_dist::ReadExResp 1513 # Transaction distribution 955system.cpu.toL2Bus.trans_dist::ReadCleanReq 9001 # Transaction distribution 956system.cpu.toL2Bus.trans_dist::ReadSharedReq 600 # Transaction distribution 957system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24009 # Packet count per connected master and slave (bytes) 958system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5308 # Packet count per connected master and slave (bytes) 959system.cpu.toL2Bus.pkt_count::total 29317 # Packet count per connected master and slave (bytes) 960system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 960512 # Cumulative packet size per connected master and slave (bytes) 961system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 136384 # Cumulative packet size per connected master and slave (bytes) 962system.cpu.toL2Bus.pkt_size::total 1096896 # Cumulative packet size per connected master and slave (bytes) 963system.cpu.toL2Bus.snoops 507 # Total snoops (count) 964system.cpu.toL2Bus.snoop_fanout::samples 11619 # Request fanout histogram 965system.cpu.toL2Bus.snoop_fanout::mean 0.094328 # Request fanout histogram 966system.cpu.toL2Bus.snoop_fanout::stdev 0.292297 # Request fanout histogram 967system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 968system.cpu.toL2Bus.snoop_fanout::0 10523 90.57% 90.57% # Request fanout histogram 969system.cpu.toL2Bus.snoop_fanout::1 1096 9.43% 100.00% # Request fanout histogram 970system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 971system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 972system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 973system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 974system.cpu.toL2Bus.snoop_fanout::total 11619 # Request fanout histogram 975system.cpu.toL2Bus.reqLayer0.occupancy 15636499 # Layer occupancy (ticks) 976system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 977system.cpu.toL2Bus.respLayer0.occupancy 13500000 # Layer occupancy (ticks) 978system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 979system.cpu.toL2Bus.respLayer1.occupancy 3422499 # Layer occupancy (ticks) 980system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 981system.membus.trans_dist::ReadResp 4149 # Transaction distribution 982system.membus.trans_dist::UpgradeReq 500 # Transaction distribution 983system.membus.trans_dist::ReadExReq 1507 # Transaction distribution 984system.membus.trans_dist::ReadExResp 1507 # Transaction distribution 985system.membus.trans_dist::ReadSharedReq 4149 # Transaction distribution 986system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11812 # Packet count per connected master and slave (bytes) 987system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11812 # Packet count per connected master and slave (bytes) 988system.membus.pkt_count::total 11812 # Packet count per connected master and slave (bytes) 989system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 361984 # Cumulative packet size per connected master and slave (bytes) 990system.membus.pkt_size_system.cpu.l2cache.mem_side::total 361984 # Cumulative packet size per connected master and slave (bytes) 991system.membus.pkt_size::total 361984 # Cumulative packet size per connected master and slave (bytes) 992system.membus.snoops 0 # Total snoops (count) 993system.membus.snoop_fanout::samples 6156 # Request fanout histogram 994system.membus.snoop_fanout::mean 0 # Request fanout histogram 995system.membus.snoop_fanout::stdev 0 # Request fanout histogram 996system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 997system.membus.snoop_fanout::0 6156 100.00% 100.00% # Request fanout histogram 998system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 999system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1000system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1001system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1002system.membus.snoop_fanout::total 6156 # Request fanout histogram 1003system.membus.reqLayer0.occupancy 7649501 # Layer occupancy (ticks) 1004system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1005system.membus.respLayer1.occupancy 30011250 # Layer occupancy (ticks) 1006system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 1007 1008---------- End Simulation Statistics ----------

stats.txt (11456:c0fb4435b80f)

stats.txt (11502:e273e86a873d)

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.103324 # Number of seconds simulated
4sim_ticks 103324153500 # Number of ticks simulated
5final_tick 103324153500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 75581 # Simulator instruction rate (inst/s)
8host_op_rate 126680 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 59129521 # Simulator tick rate (ticks/s)
10host_mem_usage 307596 # Number of bytes of host memory used
11host_seconds 1747.42 # Real time elapsed on the host
12sim_insts 132071192 # Number of instructions simulated
13sim_ops 221363384 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 231488 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 130496 # Number of bytes read from this memory
18system.physmem.bytes_read::total 361984 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 231488 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 231488 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 3617 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 2039 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 5656 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 2240405 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 1262977 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 3503382 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 2240405 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 2240405 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 2240405 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 1262977 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 3503382 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.readReqs 5656 # Number of read requests accepted
33system.physmem.writeReqs 0 # Number of write requests accepted
34system.physmem.readBursts 5656 # Number of DRAM read bursts, including those serviced by the write queue
35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
36system.physmem.bytesReadDRAM 361984 # Total number of bytes read from DRAM
37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
39system.physmem.bytesReadSys 361984 # Total read bytes from the system interface side
40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
44system.physmem.perBankRdBursts::0 310 # Per bank write bursts
45system.physmem.perBankRdBursts::1 382 # Per bank write bursts
46system.physmem.perBankRdBursts::2 476 # Per bank write bursts
47system.physmem.perBankRdBursts::3 358 # Per bank write bursts
48system.physmem.perBankRdBursts::4 362 # Per bank write bursts
49system.physmem.perBankRdBursts::5 335 # Per bank write bursts
50system.physmem.perBankRdBursts::6 419 # Per bank write bursts
51system.physmem.perBankRdBursts::7 385 # Per bank write bursts
52system.physmem.perBankRdBursts::8 389 # Per bank write bursts
53system.physmem.perBankRdBursts::9 295 # Per bank write bursts
54system.physmem.perBankRdBursts::10 260 # Per bank write bursts
55system.physmem.perBankRdBursts::11 270 # Per bank write bursts
56system.physmem.perBankRdBursts::12 228 # Per bank write bursts
57system.physmem.perBankRdBursts::13 484 # Per bank write bursts
58system.physmem.perBankRdBursts::14 420 # Per bank write bursts
59system.physmem.perBankRdBursts::15 283 # Per bank write bursts
60system.physmem.perBankWrBursts::0 0 # Per bank write bursts
61system.physmem.perBankWrBursts::1 0 # Per bank write bursts
62system.physmem.perBankWrBursts::2 0 # Per bank write bursts
63system.physmem.perBankWrBursts::3 0 # Per bank write bursts
64system.physmem.perBankWrBursts::4 0 # Per bank write bursts
65system.physmem.perBankWrBursts::5 0 # Per bank write bursts
66system.physmem.perBankWrBursts::6 0 # Per bank write bursts
67system.physmem.perBankWrBursts::7 0 # Per bank write bursts
68system.physmem.perBankWrBursts::8 0 # Per bank write bursts
69system.physmem.perBankWrBursts::9 0 # Per bank write bursts
70system.physmem.perBankWrBursts::10 0 # Per bank write bursts
71system.physmem.perBankWrBursts::11 0 # Per bank write bursts
72system.physmem.perBankWrBursts::12 0 # Per bank write bursts
73system.physmem.perBankWrBursts::13 0 # Per bank write bursts
74system.physmem.perBankWrBursts::14 0 # Per bank write bursts
75system.physmem.perBankWrBursts::15 0 # Per bank write bursts
76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
78system.physmem.totGap 103323899000 # Total gap between requests
79system.physmem.readPktSize::0 0 # Read request sizes (log2)
80system.physmem.readPktSize::1 0 # Read request sizes (log2)
81system.physmem.readPktSize::2 0 # Read request sizes (log2)
82system.physmem.readPktSize::3 0 # Read request sizes (log2)
83system.physmem.readPktSize::4 0 # Read request sizes (log2)
84system.physmem.readPktSize::5 0 # Read request sizes (log2)
85system.physmem.readPktSize::6 5656 # Read request sizes (log2)
86system.physmem.writePktSize::0 0 # Write request sizes (log2)
87system.physmem.writePktSize::1 0 # Write request sizes (log2)
88system.physmem.writePktSize::2 0 # Write request sizes (log2)
89system.physmem.writePktSize::3 0 # Write request sizes (log2)
90system.physmem.writePktSize::4 0 # Write request sizes (log2)
91system.physmem.writePktSize::5 0 # Write request sizes (log2)
92system.physmem.writePktSize::6 0 # Write request sizes (log2)
93system.physmem.rdQLenPdf::0 4508 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::1 949 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::2 169 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
189system.physmem.bytesPerActivate::samples 1264 # Bytes accessed per row activation
190system.physmem.bytesPerActivate::mean 286.278481 # Bytes accessed per row activation
191system.physmem.bytesPerActivate::gmean 164.439317 # Bytes accessed per row activation
192system.physmem.bytesPerActivate::stdev 318.670037 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::0-127 554 43.83% 43.83% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::128-255 264 20.89% 64.72% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::256-383 105 8.31% 73.02% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::384-511 69 5.46% 78.48% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::512-639 45 3.56% 82.04% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::640-767 57 4.51% 86.55% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::768-895 28 2.22% 88.77% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::896-1023 17 1.34% 90.11% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::1024-1151 125 9.89% 100.00% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::total 1264 # Bytes accessed per row activation
203system.physmem.totQLat 43672750 # Total ticks spent queuing
204system.physmem.totMemAccLat 149722750 # Total ticks spent from burst creation until serviced by the DRAM
205system.physmem.totBusLat 28280000 # Total ticks spent in databus transfers
206system.physmem.avgQLat 7721.49 # Average queueing delay per DRAM burst
207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
208system.physmem.avgMemAccLat 26471.49 # Average memory access latency per DRAM burst
209system.physmem.avgRdBW 3.50 # Average DRAM read bandwidth in MiByte/s
210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
211system.physmem.avgRdBWSys 3.50 # Average system read bandwidth in MiByte/s
212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
214system.physmem.busUtil 0.03 # Data bus utilization in percentage
215system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
217system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing
218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
219system.physmem.readRowHits 4391 # Number of row buffer hits during reads
220system.physmem.writeRowHits 0 # Number of row buffer hits during writes
221system.physmem.readRowHitRate 77.63 # Row buffer hit rate for reads
222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
223system.physmem.avgGap 18268016.09 # Average gap between requests
224system.physmem.pageHitRate 77.63 # Row buffer hit rate, read and write combined
225system.physmem_0.actEnergy 5624640 # Energy for activate commands per rank (pJ)
226system.physmem_0.preEnergy 3069000 # Energy for precharge commands per rank (pJ)
227system.physmem_0.readEnergy 23610600 # Energy for read commands per rank (pJ)
228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
229system.physmem_0.refreshEnergy 6748591200 # Energy for refresh commands per rank (pJ)
230system.physmem_0.actBackEnergy 3147948405 # Energy for active background per rank (pJ)
231system.physmem_0.preBackEnergy 59232949500 # Energy for precharge background per rank (pJ)
232system.physmem_0.totalEnergy 69161793345 # Total energy per rank (pJ)
233system.physmem_0.averagePower 669.369133 # Core power per rank (mW)
234system.physmem_0.memoryStateTime::IDLE 98535205500 # Time in different power states
235system.physmem_0.memoryStateTime::REF 3450200000 # Time in different power states
236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
237system.physmem_0.memoryStateTime::ACT 1338454000 # Time in different power states
238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
239system.physmem_1.actEnergy 3931200 # Energy for activate commands per rank (pJ)
240system.physmem_1.preEnergy 2145000 # Energy for precharge commands per rank (pJ)
241system.physmem_1.readEnergy 20490600 # Energy for read commands per rank (pJ)
242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
243system.physmem_1.refreshEnergy 6748591200 # Energy for refresh commands per rank (pJ)
244system.physmem_1.actBackEnergy 2964574845 # Energy for active background per rank (pJ)
245system.physmem_1.preBackEnergy 59393774250 # Energy for precharge background per rank (pJ)
246system.physmem_1.totalEnergy 69133507095 # Total energy per rank (pJ)
247system.physmem_1.averagePower 669.095685 # Core power per rank (mW)
248system.physmem_1.memoryStateTime::IDLE 98803806250 # Time in different power states
249system.physmem_1.memoryStateTime::REF 3450200000 # Time in different power states
250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
251system.physmem_1.memoryStateTime::ACT 1069805000 # Time in different power states
252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
253system.cpu.branchPred.lookups 40908032 # Number of BP lookups
254system.cpu.branchPred.condPredicted 40908032 # Number of conditional branches predicted
255system.cpu.branchPred.condIncorrect 6741329 # Number of conditional branches incorrect
256system.cpu.branchPred.BTBLookups 35316490 # Number of BTB lookups
257system.cpu.branchPred.BTBHits 0 # Number of BTB hits
258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
259system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
260system.cpu.branchPred.usedRAS 3206071 # Number of times the RAS was used to get a target.
261system.cpu.branchPred.RASInCorrect 604531 # Number of incorrect RAS predictions.
262system.cpu.branchPred.indirectLookups 35316490 # Number of indirect predictor lookups.
263system.cpu.branchPred.indirectHits 9869044 # Number of indirect target hits.
264system.cpu.branchPred.indirectMisses 25447446 # Number of indirect misses.
265system.cpu.branchPredindirectMispredicted 5035252 # Number of mispredicted indirect branches.
266system.cpu_clk_domain.clock 500 # Clock period in ticks
267system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
268system.cpu.workload.num_syscalls 400 # Number of system calls
269system.cpu.numCycles 206648308 # number of cpu cycles simulated
270system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
271system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
272system.cpu.fetch.icacheStallCycles 46351281 # Number of cycles fetch is stalled on an Icache miss
273system.cpu.fetch.Insts 420030465 # Number of instructions fetch has processed
274system.cpu.fetch.Branches 40908032 # Number of branches that fetch encountered
275system.cpu.fetch.predictedBranches 13075115 # Number of branches that fetch has predicted taken
276system.cpu.fetch.Cycles 152558958 # Number of cycles fetch has run and was not squashing or blocked
277system.cpu.fetch.SquashCycles 14935189 # Number of cycles fetch has spent squashing
278system.cpu.fetch.TlbCycles 126 # Number of cycles fetch has spent waiting for tlb
279system.cpu.fetch.MiscStallCycles 5881 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
280system.cpu.fetch.PendingTrapStallCycles 68758 # Number of stall cycles due to pending traps
281system.cpu.fetch.PendingQuiesceStallCycles 764 # Number of stall cycles due to pending quiesce instructions
282system.cpu.fetch.IcacheWaitRetryStallCycles 179 # Number of stall cycles due to full MSHR
283system.cpu.fetch.CacheLines 41261989 # Number of cache lines fetched
284system.cpu.fetch.IcacheSquashes 1525874 # Number of outstanding Icache misses that were squashed
285system.cpu.fetch.ItlbSquashes 8 # Number of outstanding ITLB misses that were squashed
286system.cpu.fetch.rateDist::samples 206453541 # Number of instructions fetched each cycle (Total)
287system.cpu.fetch.rateDist::mean 3.416062 # Number of instructions fetched each cycle (Total)
288system.cpu.fetch.rateDist::stdev 3.660543 # Number of instructions fetched each cycle (Total)
289system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
290system.cpu.fetch.rateDist::0 99211398 48.06% 48.06% # Number of instructions fetched each cycle (Total)
291system.cpu.fetch.rateDist::1 5135847 2.49% 50.54% # Number of instructions fetched each cycle (Total)
292system.cpu.fetch.rateDist::2 5374620 2.60% 53.15% # Number of instructions fetched each cycle (Total)
293system.cpu.fetch.rateDist::3 5328555 2.58% 55.73% # Number of instructions fetched each cycle (Total)
294system.cpu.fetch.rateDist::4 6013612 2.91% 58.64% # Number of instructions fetched each cycle (Total)
295system.cpu.fetch.rateDist::5 5856529 2.84% 61.48% # Number of instructions fetched each cycle (Total)
296system.cpu.fetch.rateDist::6 5733209 2.78% 64.25% # Number of instructions fetched each cycle (Total)
297system.cpu.fetch.rateDist::7 4747222 2.30% 66.55% # Number of instructions fetched each cycle (Total)
298system.cpu.fetch.rateDist::8 69052549 33.45% 100.00% # Number of instructions fetched each cycle (Total)
299system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
300system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
301system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
302system.cpu.fetch.rateDist::total 206453541 # Number of instructions fetched each cycle (Total)
303system.cpu.fetch.branchRate 0.197960 # Number of branch fetches per cycle
304system.cpu.fetch.rate 2.032586 # Number of inst fetches per cycle
305system.cpu.decode.IdleCycles 32305475 # Number of cycles decode is idle
306system.cpu.decode.BlockedCycles 86547165 # Number of cycles decode is blocked
307system.cpu.decode.RunCycles 62440790 # Number of cycles decode is running
308system.cpu.decode.UnblockCycles 17692517 # Number of cycles decode is unblocking
309system.cpu.decode.SquashCycles 7467594 # Number of cycles decode is squashing
310system.cpu.decode.DecodedInsts 591140753 # Number of instructions handled by decode
311system.cpu.rename.SquashCycles 7467594 # Number of cycles rename is squashing
312system.cpu.rename.IdleCycles 42099614 # Number of cycles rename is idle
313system.cpu.rename.BlockCycles 46622929 # Number of cycles rename is blocking
314system.cpu.rename.serializeStallCycles 29580 # count of cycles rename stalled for serializing inst
315system.cpu.rename.RunCycles 68917298 # Number of cycles rename is running
316system.cpu.rename.UnblockCycles 41316526 # Number of cycles rename is unblocking
317system.cpu.rename.RenamedInsts 552365156 # Number of instructions processed by rename
318system.cpu.rename.ROBFullEvents 1615 # Number of times rename has blocked due to ROB full
319system.cpu.rename.IQFullEvents 36415427 # Number of times rename has blocked due to IQ full
320system.cpu.rename.LQFullEvents 4818042 # Number of times rename has blocked due to LQ full
321system.cpu.rename.SQFullEvents 146051 # Number of times rename has blocked due to SQ full
322system.cpu.rename.RenamedOperands 629691896 # Number of destination operands rename has renamed
323system.cpu.rename.RenameLookups 1486514399 # Number of register rename lookups that rename has made
324system.cpu.rename.int_rename_lookups 974943820 # Number of integer rename lookups
325system.cpu.rename.fp_rename_lookups 15152274 # Number of floating rename lookups
326system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed
327system.cpu.rename.UndoneMaps 370262446 # Number of HB maps that are undone due to squashing
328system.cpu.rename.serializingInsts 2381 # count of serializing insts renamed
329system.cpu.rename.tempSerializingInsts 2386 # count of temporary serializing insts renamed
330system.cpu.rename.skidInsts 89347483 # count of insts added to the skid buffer
331system.cpu.memDep0.insertedLoads 128815998 # Number of loads inserted to the mem dependence unit.
332system.cpu.memDep0.insertedStores 45923960 # Number of stores inserted to the mem dependence unit.
333system.cpu.memDep0.conflictingLoads 77358410 # Number of conflicting loads.
334system.cpu.memDep0.conflictingStores 25275137 # Number of conflicting stores.
335system.cpu.iq.iqInstsAdded 490566423 # Number of instructions added to the IQ (excludes non-spec)
336system.cpu.iq.iqNonSpecInstsAdded 62065 # Number of non-speculative instructions added to the IQ
337system.cpu.iq.iqInstsIssued 338414549 # Number of instructions issued
338system.cpu.iq.iqSquashedInstsIssued 1099553 # Number of squashed instructions issued
339system.cpu.iq.iqSquashedInstsExamined 269265104 # Number of squashed instructions iterated over during squash; mainly for profiling
340system.cpu.iq.iqSquashedOperandsExamined 527048763 # Number of squashed operands that are examined and possibly removed from graph
341system.cpu.iq.iqSquashedNonSpecRemoved 60820 # Number of squashed non-spec instructions that were removed
342system.cpu.iq.issued_per_cycle::samples 206453541 # Number of insts issued each cycle
343system.cpu.iq.issued_per_cycle::mean 1.639180 # Number of insts issued each cycle
344system.cpu.iq.issued_per_cycle::stdev 1.804126 # Number of insts issued each cycle
345system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
346system.cpu.iq.issued_per_cycle::0 73345677 35.53% 35.53% # Number of insts issued each cycle
347system.cpu.iq.issued_per_cycle::1 46646037 22.59% 58.12% # Number of insts issued each cycle
348system.cpu.iq.issued_per_cycle::2 32854801 15.91% 74.03% # Number of insts issued each cycle
349system.cpu.iq.issued_per_cycle::3 20905072 10.13% 84.16% # Number of insts issued each cycle
350system.cpu.iq.issued_per_cycle::4 15063521 7.30% 91.46% # Number of insts issued each cycle
351system.cpu.iq.issued_per_cycle::5 8409386 4.07% 95.53% # Number of insts issued each cycle
352system.cpu.iq.issued_per_cycle::6 5213188 2.53% 98.05% # Number of insts issued each cycle
353system.cpu.iq.issued_per_cycle::7 2363320 1.14% 99.20% # Number of insts issued each cycle
354system.cpu.iq.issued_per_cycle::8 1652539 0.80% 100.00% # Number of insts issued each cycle
355system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
356system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
357system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
358system.cpu.iq.issued_per_cycle::total 206453541 # Number of insts issued each cycle
359system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
360system.cpu.iq.fu_full::IntAlu 758238 19.31% 19.31% # attempts to use FU when none available
361system.cpu.iq.fu_full::IntMult 0 0.00% 19.31% # attempts to use FU when none available
362system.cpu.iq.fu_full::IntDiv 0 0.00% 19.31% # attempts to use FU when none available
363system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.31% # attempts to use FU when none available
364system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.31% # attempts to use FU when none available
365system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.31% # attempts to use FU when none available
366system.cpu.iq.fu_full::FloatMult 0 0.00% 19.31% # attempts to use FU when none available
367system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.31% # attempts to use FU when none available
368system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.31% # attempts to use FU when none available
369system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.31% # attempts to use FU when none available
370system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.31% # attempts to use FU when none available
371system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.31% # attempts to use FU when none available
372system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.31% # attempts to use FU when none available
373system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.31% # attempts to use FU when none available
374system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.31% # attempts to use FU when none available
375system.cpu.iq.fu_full::SimdMult 0 0.00% 19.31% # attempts to use FU when none available
376system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.31% # attempts to use FU when none available
377system.cpu.iq.fu_full::SimdShift 0 0.00% 19.31% # attempts to use FU when none available
378system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.31% # attempts to use FU when none available
379system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.31% # attempts to use FU when none available
380system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.31% # attempts to use FU when none available
381system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.31% # attempts to use FU when none available
382system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.31% # attempts to use FU when none available
383system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.31% # attempts to use FU when none available
384system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.31% # attempts to use FU when none available
385system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.31% # attempts to use FU when none available
386system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.31% # attempts to use FU when none available
387system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.31% # attempts to use FU when none available
388system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.31% # attempts to use FU when none available
389system.cpu.iq.fu_full::MemRead 2733075 69.60% 88.91% # attempts to use FU when none available
390system.cpu.iq.fu_full::MemWrite 435620 11.09% 100.00% # attempts to use FU when none available
391system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
392system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
393system.cpu.iq.FU_type_0::No_OpClass 1211810 0.36% 0.36% # Type of FU issued
394system.cpu.iq.FU_type_0::IntAlu 216608884 64.01% 64.37% # Type of FU issued
395system.cpu.iq.FU_type_0::IntMult 799973 0.24% 64.60% # Type of FU issued
396system.cpu.iq.FU_type_0::IntDiv 7048329 2.08% 66.68% # Type of FU issued
397system.cpu.iq.FU_type_0::FloatAdd 1813849 0.54% 67.22% # Type of FU issued
398system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.22% # Type of FU issued
399system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.22% # Type of FU issued
400system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.22% # Type of FU issued
401system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.22% # Type of FU issued
402system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.22% # Type of FU issued
403system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.22% # Type of FU issued
404system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.22% # Type of FU issued
405system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.22% # Type of FU issued
406system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.22% # Type of FU issued
407system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.22% # Type of FU issued
408system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.22% # Type of FU issued
409system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.22% # Type of FU issued
410system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.22% # Type of FU issued
411system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.22% # Type of FU issued
412system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.22% # Type of FU issued
413system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.22% # Type of FU issued
414system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.22% # Type of FU issued
415system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.22% # Type of FU issued
416system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.22% # Type of FU issued
417system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.22% # Type of FU issued
418system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.22% # Type of FU issued
419system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.22% # Type of FU issued
420system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.22% # Type of FU issued
421system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.22% # Type of FU issued
422system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.22% # Type of FU issued
423system.cpu.iq.FU_type_0::MemRead 84312637 24.91% 92.13% # Type of FU issued
424system.cpu.iq.FU_type_0::MemWrite 26619067 7.87% 100.00% # Type of FU issued
425system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
426system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
427system.cpu.iq.FU_type_0::total 338414549 # Type of FU issued
428system.cpu.iq.rate 1.637635 # Inst issue rate
429system.cpu.iq.fu_busy_cnt 3926933 # FU busy when requested
430system.cpu.iq.fu_busy_rate 0.011604 # FU busy rate (busy events/executed inst)
431system.cpu.iq.int_inst_queue_reads 880106724 # Number of integer instruction queue reads
432system.cpu.iq.int_inst_queue_writes 745207821 # Number of integer instruction queue writes
433system.cpu.iq.int_inst_queue_wakeup_accesses 316030450 # Number of integer instruction queue wakeup accesses
434system.cpu.iq.fp_inst_queue_reads 8202401 # Number of floating instruction queue reads
435system.cpu.iq.fp_inst_queue_writes 15512263 # Number of floating instruction queue writes
436system.cpu.iq.fp_inst_queue_wakeup_accesses 3567674 # Number of floating instruction queue wakeup accesses
437system.cpu.iq.int_alu_accesses 337013730 # Number of integer alu accesses
438system.cpu.iq.fp_alu_accesses 4115942 # Number of floating point alu accesses
439system.cpu.iew.lsq.thread0.forwLoads 18154732 # Number of loads that had data forwarded from stores
440system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
441system.cpu.iew.lsq.thread0.squashedLoads 72166411 # Number of loads squashed
442system.cpu.iew.lsq.thread0.ignoredResponses 54986 # Number of memory responses ignored because the instruction is squashed
443system.cpu.iew.lsq.thread0.memOrderViolation 863760 # Number of memory ordering violations
444system.cpu.iew.lsq.thread0.squashedStores 25408243 # Number of stores squashed
445system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
446system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
447system.cpu.iew.lsq.thread0.rescheduledLoads 50543 # Number of loads that were rescheduled
448system.cpu.iew.lsq.thread0.cacheBlocked 53 # Number of times an access to memory failed due to the cache being blocked
449system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
450system.cpu.iew.iewSquashCycles 7467594 # Number of cycles IEW is squashing
451system.cpu.iew.iewBlockCycles 35770303 # Number of cycles IEW is blocking
452system.cpu.iew.iewUnblockCycles 592137 # Number of cycles IEW is unblocking
453system.cpu.iew.iewDispatchedInsts 490628488 # Number of instructions dispatched to IQ
454system.cpu.iew.iewDispSquashedInsts 1259959 # Number of squashed instructions skipped by dispatch
455system.cpu.iew.iewDispLoadInsts 128815998 # Number of dispatched load instructions
456system.cpu.iew.iewDispStoreInsts 45923960 # Number of dispatched store instructions
457system.cpu.iew.iewDispNonSpecInsts 22654 # Number of dispatched non-speculative instructions
458system.cpu.iew.iewIQFullEvents 545800 # Number of times the IQ has become full, causing a stall
459system.cpu.iew.iewLSQFullEvents 38626 # Number of times the LSQ has become full, causing a stall
460system.cpu.iew.memOrderViolationEvents 863760 # Number of memory order violations
461system.cpu.iew.predictedTakenIncorrect 1294864 # Number of branches that were predicted taken incorrectly
462system.cpu.iew.predictedNotTakenIncorrect 6880130 # Number of branches that were predicted not taken incorrectly
463system.cpu.iew.branchMispredicts 8174994 # Number of branch mispredicts detected at execute
464system.cpu.iew.iewExecutedInsts 326485130 # Number of executed instructions
465system.cpu.iew.iewExecLoadInsts 80685795 # Number of load instructions executed
466system.cpu.iew.iewExecSquashedInsts 11929419 # Number of squashed instructions skipped in execute
467system.cpu.iew.exec_swp 0 # number of swp insts executed
468system.cpu.iew.exec_nop 0 # number of nop insts executed
469system.cpu.iew.exec_refs 106318426 # number of memory reference insts executed
470system.cpu.iew.exec_branches 18939296 # Number of branches executed
471system.cpu.iew.exec_stores 25632631 # Number of stores executed
472system.cpu.iew.exec_rate 1.579907 # Inst execution rate
473system.cpu.iew.wb_sent 322610085 # cumulative count of insts sent to commit
474system.cpu.iew.wb_count 319598124 # cumulative count of insts written-back
475system.cpu.iew.wb_producers 256503247 # num instructions producing a value
476system.cpu.iew.wb_consumers 435667509 # num instructions consuming a value
477system.cpu.iew.wb_rate 1.546580 # insts written-back per cycle
478system.cpu.iew.wb_fanout 0.588759 # average fanout of values written-back
479system.cpu.commit.commitSquashedInsts 269290512 # The number of squashed insts skipped by commit
480system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards
481system.cpu.commit.branchMispredicts 6746174 # The number of times a branch was mispredicted
482system.cpu.commit.committed_per_cycle::samples 163890954 # Number of insts commited each cycle
483system.cpu.commit.committed_per_cycle::mean 1.350675 # Number of insts commited each cycle
484system.cpu.commit.committed_per_cycle::stdev 1.933271 # Number of insts commited each cycle
485system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
486system.cpu.commit.committed_per_cycle::0 67206524 41.01% 41.01% # Number of insts commited each cycle
487system.cpu.commit.committed_per_cycle::1 54940140 33.52% 74.53% # Number of insts commited each cycle
488system.cpu.commit.committed_per_cycle::2 13261155 8.09% 82.62% # Number of insts commited each cycle
489system.cpu.commit.committed_per_cycle::3 10687834 6.52% 89.14% # Number of insts commited each cycle
490system.cpu.commit.committed_per_cycle::4 5446779 3.32% 92.47% # Number of insts commited each cycle
491system.cpu.commit.committed_per_cycle::5 3132108 1.91% 94.38% # Number of insts commited each cycle
492system.cpu.commit.committed_per_cycle::6 1092307 0.67% 95.04% # Number of insts commited each cycle
493system.cpu.commit.committed_per_cycle::7 1156922 0.71% 95.75% # Number of insts commited each cycle
494system.cpu.commit.committed_per_cycle::8 6967185 4.25% 100.00% # Number of insts commited each cycle
495system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
496system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
497system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
498system.cpu.commit.committed_per_cycle::total 163890954 # Number of insts commited each cycle
499system.cpu.commit.committedInsts 132071192 # Number of instructions committed
500system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed
501system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
502system.cpu.commit.refs 77165304 # Number of memory references committed
503system.cpu.commit.loads 56649587 # Number of loads committed
504system.cpu.commit.membars 0 # Number of memory barriers committed
505system.cpu.commit.branches 12326938 # Number of branches committed
506system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
507system.cpu.commit.int_insts 219019985 # Number of committed integer instructions.
508system.cpu.commit.function_calls 797818 # Number of function calls committed.
509system.cpu.commit.op_class_0::No_OpClass 1176721 0.53% 0.53% # Class of committed instruction
510system.cpu.commit.op_class_0::IntAlu 134111832 60.58% 61.12% # Class of committed instruction
511system.cpu.commit.op_class_0::IntMult 772953 0.35% 61.47% # Class of committed instruction
512system.cpu.commit.op_class_0::IntDiv 7031501 3.18% 64.64% # Class of committed instruction
513system.cpu.commit.op_class_0::FloatAdd 1105073 0.50% 65.14% # Class of committed instruction
514system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.14% # Class of committed instruction
515system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.14% # Class of committed instruction
516system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.14% # Class of committed instruction
517system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.14% # Class of committed instruction
518system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.14% # Class of committed instruction
519system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.14% # Class of committed instruction
520system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.14% # Class of committed instruction
521system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.14% # Class of committed instruction
522system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.14% # Class of committed instruction
523system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.14% # Class of committed instruction
524system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.14% # Class of committed instruction
525system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.14% # Class of committed instruction
526system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.14% # Class of committed instruction
527system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.14% # Class of committed instruction
528system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.14% # Class of committed instruction
529system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.14% # Class of committed instruction
530system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.14% # Class of committed instruction
531system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.14% # Class of committed instruction
532system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.14% # Class of committed instruction
533system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.14% # Class of committed instruction
534system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.14% # Class of committed instruction
535system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.14% # Class of committed instruction
536system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction
537system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction
538system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction
539system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction
540system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction
541system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
542system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
543system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction
544system.cpu.commit.bw_lim_events 6967185 # number cycles where commit BW limit reached
545system.cpu.rob.rob_reads 647577665 # The number of ROB reads
546system.cpu.rob.rob_writes 1024269930 # The number of ROB writes
547system.cpu.timesIdled 2819 # Number of times that the entire CPU went into an idle state and unscheduled itself
548system.cpu.idleCycles 194767 # Total number of cycles that the CPU has spent unscheduled due to idling
549system.cpu.committedInsts 132071192 # Number of Instructions Simulated
550system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated
551system.cpu.cpi 1.564674 # CPI: Cycles Per Instruction
552system.cpu.cpi_total 1.564674 # CPI: Total CPI of All Threads
553system.cpu.ipc 0.639111 # IPC: Instructions Per Cycle
554system.cpu.ipc_total 0.639111 # IPC: Total IPC of All Threads
555system.cpu.int_regfile_reads 524516370 # number of integer regfile reads
556system.cpu.int_regfile_writes 289029189 # number of integer regfile writes
557system.cpu.fp_regfile_reads 4536413 # number of floating regfile reads
558system.cpu.fp_regfile_writes 3331836 # number of floating regfile writes
559system.cpu.cc_regfile_reads 107017358 # number of cc regfile reads
560system.cpu.cc_regfile_writes 65774990 # number of cc regfile writes
561system.cpu.misc_regfile_reads 176892429 # number of misc regfile reads
562system.cpu.misc_regfile_writes 1689 # number of misc regfile writes
563system.cpu.dcache.tags.replacements 72 # number of replacements
564system.cpu.dcache.tags.tagsinuse 1525.498489 # Cycle average of tags in use
565system.cpu.dcache.tags.total_refs 82766316 # Total number of references to valid blocks.
566system.cpu.dcache.tags.sampled_refs 2113 # Sample count of references to valid blocks.
567system.cpu.dcache.tags.avg_refs 39170.050166 # Average number of references to valid blocks.
568system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
569system.cpu.dcache.tags.occ_blocks::cpu.data 1525.498489 # Average occupied blocks per requestor
570system.cpu.dcache.tags.occ_percent::cpu.data 0.372436 # Average percentage of cache occupancy
571system.cpu.dcache.tags.occ_percent::total 0.372436 # Average percentage of cache occupancy
572system.cpu.dcache.tags.occ_task_id_blocks::1024 2041 # Occupied blocks per task id
573system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id
574system.cpu.dcache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id
575system.cpu.dcache.tags.age_task_id_blocks_1024::2 101 # Occupied blocks per task id
576system.cpu.dcache.tags.age_task_id_blocks_1024::3 409 # Occupied blocks per task id
577system.cpu.dcache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id
578system.cpu.dcache.tags.occ_task_id_percent::1024 0.498291 # Percentage of cache occupancy per task id
579system.cpu.dcache.tags.tag_accesses 165539971 # Number of tag accesses
580system.cpu.dcache.tags.data_accesses 165539971 # Number of data accesses
581system.cpu.dcache.ReadReq_hits::cpu.data 62251936 # number of ReadReq hits
582system.cpu.dcache.ReadReq_hits::total 62251936 # number of ReadReq hits
583system.cpu.dcache.WriteReq_hits::cpu.data 20513707 # number of WriteReq hits
584system.cpu.dcache.WriteReq_hits::total 20513707 # number of WriteReq hits
585system.cpu.dcache.demand_hits::cpu.data 82765643 # number of demand (read+write) hits
586system.cpu.dcache.demand_hits::total 82765643 # number of demand (read+write) hits
587system.cpu.dcache.overall_hits::cpu.data 82765643 # number of overall hits
588system.cpu.dcache.overall_hits::total 82765643 # number of overall hits
589system.cpu.dcache.ReadReq_misses::cpu.data 1262 # number of ReadReq misses
590system.cpu.dcache.ReadReq_misses::total 1262 # number of ReadReq misses
591system.cpu.dcache.WriteReq_misses::cpu.data 2024 # number of WriteReq misses
592system.cpu.dcache.WriteReq_misses::total 2024 # number of WriteReq misses
593system.cpu.dcache.demand_misses::cpu.data 3286 # number of demand (read+write) misses
594system.cpu.dcache.demand_misses::total 3286 # number of demand (read+write) misses
595system.cpu.dcache.overall_misses::cpu.data 3286 # number of overall misses
596system.cpu.dcache.overall_misses::total 3286 # number of overall misses
597system.cpu.dcache.ReadReq_miss_latency::cpu.data 84231000 # number of ReadReq miss cycles
598system.cpu.dcache.ReadReq_miss_latency::total 84231000 # number of ReadReq miss cycles
599system.cpu.dcache.WriteReq_miss_latency::cpu.data 131983500 # number of WriteReq miss cycles
600system.cpu.dcache.WriteReq_miss_latency::total 131983500 # number of WriteReq miss cycles
601system.cpu.dcache.demand_miss_latency::cpu.data 216214500 # number of demand (read+write) miss cycles
602system.cpu.dcache.demand_miss_latency::total 216214500 # number of demand (read+write) miss cycles
603system.cpu.dcache.overall_miss_latency::cpu.data 216214500 # number of overall miss cycles
604system.cpu.dcache.overall_miss_latency::total 216214500 # number of overall miss cycles
605system.cpu.dcache.ReadReq_accesses::cpu.data 62253198 # number of ReadReq accesses(hits+misses)
606system.cpu.dcache.ReadReq_accesses::total 62253198 # number of ReadReq accesses(hits+misses)
607system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
608system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
609system.cpu.dcache.demand_accesses::cpu.data 82768929 # number of demand (read+write) accesses
610system.cpu.dcache.demand_accesses::total 82768929 # number of demand (read+write) accesses
611system.cpu.dcache.overall_accesses::cpu.data 82768929 # number of overall (read+write) accesses
612system.cpu.dcache.overall_accesses::total 82768929 # number of overall (read+write) accesses
613system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses
614system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses
615system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000099 # miss rate for WriteReq accesses
616system.cpu.dcache.WriteReq_miss_rate::total 0.000099 # miss rate for WriteReq accesses
617system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses
618system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses
619system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses
620system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses
621system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66744.057052 # average ReadReq miss latency
622system.cpu.dcache.ReadReq_avg_miss_latency::total 66744.057052 # average ReadReq miss latency
623system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65209.239130 # average WriteReq miss latency
624system.cpu.dcache.WriteReq_avg_miss_latency::total 65209.239130 # average WriteReq miss latency
625system.cpu.dcache.demand_avg_miss_latency::cpu.data 65798.691418 # average overall miss latency
626system.cpu.dcache.demand_avg_miss_latency::total 65798.691418 # average overall miss latency
627system.cpu.dcache.overall_avg_miss_latency::cpu.data 65798.691418 # average overall miss latency
628system.cpu.dcache.overall_avg_miss_latency::total 65798.691418 # average overall miss latency
629system.cpu.dcache.blocked_cycles::no_mshrs 369 # number of cycles access was blocked
630system.cpu.dcache.blocked_cycles::no_targets 73 # number of cycles access was blocked
631system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked
632system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
633system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.125000 # average number of cycles each access was blocked
634system.cpu.dcache.avg_blocked_cycles::no_targets 36.500000 # average number of cycles each access was blocked
635system.cpu.dcache.writebacks::writebacks 18 # number of writebacks
636system.cpu.dcache.writebacks::total 18 # number of writebacks
637system.cpu.dcache.ReadReq_mshr_hits::cpu.data 661 # number of ReadReq MSHR hits
638system.cpu.dcache.ReadReq_mshr_hits::total 661 # number of ReadReq MSHR hits
639system.cpu.dcache.WriteReq_mshr_hits::cpu.data 7 # number of WriteReq MSHR hits
640system.cpu.dcache.WriteReq_mshr_hits::total 7 # number of WriteReq MSHR hits
641system.cpu.dcache.demand_mshr_hits::cpu.data 668 # number of demand (read+write) MSHR hits
642system.cpu.dcache.demand_mshr_hits::total 668 # number of demand (read+write) MSHR hits
643system.cpu.dcache.overall_mshr_hits::cpu.data 668 # number of overall MSHR hits
644system.cpu.dcache.overall_mshr_hits::total 668 # number of overall MSHR hits
645system.cpu.dcache.ReadReq_mshr_misses::cpu.data 601 # number of ReadReq MSHR misses
646system.cpu.dcache.ReadReq_mshr_misses::total 601 # number of ReadReq MSHR misses
647system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2017 # number of WriteReq MSHR misses
648system.cpu.dcache.WriteReq_mshr_misses::total 2017 # number of WriteReq MSHR misses
649system.cpu.dcache.demand_mshr_misses::cpu.data 2618 # number of demand (read+write) MSHR misses
650system.cpu.dcache.demand_mshr_misses::total 2618 # number of demand (read+write) MSHR misses
651system.cpu.dcache.overall_mshr_misses::cpu.data 2618 # number of overall MSHR misses
652system.cpu.dcache.overall_mshr_misses::total 2618 # number of overall MSHR misses
653system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47710000 # number of ReadReq MSHR miss cycles
654system.cpu.dcache.ReadReq_mshr_miss_latency::total 47710000 # number of ReadReq MSHR miss cycles
655system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 129636500 # number of WriteReq MSHR miss cycles
656system.cpu.dcache.WriteReq_mshr_miss_latency::total 129636500 # number of WriteReq MSHR miss cycles
657system.cpu.dcache.demand_mshr_miss_latency::cpu.data 177346500 # number of demand (read+write) MSHR miss cycles
658system.cpu.dcache.demand_mshr_miss_latency::total 177346500 # number of demand (read+write) MSHR miss cycles
659system.cpu.dcache.overall_mshr_miss_latency::cpu.data 177346500 # number of overall MSHR miss cycles
660system.cpu.dcache.overall_mshr_miss_latency::total 177346500 # number of overall MSHR miss cycles
661system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
662system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
663system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000098 # mshr miss rate for WriteReq accesses
664system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000098 # mshr miss rate for WriteReq accesses
665system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses
666system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses
667system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses
668system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses
669system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79384.359401 # average ReadReq mshr miss latency
670system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79384.359401 # average ReadReq mshr miss latency
671system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64271.938523 # average WriteReq mshr miss latency
672system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64271.938523 # average WriteReq mshr miss latency
673system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67741.214668 # average overall mshr miss latency
674system.cpu.dcache.demand_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency
675system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67741.214668 # average overall mshr miss latency
676system.cpu.dcache.overall_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency
677system.cpu.icache.tags.replacements 6515 # number of replacements
678system.cpu.icache.tags.tagsinuse 1663.291735 # Cycle average of tags in use
679system.cpu.icache.tags.total_refs 41248897 # Total number of references to valid blocks.
680system.cpu.icache.tags.sampled_refs 8499 # Sample count of references to valid blocks.
681system.cpu.icache.tags.avg_refs 4853.382398 # Average number of references to valid blocks.
682system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
683system.cpu.icache.tags.occ_blocks::cpu.inst 1663.291735 # Average occupied blocks per requestor
684system.cpu.icache.tags.occ_percent::cpu.inst 0.812154 # Average percentage of cache occupancy
685system.cpu.icache.tags.occ_percent::total 0.812154 # Average percentage of cache occupancy
686system.cpu.icache.tags.occ_task_id_blocks::1024 1984 # Occupied blocks per task id
687system.cpu.icache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id
688system.cpu.icache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id
689system.cpu.icache.tags.age_task_id_blocks_1024::2 845 # Occupied blocks per task id
690system.cpu.icache.tags.age_task_id_blocks_1024::3 155 # Occupied blocks per task id
691system.cpu.icache.tags.age_task_id_blocks_1024::4 736 # Occupied blocks per task id
692system.cpu.icache.tags.occ_task_id_percent::1024 0.968750 # Percentage of cache occupancy per task id
693system.cpu.icache.tags.tag_accesses 82532972 # Number of tag accesses
694system.cpu.icache.tags.data_accesses 82532972 # Number of data accesses
695system.cpu.icache.ReadReq_hits::cpu.inst 41248897 # number of ReadReq hits
696system.cpu.icache.ReadReq_hits::total 41248897 # number of ReadReq hits
697system.cpu.icache.demand_hits::cpu.inst 41248897 # number of demand (read+write) hits
698system.cpu.icache.demand_hits::total 41248897 # number of demand (read+write) hits
699system.cpu.icache.overall_hits::cpu.inst 41248897 # number of overall hits
700system.cpu.icache.overall_hits::total 41248897 # number of overall hits
701system.cpu.icache.ReadReq_misses::cpu.inst 13089 # number of ReadReq misses
702system.cpu.icache.ReadReq_misses::total 13089 # number of ReadReq misses
703system.cpu.icache.demand_misses::cpu.inst 13089 # number of demand (read+write) misses
704system.cpu.icache.demand_misses::total 13089 # number of demand (read+write) misses
705system.cpu.icache.overall_misses::cpu.inst 13089 # number of overall misses
706system.cpu.icache.overall_misses::total 13089 # number of overall misses
707system.cpu.icache.ReadReq_miss_latency::cpu.inst 485791000 # number of ReadReq miss cycles
708system.cpu.icache.ReadReq_miss_latency::total 485791000 # number of ReadReq miss cycles
709system.cpu.icache.demand_miss_latency::cpu.inst 485791000 # number of demand (read+write) miss cycles
710system.cpu.icache.demand_miss_latency::total 485791000 # number of demand (read+write) miss cycles
711system.cpu.icache.overall_miss_latency::cpu.inst 485791000 # number of overall miss cycles
712system.cpu.icache.overall_miss_latency::total 485791000 # number of overall miss cycles
713system.cpu.icache.ReadReq_accesses::cpu.inst 41261986 # number of ReadReq accesses(hits+misses)
714system.cpu.icache.ReadReq_accesses::total 41261986 # number of ReadReq accesses(hits+misses)
715system.cpu.icache.demand_accesses::cpu.inst 41261986 # number of demand (read+write) accesses
716system.cpu.icache.demand_accesses::total 41261986 # number of demand (read+write) accesses
717system.cpu.icache.overall_accesses::cpu.inst 41261986 # number of overall (read+write) accesses
718system.cpu.icache.overall_accesses::total 41261986 # number of overall (read+write) accesses
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720system.cpu.icache.ReadReq_miss_rate::total 0.000317 # miss rate for ReadReq accesses
721system.cpu.icache.demand_miss_rate::cpu.inst 0.000317 # miss rate for demand accesses
722system.cpu.icache.demand_miss_rate::total 0.000317 # miss rate for demand accesses
723system.cpu.icache.overall_miss_rate::cpu.inst 0.000317 # miss rate for overall accesses
724system.cpu.icache.overall_miss_rate::total 0.000317 # miss rate for overall accesses
725system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37114.447246 # average ReadReq miss latency
726system.cpu.icache.ReadReq_avg_miss_latency::total 37114.447246 # average ReadReq miss latency
727system.cpu.icache.demand_avg_miss_latency::cpu.inst 37114.447246 # average overall miss latency
728system.cpu.icache.demand_avg_miss_latency::total 37114.447246 # average overall miss latency
729system.cpu.icache.overall_avg_miss_latency::cpu.inst 37114.447246 # average overall miss latency
730system.cpu.icache.overall_avg_miss_latency::total 37114.447246 # average overall miss latency
731system.cpu.icache.blocked_cycles::no_mshrs 2090 # number of cycles access was blocked
732system.cpu.icache.blocked_cycles::no_targets 305 # number of cycles access was blocked
733system.cpu.icache.blocked::no_mshrs 30 # number of cycles access was blocked
734system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
735system.cpu.icache.avg_blocked_cycles::no_mshrs 69.666667 # average number of cycles each access was blocked
736system.cpu.icache.avg_blocked_cycles::no_targets 305 # average number of cycles each access was blocked
737system.cpu.icache.writebacks::writebacks 6515 # number of writebacks
738system.cpu.icache.writebacks::total 6515 # number of writebacks
739system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4088 # number of ReadReq MSHR hits
740system.cpu.icache.ReadReq_mshr_hits::total 4088 # number of ReadReq MSHR hits
741system.cpu.icache.demand_mshr_hits::cpu.inst 4088 # number of demand (read+write) MSHR hits
742system.cpu.icache.demand_mshr_hits::total 4088 # number of demand (read+write) MSHR hits
743system.cpu.icache.overall_mshr_hits::cpu.inst 4088 # number of overall MSHR hits
744system.cpu.icache.overall_mshr_hits::total 4088 # number of overall MSHR hits
745system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9001 # number of ReadReq MSHR misses
746system.cpu.icache.ReadReq_mshr_misses::total 9001 # number of ReadReq MSHR misses
747system.cpu.icache.demand_mshr_misses::cpu.inst 9001 # number of demand (read+write) MSHR misses
748system.cpu.icache.demand_mshr_misses::total 9001 # number of demand (read+write) MSHR misses
749system.cpu.icache.overall_mshr_misses::cpu.inst 9001 # number of overall MSHR misses
750system.cpu.icache.overall_mshr_misses::total 9001 # number of overall MSHR misses
751system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 340708000 # number of ReadReq MSHR miss cycles
752system.cpu.icache.ReadReq_mshr_miss_latency::total 340708000 # number of ReadReq MSHR miss cycles
753system.cpu.icache.demand_mshr_miss_latency::cpu.inst 340708000 # number of demand (read+write) MSHR miss cycles
754system.cpu.icache.demand_mshr_miss_latency::total 340708000 # number of demand (read+write) MSHR miss cycles
755system.cpu.icache.overall_mshr_miss_latency::cpu.inst 340708000 # number of overall MSHR miss cycles
756system.cpu.icache.overall_mshr_miss_latency::total 340708000 # number of overall MSHR miss cycles
757system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for ReadReq accesses
758system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000218 # mshr miss rate for ReadReq accesses
759system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for demand accesses
760system.cpu.icache.demand_mshr_miss_rate::total 0.000218 # mshr miss rate for demand accesses
761system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for overall accesses
762system.cpu.icache.overall_mshr_miss_rate::total 0.000218 # mshr miss rate for overall accesses
763system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37852.238640 # average ReadReq mshr miss latency
764system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37852.238640 # average ReadReq mshr miss latency
765system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37852.238640 # average overall mshr miss latency
766system.cpu.icache.demand_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency
767system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37852.238640 # average overall mshr miss latency
768system.cpu.icache.overall_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency
769system.cpu.l2cache.tags.replacements 0 # number of replacements
770system.cpu.l2cache.tags.tagsinuse 2796.844278 # Cycle average of tags in use
771system.cpu.l2cache.tags.total_refs 11471 # Total number of references to valid blocks.
772system.cpu.l2cache.tags.sampled_refs 4155 # Sample count of references to valid blocks.
773system.cpu.l2cache.tags.avg_refs 2.760770 # Average number of references to valid blocks.
774system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
775system.cpu.l2cache.tags.occ_blocks::writebacks 4.971138 # Average occupied blocks per requestor
776system.cpu.l2cache.tags.occ_blocks::cpu.inst 2402.103394 # Average occupied blocks per requestor
777system.cpu.l2cache.tags.occ_blocks::cpu.data 389.769746 # Average occupied blocks per requestor
778system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy
779system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073306 # Average percentage of cache occupancy
780system.cpu.l2cache.tags.occ_percent::cpu.data 0.011895 # Average percentage of cache occupancy
781system.cpu.l2cache.tags.occ_percent::total 0.085353 # Average percentage of cache occupancy
782system.cpu.l2cache.tags.occ_task_id_blocks::1024 4155 # Occupied blocks per task id
783system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
784system.cpu.l2cache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id
785system.cpu.l2cache.tags.age_task_id_blocks_1024::2 992 # Occupied blocks per task id
786system.cpu.l2cache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id
787system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2824 # Occupied blocks per task id
788system.cpu.l2cache.tags.occ_task_id_percent::1024 0.126801 # Percentage of cache occupancy per task id
789system.cpu.l2cache.tags.tag_accesses 146881 # Number of tag accesses
790system.cpu.l2cache.tags.data_accesses 146881 # Number of data accesses
791system.cpu.l2cache.WritebackDirty_hits::writebacks 18 # number of WritebackDirty hits
792system.cpu.l2cache.WritebackDirty_hits::total 18 # number of WritebackDirty hits
793system.cpu.l2cache.WritebackClean_hits::writebacks 6469 # number of WritebackClean hits
794system.cpu.l2cache.WritebackClean_hits::total 6469 # number of WritebackClean hits
795system.cpu.l2cache.UpgradeReq_hits::cpu.data 5 # number of UpgradeReq hits
796system.cpu.l2cache.UpgradeReq_hits::total 5 # number of UpgradeReq hits
797system.cpu.l2cache.ReadExReq_hits::cpu.data 6 # number of ReadExReq hits
798system.cpu.l2cache.ReadExReq_hits::total 6 # number of ReadExReq hits
799system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4877 # number of ReadCleanReq hits
800system.cpu.l2cache.ReadCleanReq_hits::total 4877 # number of ReadCleanReq hits
801system.cpu.l2cache.ReadSharedReq_hits::cpu.data 68 # number of ReadSharedReq hits
802system.cpu.l2cache.ReadSharedReq_hits::total 68 # number of ReadSharedReq hits
803system.cpu.l2cache.demand_hits::cpu.inst 4877 # number of demand (read+write) hits
804system.cpu.l2cache.demand_hits::cpu.data 74 # number of demand (read+write) hits
805system.cpu.l2cache.demand_hits::total 4951 # number of demand (read+write) hits
806system.cpu.l2cache.overall_hits::cpu.inst 4877 # number of overall hits
807system.cpu.l2cache.overall_hits::cpu.data 74 # number of overall hits
808system.cpu.l2cache.overall_hits::total 4951 # number of overall hits
809system.cpu.l2cache.UpgradeReq_misses::cpu.data 500 # number of UpgradeReq misses
810system.cpu.l2cache.UpgradeReq_misses::total 500 # number of UpgradeReq misses
811system.cpu.l2cache.ReadExReq_misses::cpu.data 1507 # number of ReadExReq misses
812system.cpu.l2cache.ReadExReq_misses::total 1507 # number of ReadExReq misses
813system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3617 # number of ReadCleanReq misses
814system.cpu.l2cache.ReadCleanReq_misses::total 3617 # number of ReadCleanReq misses
815system.cpu.l2cache.ReadSharedReq_misses::cpu.data 532 # number of ReadSharedReq misses
816system.cpu.l2cache.ReadSharedReq_misses::total 532 # number of ReadSharedReq misses
817system.cpu.l2cache.demand_misses::cpu.inst 3617 # number of demand (read+write) misses
818system.cpu.l2cache.demand_misses::cpu.data 2039 # number of demand (read+write) misses
819system.cpu.l2cache.demand_misses::total 5656 # number of demand (read+write) misses
820system.cpu.l2cache.overall_misses::cpu.inst 3617 # number of overall misses
821system.cpu.l2cache.overall_misses::cpu.data 2039 # number of overall misses
822system.cpu.l2cache.overall_misses::total 5656 # number of overall misses
823system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 112056000 # number of ReadExReq miss cycles
824system.cpu.l2cache.ReadExReq_miss_latency::total 112056000 # number of ReadExReq miss cycles
825system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 275028000 # number of ReadCleanReq miss cycles
826system.cpu.l2cache.ReadCleanReq_miss_latency::total 275028000 # number of ReadCleanReq miss cycles
827system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 45953000 # number of ReadSharedReq miss cycles
828system.cpu.l2cache.ReadSharedReq_miss_latency::total 45953000 # number of ReadSharedReq miss cycles
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830system.cpu.l2cache.demand_miss_latency::cpu.data 158009000 # number of demand (read+write) miss cycles
831system.cpu.l2cache.demand_miss_latency::total 433037000 # number of demand (read+write) miss cycles
832system.cpu.l2cache.overall_miss_latency::cpu.inst 275028000 # number of overall miss cycles
833system.cpu.l2cache.overall_miss_latency::cpu.data 158009000 # number of overall miss cycles
834system.cpu.l2cache.overall_miss_latency::total 433037000 # number of overall miss cycles
835system.cpu.l2cache.WritebackDirty_accesses::writebacks 18 # number of WritebackDirty accesses(hits+misses)
836system.cpu.l2cache.WritebackDirty_accesses::total 18 # number of WritebackDirty accesses(hits+misses)
837system.cpu.l2cache.WritebackClean_accesses::writebacks 6469 # number of WritebackClean accesses(hits+misses)
838system.cpu.l2cache.WritebackClean_accesses::total 6469 # number of WritebackClean accesses(hits+misses)
839system.cpu.l2cache.UpgradeReq_accesses::cpu.data 505 # number of UpgradeReq accesses(hits+misses)
840system.cpu.l2cache.UpgradeReq_accesses::total 505 # number of UpgradeReq accesses(hits+misses)
841system.cpu.l2cache.ReadExReq_accesses::cpu.data 1513 # number of ReadExReq accesses(hits+misses)
842system.cpu.l2cache.ReadExReq_accesses::total 1513 # number of ReadExReq accesses(hits+misses)
843system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8494 # number of ReadCleanReq accesses(hits+misses)
844system.cpu.l2cache.ReadCleanReq_accesses::total 8494 # number of ReadCleanReq accesses(hits+misses)
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846system.cpu.l2cache.ReadSharedReq_accesses::total 600 # number of ReadSharedReq accesses(hits+misses)
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851system.cpu.l2cache.overall_accesses::cpu.data 2113 # number of overall (read+write) accesses
852system.cpu.l2cache.overall_accesses::total 10607 # number of overall (read+write) accesses
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854system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990099 # miss rate for UpgradeReq accesses
855system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996034 # miss rate for ReadExReq accesses
856system.cpu.l2cache.ReadExReq_miss_rate::total 0.996034 # miss rate for ReadExReq accesses
857system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.425830 # miss rate for ReadCleanReq accesses
858system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.425830 # miss rate for ReadCleanReq accesses
859system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.886667 # miss rate for ReadSharedReq accesses
860system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.886667 # miss rate for ReadSharedReq accesses
861system.cpu.l2cache.demand_miss_rate::cpu.inst 0.425830 # miss rate for demand accesses
862system.cpu.l2cache.demand_miss_rate::cpu.data 0.964979 # miss rate for demand accesses
863system.cpu.l2cache.demand_miss_rate::total 0.533233 # miss rate for demand accesses
864system.cpu.l2cache.overall_miss_rate::cpu.inst 0.425830 # miss rate for overall accesses
865system.cpu.l2cache.overall_miss_rate::cpu.data 0.964979 # miss rate for overall accesses
866system.cpu.l2cache.overall_miss_rate::total 0.533233 # miss rate for overall accesses
867system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74357.000664 # average ReadExReq miss latency
868system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74357.000664 # average ReadExReq miss latency
869system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76037.600221 # average ReadCleanReq miss latency
870system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76037.600221 # average ReadCleanReq miss latency
871system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86377.819549 # average ReadSharedReq miss latency
872system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86377.819549 # average ReadSharedReq miss latency
873system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76037.600221 # average overall miss latency
874system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77493.379107 # average overall miss latency
875system.cpu.l2cache.demand_avg_miss_latency::total 76562.411598 # average overall miss latency
876system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76037.600221 # average overall miss latency
877system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77493.379107 # average overall miss latency
878system.cpu.l2cache.overall_avg_miss_latency::total 76562.411598 # average overall miss latency
879system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
880system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
881system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
882system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
883system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
884system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
885system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 500 # number of UpgradeReq MSHR misses
886system.cpu.l2cache.UpgradeReq_mshr_misses::total 500 # number of UpgradeReq MSHR misses
887system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1507 # number of ReadExReq MSHR misses
888system.cpu.l2cache.ReadExReq_mshr_misses::total 1507 # number of ReadExReq MSHR misses
889system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3617 # number of ReadCleanReq MSHR misses
890system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3617 # number of ReadCleanReq MSHR misses
891system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 532 # number of ReadSharedReq MSHR misses
892system.cpu.l2cache.ReadSharedReq_mshr_misses::total 532 # number of ReadSharedReq MSHR misses
893system.cpu.l2cache.demand_mshr_misses::cpu.inst 3617 # number of demand (read+write) MSHR misses
894system.cpu.l2cache.demand_mshr_misses::cpu.data 2039 # number of demand (read+write) MSHR misses
895system.cpu.l2cache.demand_mshr_misses::total 5656 # number of demand (read+write) MSHR misses
896system.cpu.l2cache.overall_mshr_misses::cpu.inst 3617 # number of overall MSHR misses
897system.cpu.l2cache.overall_mshr_misses::cpu.data 2039 # number of overall MSHR misses
898system.cpu.l2cache.overall_mshr_misses::total 5656 # number of overall MSHR misses
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900system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 9503500 # number of UpgradeReq MSHR miss cycles
901system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 96986000 # number of ReadExReq MSHR miss cycles
902system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 96986000 # number of ReadExReq MSHR miss cycles
903system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 238858000 # number of ReadCleanReq MSHR miss cycles
904system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 238858000 # number of ReadCleanReq MSHR miss cycles
905system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 40633000 # number of ReadSharedReq MSHR miss cycles
906system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 40633000 # number of ReadSharedReq MSHR miss cycles
907system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 238858000 # number of demand (read+write) MSHR miss cycles
908system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137619000 # number of demand (read+write) MSHR miss cycles
909system.cpu.l2cache.demand_mshr_miss_latency::total 376477000 # number of demand (read+write) MSHR miss cycles
910system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 238858000 # number of overall MSHR miss cycles
911system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137619000 # number of overall MSHR miss cycles
912system.cpu.l2cache.overall_mshr_miss_latency::total 376477000 # number of overall MSHR miss cycles
913system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990099 # mshr miss rate for UpgradeReq accesses
914system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990099 # mshr miss rate for UpgradeReq accesses
915system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996034 # mshr miss rate for ReadExReq accesses
916system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996034 # mshr miss rate for ReadExReq accesses
917system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.425830 # mshr miss rate for ReadCleanReq accesses
918system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.425830 # mshr miss rate for ReadCleanReq accesses
919system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.886667 # mshr miss rate for ReadSharedReq accesses
920system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.886667 # mshr miss rate for ReadSharedReq accesses
921system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.425830 # mshr miss rate for demand accesses
922system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964979 # mshr miss rate for demand accesses
923system.cpu.l2cache.demand_mshr_miss_rate::total 0.533233 # mshr miss rate for demand accesses
924system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.425830 # mshr miss rate for overall accesses
925system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964979 # mshr miss rate for overall accesses
926system.cpu.l2cache.overall_mshr_miss_rate::total 0.533233 # mshr miss rate for overall accesses
927system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19007 # average UpgradeReq mshr miss latency
928system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19007 # average UpgradeReq mshr miss latency
929system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64357.000664 # average ReadExReq mshr miss latency
930system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64357.000664 # average ReadExReq mshr miss latency
931system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66037.600221 # average ReadCleanReq mshr miss latency
932system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66037.600221 # average ReadCleanReq mshr miss latency
933system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76377.819549 # average ReadSharedReq mshr miss latency
934system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76377.819549 # average ReadSharedReq mshr miss latency
935system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66037.600221 # average overall mshr miss latency
936system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67493.379107 # average overall mshr miss latency
937system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66562.411598 # average overall mshr miss latency
938system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66037.600221 # average overall mshr miss latency
939system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67493.379107 # average overall mshr miss latency
940system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66562.411598 # average overall mshr miss latency
941system.cpu.toL2Bus.snoop_filter.tot_requests 18206 # Total number of requests made to the snoop filter.
942system.cpu.toL2Bus.snoop_filter.hit_single_requests 7138 # Number of requests hitting in the snoop filter with a single holder of the requested data.
943system.cpu.toL2Bus.snoop_filter.hit_multi_requests 549 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
944system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
945system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
946system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
947system.cpu.toL2Bus.trans_dist::ReadResp 9600 # Transaction distribution
948system.cpu.toL2Bus.trans_dist::WritebackDirty 18 # Transaction distribution
949system.cpu.toL2Bus.trans_dist::WritebackClean 6515 # Transaction distribution
950system.cpu.toL2Bus.trans_dist::CleanEvict 54 # Transaction distribution
951system.cpu.toL2Bus.trans_dist::UpgradeReq 505 # Transaction distribution
952system.cpu.toL2Bus.trans_dist::UpgradeResp 505 # Transaction distribution
953system.cpu.toL2Bus.trans_dist::ReadExReq 1513 # Transaction distribution
954system.cpu.toL2Bus.trans_dist::ReadExResp 1513 # Transaction distribution
955system.cpu.toL2Bus.trans_dist::ReadCleanReq 9001 # Transaction distribution
956system.cpu.toL2Bus.trans_dist::ReadSharedReq 600 # Transaction distribution
957system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24009 # Packet count per connected master and slave (bytes)
958system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5308 # Packet count per connected master and slave (bytes)
959system.cpu.toL2Bus.pkt_count::total 29317 # Packet count per connected master and slave (bytes)
960system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 960512 # Cumulative packet size per connected master and slave (bytes)
961system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 136384 # Cumulative packet size per connected master and slave (bytes)
962system.cpu.toL2Bus.pkt_size::total 1096896 # Cumulative packet size per connected master and slave (bytes)
963system.cpu.toL2Bus.snoops 507 # Total snoops (count)
964system.cpu.toL2Bus.snoop_fanout::samples 11619 # Request fanout histogram
965system.cpu.toL2Bus.snoop_fanout::mean 0.094328 # Request fanout histogram
966system.cpu.toL2Bus.snoop_fanout::stdev 0.292297 # Request fanout histogram
967system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
968system.cpu.toL2Bus.snoop_fanout::0 10523 90.57% 90.57% # Request fanout histogram
969system.cpu.toL2Bus.snoop_fanout::1 1096 9.43% 100.00% # Request fanout histogram
970system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
971system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
972system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
973system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
974system.cpu.toL2Bus.snoop_fanout::total 11619 # Request fanout histogram
975system.cpu.toL2Bus.reqLayer0.occupancy 15636499 # Layer occupancy (ticks)
976system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
977system.cpu.toL2Bus.respLayer0.occupancy 13500000 # Layer occupancy (ticks)
978system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
979system.cpu.toL2Bus.respLayer1.occupancy 3422499 # Layer occupancy (ticks)
980system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
981system.membus.trans_dist::ReadResp 4149 # Transaction distribution
982system.membus.trans_dist::UpgradeReq 500 # Transaction distribution
983system.membus.trans_dist::ReadExReq 1507 # Transaction distribution
984system.membus.trans_dist::ReadExResp 1507 # Transaction distribution
985system.membus.trans_dist::ReadSharedReq 4149 # Transaction distribution
986system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11812 # Packet count per connected master and slave (bytes)
987system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11812 # Packet count per connected master and slave (bytes)
988system.membus.pkt_count::total 11812 # Packet count per connected master and slave (bytes)
989system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 361984 # Cumulative packet size per connected master and slave (bytes)
990system.membus.pkt_size_system.cpu.l2cache.mem_side::total 361984 # Cumulative packet size per connected master and slave (bytes)
991system.membus.pkt_size::total 361984 # Cumulative packet size per connected master and slave (bytes)
992system.membus.snoops 0 # Total snoops (count)
993system.membus.snoop_fanout::samples 6156 # Request fanout histogram
994system.membus.snoop_fanout::mean 0 # Request fanout histogram
995system.membus.snoop_fanout::stdev 0 # Request fanout histogram
996system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
997system.membus.snoop_fanout::0 6156 100.00% 100.00% # Request fanout histogram
998system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
999system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1000system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1001system.membus.snoop_fanout::max_value 0 # Request fanout histogram
1002system.membus.snoop_fanout::total 6156 # Request fanout histogram
1003system.membus.reqLayer0.occupancy 7649501 # Layer occupancy (ticks)
1004system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1005system.membus.respLayer1.occupancy 30011250 # Layer occupancy (ticks)
1006system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
1007
1008---------- End Simulation Statistics ----------