| stats.txt (11441:0edcf757b6a2) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.103324 # Number of seconds simulated 4sim_ticks 103324153500 # Number of ticks simulated 5final_tick 103324153500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.103324 # Number of seconds simulated 4sim_ticks 103324153500 # Number of ticks simulated 5final_tick 103324153500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 72241 # Simulator instruction rate (inst/s) 8host_op_rate 121082 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 56516511 # Simulator tick rate (ticks/s) 10host_mem_usage 307592 # Number of bytes of host memory used 11host_seconds 1828.21 # Real time elapsed on the host | 7host_inst_rate 75581 # Simulator instruction rate (inst/s) 8host_op_rate 126680 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 59129521 # Simulator tick rate (ticks/s) 10host_mem_usage 307596 # Number of bytes of host memory used 11host_seconds 1747.42 # Real time elapsed on the host |
| 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221363384 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 231488 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 130496 # Number of bytes read from this memory 18system.physmem.bytes_read::total 361984 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 231488 # Number of instructions bytes read from this memory --- 607 unchanged lines hidden (view full) --- 627system.cpu.dcache.overall_avg_miss_latency::cpu.data 65798.691418 # average overall miss latency 628system.cpu.dcache.overall_avg_miss_latency::total 65798.691418 # average overall miss latency 629system.cpu.dcache.blocked_cycles::no_mshrs 369 # number of cycles access was blocked 630system.cpu.dcache.blocked_cycles::no_targets 73 # number of cycles access was blocked 631system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked 632system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked 633system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.125000 # average number of cycles each access was blocked 634system.cpu.dcache.avg_blocked_cycles::no_targets 36.500000 # average number of cycles each access was blocked | 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221363384 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 231488 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 130496 # Number of bytes read from this memory 18system.physmem.bytes_read::total 361984 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 231488 # Number of instructions bytes read from this memory --- 607 unchanged lines hidden (view full) --- 627system.cpu.dcache.overall_avg_miss_latency::cpu.data 65798.691418 # average overall miss latency 628system.cpu.dcache.overall_avg_miss_latency::total 65798.691418 # average overall miss latency 629system.cpu.dcache.blocked_cycles::no_mshrs 369 # number of cycles access was blocked 630system.cpu.dcache.blocked_cycles::no_targets 73 # number of cycles access was blocked 631system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked 632system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked 633system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.125000 # average number of cycles each access was blocked 634system.cpu.dcache.avg_blocked_cycles::no_targets 36.500000 # average number of cycles each access was blocked |
| 635system.cpu.dcache.fast_writes 0 # number of fast writes performed 636system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 637system.cpu.dcache.writebacks::writebacks 18 # number of writebacks 638system.cpu.dcache.writebacks::total 18 # number of writebacks 639system.cpu.dcache.ReadReq_mshr_hits::cpu.data 661 # number of ReadReq MSHR hits 640system.cpu.dcache.ReadReq_mshr_hits::total 661 # number of ReadReq MSHR hits 641system.cpu.dcache.WriteReq_mshr_hits::cpu.data 7 # number of WriteReq MSHR hits 642system.cpu.dcache.WriteReq_mshr_hits::total 7 # number of WriteReq MSHR hits 643system.cpu.dcache.demand_mshr_hits::cpu.data 668 # number of demand (read+write) MSHR hits 644system.cpu.dcache.demand_mshr_hits::total 668 # number of demand (read+write) MSHR hits --- 26 unchanged lines hidden (view full) --- 671system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79384.359401 # average ReadReq mshr miss latency 672system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79384.359401 # average ReadReq mshr miss latency 673system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64271.938523 # average WriteReq mshr miss latency 674system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64271.938523 # average WriteReq mshr miss latency 675system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67741.214668 # average overall mshr miss latency 676system.cpu.dcache.demand_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency 677system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67741.214668 # average overall mshr miss latency 678system.cpu.dcache.overall_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency | 635system.cpu.dcache.writebacks::writebacks 18 # number of writebacks 636system.cpu.dcache.writebacks::total 18 # number of writebacks 637system.cpu.dcache.ReadReq_mshr_hits::cpu.data 661 # number of ReadReq MSHR hits 638system.cpu.dcache.ReadReq_mshr_hits::total 661 # number of ReadReq MSHR hits 639system.cpu.dcache.WriteReq_mshr_hits::cpu.data 7 # number of WriteReq MSHR hits 640system.cpu.dcache.WriteReq_mshr_hits::total 7 # number of WriteReq MSHR hits 641system.cpu.dcache.demand_mshr_hits::cpu.data 668 # number of demand (read+write) MSHR hits 642system.cpu.dcache.demand_mshr_hits::total 668 # number of demand (read+write) MSHR hits --- 26 unchanged lines hidden (view full) --- 669system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79384.359401 # average ReadReq mshr miss latency 670system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79384.359401 # average ReadReq mshr miss latency 671system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64271.938523 # average WriteReq mshr miss latency 672system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64271.938523 # average WriteReq mshr miss latency 673system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67741.214668 # average overall mshr miss latency 674system.cpu.dcache.demand_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency 675system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67741.214668 # average overall mshr miss latency 676system.cpu.dcache.overall_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency |
| 679system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 680system.cpu.icache.tags.replacements 6515 # number of replacements 681system.cpu.icache.tags.tagsinuse 1663.291735 # Cycle average of tags in use 682system.cpu.icache.tags.total_refs 41248897 # Total number of references to valid blocks. 683system.cpu.icache.tags.sampled_refs 8499 # Sample count of references to valid blocks. 684system.cpu.icache.tags.avg_refs 4853.382398 # Average number of references to valid blocks. 685system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 686system.cpu.icache.tags.occ_blocks::cpu.inst 1663.291735 # Average occupied blocks per requestor 687system.cpu.icache.tags.occ_percent::cpu.inst 0.812154 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 732system.cpu.icache.overall_avg_miss_latency::cpu.inst 37114.447246 # average overall miss latency 733system.cpu.icache.overall_avg_miss_latency::total 37114.447246 # average overall miss latency 734system.cpu.icache.blocked_cycles::no_mshrs 2090 # number of cycles access was blocked 735system.cpu.icache.blocked_cycles::no_targets 305 # number of cycles access was blocked 736system.cpu.icache.blocked::no_mshrs 30 # number of cycles access was blocked 737system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 738system.cpu.icache.avg_blocked_cycles::no_mshrs 69.666667 # average number of cycles each access was blocked 739system.cpu.icache.avg_blocked_cycles::no_targets 305 # average number of cycles each access was blocked | 677system.cpu.icache.tags.replacements 6515 # number of replacements 678system.cpu.icache.tags.tagsinuse 1663.291735 # Cycle average of tags in use 679system.cpu.icache.tags.total_refs 41248897 # Total number of references to valid blocks. 680system.cpu.icache.tags.sampled_refs 8499 # Sample count of references to valid blocks. 681system.cpu.icache.tags.avg_refs 4853.382398 # Average number of references to valid blocks. 682system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 683system.cpu.icache.tags.occ_blocks::cpu.inst 1663.291735 # Average occupied blocks per requestor 684system.cpu.icache.tags.occ_percent::cpu.inst 0.812154 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 729system.cpu.icache.overall_avg_miss_latency::cpu.inst 37114.447246 # average overall miss latency 730system.cpu.icache.overall_avg_miss_latency::total 37114.447246 # average overall miss latency 731system.cpu.icache.blocked_cycles::no_mshrs 2090 # number of cycles access was blocked 732system.cpu.icache.blocked_cycles::no_targets 305 # number of cycles access was blocked 733system.cpu.icache.blocked::no_mshrs 30 # number of cycles access was blocked 734system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 735system.cpu.icache.avg_blocked_cycles::no_mshrs 69.666667 # average number of cycles each access was blocked 736system.cpu.icache.avg_blocked_cycles::no_targets 305 # average number of cycles each access was blocked |
| 740system.cpu.icache.fast_writes 0 # number of fast writes performed 741system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 742system.cpu.icache.writebacks::writebacks 6515 # number of writebacks 743system.cpu.icache.writebacks::total 6515 # number of writebacks 744system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4088 # number of ReadReq MSHR hits 745system.cpu.icache.ReadReq_mshr_hits::total 4088 # number of ReadReq MSHR hits 746system.cpu.icache.demand_mshr_hits::cpu.inst 4088 # number of demand (read+write) MSHR hits 747system.cpu.icache.demand_mshr_hits::total 4088 # number of demand (read+write) MSHR hits 748system.cpu.icache.overall_mshr_hits::cpu.inst 4088 # number of overall MSHR hits 749system.cpu.icache.overall_mshr_hits::total 4088 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 766system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for overall accesses 767system.cpu.icache.overall_mshr_miss_rate::total 0.000218 # mshr miss rate for overall accesses 768system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37852.238640 # average ReadReq mshr miss latency 769system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37852.238640 # average ReadReq mshr miss latency 770system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37852.238640 # average overall mshr miss latency 771system.cpu.icache.demand_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency 772system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37852.238640 # average overall mshr miss latency 773system.cpu.icache.overall_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency | 737system.cpu.icache.writebacks::writebacks 6515 # number of writebacks 738system.cpu.icache.writebacks::total 6515 # number of writebacks 739system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4088 # number of ReadReq MSHR hits 740system.cpu.icache.ReadReq_mshr_hits::total 4088 # number of ReadReq MSHR hits 741system.cpu.icache.demand_mshr_hits::cpu.inst 4088 # number of demand (read+write) MSHR hits 742system.cpu.icache.demand_mshr_hits::total 4088 # number of demand (read+write) MSHR hits 743system.cpu.icache.overall_mshr_hits::cpu.inst 4088 # number of overall MSHR hits 744system.cpu.icache.overall_mshr_hits::total 4088 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 761system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for overall accesses 762system.cpu.icache.overall_mshr_miss_rate::total 0.000218 # mshr miss rate for overall accesses 763system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37852.238640 # average ReadReq mshr miss latency 764system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37852.238640 # average ReadReq mshr miss latency 765system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37852.238640 # average overall mshr miss latency 766system.cpu.icache.demand_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency 767system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37852.238640 # average overall mshr miss latency 768system.cpu.icache.overall_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency |
| 774system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 775system.cpu.l2cache.tags.replacements 0 # number of replacements 776system.cpu.l2cache.tags.tagsinuse 2796.844278 # Cycle average of tags in use 777system.cpu.l2cache.tags.total_refs 11471 # Total number of references to valid blocks. 778system.cpu.l2cache.tags.sampled_refs 4155 # Sample count of references to valid blocks. 779system.cpu.l2cache.tags.avg_refs 2.760770 # Average number of references to valid blocks. 780system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 781system.cpu.l2cache.tags.occ_blocks::writebacks 4.971138 # Average occupied blocks per requestor 782system.cpu.l2cache.tags.occ_blocks::cpu.inst 2402.103394 # Average occupied blocks per requestor --- 100 unchanged lines hidden (view full) --- 883system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77493.379107 # average overall miss latency 884system.cpu.l2cache.overall_avg_miss_latency::total 76562.411598 # average overall miss latency 885system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 886system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 887system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 888system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 889system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 890system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 769system.cpu.l2cache.tags.replacements 0 # number of replacements 770system.cpu.l2cache.tags.tagsinuse 2796.844278 # Cycle average of tags in use 771system.cpu.l2cache.tags.total_refs 11471 # Total number of references to valid blocks. 772system.cpu.l2cache.tags.sampled_refs 4155 # Sample count of references to valid blocks. 773system.cpu.l2cache.tags.avg_refs 2.760770 # Average number of references to valid blocks. 774system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 775system.cpu.l2cache.tags.occ_blocks::writebacks 4.971138 # Average occupied blocks per requestor 776system.cpu.l2cache.tags.occ_blocks::cpu.inst 2402.103394 # Average occupied blocks per requestor --- 100 unchanged lines hidden (view full) --- 877system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77493.379107 # average overall miss latency 878system.cpu.l2cache.overall_avg_miss_latency::total 76562.411598 # average overall miss latency 879system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 880system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 881system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 882system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 883system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 884system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 891system.cpu.l2cache.fast_writes 0 # number of fast writes performed 892system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 893system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 500 # number of UpgradeReq MSHR misses 894system.cpu.l2cache.UpgradeReq_mshr_misses::total 500 # number of UpgradeReq MSHR misses 895system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1507 # number of ReadExReq MSHR misses 896system.cpu.l2cache.ReadExReq_mshr_misses::total 1507 # number of ReadExReq MSHR misses 897system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3617 # number of ReadCleanReq MSHR misses 898system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3617 # number of ReadCleanReq MSHR misses 899system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 532 # number of ReadSharedReq MSHR misses 900system.cpu.l2cache.ReadSharedReq_mshr_misses::total 532 # number of ReadSharedReq MSHR misses --- 40 unchanged lines hidden (view full) --- 941system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76377.819549 # average ReadSharedReq mshr miss latency 942system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76377.819549 # average ReadSharedReq mshr miss latency 943system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66037.600221 # average overall mshr miss latency 944system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67493.379107 # average overall mshr miss latency 945system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66562.411598 # average overall mshr miss latency 946system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66037.600221 # average overall mshr miss latency 947system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67493.379107 # average overall mshr miss latency 948system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66562.411598 # average overall mshr miss latency | 885system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 500 # number of UpgradeReq MSHR misses 886system.cpu.l2cache.UpgradeReq_mshr_misses::total 500 # number of UpgradeReq MSHR misses 887system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1507 # number of ReadExReq MSHR misses 888system.cpu.l2cache.ReadExReq_mshr_misses::total 1507 # number of ReadExReq MSHR misses 889system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3617 # number of ReadCleanReq MSHR misses 890system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3617 # number of ReadCleanReq MSHR misses 891system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 532 # number of ReadSharedReq MSHR misses 892system.cpu.l2cache.ReadSharedReq_mshr_misses::total 532 # number of ReadSharedReq MSHR misses --- 40 unchanged lines hidden (view full) --- 933system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76377.819549 # average ReadSharedReq mshr miss latency 934system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76377.819549 # average ReadSharedReq mshr miss latency 935system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66037.600221 # average overall mshr miss latency 936system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67493.379107 # average overall mshr miss latency 937system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66562.411598 # average overall mshr miss latency 938system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66037.600221 # average overall mshr miss latency 939system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67493.379107 # average overall mshr miss latency 940system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66562.411598 # average overall mshr miss latency |
| 949system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 950system.cpu.toL2Bus.snoop_filter.tot_requests 18206 # Total number of requests made to the snoop filter. 951system.cpu.toL2Bus.snoop_filter.hit_single_requests 7138 # Number of requests hitting in the snoop filter with a single holder of the requested data. 952system.cpu.toL2Bus.snoop_filter.hit_multi_requests 549 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 953system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 954system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 955system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 956system.cpu.toL2Bus.trans_dist::ReadResp 9600 # Transaction distribution 957system.cpu.toL2Bus.trans_dist::WritebackDirty 18 # Transaction distribution --- 60 unchanged lines hidden --- | 941system.cpu.toL2Bus.snoop_filter.tot_requests 18206 # Total number of requests made to the snoop filter. 942system.cpu.toL2Bus.snoop_filter.hit_single_requests 7138 # Number of requests hitting in the snoop filter with a single holder of the requested data. 943system.cpu.toL2Bus.snoop_filter.hit_multi_requests 549 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 944system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 945system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 946system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 947system.cpu.toL2Bus.trans_dist::ReadResp 9600 # Transaction distribution 948system.cpu.toL2Bus.trans_dist::WritebackDirty 18 # Transaction distribution --- 60 unchanged lines hidden --- |