| stats.txt (11214:966091379ded) | stats.txt (11336:b318499f676c) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.079230 # Number of seconds simulated 4sim_ticks 79229645000 # Number of ticks simulated 5final_tick 79229645000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.079141 # Number of seconds simulated 4sim_ticks 79140979500 # Number of ticks simulated 5final_tick 79140979500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 90742 # Simulator instruction rate (inst/s) 8host_op_rate 152092 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 54436376 # Simulator tick rate (ticks/s) 10host_mem_usage 350016 # Number of bytes of host memory used 11host_seconds 1455.45 # Real time elapsed on the host | 7host_inst_rate 91812 # Simulator instruction rate (inst/s) 8host_op_rate 153885 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 55016334 # Simulator tick rate (ticks/s) 10host_mem_usage 351180 # Number of bytes of host memory used 11host_seconds 1438.50 # Real time elapsed on the host |
| 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221363384 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221363384 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 220992 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 124928 # Number of bytes read from this memory 18system.physmem.bytes_read::total 345920 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 220992 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 220992 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 3453 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1952 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 5405 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 2789259 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 1576784 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 4366043 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 2789259 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 2789259 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 2789259 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 1576784 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 4366043 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 5405 # Number of read requests accepted | 16system.physmem.bytes_read::cpu.inst 221376 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 125056 # Number of bytes read from this memory 18system.physmem.bytes_read::total 346432 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 221376 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 221376 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 3459 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1954 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 5413 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 2797236 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 1580167 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 4377403 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 2797236 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 2797236 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 2797236 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 1580167 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 4377403 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 5413 # Number of read requests accepted |
| 33system.physmem.writeReqs 0 # Number of write requests accepted | 33system.physmem.writeReqs 0 # Number of write requests accepted |
| 34system.physmem.readBursts 5405 # Number of DRAM read bursts, including those serviced by the write queue | 34system.physmem.readBursts 5413 # Number of DRAM read bursts, including those serviced by the write queue |
| 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 36system.physmem.bytesReadDRAM 345920 # Total number of bytes read from DRAM | 36system.physmem.bytesReadDRAM 346432 # Total number of bytes read from DRAM |
| 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 39system.physmem.bytesReadSys 345920 # Total read bytes from the system interface side | 39system.physmem.bytesReadSys 346432 # Total read bytes from the system interface side |
| 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one | 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| 43system.physmem.neitherReadNorWriteReqs 261 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 295 # Per bank write bursts 45system.physmem.perBankRdBursts::1 347 # Per bank write bursts 46system.physmem.perBankRdBursts::2 460 # Per bank write bursts 47system.physmem.perBankRdBursts::3 350 # Per bank write bursts 48system.physmem.perBankRdBursts::4 341 # Per bank write bursts 49system.physmem.perBankRdBursts::5 328 # Per bank write bursts | 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 298 # Per bank write bursts 45system.physmem.perBankRdBursts::1 346 # Per bank write bursts 46system.physmem.perBankRdBursts::2 461 # Per bank write bursts 47system.physmem.perBankRdBursts::3 349 # Per bank write bursts 48system.physmem.perBankRdBursts::4 340 # Per bank write bursts 49system.physmem.perBankRdBursts::5 326 # Per bank write bursts |
| 50system.physmem.perBankRdBursts::6 402 # Per bank write bursts | 50system.physmem.perBankRdBursts::6 402 # Per bank write bursts |
| 51system.physmem.perBankRdBursts::7 383 # Per bank write bursts 52system.physmem.perBankRdBursts::8 339 # Per bank write bursts | 51system.physmem.perBankRdBursts::7 384 # Per bank write bursts 52system.physmem.perBankRdBursts::8 341 # Per bank write bursts |
| 53system.physmem.perBankRdBursts::9 281 # Per bank write bursts | 53system.physmem.perBankRdBursts::9 281 # Per bank write bursts |
| 54system.physmem.perBankRdBursts::10 240 # Per bank write bursts 55system.physmem.perBankRdBursts::11 284 # Per bank write bursts 56system.physmem.perBankRdBursts::12 217 # Per bank write bursts 57system.physmem.perBankRdBursts::13 468 # Per bank write bursts 58system.physmem.perBankRdBursts::14 388 # Per bank write bursts 59system.physmem.perBankRdBursts::15 282 # Per bank write bursts | 54system.physmem.perBankRdBursts::10 239 # Per bank write bursts 55system.physmem.perBankRdBursts::11 285 # Per bank write bursts 56system.physmem.perBankRdBursts::12 220 # Per bank write bursts 57system.physmem.perBankRdBursts::13 466 # Per bank write bursts 58system.physmem.perBankRdBursts::14 389 # Per bank write bursts 59system.physmem.perBankRdBursts::15 286 # Per bank write bursts |
| 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 79229612500 # Total gap between requests | 78system.physmem.totGap 79140890500 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 85system.physmem.readPktSize::6 5405 # Read request sizes (log2) | 85system.physmem.readPktSize::6 5413 # Read request sizes (log2) |
| 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) | 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 93system.physmem.rdQLenPdf::0 4295 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 899 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 178 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 28 # What read queue length does an incoming req see | 93system.physmem.rdQLenPdf::0 4301 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 904 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 176 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see |
| 97system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 76 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 97system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 76 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 189system.physmem.bytesPerActivate::samples 1099 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 313.361237 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 181.828976 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 329.670559 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 436 39.67% 39.67% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 230 20.93% 60.60% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 99 9.01% 69.61% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 58 5.28% 74.89% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 55 5.00% 79.89% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 56 5.10% 84.99% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 23 2.09% 87.08% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 18 1.64% 88.72% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 124 11.28% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 1099 # Bytes accessed per row activation 203system.physmem.totQLat 41940250 # Total ticks spent queuing 204system.physmem.totMemAccLat 143284000 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 27025000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 7759.53 # Average queueing delay per DRAM burst | 189system.physmem.bytesPerActivate::samples 1107 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 311.790425 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 180.924163 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 329.273428 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 441 39.84% 39.84% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 229 20.69% 60.52% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 106 9.58% 70.10% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 59 5.33% 75.43% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 51 4.61% 80.04% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 54 4.88% 84.91% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 23 2.08% 86.99% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 18 1.63% 88.62% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 126 11.38% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 1107 # Bytes accessed per row activation 203system.physmem.totQLat 40702000 # Total ticks spent queuing 204system.physmem.totMemAccLat 142195750 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 27065000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 7519.31 # Average queueing delay per DRAM burst |
| 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 208system.physmem.avgMemAccLat 26509.53 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 4.37 # Average DRAM read bandwidth in MiByte/s | 208system.physmem.avgMemAccLat 26269.31 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 4.38 # Average DRAM read bandwidth in MiByte/s |
| 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 211system.physmem.avgRdBWSys 4.37 # Average system read bandwidth in MiByte/s | 211system.physmem.avgRdBWSys 4.38 # Average system read bandwidth in MiByte/s |
| 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.03 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.03 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 217system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing | 217system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing |
| 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 219system.physmem.readRowHits 4297 # Number of row buffer hits during reads | 219system.physmem.readRowHits 4302 # Number of row buffer hits during reads |
| 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 221system.physmem.readRowHitRate 79.50 # Row buffer hit rate for reads | 221system.physmem.readRowHitRate 79.48 # Row buffer hit rate for reads |
| 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 223system.physmem.avgGap 14658577.71 # Average gap between requests 224system.physmem.pageHitRate 79.50 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 4906440 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 2677125 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 22526400 # Energy for read commands per rank (pJ) | 223system.physmem.avgGap 14620522.91 # Average gap between requests 224system.physmem.pageHitRate 79.48 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 4898880 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 2673000 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 22659000 # Energy for read commands per rank (pJ) |
| 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) | 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 229system.physmem_0.refreshEnergy 5174598000 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 2444474070 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 45390936750 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 53040118785 # Total energy per rank (pJ) 233system.physmem_0.averagePower 669.484152 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 75508317500 # Time in different power states 235system.physmem_0.memoryStateTime::REF 2645500000 # Time in different power states | 229system.physmem_0.refreshEnergy 5169003840 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 2477527515 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 45310553250 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 52987315485 # Total energy per rank (pJ) 233system.physmem_0.averagePower 669.541483 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 75375284500 # Time in different power states 235system.physmem_0.memoryStateTime::REF 2642640000 # Time in different power states |
| 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 237system.physmem_0.memoryStateTime::ACT 1071550000 # Time in different power states | 237system.physmem_0.memoryStateTime::ACT 1122707500 # Time in different power states |
| 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 239system.physmem_1.actEnergy 3386880 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 1848000 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 19312800 # Energy for read commands per rank (pJ) | 239system.physmem_1.actEnergy 3470040 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 1893375 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 19406400 # Energy for read commands per rank (pJ) |
| 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) | 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 243system.physmem_1.refreshEnergy 5174598000 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 2297025045 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 45520269750 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 53016440475 # Total energy per rank (pJ) 247system.physmem_1.averagePower 669.185395 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 75726888000 # Time in different power states 249system.physmem_1.memoryStateTime::REF 2645500000 # Time in different power states | 243system.physmem_1.refreshEnergy 5169003840 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 2315256210 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 45452899500 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 52961929365 # Total energy per rank (pJ) 247system.physmem_1.averagePower 669.220665 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 75612477000 # Time in different power states 249system.physmem_1.memoryStateTime::REF 2642640000 # Time in different power states |
| 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 251system.physmem_1.memoryStateTime::ACT 855243500 # Time in different power states | 251system.physmem_1.memoryStateTime::ACT 884606250 # Time in different power states |
| 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 253system.cpu.branchPred.lookups 20592907 # Number of BP lookups 254system.cpu.branchPred.condPredicted 20592907 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 1327799 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 12698364 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 12013605 # Number of BTB hits | 253system.cpu.branchPred.lookups 20604097 # Number of BP lookups 254system.cpu.branchPred.condPredicted 20604097 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 1328804 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 12707128 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 12016947 # Number of BTB hits |
| 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 259system.cpu.branchPred.BTBHitPct 94.607502 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 1441126 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 16761 # Number of incorrect RAS predictions. | 259system.cpu.branchPred.BTBHitPct 94.568552 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 1442846 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 16873 # Number of incorrect RAS predictions. |
| 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 264system.cpu.workload.num_syscalls 400 # Number of system calls | 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 264system.cpu.workload.num_syscalls 400 # Number of system calls |
| 265system.cpu.numCycles 158459291 # number of cpu cycles simulated | 265system.cpu.numCycles 158281960 # number of cpu cycles simulated |
| 266system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 267system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 266system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 267system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 268system.cpu.fetch.icacheStallCycles 25251668 # Number of cycles fetch is stalled on an Icache miss 269system.cpu.fetch.Insts 227436303 # Number of instructions fetch has processed 270system.cpu.fetch.Branches 20592907 # Number of branches that fetch encountered 271system.cpu.fetch.predictedBranches 13454731 # Number of branches that fetch has predicted taken 272system.cpu.fetch.Cycles 131379126 # Number of cycles fetch has run and was not squashing or blocked 273system.cpu.fetch.SquashCycles 3193881 # Number of cycles fetch has spent squashing 274system.cpu.fetch.TlbCycles 1 # Number of cycles fetch has spent waiting for tlb 275system.cpu.fetch.MiscStallCycles 2041 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 276system.cpu.fetch.PendingTrapStallCycles 21671 # Number of stall cycles due to pending traps | 268system.cpu.fetch.icacheStallCycles 25261186 # Number of cycles fetch is stalled on an Icache miss 269system.cpu.fetch.Insts 227540230 # Number of instructions fetch has processed 270system.cpu.fetch.Branches 20604097 # Number of branches that fetch encountered 271system.cpu.fetch.predictedBranches 13459793 # Number of branches that fetch has predicted taken 272system.cpu.fetch.Cycles 131194120 # Number of cycles fetch has run and was not squashing or blocked 273system.cpu.fetch.SquashCycles 3196201 # Number of cycles fetch has spent squashing 274system.cpu.fetch.TlbCycles 20 # Number of cycles fetch has spent waiting for tlb 275system.cpu.fetch.MiscStallCycles 1974 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 276system.cpu.fetch.PendingTrapStallCycles 21216 # Number of stall cycles due to pending traps |
| 277system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions 278system.cpu.fetch.IcacheWaitRetryStallCycles 47 # Number of stall cycles due to full MSHR | 277system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions 278system.cpu.fetch.IcacheWaitRetryStallCycles 47 # Number of stall cycles due to full MSHR |
| 279system.cpu.fetch.CacheLines 24259483 # Number of cache lines fetched 280system.cpu.fetch.IcacheSquashes 266288 # Number of outstanding Icache misses that were squashed 281system.cpu.fetch.rateDist::samples 158251507 # Number of instructions fetched each cycle (Total) 282system.cpu.fetch.rateDist::mean 2.376692 # Number of instructions fetched each cycle (Total) 283system.cpu.fetch.rateDist::stdev 3.323734 # Number of instructions fetched each cycle (Total) | 279system.cpu.fetch.CacheLines 24267792 # Number of cache lines fetched 280system.cpu.fetch.IcacheSquashes 266999 # Number of outstanding Icache misses that were squashed 281system.cpu.fetch.rateDist::samples 158076676 # Number of instructions fetched each cycle (Total) 282system.cpu.fetch.rateDist::mean 2.380152 # Number of instructions fetched each cycle (Total) 283system.cpu.fetch.rateDist::stdev 3.324972 # Number of instructions fetched each cycle (Total) |
| 284system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 284system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 285system.cpu.fetch.rateDist::0 95931722 60.62% 60.62% # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::1 4757646 3.01% 63.63% # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::2 3806394 2.41% 66.03% # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::3 4363208 2.76% 68.79% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::4 4227713 2.67% 71.46% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::5 4814821 3.04% 74.50% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::6 4714702 2.98% 77.48% # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::7 3700525 2.34% 79.82% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::8 31934776 20.18% 100.00% # Number of instructions fetched each cycle (Total) | 285system.cpu.fetch.rateDist::0 95737540 60.56% 60.56% # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::1 4758449 3.01% 63.57% # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::2 3804662 2.41% 65.98% # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::3 4365114 2.76% 68.74% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::4 4234763 2.68% 71.42% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::5 4816061 3.05% 74.47% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::6 4706873 2.98% 77.45% # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::7 3702906 2.34% 79.79% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::8 31950308 20.21% 100.00% # Number of instructions fetched each cycle (Total) |
| 294system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 294system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 297system.cpu.fetch.rateDist::total 158251507 # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.branchRate 0.129957 # Number of branch fetches per cycle 299system.cpu.fetch.rate 1.435298 # Number of inst fetches per cycle 300system.cpu.decode.IdleCycles 15405673 # Number of cycles decode is idle 301system.cpu.decode.BlockedCycles 96363491 # Number of cycles decode is blocked 302system.cpu.decode.RunCycles 23242332 # Number of cycles decode is running 303system.cpu.decode.UnblockCycles 21643071 # Number of cycles decode is unblocking 304system.cpu.decode.SquashCycles 1596940 # Number of cycles decode is squashing 305system.cpu.decode.DecodedInsts 336546765 # Number of instructions handled by decode 306system.cpu.rename.SquashCycles 1596940 # Number of cycles rename is squashing 307system.cpu.rename.IdleCycles 23300664 # Number of cycles rename is idle 308system.cpu.rename.BlockCycles 31883477 # Number of cycles rename is blocking 309system.cpu.rename.serializeStallCycles 30445 # count of cycles rename stalled for serializing inst 310system.cpu.rename.RunCycles 35976653 # Number of cycles rename is running 311system.cpu.rename.UnblockCycles 65463328 # Number of cycles rename is unblocking 312system.cpu.rename.RenamedInsts 328193711 # Number of instructions processed by rename 313system.cpu.rename.ROBFullEvents 1319 # Number of times rename has blocked due to ROB full 314system.cpu.rename.IQFullEvents 57856617 # Number of times rename has blocked due to IQ full 315system.cpu.rename.LQFullEvents 7708627 # Number of times rename has blocked due to LQ full 316system.cpu.rename.SQFullEvents 165863 # Number of times rename has blocked due to SQ full 317system.cpu.rename.RenamedOperands 380358715 # Number of destination operands rename has renamed 318system.cpu.rename.RenameLookups 909771649 # Number of register rename lookups that rename has made 319system.cpu.rename.int_rename_lookups 600461611 # Number of integer rename lookups 320system.cpu.rename.fp_rename_lookups 4182617 # Number of floating rename lookups | 297system.cpu.fetch.rateDist::total 158076676 # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.branchRate 0.130173 # Number of branch fetches per cycle 299system.cpu.fetch.rate 1.437563 # Number of inst fetches per cycle 300system.cpu.decode.IdleCycles 15410588 # Number of cycles decode is idle 301system.cpu.decode.BlockedCycles 96165479 # Number of cycles decode is blocked 302system.cpu.decode.RunCycles 23286260 # Number of cycles decode is running 303system.cpu.decode.UnblockCycles 21616249 # Number of cycles decode is unblocking 304system.cpu.decode.SquashCycles 1598100 # Number of cycles decode is squashing 305system.cpu.decode.DecodedInsts 336629364 # Number of instructions handled by decode 306system.cpu.rename.SquashCycles 1598100 # Number of cycles rename is squashing 307system.cpu.rename.IdleCycles 23294905 # Number of cycles rename is idle 308system.cpu.rename.BlockCycles 31785654 # Number of cycles rename is blocking 309system.cpu.rename.serializeStallCycles 30420 # count of cycles rename stalled for serializing inst 310system.cpu.rename.RunCycles 36005072 # Number of cycles rename is running 311system.cpu.rename.UnblockCycles 65362525 # Number of cycles rename is unblocking 312system.cpu.rename.RenamedInsts 328266719 # Number of instructions processed by rename 313system.cpu.rename.ROBFullEvents 1575 # Number of times rename has blocked due to ROB full 314system.cpu.rename.IQFullEvents 57713162 # Number of times rename has blocked due to IQ full 315system.cpu.rename.LQFullEvents 7745606 # Number of times rename has blocked due to LQ full 316system.cpu.rename.SQFullEvents 167786 # Number of times rename has blocked due to SQ full 317system.cpu.rename.RenamedOperands 380441374 # Number of destination operands rename has renamed 318system.cpu.rename.RenameLookups 910027756 # Number of register rename lookups that rename has made 319system.cpu.rename.int_rename_lookups 600617832 # Number of integer rename lookups 320system.cpu.rename.fp_rename_lookups 4182134 # Number of floating rename lookups |
| 321system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed | 321system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed |
| 322system.cpu.rename.UndoneMaps 120929265 # Number of HB maps that are undone due to squashing 323system.cpu.rename.serializingInsts 2085 # count of serializing insts renamed 324system.cpu.rename.tempSerializingInsts 2059 # count of temporary serializing insts renamed 325system.cpu.rename.skidInsts 121166066 # count of insts added to the skid buffer 326system.cpu.memDep0.insertedLoads 82747977 # Number of loads inserted to the mem dependence unit. 327system.cpu.memDep0.insertedStores 29791267 # Number of stores inserted to the mem dependence unit. 328system.cpu.memDep0.conflictingLoads 59612118 # Number of conflicting loads. 329system.cpu.memDep0.conflictingStores 20405352 # Number of conflicting stores. 330system.cpu.iq.iqInstsAdded 317780620 # Number of instructions added to the IQ (excludes non-spec) 331system.cpu.iq.iqNonSpecInstsAdded 4165 # Number of non-speculative instructions added to the IQ 332system.cpu.iq.iqInstsIssued 259339471 # Number of instructions issued 333system.cpu.iq.iqSquashedInstsIssued 71881 # Number of squashed instructions issued 334system.cpu.iq.iqSquashedInstsExamined 96421401 # Number of squashed instructions iterated over during squash; mainly for profiling 335system.cpu.iq.iqSquashedOperandsExamined 197095861 # Number of squashed operands that are examined and possibly removed from graph 336system.cpu.iq.iqSquashedNonSpecRemoved 2920 # Number of squashed non-spec instructions that were removed 337system.cpu.iq.issued_per_cycle::samples 158251507 # Number of insts issued each cycle 338system.cpu.iq.issued_per_cycle::mean 1.638780 # Number of insts issued each cycle 339system.cpu.iq.issued_per_cycle::stdev 1.522654 # Number of insts issued each cycle | 322system.cpu.rename.UndoneMaps 121011924 # Number of HB maps that are undone due to squashing 323system.cpu.rename.serializingInsts 1942 # count of serializing insts renamed 324system.cpu.rename.tempSerializingInsts 1920 # count of temporary serializing insts renamed 325system.cpu.rename.skidInsts 120996232 # count of insts added to the skid buffer 326system.cpu.memDep0.insertedLoads 82787392 # Number of loads inserted to the mem dependence unit. 327system.cpu.memDep0.insertedStores 29790688 # Number of stores inserted to the mem dependence unit. 328system.cpu.memDep0.conflictingLoads 59618216 # Number of conflicting loads. 329system.cpu.memDep0.conflictingStores 20385329 # Number of conflicting stores. 330system.cpu.iq.iqInstsAdded 317847109 # Number of instructions added to the IQ (excludes non-spec) 331system.cpu.iq.iqNonSpecInstsAdded 5129 # Number of non-speculative instructions added to the IQ 332system.cpu.iq.iqInstsIssued 259397690 # Number of instructions issued 333system.cpu.iq.iqSquashedInstsIssued 74444 # Number of squashed instructions issued 334system.cpu.iq.iqSquashedInstsExamined 96488854 # Number of squashed instructions iterated over during squash; mainly for profiling 335system.cpu.iq.iqSquashedOperandsExamined 197170724 # Number of squashed operands that are examined and possibly removed from graph 336system.cpu.iq.iqSquashedNonSpecRemoved 3884 # Number of squashed non-spec instructions that were removed 337system.cpu.iq.issued_per_cycle::samples 158076676 # Number of insts issued each cycle 338system.cpu.iq.issued_per_cycle::mean 1.640961 # Number of insts issued each cycle 339system.cpu.iq.issued_per_cycle::stdev 1.524821 # Number of insts issued each cycle |
| 340system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 340system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 341system.cpu.iq.issued_per_cycle::0 40084558 25.33% 25.33% # Number of insts issued each cycle 342system.cpu.iq.issued_per_cycle::1 47634072 30.10% 55.43% # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::2 33122012 20.93% 76.36% # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::3 18013851 11.38% 87.74% # Number of insts issued each cycle 345system.cpu.iq.issued_per_cycle::4 10936157 6.91% 94.65% # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::5 4740478 3.00% 97.65% # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::6 2457312 1.55% 99.20% # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::7 875604 0.55% 99.76% # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::8 387463 0.24% 100.00% # Number of insts issued each cycle | 341system.cpu.iq.issued_per_cycle::0 40037946 25.33% 25.33% # Number of insts issued each cycle 342system.cpu.iq.issued_per_cycle::1 47502915 30.05% 55.38% # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::2 33077309 20.92% 76.30% # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::3 17993681 11.38% 87.69% # Number of insts issued each cycle 345system.cpu.iq.issued_per_cycle::4 10964078 6.94% 94.62% # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::5 4766946 3.02% 97.64% # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::6 2459939 1.56% 99.19% # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::7 882458 0.56% 99.75% # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::8 391404 0.25% 100.00% # Number of insts issued each cycle |
| 350system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 351system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 352system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 350system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 351system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 352system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 353system.cpu.iq.issued_per_cycle::total 158251507 # Number of insts issued each cycle | 353system.cpu.iq.issued_per_cycle::total 158076676 # Number of insts issued each cycle |
| 354system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 354system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 355system.cpu.iq.fu_full::IntAlu 234483 7.38% 7.38% # attempts to use FU when none available 356system.cpu.iq.fu_full::IntMult 0 0.00% 7.38% # attempts to use FU when none available 357system.cpu.iq.fu_full::IntDiv 0 0.00% 7.38% # attempts to use FU when none available 358system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.38% # attempts to use FU when none available 359system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.38% # attempts to use FU when none available 360system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.38% # attempts to use FU when none available 361system.cpu.iq.fu_full::FloatMult 0 0.00% 7.38% # attempts to use FU when none available 362system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.38% # attempts to use FU when none available 363system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.38% # attempts to use FU when none available 364system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.38% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.38% # attempts to use FU when none available 366system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.38% # attempts to use FU when none available 367system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.38% # attempts to use FU when none available 368system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.38% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.38% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdMult 0 0.00% 7.38% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.38% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdShift 0 0.00% 7.38% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.38% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.38% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.38% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.38% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.38% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.38% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.38% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.38% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.38% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.38% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.38% # attempts to use FU when none available 384system.cpu.iq.fu_full::MemRead 2555698 80.47% 87.85% # attempts to use FU when none available 385system.cpu.iq.fu_full::MemWrite 385880 12.15% 100.00% # attempts to use FU when none available | 355system.cpu.iq.fu_full::IntAlu 232299 7.31% 7.31% # attempts to use FU when none available 356system.cpu.iq.fu_full::IntMult 0 0.00% 7.31% # attempts to use FU when none available 357system.cpu.iq.fu_full::IntDiv 0 0.00% 7.31% # attempts to use FU when none available 358system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.31% # attempts to use FU when none available 359system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.31% # attempts to use FU when none available 360system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.31% # attempts to use FU when none available 361system.cpu.iq.fu_full::FloatMult 0 0.00% 7.31% # attempts to use FU when none available 362system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.31% # attempts to use FU when none available 363system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.31% # attempts to use FU when none available 364system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.31% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.31% # attempts to use FU when none available 366system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.31% # attempts to use FU when none available 367system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.31% # attempts to use FU when none available 368system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.31% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.31% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdMult 0 0.00% 7.31% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.31% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdShift 0 0.00% 7.31% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.31% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.31% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.31% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.31% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.31% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.31% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.31% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.31% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.31% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.31% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.31% # attempts to use FU when none available 384system.cpu.iq.fu_full::MemRead 2560752 80.62% 87.93% # attempts to use FU when none available 385system.cpu.iq.fu_full::MemWrite 383461 12.07% 100.00% # attempts to use FU when none available |
| 386system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 387system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 386system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 387system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 388system.cpu.iq.FU_type_0::No_OpClass 1212784 0.47% 0.47% # Type of FU issued 389system.cpu.iq.FU_type_0::IntAlu 161792342 62.39% 62.85% # Type of FU issued 390system.cpu.iq.FU_type_0::IntMult 789140 0.30% 63.16% # Type of FU issued 391system.cpu.iq.FU_type_0::IntDiv 7038106 2.71% 65.87% # Type of FU issued 392system.cpu.iq.FU_type_0::FloatAdd 1186493 0.46% 66.33% # Type of FU issued 393system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.33% # Type of FU issued 394system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.33% # Type of FU issued 395system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.33% # Type of FU issued 396system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.33% # Type of FU issued 397system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.33% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.33% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.33% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.33% # Type of FU issued 401system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.33% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.33% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.33% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.33% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.33% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.33% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.33% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.33% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.33% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.33% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.33% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.33% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.33% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.33% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.33% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.33% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.33% # Type of FU issued 418system.cpu.iq.FU_type_0::MemRead 64866325 25.01% 91.34% # Type of FU issued 419system.cpu.iq.FU_type_0::MemWrite 22454281 8.66% 100.00% # Type of FU issued | 388system.cpu.iq.FU_type_0::No_OpClass 1212757 0.47% 0.47% # Type of FU issued 389system.cpu.iq.FU_type_0::IntAlu 161810980 62.38% 62.85% # Type of FU issued 390system.cpu.iq.FU_type_0::IntMult 789695 0.30% 63.15% # Type of FU issued 391system.cpu.iq.FU_type_0::IntDiv 7037932 2.71% 65.86% # Type of FU issued 392system.cpu.iq.FU_type_0::FloatAdd 1186383 0.46% 66.32% # Type of FU issued 393system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.32% # Type of FU issued 394system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.32% # Type of FU issued 395system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.32% # Type of FU issued 396system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.32% # Type of FU issued 397system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.32% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.32% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.32% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.32% # Type of FU issued 401system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.32% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.32% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.32% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.32% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.32% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.32% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.32% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.32% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.32% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.32% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.32% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.32% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.32% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.32% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.32% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.32% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.32% # Type of FU issued 418system.cpu.iq.FU_type_0::MemRead 64896242 25.02% 91.34% # Type of FU issued 419system.cpu.iq.FU_type_0::MemWrite 22463701 8.66% 100.00% # Type of FU issued |
| 420system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 421system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 420system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 421system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 422system.cpu.iq.FU_type_0::total 259339471 # Type of FU issued 423system.cpu.iq.rate 1.636632 # Inst issue rate 424system.cpu.iq.fu_busy_cnt 3176061 # FU busy when requested 425system.cpu.iq.fu_busy_rate 0.012247 # FU busy rate (busy events/executed inst) 426system.cpu.iq.int_inst_queue_reads 675323210 # Number of integer instruction queue reads 427system.cpu.iq.int_inst_queue_writes 410805836 # Number of integer instruction queue writes 428system.cpu.iq.int_inst_queue_wakeup_accesses 253605894 # Number of integer instruction queue wakeup accesses 429system.cpu.iq.fp_inst_queue_reads 4855181 # Number of floating instruction queue reads 430system.cpu.iq.fp_inst_queue_writes 3696441 # Number of floating instruction queue writes 431system.cpu.iq.fp_inst_queue_wakeup_accesses 2340510 # Number of floating instruction queue wakeup accesses 432system.cpu.iq.int_alu_accesses 258858304 # Number of integer alu accesses 433system.cpu.iq.fp_alu_accesses 2444444 # Number of floating point alu accesses 434system.cpu.iew.lsq.thread0.forwLoads 18689568 # Number of loads that had data forwarded from stores | 422system.cpu.iq.FU_type_0::total 259397690 # Type of FU issued 423system.cpu.iq.rate 1.638833 # Inst issue rate 424system.cpu.iq.fu_busy_cnt 3176512 # FU busy when requested 425system.cpu.iq.fu_busy_rate 0.012246 # FU busy rate (busy events/executed inst) 426system.cpu.iq.int_inst_queue_reads 675268343 # Number of integer instruction queue reads 427system.cpu.iq.int_inst_queue_writes 410944123 # Number of integer instruction queue writes 428system.cpu.iq.int_inst_queue_wakeup_accesses 253662317 # Number of integer instruction queue wakeup accesses 429system.cpu.iq.fp_inst_queue_reads 4854669 # Number of floating instruction queue reads 430system.cpu.iq.fp_inst_queue_writes 3693735 # Number of floating instruction queue writes 431system.cpu.iq.fp_inst_queue_wakeup_accesses 2339703 # Number of floating instruction queue wakeup accesses 432system.cpu.iq.int_alu_accesses 258916834 # Number of integer alu accesses 433system.cpu.iq.fp_alu_accesses 2444611 # Number of floating point alu accesses 434system.cpu.iew.lsq.thread0.forwLoads 18724074 # Number of loads that had data forwarded from stores |
| 435system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 435system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 436system.cpu.iew.lsq.thread0.squashedLoads 26098390 # Number of loads squashed 437system.cpu.iew.lsq.thread0.ignoredResponses 12338 # Number of memory responses ignored because the instruction is squashed 438system.cpu.iew.lsq.thread0.memOrderViolation 302582 # Number of memory ordering violations 439system.cpu.iew.lsq.thread0.squashedStores 9275550 # Number of stores squashed | 436system.cpu.iew.lsq.thread0.squashedLoads 26137805 # Number of loads squashed 437system.cpu.iew.lsq.thread0.ignoredResponses 13130 # Number of memory responses ignored because the instruction is squashed 438system.cpu.iew.lsq.thread0.memOrderViolation 303242 # Number of memory ordering violations 439system.cpu.iew.lsq.thread0.squashedStores 9274971 # Number of stores squashed |
| 440system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 441system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 440system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 441system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 442system.cpu.iew.lsq.thread0.rescheduledLoads 50123 # Number of loads that were rescheduled | 442system.cpu.iew.lsq.thread0.rescheduledLoads 49888 # Number of loads that were rescheduled |
| 443system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked 444system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 443system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked 444system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 445system.cpu.iew.iewSquashCycles 1596940 # Number of cycles IEW is squashing 446system.cpu.iew.iewBlockCycles 12493200 # Number of cycles IEW is blocking 447system.cpu.iew.iewUnblockCycles 494306 # Number of cycles IEW is unblocking 448system.cpu.iew.iewDispatchedInsts 317784785 # Number of instructions dispatched to IQ 449system.cpu.iew.iewDispSquashedInsts 94743 # Number of squashed instructions skipped by dispatch 450system.cpu.iew.iewDispLoadInsts 82747977 # Number of dispatched load instructions 451system.cpu.iew.iewDispStoreInsts 29791267 # Number of dispatched store instructions 452system.cpu.iew.iewDispNonSpecInsts 1931 # Number of dispatched non-speculative instructions 453system.cpu.iew.iewIQFullEvents 389039 # Number of times the IQ has become full, causing a stall 454system.cpu.iew.iewLSQFullEvents 63652 # Number of times the LSQ has become full, causing a stall 455system.cpu.iew.memOrderViolationEvents 302582 # Number of memory order violations 456system.cpu.iew.predictedTakenIncorrect 551479 # Number of branches that were predicted taken incorrectly 457system.cpu.iew.predictedNotTakenIncorrect 825731 # Number of branches that were predicted not taken incorrectly 458system.cpu.iew.branchMispredicts 1377210 # Number of branch mispredicts detected at execute 459system.cpu.iew.iewExecutedInsts 257282682 # Number of executed instructions 460system.cpu.iew.iewExecLoadInsts 64058012 # Number of load instructions executed 461system.cpu.iew.iewExecSquashedInsts 2056789 # Number of squashed instructions skipped in execute | 445system.cpu.iew.iewSquashCycles 1598100 # Number of cycles IEW is squashing 446system.cpu.iew.iewBlockCycles 12496396 # Number of cycles IEW is blocking 447system.cpu.iew.iewUnblockCycles 489060 # Number of cycles IEW is unblocking 448system.cpu.iew.iewDispatchedInsts 317852238 # Number of instructions dispatched to IQ 449system.cpu.iew.iewDispSquashedInsts 92568 # Number of squashed instructions skipped by dispatch 450system.cpu.iew.iewDispLoadInsts 82787392 # Number of dispatched load instructions 451system.cpu.iew.iewDispStoreInsts 29790688 # Number of dispatched store instructions 452system.cpu.iew.iewDispNonSpecInsts 2962 # Number of dispatched non-speculative instructions 453system.cpu.iew.iewIQFullEvents 383739 # Number of times the IQ has become full, causing a stall 454system.cpu.iew.iewLSQFullEvents 63074 # Number of times the LSQ has become full, causing a stall 455system.cpu.iew.memOrderViolationEvents 303242 # Number of memory order violations 456system.cpu.iew.predictedTakenIncorrect 551670 # Number of branches that were predicted taken incorrectly 457system.cpu.iew.predictedNotTakenIncorrect 826736 # Number of branches that were predicted not taken incorrectly 458system.cpu.iew.branchMispredicts 1378406 # Number of branch mispredicts detected at execute 459system.cpu.iew.iewExecutedInsts 257339860 # Number of executed instructions 460system.cpu.iew.iewExecLoadInsts 64084690 # Number of load instructions executed 461system.cpu.iew.iewExecSquashedInsts 2057830 # Number of squashed instructions skipped in execute |
| 462system.cpu.iew.exec_swp 0 # number of swp insts executed 463system.cpu.iew.exec_nop 0 # number of nop insts executed | 462system.cpu.iew.exec_swp 0 # number of swp insts executed 463system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 464system.cpu.iew.exec_refs 86333641 # number of memory reference insts executed 465system.cpu.iew.exec_branches 14326229 # Number of branches executed 466system.cpu.iew.exec_stores 22275629 # Number of stores executed 467system.cpu.iew.exec_rate 1.623652 # Inst execution rate 468system.cpu.iew.wb_sent 256637538 # cumulative count of insts sent to commit 469system.cpu.iew.wb_count 255946404 # cumulative count of insts written-back 470system.cpu.iew.wb_producers 204333247 # num instructions producing a value 471system.cpu.iew.wb_consumers 369622334 # num instructions consuming a value 472system.cpu.iew.wb_rate 1.615219 # insts written-back per cycle 473system.cpu.iew.wb_fanout 0.552816 # average fanout of values written-back 474system.cpu.commit.commitSquashedInsts 96429188 # The number of squashed insts skipped by commit | 464system.cpu.iew.exec_refs 86369701 # number of memory reference insts executed 465system.cpu.iew.exec_branches 14330688 # Number of branches executed 466system.cpu.iew.exec_stores 22285011 # Number of stores executed 467system.cpu.iew.exec_rate 1.625832 # Inst execution rate 468system.cpu.iew.wb_sent 256690834 # cumulative count of insts sent to commit 469system.cpu.iew.wb_count 256002020 # cumulative count of insts written-back 470system.cpu.iew.wb_producers 204396158 # num instructions producing a value 471system.cpu.iew.wb_consumers 369708067 # num instructions consuming a value 472system.cpu.iew.wb_rate 1.617380 # insts written-back per cycle 473system.cpu.iew.wb_fanout 0.552858 # average fanout of values written-back 474system.cpu.commit.commitSquashedInsts 96496531 # The number of squashed insts skipped by commit |
| 475system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards | 475system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards |
| 476system.cpu.commit.branchMispredicts 1329692 # The number of times a branch was mispredicted 477system.cpu.commit.committed_per_cycle::samples 145106129 # Number of insts commited each cycle 478system.cpu.commit.committed_per_cycle::mean 1.525527 # Number of insts commited each cycle 479system.cpu.commit.committed_per_cycle::stdev 1.953873 # Number of insts commited each cycle | 476system.cpu.commit.branchMispredicts 1330625 # The number of times a branch was mispredicted 477system.cpu.commit.committed_per_cycle::samples 144920748 # Number of insts commited each cycle 478system.cpu.commit.committed_per_cycle::mean 1.527479 # Number of insts commited each cycle 479system.cpu.commit.committed_per_cycle::stdev 1.956907 # Number of insts commited each cycle |
| 480system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 480system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 481system.cpu.commit.committed_per_cycle::0 45566766 31.40% 31.40% # Number of insts commited each cycle 482system.cpu.commit.committed_per_cycle::1 57414676 39.57% 70.97% # Number of insts commited each cycle 483system.cpu.commit.committed_per_cycle::2 14193363 9.78% 80.75% # Number of insts commited each cycle 484system.cpu.commit.committed_per_cycle::3 12012309 8.28% 89.03% # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::4 4072580 2.81% 91.84% # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::5 2869750 1.98% 93.81% # Number of insts commited each cycle 487system.cpu.commit.committed_per_cycle::6 928162 0.64% 94.45% # Number of insts commited each cycle 488system.cpu.commit.committed_per_cycle::7 1071171 0.74% 95.19% # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::8 6977352 4.81% 100.00% # Number of insts commited each cycle | 481system.cpu.commit.committed_per_cycle::0 45508636 31.40% 31.40% # Number of insts commited each cycle 482system.cpu.commit.committed_per_cycle::1 57312376 39.55% 70.95% # Number of insts commited each cycle 483system.cpu.commit.committed_per_cycle::2 14158342 9.77% 80.72% # Number of insts commited each cycle 484system.cpu.commit.committed_per_cycle::3 11991162 8.27% 88.99% # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::4 4086517 2.82% 91.81% # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::5 2858053 1.97% 93.79% # Number of insts commited each cycle 487system.cpu.commit.committed_per_cycle::6 923800 0.64% 94.42% # Number of insts commited each cycle 488system.cpu.commit.committed_per_cycle::7 1073191 0.74% 95.16% # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::8 7008671 4.84% 100.00% # Number of insts commited each cycle |
| 490system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 491system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 492system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 490system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 491system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 492system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 493system.cpu.commit.committed_per_cycle::total 145106129 # Number of insts commited each cycle | 493system.cpu.commit.committed_per_cycle::total 144920748 # Number of insts commited each cycle |
| 494system.cpu.commit.committedInsts 132071192 # Number of instructions committed 495system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed 496system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 497system.cpu.commit.refs 77165304 # Number of memory references committed 498system.cpu.commit.loads 56649587 # Number of loads committed 499system.cpu.commit.membars 0 # Number of memory barriers committed 500system.cpu.commit.branches 12326938 # Number of branches committed 501system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 531system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction 532system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction 533system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction 534system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction 535system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction 536system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 537system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 538system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction | 494system.cpu.commit.committedInsts 132071192 # Number of instructions committed 495system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed 496system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 497system.cpu.commit.refs 77165304 # Number of memory references committed 498system.cpu.commit.loads 56649587 # Number of loads committed 499system.cpu.commit.membars 0 # Number of memory barriers committed 500system.cpu.commit.branches 12326938 # Number of branches committed 501system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 531system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction 532system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction 533system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction 534system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction 535system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction 536system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 537system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 538system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction |
| 539system.cpu.commit.bw_lim_events 6977352 # number cycles where commit BW limit reached 540system.cpu.rob.rob_reads 455921349 # The number of ROB reads 541system.cpu.rob.rob_writes 648768029 # The number of ROB writes 542system.cpu.timesIdled 2647 # Number of times that the entire CPU went into an idle state and unscheduled itself 543system.cpu.idleCycles 207784 # Total number of cycles that the CPU has spent unscheduled due to idling | 539system.cpu.commit.bw_lim_events 7008671 # number cycles where commit BW limit reached 540system.cpu.rob.rob_reads 455771992 # The number of ROB reads 541system.cpu.rob.rob_writes 648913303 # The number of ROB writes 542system.cpu.timesIdled 2665 # Number of times that the entire CPU went into an idle state and unscheduled itself 543system.cpu.idleCycles 205284 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 544system.cpu.committedInsts 132071192 # Number of Instructions Simulated 545system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated | 544system.cpu.committedInsts 132071192 # Number of Instructions Simulated 545system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated |
| 546system.cpu.cpi 1.199802 # CPI: Cycles Per Instruction 547system.cpu.cpi_total 1.199802 # CPI: Total CPI of All Threads 548system.cpu.ipc 0.833471 # IPC: Instructions Per Cycle 549system.cpu.ipc_total 0.833471 # IPC: Total IPC of All Threads 550system.cpu.int_regfile_reads 448461429 # number of integer regfile reads 551system.cpu.int_regfile_writes 232562681 # number of integer regfile writes 552system.cpu.fp_regfile_reads 3213153 # number of floating regfile reads 553system.cpu.fp_regfile_writes 1998427 # number of floating regfile writes 554system.cpu.cc_regfile_reads 102530427 # number of cc regfile reads 555system.cpu.cc_regfile_writes 59507422 # number of cc regfile writes 556system.cpu.misc_regfile_reads 132428508 # number of misc regfile reads | 546system.cpu.cpi 1.198459 # CPI: Cycles Per Instruction 547system.cpu.cpi_total 1.198459 # CPI: Total CPI of All Threads 548system.cpu.ipc 0.834405 # IPC: Instructions Per Cycle 549system.cpu.ipc_total 0.834405 # IPC: Total IPC of All Threads 550system.cpu.int_regfile_reads 448575218 # number of integer regfile reads 551system.cpu.int_regfile_writes 232602901 # number of integer regfile writes 552system.cpu.fp_regfile_reads 3212636 # number of floating regfile reads 553system.cpu.fp_regfile_writes 1997796 # number of floating regfile writes 554system.cpu.cc_regfile_reads 102540240 # number of cc regfile reads 555system.cpu.cc_regfile_writes 59516414 # number of cc regfile writes 556system.cpu.misc_regfile_reads 132474844 # number of misc regfile reads |
| 557system.cpu.misc_regfile_writes 1689 # number of misc regfile writes 558system.cpu.dcache.tags.replacements 51 # number of replacements | 557system.cpu.misc_regfile_writes 1689 # number of misc regfile writes 558system.cpu.dcache.tags.replacements 51 # number of replacements |
| 559system.cpu.dcache.tags.tagsinuse 1429.692139 # Cycle average of tags in use 560system.cpu.dcache.tags.total_refs 65755137 # Total number of references to valid blocks. 561system.cpu.dcache.tags.sampled_refs 1993 # Sample count of references to valid blocks. 562system.cpu.dcache.tags.avg_refs 32993.044155 # Average number of references to valid blocks. | 559system.cpu.dcache.tags.tagsinuse 1429.115986 # Cycle average of tags in use 560system.cpu.dcache.tags.total_refs 65747317 # Total number of references to valid blocks. 561system.cpu.dcache.tags.sampled_refs 1995 # Sample count of references to valid blocks. 562system.cpu.dcache.tags.avg_refs 32956.048622 # Average number of references to valid blocks. |
| 563system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 563system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 564system.cpu.dcache.tags.occ_blocks::cpu.data 1429.692139 # Average occupied blocks per requestor 565system.cpu.dcache.tags.occ_percent::cpu.data 0.349046 # Average percentage of cache occupancy 566system.cpu.dcache.tags.occ_percent::total 0.349046 # Average percentage of cache occupancy 567system.cpu.dcache.tags.occ_task_id_blocks::1024 1942 # Occupied blocks per task id | 564system.cpu.dcache.tags.occ_blocks::cpu.data 1429.115986 # Average occupied blocks per requestor 565system.cpu.dcache.tags.occ_percent::cpu.data 0.348905 # Average percentage of cache occupancy 566system.cpu.dcache.tags.occ_percent::total 0.348905 # Average percentage of cache occupancy 567system.cpu.dcache.tags.occ_task_id_blocks::1024 1944 # Occupied blocks per task id |
| 568system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id 569system.cpu.dcache.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id | 568system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id 569system.cpu.dcache.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id |
| 570system.cpu.dcache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id | 570system.cpu.dcache.tags.age_task_id_blocks_1024::2 498 # Occupied blocks per task id |
| 571system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id | 571system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id |
| 572system.cpu.dcache.tags.age_task_id_blocks_1024::4 1395 # Occupied blocks per task id 573system.cpu.dcache.tags.occ_task_id_percent::1024 0.474121 # Percentage of cache occupancy per task id 574system.cpu.dcache.tags.tag_accesses 131517093 # Number of tag accesses 575system.cpu.dcache.tags.data_accesses 131517093 # Number of data accesses 576system.cpu.dcache.ReadReq_hits::cpu.data 45240855 # number of ReadReq hits 577system.cpu.dcache.ReadReq_hits::total 45240855 # number of ReadReq hits 578system.cpu.dcache.WriteReq_hits::cpu.data 20513928 # number of WriteReq hits 579system.cpu.dcache.WriteReq_hits::total 20513928 # number of WriteReq hits 580system.cpu.dcache.demand_hits::cpu.data 65754783 # number of demand (read+write) hits 581system.cpu.dcache.demand_hits::total 65754783 # number of demand (read+write) hits 582system.cpu.dcache.overall_hits::cpu.data 65754783 # number of overall hits 583system.cpu.dcache.overall_hits::total 65754783 # number of overall hits 584system.cpu.dcache.ReadReq_misses::cpu.data 964 # number of ReadReq misses 585system.cpu.dcache.ReadReq_misses::total 964 # number of ReadReq misses 586system.cpu.dcache.WriteReq_misses::cpu.data 1803 # number of WriteReq misses 587system.cpu.dcache.WriteReq_misses::total 1803 # number of WriteReq misses 588system.cpu.dcache.demand_misses::cpu.data 2767 # number of demand (read+write) misses 589system.cpu.dcache.demand_misses::total 2767 # number of demand (read+write) misses 590system.cpu.dcache.overall_misses::cpu.data 2767 # number of overall misses 591system.cpu.dcache.overall_misses::total 2767 # number of overall misses 592system.cpu.dcache.ReadReq_miss_latency::cpu.data 65032500 # number of ReadReq miss cycles 593system.cpu.dcache.ReadReq_miss_latency::total 65032500 # number of ReadReq miss cycles 594system.cpu.dcache.WriteReq_miss_latency::cpu.data 127862500 # number of WriteReq miss cycles 595system.cpu.dcache.WriteReq_miss_latency::total 127862500 # number of WriteReq miss cycles 596system.cpu.dcache.demand_miss_latency::cpu.data 192895000 # number of demand (read+write) miss cycles 597system.cpu.dcache.demand_miss_latency::total 192895000 # number of demand (read+write) miss cycles 598system.cpu.dcache.overall_miss_latency::cpu.data 192895000 # number of overall miss cycles 599system.cpu.dcache.overall_miss_latency::total 192895000 # number of overall miss cycles 600system.cpu.dcache.ReadReq_accesses::cpu.data 45241819 # number of ReadReq accesses(hits+misses) 601system.cpu.dcache.ReadReq_accesses::total 45241819 # number of ReadReq accesses(hits+misses) | 572system.cpu.dcache.tags.age_task_id_blocks_1024::4 1394 # Occupied blocks per task id 573system.cpu.dcache.tags.occ_task_id_percent::1024 0.474609 # Percentage of cache occupancy per task id 574system.cpu.dcache.tags.tag_accesses 131501473 # Number of tag accesses 575system.cpu.dcache.tags.data_accesses 131501473 # Number of data accesses 576system.cpu.dcache.ReadReq_hits::cpu.data 45233028 # number of ReadReq hits 577system.cpu.dcache.ReadReq_hits::total 45233028 # number of ReadReq hits 578system.cpu.dcache.WriteReq_hits::cpu.data 20513911 # number of WriteReq hits 579system.cpu.dcache.WriteReq_hits::total 20513911 # number of WriteReq hits 580system.cpu.dcache.demand_hits::cpu.data 65746939 # number of demand (read+write) hits 581system.cpu.dcache.demand_hits::total 65746939 # number of demand (read+write) hits 582system.cpu.dcache.overall_hits::cpu.data 65746939 # number of overall hits 583system.cpu.dcache.overall_hits::total 65746939 # number of overall hits 584system.cpu.dcache.ReadReq_misses::cpu.data 980 # number of ReadReq misses 585system.cpu.dcache.ReadReq_misses::total 980 # number of ReadReq misses 586system.cpu.dcache.WriteReq_misses::cpu.data 1820 # number of WriteReq misses 587system.cpu.dcache.WriteReq_misses::total 1820 # number of WriteReq misses 588system.cpu.dcache.demand_misses::cpu.data 2800 # number of demand (read+write) misses 589system.cpu.dcache.demand_misses::total 2800 # number of demand (read+write) misses 590system.cpu.dcache.overall_misses::cpu.data 2800 # number of overall misses 591system.cpu.dcache.overall_misses::total 2800 # number of overall misses 592system.cpu.dcache.ReadReq_miss_latency::cpu.data 65148000 # number of ReadReq miss cycles 593system.cpu.dcache.ReadReq_miss_latency::total 65148000 # number of ReadReq miss cycles 594system.cpu.dcache.WriteReq_miss_latency::cpu.data 128547000 # number of WriteReq miss cycles 595system.cpu.dcache.WriteReq_miss_latency::total 128547000 # number of WriteReq miss cycles 596system.cpu.dcache.demand_miss_latency::cpu.data 193695000 # number of demand (read+write) miss cycles 597system.cpu.dcache.demand_miss_latency::total 193695000 # number of demand (read+write) miss cycles 598system.cpu.dcache.overall_miss_latency::cpu.data 193695000 # number of overall miss cycles 599system.cpu.dcache.overall_miss_latency::total 193695000 # number of overall miss cycles 600system.cpu.dcache.ReadReq_accesses::cpu.data 45234008 # number of ReadReq accesses(hits+misses) 601system.cpu.dcache.ReadReq_accesses::total 45234008 # number of ReadReq accesses(hits+misses) |
| 602system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) 603system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) | 602system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) 603system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) |
| 604system.cpu.dcache.demand_accesses::cpu.data 65757550 # number of demand (read+write) accesses 605system.cpu.dcache.demand_accesses::total 65757550 # number of demand (read+write) accesses 606system.cpu.dcache.overall_accesses::cpu.data 65757550 # number of overall (read+write) accesses 607system.cpu.dcache.overall_accesses::total 65757550 # number of overall (read+write) accesses 608system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses 609system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses 610system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000088 # miss rate for WriteReq accesses 611system.cpu.dcache.WriteReq_miss_rate::total 0.000088 # miss rate for WriteReq accesses 612system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 # miss rate for demand accesses 613system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses 614system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses 615system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses 616system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67461.099585 # average ReadReq miss latency 617system.cpu.dcache.ReadReq_avg_miss_latency::total 67461.099585 # average ReadReq miss latency 618system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70916.528009 # average WriteReq miss latency 619system.cpu.dcache.WriteReq_avg_miss_latency::total 70916.528009 # average WriteReq miss latency 620system.cpu.dcache.demand_avg_miss_latency::cpu.data 69712.685219 # average overall miss latency 621system.cpu.dcache.demand_avg_miss_latency::total 69712.685219 # average overall miss latency 622system.cpu.dcache.overall_avg_miss_latency::cpu.data 69712.685219 # average overall miss latency 623system.cpu.dcache.overall_avg_miss_latency::total 69712.685219 # average overall miss latency | 604system.cpu.dcache.demand_accesses::cpu.data 65749739 # number of demand (read+write) accesses 605system.cpu.dcache.demand_accesses::total 65749739 # number of demand (read+write) accesses 606system.cpu.dcache.overall_accesses::cpu.data 65749739 # number of overall (read+write) accesses 607system.cpu.dcache.overall_accesses::total 65749739 # number of overall (read+write) accesses 608system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses 609system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses 610system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses 611system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses 612system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses 613system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses 614system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses 615system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses 616system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66477.551020 # average ReadReq miss latency 617system.cpu.dcache.ReadReq_avg_miss_latency::total 66477.551020 # average ReadReq miss latency 618system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70630.219780 # average WriteReq miss latency 619system.cpu.dcache.WriteReq_avg_miss_latency::total 70630.219780 # average WriteReq miss latency 620system.cpu.dcache.demand_avg_miss_latency::cpu.data 69176.785714 # average overall miss latency 621system.cpu.dcache.demand_avg_miss_latency::total 69176.785714 # average overall miss latency 622system.cpu.dcache.overall_avg_miss_latency::cpu.data 69176.785714 # average overall miss latency 623system.cpu.dcache.overall_avg_miss_latency::total 69176.785714 # average overall miss latency |
| 624system.cpu.dcache.blocked_cycles::no_mshrs 656 # number of cycles access was blocked 625system.cpu.dcache.blocked_cycles::no_targets 70 # number of cycles access was blocked 626system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked 627system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked 628system.cpu.dcache.avg_blocked_cycles::no_mshrs 93.714286 # average number of cycles each access was blocked 629system.cpu.dcache.avg_blocked_cycles::no_targets 70 # average number of cycles each access was blocked 630system.cpu.dcache.fast_writes 0 # number of fast writes performed 631system.cpu.dcache.cache_copies 0 # number of cache copies performed 632system.cpu.dcache.writebacks::writebacks 10 # number of writebacks 633system.cpu.dcache.writebacks::total 10 # number of writebacks | 624system.cpu.dcache.blocked_cycles::no_mshrs 656 # number of cycles access was blocked 625system.cpu.dcache.blocked_cycles::no_targets 70 # number of cycles access was blocked 626system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked 627system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked 628system.cpu.dcache.avg_blocked_cycles::no_mshrs 93.714286 # average number of cycles each access was blocked 629system.cpu.dcache.avg_blocked_cycles::no_targets 70 # average number of cycles each access was blocked 630system.cpu.dcache.fast_writes 0 # number of fast writes performed 631system.cpu.dcache.cache_copies 0 # number of cache copies performed 632system.cpu.dcache.writebacks::writebacks 10 # number of writebacks 633system.cpu.dcache.writebacks::total 10 # number of writebacks |
| 634system.cpu.dcache.ReadReq_mshr_hits::cpu.data 511 # number of ReadReq MSHR hits 635system.cpu.dcache.ReadReq_mshr_hits::total 511 # number of ReadReq MSHR hits | 634system.cpu.dcache.ReadReq_mshr_hits::cpu.data 526 # number of ReadReq MSHR hits 635system.cpu.dcache.ReadReq_mshr_hits::total 526 # number of ReadReq MSHR hits |
| 636system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits 637system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits | 636system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits 637system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits |
| 638system.cpu.dcache.demand_mshr_hits::cpu.data 513 # number of demand (read+write) MSHR hits 639system.cpu.dcache.demand_mshr_hits::total 513 # number of demand (read+write) MSHR hits 640system.cpu.dcache.overall_mshr_hits::cpu.data 513 # number of overall MSHR hits 641system.cpu.dcache.overall_mshr_hits::total 513 # number of overall MSHR hits 642system.cpu.dcache.ReadReq_mshr_misses::cpu.data 453 # number of ReadReq MSHR misses 643system.cpu.dcache.ReadReq_mshr_misses::total 453 # number of ReadReq MSHR misses 644system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1801 # number of WriteReq MSHR misses 645system.cpu.dcache.WriteReq_mshr_misses::total 1801 # number of WriteReq MSHR misses 646system.cpu.dcache.demand_mshr_misses::cpu.data 2254 # number of demand (read+write) MSHR misses 647system.cpu.dcache.demand_mshr_misses::total 2254 # number of demand (read+write) MSHR misses 648system.cpu.dcache.overall_mshr_misses::cpu.data 2254 # number of overall MSHR misses 649system.cpu.dcache.overall_mshr_misses::total 2254 # number of overall MSHR misses 650system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36207500 # number of ReadReq MSHR miss cycles 651system.cpu.dcache.ReadReq_mshr_miss_latency::total 36207500 # number of ReadReq MSHR miss cycles 652system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 125915500 # number of WriteReq MSHR miss cycles 653system.cpu.dcache.WriteReq_mshr_miss_latency::total 125915500 # number of WriteReq MSHR miss cycles 654system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162123000 # number of demand (read+write) MSHR miss cycles 655system.cpu.dcache.demand_mshr_miss_latency::total 162123000 # number of demand (read+write) MSHR miss cycles 656system.cpu.dcache.overall_mshr_miss_latency::cpu.data 162123000 # number of overall MSHR miss cycles 657system.cpu.dcache.overall_mshr_miss_latency::total 162123000 # number of overall MSHR miss cycles | 638system.cpu.dcache.demand_mshr_hits::cpu.data 528 # number of demand (read+write) MSHR hits 639system.cpu.dcache.demand_mshr_hits::total 528 # number of demand (read+write) MSHR hits 640system.cpu.dcache.overall_mshr_hits::cpu.data 528 # number of overall MSHR hits 641system.cpu.dcache.overall_mshr_hits::total 528 # number of overall MSHR hits 642system.cpu.dcache.ReadReq_mshr_misses::cpu.data 454 # number of ReadReq MSHR misses 643system.cpu.dcache.ReadReq_mshr_misses::total 454 # number of ReadReq MSHR misses 644system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1818 # number of WriteReq MSHR misses 645system.cpu.dcache.WriteReq_mshr_misses::total 1818 # number of WriteReq MSHR misses 646system.cpu.dcache.demand_mshr_misses::cpu.data 2272 # number of demand (read+write) MSHR misses 647system.cpu.dcache.demand_mshr_misses::total 2272 # number of demand (read+write) MSHR misses 648system.cpu.dcache.overall_mshr_misses::cpu.data 2272 # number of overall MSHR misses 649system.cpu.dcache.overall_mshr_misses::total 2272 # number of overall MSHR misses 650system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36063000 # number of ReadReq MSHR miss cycles 651system.cpu.dcache.ReadReq_mshr_miss_latency::total 36063000 # number of ReadReq MSHR miss cycles 652system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 126583000 # number of WriteReq MSHR miss cycles 653system.cpu.dcache.WriteReq_mshr_miss_latency::total 126583000 # number of WriteReq MSHR miss cycles 654system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162646000 # number of demand (read+write) MSHR miss cycles 655system.cpu.dcache.demand_mshr_miss_latency::total 162646000 # number of demand (read+write) MSHR miss cycles 656system.cpu.dcache.overall_mshr_miss_latency::cpu.data 162646000 # number of overall MSHR miss cycles 657system.cpu.dcache.overall_mshr_miss_latency::total 162646000 # number of overall MSHR miss cycles |
| 658system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses 659system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses | 658system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses 659system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses |
| 660system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses 661system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses 662system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for demand accesses 663system.cpu.dcache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses 664system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for overall accesses 665system.cpu.dcache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses 666system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79928.256071 # average ReadReq mshr miss latency 667system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79928.256071 # average ReadReq mshr miss latency 668system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69914.214325 # average WriteReq mshr miss latency 669system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69914.214325 # average WriteReq mshr miss latency 670system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71926.796806 # average overall mshr miss latency 671system.cpu.dcache.demand_avg_mshr_miss_latency::total 71926.796806 # average overall mshr miss latency 672system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71926.796806 # average overall mshr miss latency 673system.cpu.dcache.overall_avg_mshr_miss_latency::total 71926.796806 # average overall mshr miss latency | 660system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses 661system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses 662system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for demand accesses 663system.cpu.dcache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses 664system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for overall accesses 665system.cpu.dcache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses 666system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79433.920705 # average ReadReq mshr miss latency 667system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79433.920705 # average ReadReq mshr miss latency 668system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69627.612761 # average WriteReq mshr miss latency 669system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69627.612761 # average WriteReq mshr miss latency 670system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71587.147887 # average overall mshr miss latency 671system.cpu.dcache.demand_avg_mshr_miss_latency::total 71587.147887 # average overall mshr miss latency 672system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71587.147887 # average overall mshr miss latency 673system.cpu.dcache.overall_avg_mshr_miss_latency::total 71587.147887 # average overall mshr miss latency |
| 674system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 674system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 675system.cpu.icache.tags.replacements 4974 # number of replacements 676system.cpu.icache.tags.tagsinuse 1637.723048 # Cycle average of tags in use 677system.cpu.icache.tags.total_refs 24250086 # Total number of references to valid blocks. 678system.cpu.icache.tags.sampled_refs 6949 # Sample count of references to valid blocks. 679system.cpu.icache.tags.avg_refs 3489.723126 # Average number of references to valid blocks. | 675system.cpu.icache.tags.replacements 5017 # number of replacements 676system.cpu.icache.tags.tagsinuse 1636.801929 # Cycle average of tags in use 677system.cpu.icache.tags.total_refs 24258361 # Total number of references to valid blocks. 678system.cpu.icache.tags.sampled_refs 6993 # Sample count of references to valid blocks. 679system.cpu.icache.tags.avg_refs 3468.949092 # Average number of references to valid blocks. |
| 680system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 680system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 681system.cpu.icache.tags.occ_blocks::cpu.inst 1637.723048 # Average occupied blocks per requestor 682system.cpu.icache.tags.occ_percent::cpu.inst 0.799669 # Average percentage of cache occupancy 683system.cpu.icache.tags.occ_percent::total 0.799669 # Average percentage of cache occupancy 684system.cpu.icache.tags.occ_task_id_blocks::1024 1975 # Occupied blocks per task id 685system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id 686system.cpu.icache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id 687system.cpu.icache.tags.age_task_id_blocks_1024::2 867 # Occupied blocks per task id | 681system.cpu.icache.tags.occ_blocks::cpu.inst 1636.801929 # Average occupied blocks per requestor 682system.cpu.icache.tags.occ_percent::cpu.inst 0.799220 # Average percentage of cache occupancy 683system.cpu.icache.tags.occ_percent::total 0.799220 # Average percentage of cache occupancy 684system.cpu.icache.tags.occ_task_id_blocks::1024 1976 # Occupied blocks per task id 685system.cpu.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id 686system.cpu.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id 687system.cpu.icache.tags.age_task_id_blocks_1024::2 869 # Occupied blocks per task id |
| 688system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id | 688system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id |
| 689system.cpu.icache.tags.age_task_id_blocks_1024::4 792 # Occupied blocks per task id 690system.cpu.icache.tags.occ_task_id_percent::1024 0.964355 # Percentage of cache occupancy per task id 691system.cpu.icache.tags.tag_accesses 48526174 # Number of tag accesses 692system.cpu.icache.tags.data_accesses 48526174 # Number of data accesses 693system.cpu.icache.ReadReq_hits::cpu.inst 24250086 # number of ReadReq hits 694system.cpu.icache.ReadReq_hits::total 24250086 # number of ReadReq hits 695system.cpu.icache.demand_hits::cpu.inst 24250086 # number of demand (read+write) hits 696system.cpu.icache.demand_hits::total 24250086 # number of demand (read+write) hits 697system.cpu.icache.overall_hits::cpu.inst 24250086 # number of overall hits 698system.cpu.icache.overall_hits::total 24250086 # number of overall hits 699system.cpu.icache.ReadReq_misses::cpu.inst 9396 # number of ReadReq misses 700system.cpu.icache.ReadReq_misses::total 9396 # number of ReadReq misses 701system.cpu.icache.demand_misses::cpu.inst 9396 # number of demand (read+write) misses 702system.cpu.icache.demand_misses::total 9396 # number of demand (read+write) misses 703system.cpu.icache.overall_misses::cpu.inst 9396 # number of overall misses 704system.cpu.icache.overall_misses::total 9396 # number of overall misses 705system.cpu.icache.ReadReq_miss_latency::cpu.inst 410761999 # number of ReadReq miss cycles 706system.cpu.icache.ReadReq_miss_latency::total 410761999 # number of ReadReq miss cycles 707system.cpu.icache.demand_miss_latency::cpu.inst 410761999 # number of demand (read+write) miss cycles 708system.cpu.icache.demand_miss_latency::total 410761999 # number of demand (read+write) miss cycles 709system.cpu.icache.overall_miss_latency::cpu.inst 410761999 # number of overall miss cycles 710system.cpu.icache.overall_miss_latency::total 410761999 # number of overall miss cycles 711system.cpu.icache.ReadReq_accesses::cpu.inst 24259482 # number of ReadReq accesses(hits+misses) 712system.cpu.icache.ReadReq_accesses::total 24259482 # number of ReadReq accesses(hits+misses) 713system.cpu.icache.demand_accesses::cpu.inst 24259482 # number of demand (read+write) accesses 714system.cpu.icache.demand_accesses::total 24259482 # number of demand (read+write) accesses 715system.cpu.icache.overall_accesses::cpu.inst 24259482 # number of overall (read+write) accesses 716system.cpu.icache.overall_accesses::total 24259482 # number of overall (read+write) accesses 717system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000387 # miss rate for ReadReq accesses 718system.cpu.icache.ReadReq_miss_rate::total 0.000387 # miss rate for ReadReq accesses 719system.cpu.icache.demand_miss_rate::cpu.inst 0.000387 # miss rate for demand accesses 720system.cpu.icache.demand_miss_rate::total 0.000387 # miss rate for demand accesses 721system.cpu.icache.overall_miss_rate::cpu.inst 0.000387 # miss rate for overall accesses 722system.cpu.icache.overall_miss_rate::total 0.000387 # miss rate for overall accesses 723system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43716.687846 # average ReadReq miss latency 724system.cpu.icache.ReadReq_avg_miss_latency::total 43716.687846 # average ReadReq miss latency 725system.cpu.icache.demand_avg_miss_latency::cpu.inst 43716.687846 # average overall miss latency 726system.cpu.icache.demand_avg_miss_latency::total 43716.687846 # average overall miss latency 727system.cpu.icache.overall_avg_miss_latency::cpu.inst 43716.687846 # average overall miss latency 728system.cpu.icache.overall_avg_miss_latency::total 43716.687846 # average overall miss latency 729system.cpu.icache.blocked_cycles::no_mshrs 900 # number of cycles access was blocked | 689system.cpu.icache.tags.age_task_id_blocks_1024::4 788 # Occupied blocks per task id 690system.cpu.icache.tags.occ_task_id_percent::1024 0.964844 # Percentage of cache occupancy per task id 691system.cpu.icache.tags.tag_accesses 48542851 # Number of tag accesses 692system.cpu.icache.tags.data_accesses 48542851 # Number of data accesses 693system.cpu.icache.ReadReq_hits::cpu.inst 24258362 # number of ReadReq hits 694system.cpu.icache.ReadReq_hits::total 24258362 # number of ReadReq hits 695system.cpu.icache.demand_hits::cpu.inst 24258362 # number of demand (read+write) hits 696system.cpu.icache.demand_hits::total 24258362 # number of demand (read+write) hits 697system.cpu.icache.overall_hits::cpu.inst 24258362 # number of overall hits 698system.cpu.icache.overall_hits::total 24258362 # number of overall hits 699system.cpu.icache.ReadReq_misses::cpu.inst 9429 # number of ReadReq misses 700system.cpu.icache.ReadReq_misses::total 9429 # number of ReadReq misses 701system.cpu.icache.demand_misses::cpu.inst 9429 # number of demand (read+write) misses 702system.cpu.icache.demand_misses::total 9429 # number of demand (read+write) misses 703system.cpu.icache.overall_misses::cpu.inst 9429 # number of overall misses 704system.cpu.icache.overall_misses::total 9429 # number of overall misses 705system.cpu.icache.ReadReq_miss_latency::cpu.inst 409019999 # number of ReadReq miss cycles 706system.cpu.icache.ReadReq_miss_latency::total 409019999 # number of ReadReq miss cycles 707system.cpu.icache.demand_miss_latency::cpu.inst 409019999 # number of demand (read+write) miss cycles 708system.cpu.icache.demand_miss_latency::total 409019999 # number of demand (read+write) miss cycles 709system.cpu.icache.overall_miss_latency::cpu.inst 409019999 # number of overall miss cycles 710system.cpu.icache.overall_miss_latency::total 409019999 # number of overall miss cycles 711system.cpu.icache.ReadReq_accesses::cpu.inst 24267791 # number of ReadReq accesses(hits+misses) 712system.cpu.icache.ReadReq_accesses::total 24267791 # number of ReadReq accesses(hits+misses) 713system.cpu.icache.demand_accesses::cpu.inst 24267791 # number of demand (read+write) accesses 714system.cpu.icache.demand_accesses::total 24267791 # number of demand (read+write) accesses 715system.cpu.icache.overall_accesses::cpu.inst 24267791 # number of overall (read+write) accesses 716system.cpu.icache.overall_accesses::total 24267791 # number of overall (read+write) accesses 717system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000389 # miss rate for ReadReq accesses 718system.cpu.icache.ReadReq_miss_rate::total 0.000389 # miss rate for ReadReq accesses 719system.cpu.icache.demand_miss_rate::cpu.inst 0.000389 # miss rate for demand accesses 720system.cpu.icache.demand_miss_rate::total 0.000389 # miss rate for demand accesses 721system.cpu.icache.overall_miss_rate::cpu.inst 0.000389 # miss rate for overall accesses 722system.cpu.icache.overall_miss_rate::total 0.000389 # miss rate for overall accesses 723system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43378.937215 # average ReadReq miss latency 724system.cpu.icache.ReadReq_avg_miss_latency::total 43378.937215 # average ReadReq miss latency 725system.cpu.icache.demand_avg_miss_latency::cpu.inst 43378.937215 # average overall miss latency 726system.cpu.icache.demand_avg_miss_latency::total 43378.937215 # average overall miss latency 727system.cpu.icache.overall_avg_miss_latency::cpu.inst 43378.937215 # average overall miss latency 728system.cpu.icache.overall_avg_miss_latency::total 43378.937215 # average overall miss latency 729system.cpu.icache.blocked_cycles::no_mshrs 793 # number of cycles access was blocked |
| 730system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 731system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked 732system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 730system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 731system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked 732system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 733system.cpu.icache.avg_blocked_cycles::no_mshrs 69.230769 # average number of cycles each access was blocked | 733system.cpu.icache.avg_blocked_cycles::no_mshrs 61 # average number of cycles each access was blocked |
| 734system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 735system.cpu.icache.fast_writes 0 # number of fast writes performed 736system.cpu.icache.cache_copies 0 # number of cache copies performed | 734system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 735system.cpu.icache.fast_writes 0 # number of fast writes performed 736system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 737system.cpu.icache.writebacks::writebacks 4974 # number of writebacks 738system.cpu.icache.writebacks::total 4974 # number of writebacks 739system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2184 # number of ReadReq MSHR hits 740system.cpu.icache.ReadReq_mshr_hits::total 2184 # number of ReadReq MSHR hits 741system.cpu.icache.demand_mshr_hits::cpu.inst 2184 # number of demand (read+write) MSHR hits 742system.cpu.icache.demand_mshr_hits::total 2184 # number of demand (read+write) MSHR hits 743system.cpu.icache.overall_mshr_hits::cpu.inst 2184 # number of overall MSHR hits 744system.cpu.icache.overall_mshr_hits::total 2184 # number of overall MSHR hits 745system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7212 # number of ReadReq MSHR misses 746system.cpu.icache.ReadReq_mshr_misses::total 7212 # number of ReadReq MSHR misses 747system.cpu.icache.demand_mshr_misses::cpu.inst 7212 # number of demand (read+write) MSHR misses 748system.cpu.icache.demand_mshr_misses::total 7212 # number of demand (read+write) MSHR misses 749system.cpu.icache.overall_mshr_misses::cpu.inst 7212 # number of overall MSHR misses 750system.cpu.icache.overall_mshr_misses::total 7212 # number of overall MSHR misses 751system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312005999 # number of ReadReq MSHR miss cycles 752system.cpu.icache.ReadReq_mshr_miss_latency::total 312005999 # number of ReadReq MSHR miss cycles 753system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312005999 # number of demand (read+write) MSHR miss cycles 754system.cpu.icache.demand_mshr_miss_latency::total 312005999 # number of demand (read+write) MSHR miss cycles 755system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312005999 # number of overall MSHR miss cycles 756system.cpu.icache.overall_mshr_miss_latency::total 312005999 # number of overall MSHR miss cycles 757system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000297 # mshr miss rate for ReadReq accesses 758system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000297 # mshr miss rate for ReadReq accesses 759system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000297 # mshr miss rate for demand accesses 760system.cpu.icache.demand_mshr_miss_rate::total 0.000297 # mshr miss rate for demand accesses 761system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000297 # mshr miss rate for overall accesses 762system.cpu.icache.overall_mshr_miss_rate::total 0.000297 # mshr miss rate for overall accesses 763system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43262.063089 # average ReadReq mshr miss latency 764system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43262.063089 # average ReadReq mshr miss latency 765system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43262.063089 # average overall mshr miss latency 766system.cpu.icache.demand_avg_mshr_miss_latency::total 43262.063089 # average overall mshr miss latency 767system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43262.063089 # average overall mshr miss latency 768system.cpu.icache.overall_avg_mshr_miss_latency::total 43262.063089 # average overall mshr miss latency | 737system.cpu.icache.writebacks::writebacks 5017 # number of writebacks 738system.cpu.icache.writebacks::total 5017 # number of writebacks 739system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2159 # number of ReadReq MSHR hits 740system.cpu.icache.ReadReq_mshr_hits::total 2159 # number of ReadReq MSHR hits 741system.cpu.icache.demand_mshr_hits::cpu.inst 2159 # number of demand (read+write) MSHR hits 742system.cpu.icache.demand_mshr_hits::total 2159 # number of demand (read+write) MSHR hits 743system.cpu.icache.overall_mshr_hits::cpu.inst 2159 # number of overall MSHR hits 744system.cpu.icache.overall_mshr_hits::total 2159 # number of overall MSHR hits 745system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7270 # number of ReadReq MSHR misses 746system.cpu.icache.ReadReq_mshr_misses::total 7270 # number of ReadReq MSHR misses 747system.cpu.icache.demand_mshr_misses::cpu.inst 7270 # number of demand (read+write) MSHR misses 748system.cpu.icache.demand_mshr_misses::total 7270 # number of demand (read+write) MSHR misses 749system.cpu.icache.overall_mshr_misses::cpu.inst 7270 # number of overall MSHR misses 750system.cpu.icache.overall_mshr_misses::total 7270 # number of overall MSHR misses 751system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 311109999 # number of ReadReq MSHR miss cycles 752system.cpu.icache.ReadReq_mshr_miss_latency::total 311109999 # number of ReadReq MSHR miss cycles 753system.cpu.icache.demand_mshr_miss_latency::cpu.inst 311109999 # number of demand (read+write) MSHR miss cycles 754system.cpu.icache.demand_mshr_miss_latency::total 311109999 # number of demand (read+write) MSHR miss cycles 755system.cpu.icache.overall_mshr_miss_latency::cpu.inst 311109999 # number of overall MSHR miss cycles 756system.cpu.icache.overall_mshr_miss_latency::total 311109999 # number of overall MSHR miss cycles 757system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000300 # mshr miss rate for ReadReq accesses 758system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000300 # mshr miss rate for ReadReq accesses 759system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000300 # mshr miss rate for demand accesses 760system.cpu.icache.demand_mshr_miss_rate::total 0.000300 # mshr miss rate for demand accesses 761system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000300 # mshr miss rate for overall accesses 762system.cpu.icache.overall_mshr_miss_rate::total 0.000300 # mshr miss rate for overall accesses 763system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42793.672490 # average ReadReq mshr miss latency 764system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42793.672490 # average ReadReq mshr miss latency 765system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42793.672490 # average overall mshr miss latency 766system.cpu.icache.demand_avg_mshr_miss_latency::total 42793.672490 # average overall mshr miss latency 767system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42793.672490 # average overall mshr miss latency 768system.cpu.icache.overall_avg_mshr_miss_latency::total 42793.672490 # average overall mshr miss latency |
| 769system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 770system.cpu.l2cache.tags.replacements 0 # number of replacements | 769system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 770system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 771system.cpu.l2cache.tags.tagsinuse 2583.684571 # Cycle average of tags in use 772system.cpu.l2cache.tags.total_refs 8457 # Total number of references to valid blocks. 773system.cpu.l2cache.tags.sampled_refs 3872 # Sample count of references to valid blocks. 774system.cpu.l2cache.tags.avg_refs 2.184143 # Average number of references to valid blocks. | 771system.cpu.l2cache.tags.tagsinuse 2581.252539 # Cycle average of tags in use 772system.cpu.l2cache.tags.total_refs 8528 # Total number of references to valid blocks. 773system.cpu.l2cache.tags.sampled_refs 3879 # Sample count of references to valid blocks. 774system.cpu.l2cache.tags.avg_refs 2.198505 # Average number of references to valid blocks. |
| 775system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 775system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 776system.cpu.l2cache.tags.occ_blocks::writebacks 1.785192 # Average occupied blocks per requestor 777system.cpu.l2cache.tags.occ_blocks::cpu.inst 2278.815860 # Average occupied blocks per requestor 778system.cpu.l2cache.tags.occ_blocks::cpu.data 303.083519 # Average occupied blocks per requestor | 776system.cpu.l2cache.tags.occ_blocks::writebacks 1.770890 # Average occupied blocks per requestor 777system.cpu.l2cache.tags.occ_blocks::cpu.inst 2276.984589 # Average occupied blocks per requestor 778system.cpu.l2cache.tags.occ_blocks::cpu.data 302.497060 # Average occupied blocks per requestor |
| 779system.cpu.l2cache.tags.occ_percent::writebacks 0.000054 # Average percentage of cache occupancy | 779system.cpu.l2cache.tags.occ_percent::writebacks 0.000054 # Average percentage of cache occupancy |
| 780system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069544 # Average percentage of cache occupancy 781system.cpu.l2cache.tags.occ_percent::cpu.data 0.009249 # Average percentage of cache occupancy 782system.cpu.l2cache.tags.occ_percent::total 0.078848 # Average percentage of cache occupancy 783system.cpu.l2cache.tags.occ_task_id_blocks::1024 3872 # Occupied blocks per task id | 780system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069488 # Average percentage of cache occupancy 781system.cpu.l2cache.tags.occ_percent::cpu.data 0.009231 # Average percentage of cache occupancy 782system.cpu.l2cache.tags.occ_percent::total 0.078774 # Average percentage of cache occupancy 783system.cpu.l2cache.tags.occ_task_id_blocks::1024 3879 # Occupied blocks per task id |
| 784system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id | 784system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id |
| 785system.cpu.l2cache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id 786system.cpu.l2cache.tags.age_task_id_blocks_1024::2 991 # Occupied blocks per task id 787system.cpu.l2cache.tags.age_task_id_blocks_1024::3 38 # Occupied blocks per task id 788system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2610 # Occupied blocks per task id 789system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118164 # Percentage of cache occupancy per task id 790system.cpu.l2cache.tags.tag_accesses 118500 # Number of tag accesses 791system.cpu.l2cache.tags.data_accesses 118500 # Number of data accesses | 785system.cpu.l2cache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id 786system.cpu.l2cache.tags.age_task_id_blocks_1024::2 999 # Occupied blocks per task id 787system.cpu.l2cache.tags.age_task_id_blocks_1024::3 41 # Occupied blocks per task id 788system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2611 # Occupied blocks per task id 789system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118378 # Percentage of cache occupancy per task id 790system.cpu.l2cache.tags.tag_accesses 119261 # Number of tag accesses 791system.cpu.l2cache.tags.data_accesses 119261 # Number of data accesses |
| 792system.cpu.l2cache.WritebackDirty_hits::writebacks 10 # number of WritebackDirty hits 793system.cpu.l2cache.WritebackDirty_hits::total 10 # number of WritebackDirty hits | 792system.cpu.l2cache.WritebackDirty_hits::writebacks 10 # number of WritebackDirty hits 793system.cpu.l2cache.WritebackDirty_hits::total 10 # number of WritebackDirty hits |
| 794system.cpu.l2cache.WritebackClean_hits::writebacks 4883 # number of WritebackClean hits 795system.cpu.l2cache.WritebackClean_hits::total 4883 # number of WritebackClean hits | 794system.cpu.l2cache.WritebackClean_hits::writebacks 4917 # number of WritebackClean hits 795system.cpu.l2cache.WritebackClean_hits::total 4917 # number of WritebackClean hits 796system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 797system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits |
| 796system.cpu.l2cache.ReadExReq_hits::cpu.data 6 # number of ReadExReq hits 797system.cpu.l2cache.ReadExReq_hits::total 6 # number of ReadExReq hits | 798system.cpu.l2cache.ReadExReq_hits::cpu.data 6 # number of ReadExReq hits 799system.cpu.l2cache.ReadExReq_hits::total 6 # number of ReadExReq hits |
| 798system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3495 # number of ReadCleanReq hits 799system.cpu.l2cache.ReadCleanReq_hits::total 3495 # number of ReadCleanReq hits | 800system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3531 # number of ReadCleanReq hits 801system.cpu.l2cache.ReadCleanReq_hits::total 3531 # number of ReadCleanReq hits |
| 800system.cpu.l2cache.ReadSharedReq_hits::cpu.data 35 # number of ReadSharedReq hits 801system.cpu.l2cache.ReadSharedReq_hits::total 35 # number of ReadSharedReq hits | 802system.cpu.l2cache.ReadSharedReq_hits::cpu.data 35 # number of ReadSharedReq hits 803system.cpu.l2cache.ReadSharedReq_hits::total 35 # number of ReadSharedReq hits |
| 802system.cpu.l2cache.demand_hits::cpu.inst 3495 # number of demand (read+write) hits | 804system.cpu.l2cache.demand_hits::cpu.inst 3531 # number of demand (read+write) hits |
| 803system.cpu.l2cache.demand_hits::cpu.data 41 # number of demand (read+write) hits | 805system.cpu.l2cache.demand_hits::cpu.data 41 # number of demand (read+write) hits |
| 804system.cpu.l2cache.demand_hits::total 3536 # number of demand (read+write) hits 805system.cpu.l2cache.overall_hits::cpu.inst 3495 # number of overall hits | 806system.cpu.l2cache.demand_hits::total 3572 # number of demand (read+write) hits 807system.cpu.l2cache.overall_hits::cpu.inst 3531 # number of overall hits |
| 806system.cpu.l2cache.overall_hits::cpu.data 41 # number of overall hits | 808system.cpu.l2cache.overall_hits::cpu.data 41 # number of overall hits |
| 807system.cpu.l2cache.overall_hits::total 3536 # number of overall hits 808system.cpu.l2cache.UpgradeReq_misses::cpu.data 261 # number of UpgradeReq misses 809system.cpu.l2cache.UpgradeReq_misses::total 261 # number of UpgradeReq misses 810system.cpu.l2cache.ReadExReq_misses::cpu.data 1534 # number of ReadExReq misses 811system.cpu.l2cache.ReadExReq_misses::total 1534 # number of ReadExReq misses 812system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3454 # number of ReadCleanReq misses 813system.cpu.l2cache.ReadCleanReq_misses::total 3454 # number of ReadCleanReq misses 814system.cpu.l2cache.ReadSharedReq_misses::cpu.data 418 # number of ReadSharedReq misses 815system.cpu.l2cache.ReadSharedReq_misses::total 418 # number of ReadSharedReq misses 816system.cpu.l2cache.demand_misses::cpu.inst 3454 # number of demand (read+write) misses 817system.cpu.l2cache.demand_misses::cpu.data 1952 # number of demand (read+write) misses 818system.cpu.l2cache.demand_misses::total 5406 # number of demand (read+write) misses 819system.cpu.l2cache.overall_misses::cpu.inst 3454 # number of overall misses 820system.cpu.l2cache.overall_misses::cpu.data 1952 # number of overall misses 821system.cpu.l2cache.overall_misses::total 5406 # number of overall misses 822system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 114869500 # number of ReadExReq miss cycles 823system.cpu.l2cache.ReadExReq_miss_latency::total 114869500 # number of ReadExReq miss cycles 824system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 263804000 # number of ReadCleanReq miss cycles 825system.cpu.l2cache.ReadCleanReq_miss_latency::total 263804000 # number of ReadCleanReq miss cycles 826system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35120500 # number of ReadSharedReq miss cycles 827system.cpu.l2cache.ReadSharedReq_miss_latency::total 35120500 # number of ReadSharedReq miss cycles 828system.cpu.l2cache.demand_miss_latency::cpu.inst 263804000 # number of demand (read+write) miss cycles 829system.cpu.l2cache.demand_miss_latency::cpu.data 149990000 # number of demand (read+write) miss cycles 830system.cpu.l2cache.demand_miss_latency::total 413794000 # number of demand (read+write) miss cycles 831system.cpu.l2cache.overall_miss_latency::cpu.inst 263804000 # number of overall miss cycles 832system.cpu.l2cache.overall_miss_latency::cpu.data 149990000 # number of overall miss cycles 833system.cpu.l2cache.overall_miss_latency::total 413794000 # number of overall miss cycles | 809system.cpu.l2cache.overall_hits::total 3572 # number of overall hits 810system.cpu.l2cache.UpgradeReq_misses::cpu.data 276 # number of UpgradeReq misses 811system.cpu.l2cache.UpgradeReq_misses::total 276 # number of UpgradeReq misses 812system.cpu.l2cache.ReadExReq_misses::cpu.data 1535 # number of ReadExReq misses 813system.cpu.l2cache.ReadExReq_misses::total 1535 # number of ReadExReq misses 814system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3460 # number of ReadCleanReq misses 815system.cpu.l2cache.ReadCleanReq_misses::total 3460 # number of ReadCleanReq misses 816system.cpu.l2cache.ReadSharedReq_misses::cpu.data 419 # number of ReadSharedReq misses 817system.cpu.l2cache.ReadSharedReq_misses::total 419 # number of ReadSharedReq misses 818system.cpu.l2cache.demand_misses::cpu.inst 3460 # number of demand (read+write) misses 819system.cpu.l2cache.demand_misses::cpu.data 1954 # number of demand (read+write) misses 820system.cpu.l2cache.demand_misses::total 5414 # number of demand (read+write) misses 821system.cpu.l2cache.overall_misses::cpu.inst 3460 # number of overall misses 822system.cpu.l2cache.overall_misses::cpu.data 1954 # number of overall misses 823system.cpu.l2cache.overall_misses::total 5414 # number of overall misses 824system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 115784500 # number of ReadExReq miss cycles 825system.cpu.l2cache.ReadExReq_miss_latency::total 115784500 # number of ReadExReq miss cycles 826system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 262406500 # number of ReadCleanReq miss cycles 827system.cpu.l2cache.ReadCleanReq_miss_latency::total 262406500 # number of ReadCleanReq miss cycles 828system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 34977000 # number of ReadSharedReq miss cycles 829system.cpu.l2cache.ReadSharedReq_miss_latency::total 34977000 # number of ReadSharedReq miss cycles 830system.cpu.l2cache.demand_miss_latency::cpu.inst 262406500 # number of demand (read+write) miss cycles 831system.cpu.l2cache.demand_miss_latency::cpu.data 150761500 # number of demand (read+write) miss cycles 832system.cpu.l2cache.demand_miss_latency::total 413168000 # number of demand (read+write) miss cycles 833system.cpu.l2cache.overall_miss_latency::cpu.inst 262406500 # number of overall miss cycles 834system.cpu.l2cache.overall_miss_latency::cpu.data 150761500 # number of overall miss cycles 835system.cpu.l2cache.overall_miss_latency::total 413168000 # number of overall miss cycles |
| 834system.cpu.l2cache.WritebackDirty_accesses::writebacks 10 # number of WritebackDirty accesses(hits+misses) 835system.cpu.l2cache.WritebackDirty_accesses::total 10 # number of WritebackDirty accesses(hits+misses) | 836system.cpu.l2cache.WritebackDirty_accesses::writebacks 10 # number of WritebackDirty accesses(hits+misses) 837system.cpu.l2cache.WritebackDirty_accesses::total 10 # number of WritebackDirty accesses(hits+misses) |
| 836system.cpu.l2cache.WritebackClean_accesses::writebacks 4883 # number of WritebackClean accesses(hits+misses) 837system.cpu.l2cache.WritebackClean_accesses::total 4883 # number of WritebackClean accesses(hits+misses) 838system.cpu.l2cache.UpgradeReq_accesses::cpu.data 261 # number of UpgradeReq accesses(hits+misses) 839system.cpu.l2cache.UpgradeReq_accesses::total 261 # number of UpgradeReq accesses(hits+misses) 840system.cpu.l2cache.ReadExReq_accesses::cpu.data 1540 # number of ReadExReq accesses(hits+misses) 841system.cpu.l2cache.ReadExReq_accesses::total 1540 # number of ReadExReq accesses(hits+misses) 842system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6949 # number of ReadCleanReq accesses(hits+misses) 843system.cpu.l2cache.ReadCleanReq_accesses::total 6949 # number of ReadCleanReq accesses(hits+misses) 844system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 453 # number of ReadSharedReq accesses(hits+misses) 845system.cpu.l2cache.ReadSharedReq_accesses::total 453 # number of ReadSharedReq accesses(hits+misses) 846system.cpu.l2cache.demand_accesses::cpu.inst 6949 # number of demand (read+write) accesses 847system.cpu.l2cache.demand_accesses::cpu.data 1993 # number of demand (read+write) accesses 848system.cpu.l2cache.demand_accesses::total 8942 # number of demand (read+write) accesses 849system.cpu.l2cache.overall_accesses::cpu.inst 6949 # number of overall (read+write) accesses 850system.cpu.l2cache.overall_accesses::cpu.data 1993 # number of overall (read+write) accesses 851system.cpu.l2cache.overall_accesses::total 8942 # number of overall (read+write) accesses 852system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 853system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 854system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996104 # miss rate for ReadExReq accesses 855system.cpu.l2cache.ReadExReq_miss_rate::total 0.996104 # miss rate for ReadExReq accesses 856system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.497050 # miss rate for ReadCleanReq accesses 857system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.497050 # miss rate for ReadCleanReq accesses 858system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.922737 # miss rate for ReadSharedReq accesses 859system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.922737 # miss rate for ReadSharedReq accesses 860system.cpu.l2cache.demand_miss_rate::cpu.inst 0.497050 # miss rate for demand accesses 861system.cpu.l2cache.demand_miss_rate::cpu.data 0.979428 # miss rate for demand accesses 862system.cpu.l2cache.demand_miss_rate::total 0.604563 # miss rate for demand accesses 863system.cpu.l2cache.overall_miss_rate::cpu.inst 0.497050 # miss rate for overall accesses 864system.cpu.l2cache.overall_miss_rate::cpu.data 0.979428 # miss rate for overall accesses 865system.cpu.l2cache.overall_miss_rate::total 0.604563 # miss rate for overall accesses 866system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74882.333768 # average ReadExReq miss latency 867system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74882.333768 # average ReadExReq miss latency 868system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76376.375217 # average ReadCleanReq miss latency 869system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76376.375217 # average ReadCleanReq miss latency 870system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84020.334928 # average ReadSharedReq miss latency 871system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84020.334928 # average ReadSharedReq miss latency 872system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76376.375217 # average overall miss latency 873system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76839.139344 # average overall miss latency 874system.cpu.l2cache.demand_avg_miss_latency::total 76543.470218 # average overall miss latency 875system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76376.375217 # average overall miss latency 876system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76839.139344 # average overall miss latency 877system.cpu.l2cache.overall_avg_miss_latency::total 76543.470218 # average overall miss latency | 838system.cpu.l2cache.WritebackClean_accesses::writebacks 4917 # number of WritebackClean accesses(hits+misses) 839system.cpu.l2cache.WritebackClean_accesses::total 4917 # number of WritebackClean accesses(hits+misses) 840system.cpu.l2cache.UpgradeReq_accesses::cpu.data 277 # number of UpgradeReq accesses(hits+misses) 841system.cpu.l2cache.UpgradeReq_accesses::total 277 # number of UpgradeReq accesses(hits+misses) 842system.cpu.l2cache.ReadExReq_accesses::cpu.data 1541 # number of ReadExReq accesses(hits+misses) 843system.cpu.l2cache.ReadExReq_accesses::total 1541 # number of ReadExReq accesses(hits+misses) 844system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6991 # number of ReadCleanReq accesses(hits+misses) 845system.cpu.l2cache.ReadCleanReq_accesses::total 6991 # number of ReadCleanReq accesses(hits+misses) 846system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 454 # number of ReadSharedReq accesses(hits+misses) 847system.cpu.l2cache.ReadSharedReq_accesses::total 454 # number of ReadSharedReq accesses(hits+misses) 848system.cpu.l2cache.demand_accesses::cpu.inst 6991 # number of demand (read+write) accesses 849system.cpu.l2cache.demand_accesses::cpu.data 1995 # number of demand (read+write) accesses 850system.cpu.l2cache.demand_accesses::total 8986 # number of demand (read+write) accesses 851system.cpu.l2cache.overall_accesses::cpu.inst 6991 # number of overall (read+write) accesses 852system.cpu.l2cache.overall_accesses::cpu.data 1995 # number of overall (read+write) accesses 853system.cpu.l2cache.overall_accesses::total 8986 # number of overall (read+write) accesses 854system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.996390 # miss rate for UpgradeReq accesses 855system.cpu.l2cache.UpgradeReq_miss_rate::total 0.996390 # miss rate for UpgradeReq accesses 856system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996106 # miss rate for ReadExReq accesses 857system.cpu.l2cache.ReadExReq_miss_rate::total 0.996106 # miss rate for ReadExReq accesses 858system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.494922 # miss rate for ReadCleanReq accesses 859system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.494922 # miss rate for ReadCleanReq accesses 860system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.922907 # miss rate for ReadSharedReq accesses 861system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.922907 # miss rate for ReadSharedReq accesses 862system.cpu.l2cache.demand_miss_rate::cpu.inst 0.494922 # miss rate for demand accesses 863system.cpu.l2cache.demand_miss_rate::cpu.data 0.979449 # miss rate for demand accesses 864system.cpu.l2cache.demand_miss_rate::total 0.602493 # miss rate for demand accesses 865system.cpu.l2cache.overall_miss_rate::cpu.inst 0.494922 # miss rate for overall accesses 866system.cpu.l2cache.overall_miss_rate::cpu.data 0.979449 # miss rate for overall accesses 867system.cpu.l2cache.overall_miss_rate::total 0.602493 # miss rate for overall accesses 868system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75429.641694 # average ReadExReq miss latency 869system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75429.641694 # average ReadExReq miss latency 870system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75840.028902 # average ReadCleanReq miss latency 871system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75840.028902 # average ReadCleanReq miss latency 872system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83477.326969 # average ReadSharedReq miss latency 873system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83477.326969 # average ReadSharedReq miss latency 874system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75840.028902 # average overall miss latency 875system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77155.322416 # average overall miss latency 876system.cpu.l2cache.demand_avg_miss_latency::total 76314.739564 # average overall miss latency 877system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75840.028902 # average overall miss latency 878system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77155.322416 # average overall miss latency 879system.cpu.l2cache.overall_avg_miss_latency::total 76314.739564 # average overall miss latency |
| 878system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 879system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 880system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 881system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 882system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 883system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 884system.cpu.l2cache.fast_writes 0 # number of fast writes performed 885system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 880system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 881system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 882system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 883system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 884system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 885system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 886system.cpu.l2cache.fast_writes 0 # number of fast writes performed 887system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 886system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 261 # number of UpgradeReq MSHR misses 887system.cpu.l2cache.UpgradeReq_mshr_misses::total 261 # number of UpgradeReq MSHR misses 888system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1534 # number of ReadExReq MSHR misses 889system.cpu.l2cache.ReadExReq_mshr_misses::total 1534 # number of ReadExReq MSHR misses 890system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3454 # number of ReadCleanReq MSHR misses 891system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3454 # number of ReadCleanReq MSHR misses 892system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 418 # number of ReadSharedReq MSHR misses 893system.cpu.l2cache.ReadSharedReq_mshr_misses::total 418 # number of ReadSharedReq MSHR misses 894system.cpu.l2cache.demand_mshr_misses::cpu.inst 3454 # number of demand (read+write) MSHR misses 895system.cpu.l2cache.demand_mshr_misses::cpu.data 1952 # number of demand (read+write) MSHR misses 896system.cpu.l2cache.demand_mshr_misses::total 5406 # number of demand (read+write) MSHR misses 897system.cpu.l2cache.overall_mshr_misses::cpu.inst 3454 # number of overall MSHR misses 898system.cpu.l2cache.overall_mshr_misses::cpu.data 1952 # number of overall MSHR misses 899system.cpu.l2cache.overall_mshr_misses::total 5406 # number of overall MSHR misses 900system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5671500 # number of UpgradeReq MSHR miss cycles 901system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5671500 # number of UpgradeReq MSHR miss cycles 902system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 99529500 # number of ReadExReq MSHR miss cycles 903system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 99529500 # number of ReadExReq MSHR miss cycles 904system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 229284000 # number of ReadCleanReq MSHR miss cycles 905system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 229284000 # number of ReadCleanReq MSHR miss cycles 906system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30940500 # number of ReadSharedReq MSHR miss cycles 907system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30940500 # number of ReadSharedReq MSHR miss cycles 908system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 229284000 # number of demand (read+write) MSHR miss cycles 909system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 130470000 # number of demand (read+write) MSHR miss cycles 910system.cpu.l2cache.demand_mshr_miss_latency::total 359754000 # number of demand (read+write) MSHR miss cycles 911system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 229284000 # number of overall MSHR miss cycles 912system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 130470000 # number of overall MSHR miss cycles 913system.cpu.l2cache.overall_mshr_miss_latency::total 359754000 # number of overall MSHR miss cycles 914system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 915system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 916system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996104 # 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mshr miss rate for overall accesses 927system.cpu.l2cache.overall_mshr_miss_rate::total 0.604563 # mshr miss rate for overall accesses 928system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21729.885057 # average UpgradeReq mshr miss latency 929system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21729.885057 # average UpgradeReq mshr miss latency 930system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64882.333768 # average ReadExReq mshr miss latency 931system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64882.333768 # average ReadExReq mshr miss latency 932system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66382.165605 # average ReadCleanReq mshr miss latency 933system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66382.165605 # average ReadCleanReq mshr miss latency 934system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74020.334928 # average ReadSharedReq mshr miss latency 935system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74020.334928 # average ReadSharedReq mshr miss latency 936system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66382.165605 # average overall mshr miss latency 937system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66839.139344 # average overall mshr miss latency 938system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66547.169811 # average overall mshr miss latency 939system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66382.165605 # average overall mshr miss latency 940system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66839.139344 # average overall mshr miss latency 941system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66547.169811 # average overall mshr miss latency | 888system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 276 # number of UpgradeReq MSHR misses 889system.cpu.l2cache.UpgradeReq_mshr_misses::total 276 # number of UpgradeReq MSHR misses 890system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1535 # number of ReadExReq MSHR misses 891system.cpu.l2cache.ReadExReq_mshr_misses::total 1535 # number of ReadExReq MSHR misses 892system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3460 # number of ReadCleanReq MSHR misses 893system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3460 # number of ReadCleanReq MSHR misses 894system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 419 # number of ReadSharedReq MSHR misses 895system.cpu.l2cache.ReadSharedReq_mshr_misses::total 419 # number of ReadSharedReq MSHR misses 896system.cpu.l2cache.demand_mshr_misses::cpu.inst 3460 # number of demand (read+write) MSHR misses 897system.cpu.l2cache.demand_mshr_misses::cpu.data 1954 # number of demand (read+write) MSHR misses 898system.cpu.l2cache.demand_mshr_misses::total 5414 # number of demand (read+write) MSHR misses 899system.cpu.l2cache.overall_mshr_misses::cpu.inst 3460 # number of overall MSHR misses 900system.cpu.l2cache.overall_mshr_misses::cpu.data 1954 # number of overall MSHR misses 901system.cpu.l2cache.overall_mshr_misses::total 5414 # number of overall MSHR misses 902system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5237000 # number of UpgradeReq MSHR miss cycles 903system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5237000 # number of UpgradeReq MSHR miss cycles 904system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 100434500 # number of ReadExReq MSHR miss cycles 905system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 100434500 # number of ReadExReq MSHR miss cycles 906system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 227816500 # number of ReadCleanReq MSHR miss cycles 907system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 227816500 # number of ReadCleanReq MSHR miss cycles 908system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30787000 # number of ReadSharedReq MSHR miss cycles 909system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30787000 # number of ReadSharedReq MSHR miss cycles 910system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 227816500 # number of demand (read+write) MSHR miss cycles 911system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131221500 # number of demand (read+write) MSHR miss cycles 912system.cpu.l2cache.demand_mshr_miss_latency::total 359038000 # number of demand (read+write) MSHR miss cycles 913system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 227816500 # number of overall MSHR miss cycles 914system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131221500 # number of overall MSHR miss cycles 915system.cpu.l2cache.overall_mshr_miss_latency::total 359038000 # number of overall MSHR miss cycles 916system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.996390 # mshr miss rate for UpgradeReq accesses 917system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.996390 # mshr miss rate for UpgradeReq accesses 918system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996106 # mshr miss rate for ReadExReq accesses 919system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996106 # mshr miss rate for ReadExReq accesses 920system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.494922 # mshr miss rate for ReadCleanReq accesses 921system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.494922 # mshr miss rate for ReadCleanReq accesses 922system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.922907 # mshr miss rate for ReadSharedReq accesses 923system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.922907 # mshr miss rate for ReadSharedReq accesses 924system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.494922 # mshr miss rate for demand accesses 925system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.979449 # mshr miss rate for demand accesses 926system.cpu.l2cache.demand_mshr_miss_rate::total 0.602493 # mshr miss rate for demand accesses 927system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.494922 # mshr miss rate for overall accesses 928system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.979449 # mshr miss rate for overall accesses 929system.cpu.l2cache.overall_mshr_miss_rate::total 0.602493 # mshr miss rate for overall accesses 930system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18974.637681 # average UpgradeReq mshr miss latency 931system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18974.637681 # average UpgradeReq mshr miss latency 932system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65429.641694 # average ReadExReq mshr miss latency 933system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65429.641694 # average ReadExReq mshr miss latency 934system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65842.919075 # average ReadCleanReq mshr miss latency 935system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65842.919075 # average ReadCleanReq mshr miss latency 936system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73477.326969 # average ReadSharedReq mshr miss latency 937system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73477.326969 # average ReadSharedReq mshr miss latency 938system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65842.919075 # average overall mshr miss latency 939system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67155.322416 # average overall mshr miss latency 940system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66316.586627 # average overall mshr miss latency 941system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65842.919075 # average overall mshr miss latency 942system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67155.322416 # average overall mshr miss latency 943system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66316.586627 # average overall mshr miss latency |
| 942system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 944system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 943system.cpu.toL2Bus.snoop_filter.tot_requests 14491 # Total number of requests made to the snoop filter. 944system.cpu.toL2Bus.snoop_filter.hit_single_requests 5309 # Number of requests hitting in the snoop filter with a single holder of the requested data. 945system.cpu.toL2Bus.snoop_filter.hit_multi_requests 353 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. | 945system.cpu.toL2Bus.snoop_filter.tot_requests 14610 # Total number of requests made to the snoop filter. 946system.cpu.toL2Bus.snoop_filter.hit_single_requests 5368 # Number of requests hitting in the snoop filter with a single holder of the requested data. 947system.cpu.toL2Bus.snoop_filter.hit_multi_requests 377 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 946system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 947system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 948system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 948system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 949system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 950system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 949system.cpu.toL2Bus.trans_dist::ReadResp 7663 # Transaction distribution | 951system.cpu.toL2Bus.trans_dist::ReadResp 7723 # Transaction distribution |
| 950system.cpu.toL2Bus.trans_dist::WritebackDirty 10 # Transaction distribution | 952system.cpu.toL2Bus.trans_dist::WritebackDirty 10 # Transaction distribution |
| 951system.cpu.toL2Bus.trans_dist::WritebackClean 4883 # Transaction distribution 952system.cpu.toL2Bus.trans_dist::CleanEvict 40 # Transaction distribution 953system.cpu.toL2Bus.trans_dist::UpgradeReq 261 # Transaction distribution 954system.cpu.toL2Bus.trans_dist::UpgradeResp 261 # Transaction distribution 955system.cpu.toL2Bus.trans_dist::ReadExReq 1540 # Transaction distribution 956system.cpu.toL2Bus.trans_dist::ReadExResp 1540 # Transaction distribution 957system.cpu.toL2Bus.trans_dist::ReadCleanReq 7212 # Transaction distribution 958system.cpu.toL2Bus.trans_dist::ReadSharedReq 453 # Transaction distribution 959system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19042 # Packet count per connected master and slave (bytes) 960system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4558 # Packet count per connected master and slave (bytes) 961system.cpu.toL2Bus.pkt_count::total 23600 # Packet count per connected master and slave (bytes) 962system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 757120 # Cumulative packet size per connected master and slave (bytes) 963system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128192 # Cumulative packet size per connected master and slave (bytes) 964system.cpu.toL2Bus.pkt_size::total 885312 # Cumulative packet size per connected master and slave (bytes) 965system.cpu.toL2Bus.snoops 263 # Total snoops (count) 966system.cpu.toL2Bus.snoop_fanout::samples 9466 # Request fanout histogram 967system.cpu.toL2Bus.snoop_fanout::mean 0.067293 # Request fanout histogram 968system.cpu.toL2Bus.snoop_fanout::stdev 0.250543 # Request fanout histogram | 953system.cpu.toL2Bus.trans_dist::WritebackClean 5017 # Transaction distribution 954system.cpu.toL2Bus.trans_dist::CleanEvict 41 # Transaction distribution 955system.cpu.toL2Bus.trans_dist::UpgradeReq 277 # Transaction distribution 956system.cpu.toL2Bus.trans_dist::UpgradeResp 277 # Transaction distribution 957system.cpu.toL2Bus.trans_dist::ReadExReq 1541 # Transaction distribution 958system.cpu.toL2Bus.trans_dist::ReadExResp 1541 # Transaction distribution 959system.cpu.toL2Bus.trans_dist::ReadCleanReq 7270 # Transaction distribution 960system.cpu.toL2Bus.trans_dist::ReadSharedReq 454 # Transaction distribution 961system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19277 # Packet count per connected master and slave (bytes) 962system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4595 # Packet count per connected master and slave (bytes) 963system.cpu.toL2Bus.pkt_count::total 23872 # Packet count per connected master and slave (bytes) 964system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 768448 # Cumulative packet size per connected master and slave (bytes) 965system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128320 # Cumulative packet size per connected master and slave (bytes) 966system.cpu.toL2Bus.pkt_size::total 896768 # Cumulative packet size per connected master and slave (bytes) 967system.cpu.toL2Bus.snoops 279 # Total snoops (count) 968system.cpu.toL2Bus.snoop_fanout::samples 9542 # Request fanout histogram 969system.cpu.toL2Bus.snoop_fanout::mean 0.070845 # Request fanout histogram 970system.cpu.toL2Bus.snoop_fanout::stdev 0.256579 # Request fanout histogram |
| 969system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 971system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 970system.cpu.toL2Bus.snoop_fanout::0 8829 93.27% 93.27% # Request fanout histogram 971system.cpu.toL2Bus.snoop_fanout::1 637 6.73% 100.00% # Request fanout histogram | 972system.cpu.toL2Bus.snoop_fanout::0 8866 92.92% 92.92% # Request fanout histogram 973system.cpu.toL2Bus.snoop_fanout::1 676 7.08% 100.00% # Request fanout histogram |
| 972system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 973system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 974system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 975system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 974system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 975system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 976system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 977system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 976system.cpu.toL2Bus.snoop_fanout::total 9466 # Request fanout histogram 977system.cpu.toL2Bus.reqLayer0.occupancy 12229500 # Layer occupancy (ticks) | 978system.cpu.toL2Bus.snoop_fanout::total 9542 # Request fanout histogram 979system.cpu.toL2Bus.reqLayer0.occupancy 12332000 # Layer occupancy (ticks) |
| 978system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 980system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 979system.cpu.toL2Bus.respLayer0.occupancy 10815000 # Layer occupancy (ticks) | 981system.cpu.toL2Bus.respLayer0.occupancy 10903500 # Layer occupancy (ticks) |
| 980system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 982system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 981system.cpu.toL2Bus.respLayer1.occupancy 3120998 # Layer occupancy (ticks) | 983system.cpu.toL2Bus.respLayer1.occupancy 3131998 # Layer occupancy (ticks) |
| 982system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 984system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 983system.membus.trans_dist::ReadResp 3870 # Transaction distribution 984system.membus.trans_dist::UpgradeReq 261 # Transaction distribution 985system.membus.trans_dist::UpgradeResp 261 # Transaction distribution 986system.membus.trans_dist::ReadExReq 1534 # Transaction distribution 987system.membus.trans_dist::ReadExResp 1534 # Transaction distribution 988system.membus.trans_dist::ReadSharedReq 3871 # Transaction distribution 989system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11331 # Packet count per connected master and slave (bytes) 990system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11331 # Packet count per connected master and slave (bytes) 991system.membus.pkt_count::total 11331 # Packet count per connected master and slave (bytes) 992system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 345856 # Cumulative packet size per connected master and slave (bytes) 993system.membus.pkt_size_system.cpu.l2cache.mem_side::total 345856 # Cumulative packet size per connected master and slave (bytes) 994system.membus.pkt_size::total 345856 # Cumulative packet size per connected master and slave (bytes) | 985system.membus.trans_dist::ReadResp 3878 # Transaction distribution 986system.membus.trans_dist::UpgradeReq 276 # Transaction distribution 987system.membus.trans_dist::ReadExReq 1535 # Transaction distribution 988system.membus.trans_dist::ReadExResp 1535 # Transaction distribution 989system.membus.trans_dist::ReadSharedReq 3878 # Transaction distribution 990system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11102 # Packet count per connected master and slave (bytes) 991system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11102 # Packet count per connected master and slave (bytes) 992system.membus.pkt_count::total 11102 # Packet count per connected master and slave (bytes) 993system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 346432 # Cumulative packet size per connected master and slave (bytes) 994system.membus.pkt_size_system.cpu.l2cache.mem_side::total 346432 # Cumulative packet size per connected master and slave (bytes) 995system.membus.pkt_size::total 346432 # Cumulative packet size per connected master and slave (bytes) |
| 995system.membus.snoops 0 # Total snoops (count) | 996system.membus.snoops 0 # Total snoops (count) |
| 996system.membus.snoop_fanout::samples 5666 # Request fanout histogram | 997system.membus.snoop_fanout::samples 5689 # Request fanout histogram |
| 997system.membus.snoop_fanout::mean 0 # Request fanout histogram 998system.membus.snoop_fanout::stdev 0 # Request fanout histogram 999system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 998system.membus.snoop_fanout::mean 0 # Request fanout histogram 999system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1000system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1000system.membus.snoop_fanout::0 5666 100.00% 100.00% # Request fanout histogram | 1001system.membus.snoop_fanout::0 5689 100.00% 100.00% # Request fanout histogram |
| 1001system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1002system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1003system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1004system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 1002system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1003system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1004system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1005system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 1005system.membus.snoop_fanout::total 5666 # Request fanout histogram 1006system.membus.reqLayer0.occupancy 6923000 # Layer occupancy (ticks) | 1006system.membus.snoop_fanout::total 5689 # Request fanout histogram 1007system.membus.reqLayer0.occupancy 6955500 # Layer occupancy (ticks) |
| 1007system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1008system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1008system.membus.respLayer1.occupancy 29158989 # Layer occupancy (ticks) | 1009system.membus.respLayer1.occupancy 28681250 # Layer occupancy (ticks) |
| 1009system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 1010 1011---------- End Simulation Statistics ---------- | 1010system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 1011 1012---------- End Simulation Statistics ---------- |