| stats.txt (11103:38f6188421e0) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.079147 # Number of seconds simulated 4sim_ticks 79147317000 # Number of ticks simulated 5final_tick 79147317000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.079190 # Number of seconds simulated 4sim_ticks 79190347500 # Number of ticks simulated 5final_tick 79190347500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 70947 # Simulator instruction rate (inst/s) 8host_op_rate 118914 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 42517019 # Simulator tick rate (ticks/s) 10host_mem_usage 343896 # Number of bytes of host memory used 11host_seconds 1861.54 # Real time elapsed on the host | 7host_inst_rate 91850 # Simulator instruction rate (inst/s) 8host_op_rate 153949 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 55073733 # Simulator tick rate (ticks/s) 10host_mem_usage 350132 # Number of bytes of host memory used 11host_seconds 1437.90 # Real time elapsed on the host |
| 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221363384 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221363384 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 221376 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 124928 # Number of bytes read from this memory 18system.physmem.bytes_read::total 346304 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 221376 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 221376 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 3459 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1952 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 5411 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 2797012 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 1578424 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 4375436 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 2797012 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 2797012 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 2797012 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 1578424 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 4375436 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 5413 # Number of read requests accepted | 16system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 125120 # Number of bytes read from this memory 18system.physmem.bytes_read::total 345920 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 220800 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 220800 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 3450 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1955 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 5405 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 2788219 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 1579991 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 4368209 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 2788219 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 2788219 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 2788219 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 1579991 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 4368209 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 5405 # Number of read requests accepted |
| 33system.physmem.writeReqs 0 # Number of write requests accepted | 33system.physmem.writeReqs 0 # Number of write requests accepted |
| 34system.physmem.readBursts 5413 # Number of DRAM read bursts, including those serviced by the write queue | 34system.physmem.readBursts 5405 # Number of DRAM read bursts, including those serviced by the write queue |
| 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 36system.physmem.bytesReadDRAM 346304 # Total number of bytes read from DRAM | 36system.physmem.bytesReadDRAM 345920 # Total number of bytes read from DRAM |
| 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 39system.physmem.bytesReadSys 346432 # Total read bytes from the system interface side | 39system.physmem.bytesReadSys 345920 # Total read bytes from the system interface side |
| 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one | 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| 43system.physmem.neitherReadNorWriteReqs 303 # Number of requests that are neither read nor write | 43system.physmem.neitherReadNorWriteReqs 296 # Number of requests that are neither read nor write |
| 44system.physmem.perBankRdBursts::0 299 # Per bank write bursts | 44system.physmem.perBankRdBursts::0 299 # Per bank write bursts |
| 45system.physmem.perBankRdBursts::1 344 # Per bank write bursts | 45system.physmem.perBankRdBursts::1 345 # Per bank write bursts |
| 46system.physmem.perBankRdBursts::2 461 # Per bank write bursts | 46system.physmem.perBankRdBursts::2 461 # Per bank write bursts |
| 47system.physmem.perBankRdBursts::3 354 # Per bank write bursts 48system.physmem.perBankRdBursts::4 343 # Per bank write bursts 49system.physmem.perBankRdBursts::5 326 # Per bank write bursts 50system.physmem.perBankRdBursts::6 401 # Per bank write bursts 51system.physmem.perBankRdBursts::7 385 # Per bank write bursts 52system.physmem.perBankRdBursts::8 338 # Per bank write bursts | 47system.physmem.perBankRdBursts::3 350 # Per bank write bursts 48system.physmem.perBankRdBursts::4 340 # Per bank write bursts 49system.physmem.perBankRdBursts::5 325 # Per bank write bursts 50system.physmem.perBankRdBursts::6 403 # Per bank write bursts 51system.physmem.perBankRdBursts::7 384 # Per bank write bursts 52system.physmem.perBankRdBursts::8 342 # Per bank write bursts |
| 53system.physmem.perBankRdBursts::9 281 # Per bank write bursts | 53system.physmem.perBankRdBursts::9 281 # Per bank write bursts |
| 54system.physmem.perBankRdBursts::10 237 # Per bank write bursts 55system.physmem.perBankRdBursts::11 285 # Per bank write bursts 56system.physmem.perBankRdBursts::12 221 # Per bank write bursts 57system.physmem.perBankRdBursts::13 466 # Per bank write bursts 58system.physmem.perBankRdBursts::14 386 # Per bank write bursts 59system.physmem.perBankRdBursts::15 284 # Per bank write bursts | 54system.physmem.perBankRdBursts::10 239 # Per bank write bursts 55system.physmem.perBankRdBursts::11 284 # Per bank write bursts 56system.physmem.perBankRdBursts::12 217 # Per bank write bursts 57system.physmem.perBankRdBursts::13 467 # Per bank write bursts 58system.physmem.perBankRdBursts::14 385 # Per bank write bursts 59system.physmem.perBankRdBursts::15 283 # Per bank write bursts |
| 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 79147284500 # Total gap between requests | 78system.physmem.totGap 79190259000 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 85system.physmem.readPktSize::6 5413 # Read request sizes (log2) | 85system.physmem.readPktSize::6 5405 # Read request sizes (log2) |
| 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) | 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 93system.physmem.rdQLenPdf::0 4288 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 911 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 178 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see | 93system.physmem.rdQLenPdf::0 4301 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 898 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 174 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 28 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see |
| 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 75 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 75 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 189system.physmem.bytesPerActivate::samples 1109 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 312.266907 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 183.102740 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 326.449427 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 425 38.32% 38.32% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 245 22.09% 60.41% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 103 9.29% 69.70% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 58 5.23% 74.93% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 62 5.59% 80.52% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 52 4.69% 85.21% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 24 2.16% 87.38% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 18 1.62% 89.00% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 122 11.00% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 1109 # Bytes accessed per row activation 203system.physmem.totQLat 39588000 # Total ticks spent queuing 204system.physmem.totMemAccLat 141044250 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 27055000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 7313.50 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 4998.15 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 26056.58 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 4.38 # Average DRAM read bandwidth in MiByte/s | 189system.physmem.bytesPerActivate::samples 1097 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 314.107566 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 184.474477 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 326.278271 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 419 38.20% 38.20% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 241 21.97% 60.16% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 97 8.84% 69.01% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 63 5.74% 74.75% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 63 5.74% 80.49% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 54 4.92% 85.41% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 22 2.01% 87.42% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 17 1.55% 88.97% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 121 11.03% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 1097 # Bytes accessed per row activation 203system.physmem.totQLat 39419500 # Total ticks spent queuing 204system.physmem.totMemAccLat 140763250 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 27025000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 7293.15 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 26043.15 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 4.37 # Average DRAM read bandwidth in MiByte/s |
| 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 211system.physmem.avgRdBWSys 4.38 # Average system read bandwidth in MiByte/s | 211system.physmem.avgRdBWSys 4.37 # Average system read bandwidth in MiByte/s |
| 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.03 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.03 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 217system.physmem.avgRdQLen 1.32 # Average read queue length when enqueuing | 217system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing |
| 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 219system.physmem.readRowHits 4302 # Number of row buffer hits during reads | 219system.physmem.readRowHits 4299 # Number of row buffer hits during reads |
| 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 221system.physmem.readRowHitRate 79.48 # Row buffer hit rate for reads | 221system.physmem.readRowHitRate 79.54 # Row buffer hit rate for reads |
| 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 223system.physmem.avgGap 14621704.14 # Average gap between requests 224system.physmem.pageHitRate 79.48 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 4951800 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 2701875 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 22721400 # Energy for read commands per rank (pJ) | 223system.physmem.avgGap 14651296.76 # Average gap between requests 224system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 4883760 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 2664750 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 22565400 # Energy for read commands per rank (pJ) |
| 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) | 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 229system.physmem_0.refreshEnergy 5169512400 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 2476092825 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 45316483500 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 52992463800 # Total energy per rank (pJ) 233system.physmem_0.averagePower 669.540663 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 75384383500 # Time in different power states 235system.physmem_0.memoryStateTime::REF 2642640000 # Time in different power states | 229system.physmem_0.refreshEnergy 5172055200 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 2473079805 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 45342485250 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 53017734165 # Total energy per rank (pJ) 233system.physmem_0.averagePower 669.530615 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 75427842500 # Time in different power states 235system.physmem_0.memoryStateTime::REF 2644200000 # Time in different power states |
| 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 237system.physmem_0.memoryStateTime::ACT 1120221500 # Time in different power states | 237system.physmem_0.memoryStateTime::ACT 1114667500 # Time in different power states |
| 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 239system.physmem_1.actEnergy 3432240 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 1872750 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 19484400 # Energy for read commands per rank (pJ) | 239system.physmem_1.actEnergy 3402000 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 1856250 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 19305000 # Energy for read commands per rank (pJ) |
| 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) | 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 243system.physmem_1.refreshEnergy 5169512400 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 2281510215 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 45487170000 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 52962982005 # Total energy per rank (pJ) 247system.physmem_1.averagePower 669.168172 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 75669637750 # Time in different power states 249system.physmem_1.memoryStateTime::REF 2642640000 # Time in different power states | 243system.physmem_1.refreshEnergy 5172055200 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 2272318965 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 45518583000 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 52987520415 # Total energy per rank (pJ) 247system.physmem_1.averagePower 669.149179 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 75723788000 # Time in different power states 249system.physmem_1.memoryStateTime::REF 2644200000 # Time in different power states |
| 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 251system.physmem_1.memoryStateTime::ACT 834967250 # Time in different power states | 251system.physmem_1.memoryStateTime::ACT 820354000 # Time in different power states |
| 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 253system.cpu.branchPred.lookups 20588400 # Number of BP lookups 254system.cpu.branchPred.condPredicted 20588400 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 1327971 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 12696525 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 12013993 # Number of BTB hits | 253system.cpu.branchPred.lookups 20589195 # Number of BP lookups 254system.cpu.branchPred.condPredicted 20589195 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 1327817 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 12690862 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 12013274 # Number of BTB hits |
| 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 259system.cpu.branchPred.BTBHitPct 94.624261 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 1440282 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 16776 # Number of incorrect RAS predictions. | 259system.cpu.branchPred.BTBHitPct 94.660820 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 1440361 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 16897 # Number of incorrect RAS predictions. |
| 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 264system.cpu.workload.num_syscalls 400 # Number of system calls | 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 264system.cpu.workload.num_syscalls 400 # Number of system calls |
| 265system.cpu.numCycles 158294635 # number of cpu cycles simulated | 265system.cpu.numCycles 158380696 # number of cpu cycles simulated |
| 266system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 267system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 266system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 267system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 268system.cpu.fetch.icacheStallCycles 25247816 # Number of cycles fetch is stalled on an Icache miss 269system.cpu.fetch.Insts 227405263 # Number of instructions fetch has processed 270system.cpu.fetch.Branches 20588400 # Number of branches that fetch encountered 271system.cpu.fetch.predictedBranches 13454275 # Number of branches that fetch has predicted taken 272system.cpu.fetch.Cycles 131222766 # Number of cycles fetch has run and was not squashing or blocked 273system.cpu.fetch.SquashCycles 3194613 # Number of cycles fetch has spent squashing 274system.cpu.fetch.TlbCycles 4 # Number of cycles fetch has spent waiting for tlb 275system.cpu.fetch.MiscStallCycles 1919 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 276system.cpu.fetch.PendingTrapStallCycles 20727 # Number of stall cycles due to pending traps | 268system.cpu.fetch.icacheStallCycles 25245702 # Number of cycles fetch is stalled on an Icache miss 269system.cpu.fetch.Insts 227408017 # Number of instructions fetch has processed 270system.cpu.fetch.Branches 20589195 # Number of branches that fetch encountered 271system.cpu.fetch.predictedBranches 13453635 # Number of branches that fetch has predicted taken 272system.cpu.fetch.Cycles 131309354 # Number of cycles fetch has run and was not squashing or blocked 273system.cpu.fetch.SquashCycles 3192879 # Number of cycles fetch has spent squashing 274system.cpu.fetch.TlbCycles 16 # Number of cycles fetch has spent waiting for tlb 275system.cpu.fetch.MiscStallCycles 1952 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 276system.cpu.fetch.PendingTrapStallCycles 21042 # Number of stall cycles due to pending traps |
| 277system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions 278system.cpu.fetch.IcacheWaitRetryStallCycles 47 # Number of stall cycles due to full MSHR | 277system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions 278system.cpu.fetch.IcacheWaitRetryStallCycles 47 # Number of stall cycles due to full MSHR |
| 279system.cpu.fetch.CacheLines 24255799 # Number of cache lines fetched 280system.cpu.fetch.IcacheSquashes 267811 # Number of outstanding Icache misses that were squashed 281system.cpu.fetch.rateDist::samples 158090598 # Number of instructions fetched each cycle (Total) 282system.cpu.fetch.rateDist::mean 2.379045 # Number of instructions fetched each cycle (Total) 283system.cpu.fetch.rateDist::stdev 3.324681 # Number of instructions fetched each cycle (Total) | 279system.cpu.fetch.CacheLines 24254364 # Number of cache lines fetched 280system.cpu.fetch.IcacheSquashes 267325 # Number of outstanding Icache misses that were squashed 281system.cpu.fetch.rateDist::samples 158174565 # Number of instructions fetched each cycle (Total) 282system.cpu.fetch.rateDist::mean 2.377629 # Number of instructions fetched each cycle (Total) 283system.cpu.fetch.rateDist::stdev 3.324169 # Number of instructions fetched each cycle (Total) |
| 284system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 284system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 285system.cpu.fetch.rateDist::0 95773120 60.58% 60.58% # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::1 4766421 3.01% 63.60% # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::2 3796193 2.40% 66.00% # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::3 4366321 2.76% 68.76% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::4 4228924 2.68% 71.43% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::5 4813507 3.04% 74.48% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::6 4702194 2.97% 77.45% # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::7 3700875 2.34% 79.79% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::8 31943043 20.21% 100.00% # Number of instructions fetched each cycle (Total) | 285system.cpu.fetch.rateDist::0 95855369 60.60% 60.60% # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::1 4772394 3.02% 63.62% # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::2 3794325 2.40% 66.02% # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::3 4370382 2.76% 68.78% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::4 4226374 2.67% 71.45% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::5 4818979 3.05% 74.50% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::6 4692035 2.97% 77.46% # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::7 3702011 2.34% 79.81% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::8 31942696 20.19% 100.00% # Number of instructions fetched each cycle (Total) |
| 294system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 294system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 297system.cpu.fetch.rateDist::total 158090598 # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.branchRate 0.130064 # Number of branch fetches per cycle 299system.cpu.fetch.rate 1.436595 # Number of inst fetches per cycle 300system.cpu.decode.IdleCycles 15405711 # Number of cycles decode is idle 301system.cpu.decode.BlockedCycles 96196393 # Number of cycles decode is blocked 302system.cpu.decode.RunCycles 23270128 # Number of cycles decode is running 303system.cpu.decode.UnblockCycles 21621060 # Number of cycles decode is unblocking 304system.cpu.decode.SquashCycles 1597306 # Number of cycles decode is squashing 305system.cpu.decode.DecodedInsts 336557336 # Number of instructions handled by decode 306system.cpu.rename.SquashCycles 1597306 # Number of cycles rename is squashing 307system.cpu.rename.IdleCycles 23296942 # Number of cycles rename is idle 308system.cpu.rename.BlockCycles 31816084 # Number of cycles rename is blocking 309system.cpu.rename.serializeStallCycles 30705 # count of cycles rename stalled for serializing inst 310system.cpu.rename.RunCycles 35988234 # Number of cycles rename is running 311system.cpu.rename.UnblockCycles 65361327 # Number of cycles rename is unblocking 312system.cpu.rename.RenamedInsts 328199746 # Number of instructions processed by rename 313system.cpu.rename.ROBFullEvents 1272 # Number of times rename has blocked due to ROB full 314system.cpu.rename.IQFullEvents 57739687 # Number of times rename has blocked due to IQ full 315system.cpu.rename.LQFullEvents 7687780 # Number of times rename has blocked due to LQ full 316system.cpu.rename.SQFullEvents 164697 # Number of times rename has blocked due to SQ full 317system.cpu.rename.RenamedOperands 380395487 # Number of destination operands rename has renamed 318system.cpu.rename.RenameLookups 909798638 # Number of register rename lookups that rename has made 319system.cpu.rename.int_rename_lookups 600491080 # Number of integer rename lookups 320system.cpu.rename.fp_rename_lookups 4191135 # Number of floating rename lookups | 297system.cpu.fetch.rateDist::total 158174565 # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.branchRate 0.129998 # Number of branch fetches per cycle 299system.cpu.fetch.rate 1.435832 # Number of inst fetches per cycle 300system.cpu.decode.IdleCycles 15399565 # Number of cycles decode is idle 301system.cpu.decode.BlockedCycles 96291119 # Number of cycles decode is blocked 302system.cpu.decode.RunCycles 23261573 # Number of cycles decode is running 303system.cpu.decode.UnblockCycles 21625869 # Number of cycles decode is unblocking 304system.cpu.decode.SquashCycles 1596439 # Number of cycles decode is squashing 305system.cpu.decode.DecodedInsts 336537122 # Number of instructions handled by decode 306system.cpu.rename.SquashCycles 1596439 # Number of cycles rename is squashing 307system.cpu.rename.IdleCycles 23302832 # Number of cycles rename is idle 308system.cpu.rename.BlockCycles 31798352 # Number of cycles rename is blocking 309system.cpu.rename.serializeStallCycles 30486 # count of cycles rename stalled for serializing inst 310system.cpu.rename.RunCycles 35975056 # Number of cycles rename is running 311system.cpu.rename.UnblockCycles 65471400 # Number of cycles rename is unblocking 312system.cpu.rename.RenamedInsts 328175182 # Number of instructions processed by rename 313system.cpu.rename.ROBFullEvents 1530 # Number of times rename has blocked due to ROB full 314system.cpu.rename.IQFullEvents 57810134 # Number of times rename has blocked due to IQ full 315system.cpu.rename.LQFullEvents 7763747 # Number of times rename has blocked due to LQ full 316system.cpu.rename.SQFullEvents 166308 # Number of times rename has blocked due to SQ full 317system.cpu.rename.RenamedOperands 380366291 # Number of destination operands rename has renamed 318system.cpu.rename.RenameLookups 909731361 # Number of register rename lookups that rename has made 319system.cpu.rename.int_rename_lookups 600445935 # Number of integer rename lookups 320system.cpu.rename.fp_rename_lookups 4186121 # Number of floating rename lookups |
| 321system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed | 321system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed |
| 322system.cpu.rename.UndoneMaps 120966037 # Number of HB maps that are undone due to squashing 323system.cpu.rename.serializingInsts 1948 # count of serializing insts renamed 324system.cpu.rename.tempSerializingInsts 1925 # count of temporary serializing insts renamed 325system.cpu.rename.skidInsts 121028118 # count of insts added to the skid buffer 326system.cpu.memDep0.insertedLoads 82726275 # Number of loads inserted to the mem dependence unit. 327system.cpu.memDep0.insertedStores 29782185 # Number of stores inserted to the mem dependence unit. 328system.cpu.memDep0.conflictingLoads 59498195 # Number of conflicting loads. 329system.cpu.memDep0.conflictingStores 20364114 # Number of conflicting stores. 330system.cpu.iq.iqInstsAdded 317775977 # Number of instructions added to the IQ (excludes non-spec) 331system.cpu.iq.iqNonSpecInstsAdded 4062 # Number of non-speculative instructions added to the IQ 332system.cpu.iq.iqInstsIssued 259339716 # Number of instructions issued 333system.cpu.iq.iqSquashedInstsIssued 70716 # Number of squashed instructions issued 334system.cpu.iq.iqSquashedInstsExamined 96416655 # Number of squashed instructions iterated over during squash; mainly for profiling 335system.cpu.iq.iqSquashedOperandsExamined 197093622 # Number of squashed operands that are examined and possibly removed from graph 336system.cpu.iq.iqSquashedNonSpecRemoved 2817 # Number of squashed non-spec instructions that were removed 337system.cpu.iq.issued_per_cycle::samples 158090598 # Number of insts issued each cycle 338system.cpu.iq.issued_per_cycle::mean 1.640450 # Number of insts issued each cycle 339system.cpu.iq.issued_per_cycle::stdev 1.524161 # Number of insts issued each cycle | 322system.cpu.rename.UndoneMaps 120936841 # Number of HB maps that are undone due to squashing 323system.cpu.rename.serializingInsts 1921 # count of serializing insts renamed 324system.cpu.rename.tempSerializingInsts 1898 # count of temporary serializing insts renamed 325system.cpu.rename.skidInsts 121141633 # count of insts added to the skid buffer 326system.cpu.memDep0.insertedLoads 82738842 # Number of loads inserted to the mem dependence unit. 327system.cpu.memDep0.insertedStores 29779777 # Number of stores inserted to the mem dependence unit. 328system.cpu.memDep0.conflictingLoads 59550134 # Number of conflicting loads. 329system.cpu.memDep0.conflictingStores 20391789 # Number of conflicting stores. 330system.cpu.iq.iqInstsAdded 317761802 # Number of instructions added to the IQ (excludes non-spec) 331system.cpu.iq.iqNonSpecInstsAdded 4069 # Number of non-speculative instructions added to the IQ 332system.cpu.iq.iqInstsIssued 259358612 # Number of instructions issued 333system.cpu.iq.iqSquashedInstsIssued 72184 # Number of squashed instructions issued 334system.cpu.iq.iqSquashedInstsExamined 96402487 # Number of squashed instructions iterated over during squash; mainly for profiling 335system.cpu.iq.iqSquashedOperandsExamined 196983368 # Number of squashed operands that are examined and possibly removed from graph 336system.cpu.iq.iqSquashedNonSpecRemoved 2824 # Number of squashed non-spec instructions that were removed 337system.cpu.iq.issued_per_cycle::samples 158174565 # Number of insts issued each cycle 338system.cpu.iq.issued_per_cycle::mean 1.639699 # Number of insts issued each cycle 339system.cpu.iq.issued_per_cycle::stdev 1.523293 # Number of insts issued each cycle |
| 340system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 340system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 341system.cpu.iq.issued_per_cycle::0 40031018 25.32% 25.32% # Number of insts issued each cycle 342system.cpu.iq.issued_per_cycle::1 47550925 30.08% 55.40% # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::2 33058238 20.91% 76.31% # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::3 17999758 11.39% 87.70% # Number of insts issued each cycle 345system.cpu.iq.issued_per_cycle::4 10966409 6.94% 94.63% # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::5 4755401 3.01% 97.64% # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::6 2459487 1.56% 99.20% # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::7 881418 0.56% 99.75% # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::8 387944 0.25% 100.00% # Number of insts issued each cycle | 341system.cpu.iq.issued_per_cycle::0 40029224 25.31% 25.31% # Number of insts issued each cycle 342system.cpu.iq.issued_per_cycle::1 47620381 30.11% 55.41% # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::2 33114320 20.94% 76.35% # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::3 17999452 11.38% 87.73% # Number of insts issued each cycle 345system.cpu.iq.issued_per_cycle::4 10926984 6.91% 94.64% # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::5 4757371 3.01% 97.64% # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::6 2459469 1.55% 99.20% # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::7 879282 0.56% 99.75% # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::8 388082 0.25% 100.00% # Number of insts issued each cycle |
| 350system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 351system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 352system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 350system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 351system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 352system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 353system.cpu.iq.issued_per_cycle::total 158090598 # Number of insts issued each cycle | 353system.cpu.iq.issued_per_cycle::total 158174565 # Number of insts issued each cycle |
| 354system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 354system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 355system.cpu.iq.fu_full::IntAlu 232409 7.35% 7.35% # attempts to use FU when none available 356system.cpu.iq.fu_full::IntMult 0 0.00% 7.35% # attempts to use FU when none available 357system.cpu.iq.fu_full::IntDiv 0 0.00% 7.35% # attempts to use FU when none available 358system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.35% # attempts to use FU when none available 359system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.35% # attempts to use FU when none available 360system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.35% # attempts to use FU when none available 361system.cpu.iq.fu_full::FloatMult 0 0.00% 7.35% # attempts to use FU when none available 362system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.35% # attempts to use FU when none available 363system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.35% # attempts to use FU when none available 364system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.35% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.35% # attempts to use FU when none available 366system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.35% # attempts to use FU when none available 367system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.35% # attempts to use FU when none available 368system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.35% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.35% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdMult 0 0.00% 7.35% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.35% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdShift 0 0.00% 7.35% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.35% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.35% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.35% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.35% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.35% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.35% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.35% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.35% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.35% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.35% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.35% # attempts to use FU when none available 384system.cpu.iq.fu_full::MemRead 2543467 80.43% 87.78% # attempts to use FU when none available 385system.cpu.iq.fu_full::MemWrite 386453 12.22% 100.00% # attempts to use FU when none available | 355system.cpu.iq.fu_full::IntAlu 231613 7.32% 7.32% # attempts to use FU when none available 356system.cpu.iq.fu_full::IntMult 0 0.00% 7.32% # attempts to use FU when none available 357system.cpu.iq.fu_full::IntDiv 0 0.00% 7.32% # attempts to use FU when none available 358system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.32% # attempts to use FU when none available 359system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.32% # attempts to use FU when none available 360system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.32% # attempts to use FU when none available 361system.cpu.iq.fu_full::FloatMult 0 0.00% 7.32% # attempts to use FU when none available 362system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.32% # attempts to use FU when none available 363system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.32% # attempts to use FU when none available 364system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.32% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.32% # attempts to use FU when none available 366system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.32% # attempts to use FU when none available 367system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.32% # attempts to use FU when none available 368system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.32% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.32% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdMult 0 0.00% 7.32% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.32% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdShift 0 0.00% 7.32% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.32% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.32% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.32% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.32% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.32% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.32% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.32% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.32% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.32% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.32% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.32% # attempts to use FU when none available 384system.cpu.iq.fu_full::MemRead 2544922 80.40% 87.72% # attempts to use FU when none available 385system.cpu.iq.fu_full::MemWrite 388680 12.28% 100.00% # attempts to use FU when none available |
| 386system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 387system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 386system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 387system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 388system.cpu.iq.FU_type_0::No_OpClass 1213129 0.47% 0.47% # Type of FU issued 389system.cpu.iq.FU_type_0::IntAlu 161789317 62.39% 62.85% # Type of FU issued 390system.cpu.iq.FU_type_0::IntMult 789379 0.30% 63.16% # Type of FU issued 391system.cpu.iq.FU_type_0::IntDiv 7038032 2.71% 65.87% # Type of FU issued 392system.cpu.iq.FU_type_0::FloatAdd 1187047 0.46% 66.33% # Type of FU issued 393system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.33% # Type of FU issued 394system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.33% # Type of FU issued 395system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.33% # Type of FU issued 396system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.33% # Type of FU issued 397system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.33% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.33% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.33% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.33% # Type of FU issued 401system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.33% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.33% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.33% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.33% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.33% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.33% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.33% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.33% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.33% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.33% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.33% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.33% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.33% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.33% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.33% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.33% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.33% # Type of FU issued 418system.cpu.iq.FU_type_0::MemRead 64866508 25.01% 91.34% # Type of FU issued 419system.cpu.iq.FU_type_0::MemWrite 22456304 8.66% 100.00% # Type of FU issued | 388system.cpu.iq.FU_type_0::No_OpClass 1213055 0.47% 0.47% # Type of FU issued 389system.cpu.iq.FU_type_0::IntAlu 161788642 62.38% 62.85% # Type of FU issued 390system.cpu.iq.FU_type_0::IntMult 789415 0.30% 63.15% # Type of FU issued 391system.cpu.iq.FU_type_0::IntDiv 7038152 2.71% 65.87% # Type of FU issued 392system.cpu.iq.FU_type_0::FloatAdd 1187589 0.46% 66.32% # Type of FU issued 393system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.32% # Type of FU issued 394system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.32% # Type of FU issued 395system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.32% # Type of FU issued 396system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.32% # Type of FU issued 397system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.32% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.32% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.32% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.32% # Type of FU issued 401system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.32% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.32% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.32% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.32% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.32% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.32% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.32% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.32% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.32% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.32% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.32% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.32% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.32% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.32% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.32% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.32% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.32% # Type of FU issued 418system.cpu.iq.FU_type_0::MemRead 64884960 25.02% 91.34% # Type of FU issued 419system.cpu.iq.FU_type_0::MemWrite 22456799 8.66% 100.00% # Type of FU issued |
| 420system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 421system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 420system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 421system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 422system.cpu.iq.FU_type_0::total 259339716 # Type of FU issued 423system.cpu.iq.rate 1.638335 # Inst issue rate 424system.cpu.iq.fu_busy_cnt 3162329 # FU busy when requested 425system.cpu.iq.fu_busy_rate 0.012194 # FU busy rate (busy events/executed inst) 426system.cpu.iq.int_inst_queue_reads 675146049 # Number of integer instruction queue reads 427system.cpu.iq.int_inst_queue_writes 410783686 # Number of integer instruction queue writes 428system.cpu.iq.int_inst_queue_wakeup_accesses 253609186 # Number of integer instruction queue wakeup accesses 429system.cpu.iq.fp_inst_queue_reads 4857026 # Number of floating instruction queue reads 430system.cpu.iq.fp_inst_queue_writes 3709843 # Number of floating instruction queue writes 431system.cpu.iq.fp_inst_queue_wakeup_accesses 2340813 # Number of floating instruction queue wakeup accesses 432system.cpu.iq.int_alu_accesses 258843472 # Number of integer alu accesses 433system.cpu.iq.fp_alu_accesses 2445444 # Number of floating point alu accesses 434system.cpu.iew.lsq.thread0.forwLoads 18733712 # Number of loads that had data forwarded from stores | 422system.cpu.iq.FU_type_0::total 259358612 # Type of FU issued 423system.cpu.iq.rate 1.637565 # Inst issue rate 424system.cpu.iq.fu_busy_cnt 3165215 # FU busy when requested 425system.cpu.iq.fu_busy_rate 0.012204 # FU busy rate (busy events/executed inst) 426system.cpu.iq.int_inst_queue_reads 675270057 # Number of integer instruction queue reads 427system.cpu.iq.int_inst_queue_writes 410763185 # Number of integer instruction queue writes 428system.cpu.iq.int_inst_queue_wakeup_accesses 253622616 # Number of integer instruction queue wakeup accesses 429system.cpu.iq.fp_inst_queue_reads 4859131 # Number of floating instruction queue reads 430system.cpu.iq.fp_inst_queue_writes 3700913 # Number of floating instruction queue writes 431system.cpu.iq.fp_inst_queue_wakeup_accesses 2341090 # Number of floating instruction queue wakeup accesses 432system.cpu.iq.int_alu_accesses 258863930 # Number of integer alu accesses 433system.cpu.iq.fp_alu_accesses 2446842 # Number of floating point alu accesses 434system.cpu.iew.lsq.thread0.forwLoads 18717155 # Number of loads that had data forwarded from stores |
| 435system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 435system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 436system.cpu.iew.lsq.thread0.squashedLoads 26076688 # Number of loads squashed 437system.cpu.iew.lsq.thread0.ignoredResponses 12661 # Number of memory responses ignored because the instruction is squashed 438system.cpu.iew.lsq.thread0.memOrderViolation 303068 # Number of memory ordering violations 439system.cpu.iew.lsq.thread0.squashedStores 9266468 # Number of stores squashed | 436system.cpu.iew.lsq.thread0.squashedLoads 26089255 # Number of loads squashed 437system.cpu.iew.lsq.thread0.ignoredResponses 12841 # Number of memory responses ignored because the instruction is squashed 438system.cpu.iew.lsq.thread0.memOrderViolation 302099 # Number of memory ordering violations 439system.cpu.iew.lsq.thread0.squashedStores 9264060 # Number of stores squashed |
| 440system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 441system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 440system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 441system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 442system.cpu.iew.lsq.thread0.rescheduledLoads 50753 # Number of loads that were rescheduled 443system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked | 442system.cpu.iew.lsq.thread0.rescheduledLoads 50731 # Number of loads that were rescheduled 443system.cpu.iew.lsq.thread0.cacheBlocked 43 # Number of times an access to memory failed due to the cache being blocked |
| 444system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 444system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 445system.cpu.iew.iewSquashCycles 1597306 # Number of cycles IEW is squashing 446system.cpu.iew.iewBlockCycles 12475143 # Number of cycles IEW is blocking 447system.cpu.iew.iewUnblockCycles 492608 # Number of cycles IEW is unblocking 448system.cpu.iew.iewDispatchedInsts 317780039 # Number of instructions dispatched to IQ 449system.cpu.iew.iewDispSquashedInsts 92128 # Number of squashed instructions skipped by dispatch 450system.cpu.iew.iewDispLoadInsts 82726275 # Number of dispatched load instructions 451system.cpu.iew.iewDispStoreInsts 29782185 # Number of dispatched store instructions 452system.cpu.iew.iewDispNonSpecInsts 1904 # Number of dispatched non-speculative instructions 453system.cpu.iew.iewIQFullEvents 385254 # Number of times the IQ has become full, causing a stall 454system.cpu.iew.iewLSQFullEvents 64210 # Number of times the LSQ has become full, causing a stall 455system.cpu.iew.memOrderViolationEvents 303068 # Number of memory order violations 456system.cpu.iew.predictedTakenIncorrect 551876 # Number of branches that were predicted taken incorrectly 457system.cpu.iew.predictedNotTakenIncorrect 825683 # Number of branches that were predicted not taken incorrectly 458system.cpu.iew.branchMispredicts 1377559 # Number of branch mispredicts detected at execute 459system.cpu.iew.iewExecutedInsts 257278299 # Number of executed instructions 460system.cpu.iew.iewExecLoadInsts 64049933 # Number of load instructions executed 461system.cpu.iew.iewExecSquashedInsts 2061417 # Number of squashed instructions skipped in execute | 445system.cpu.iew.iewSquashCycles 1596439 # Number of cycles IEW is squashing 446system.cpu.iew.iewBlockCycles 12482349 # Number of cycles IEW is blocking 447system.cpu.iew.iewUnblockCycles 492760 # Number of cycles IEW is unblocking 448system.cpu.iew.iewDispatchedInsts 317765871 # Number of instructions dispatched to IQ 449system.cpu.iew.iewDispSquashedInsts 91851 # Number of squashed instructions skipped by dispatch 450system.cpu.iew.iewDispLoadInsts 82738842 # Number of dispatched load instructions 451system.cpu.iew.iewDispStoreInsts 29779777 # Number of dispatched store instructions 452system.cpu.iew.iewDispNonSpecInsts 1874 # Number of dispatched non-speculative instructions 453system.cpu.iew.iewIQFullEvents 386744 # Number of times the IQ has become full, causing a stall 454system.cpu.iew.iewLSQFullEvents 63788 # Number of times the LSQ has become full, causing a stall 455system.cpu.iew.memOrderViolationEvents 302099 # Number of memory order violations 456system.cpu.iew.predictedTakenIncorrect 551455 # Number of branches that were predicted taken incorrectly 457system.cpu.iew.predictedNotTakenIncorrect 825732 # Number of branches that were predicted not taken incorrectly 458system.cpu.iew.branchMispredicts 1377187 # Number of branch mispredicts detected at execute 459system.cpu.iew.iewExecutedInsts 257295592 # Number of executed instructions 460system.cpu.iew.iewExecLoadInsts 64068122 # Number of load instructions executed 461system.cpu.iew.iewExecSquashedInsts 2063020 # Number of squashed instructions skipped in execute |
| 462system.cpu.iew.exec_swp 0 # number of swp insts executed 463system.cpu.iew.exec_nop 0 # number of nop insts executed | 462system.cpu.iew.exec_swp 0 # number of swp insts executed 463system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 464system.cpu.iew.exec_refs 86328991 # number of memory reference insts executed 465system.cpu.iew.exec_branches 14325599 # Number of branches executed 466system.cpu.iew.exec_stores 22279058 # Number of stores executed 467system.cpu.iew.exec_rate 1.625313 # Inst execution rate 468system.cpu.iew.wb_sent 256636877 # cumulative count of insts sent to commit 469system.cpu.iew.wb_count 255949999 # cumulative count of insts written-back 470system.cpu.iew.wb_producers 204329368 # num instructions producing a value 471system.cpu.iew.wb_consumers 369642243 # num instructions consuming a value | 464system.cpu.iew.exec_refs 86346654 # number of memory reference insts executed 465system.cpu.iew.exec_branches 14327856 # Number of branches executed 466system.cpu.iew.exec_stores 22278532 # Number of stores executed 467system.cpu.iew.exec_rate 1.624539 # Inst execution rate 468system.cpu.iew.wb_sent 256649039 # cumulative count of insts sent to commit 469system.cpu.iew.wb_count 255963706 # cumulative count of insts written-back 470system.cpu.iew.wb_producers 204348842 # num instructions producing a value 471system.cpu.iew.wb_consumers 369627181 # num instructions consuming a value |
| 472system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 472system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 473system.cpu.iew.wb_rate 1.616922 # insts written-back per cycle 474system.cpu.iew.wb_fanout 0.552776 # average fanout of values written-back | 473system.cpu.iew.wb_rate 1.616129 # insts written-back per cycle 474system.cpu.iew.wb_fanout 0.552851 # average fanout of values written-back |
| 475system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 475system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 476system.cpu.commit.commitSquashedInsts 96424533 # The number of squashed insts skipped by commit | 476system.cpu.commit.commitSquashedInsts 96410316 # The number of squashed insts skipped by commit |
| 477system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards | 477system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards |
| 478system.cpu.commit.branchMispredicts 1329745 # The number of times a branch was mispredicted 479system.cpu.commit.committed_per_cycle::samples 144946815 # Number of insts commited each cycle 480system.cpu.commit.committed_per_cycle::mean 1.527204 # Number of insts commited each cycle 481system.cpu.commit.committed_per_cycle::stdev 1.957309 # Number of insts commited each cycle | 478system.cpu.commit.branchMispredicts 1329636 # The number of times a branch was mispredicted 479system.cpu.commit.committed_per_cycle::samples 145035845 # Number of insts commited each cycle 480system.cpu.commit.committed_per_cycle::mean 1.526267 # Number of insts commited each cycle 481system.cpu.commit.committed_per_cycle::stdev 1.955883 # Number of insts commited each cycle |
| 482system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 482system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 483system.cpu.commit.committed_per_cycle::0 45502245 31.39% 31.39% # Number of insts commited each cycle 484system.cpu.commit.committed_per_cycle::1 57364882 39.58% 70.97% # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::2 14168547 9.77% 80.74% # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::3 11990061 8.27% 89.02% # Number of insts commited each cycle 487system.cpu.commit.committed_per_cycle::4 4061557 2.80% 91.82% # Number of insts commited each cycle 488system.cpu.commit.committed_per_cycle::5 2847156 1.96% 93.78% # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::6 903972 0.62% 94.41% # Number of insts commited each cycle 490system.cpu.commit.committed_per_cycle::7 1081775 0.75% 95.15% # Number of insts commited each cycle 491system.cpu.commit.committed_per_cycle::8 7026620 4.85% 100.00% # Number of insts commited each cycle | 483system.cpu.commit.committed_per_cycle::0 45546155 31.40% 31.40% # Number of insts commited each cycle 484system.cpu.commit.committed_per_cycle::1 57399506 39.58% 70.98% # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::2 14176238 9.77% 80.75% # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::3 11993202 8.27% 89.02% # Number of insts commited each cycle 487system.cpu.commit.committed_per_cycle::4 4061532 2.80% 91.82% # Number of insts commited each cycle 488system.cpu.commit.committed_per_cycle::5 2861406 1.97% 93.80% # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::6 912773 0.63% 94.43% # Number of insts commited each cycle 490system.cpu.commit.committed_per_cycle::7 1078264 0.74% 95.17% # Number of insts commited each cycle 491system.cpu.commit.committed_per_cycle::8 7006769 4.83% 100.00% # Number of insts commited each cycle |
| 492system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 493system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 494system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 492system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 493system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 494system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 495system.cpu.commit.committed_per_cycle::total 144946815 # Number of insts commited each cycle | 495system.cpu.commit.committed_per_cycle::total 145035845 # Number of insts commited each cycle |
| 496system.cpu.commit.committedInsts 132071192 # Number of instructions committed 497system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed 498system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 499system.cpu.commit.refs 77165304 # Number of memory references committed 500system.cpu.commit.loads 56649587 # Number of loads committed 501system.cpu.commit.membars 0 # Number of memory barriers committed 502system.cpu.commit.branches 12326938 # Number of branches committed 503system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 533system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction 534system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction 535system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction 536system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction 537system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction 538system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 539system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 540system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction | 496system.cpu.commit.committedInsts 132071192 # Number of instructions committed 497system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed 498system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 499system.cpu.commit.refs 77165304 # Number of memory references committed 500system.cpu.commit.loads 56649587 # Number of loads committed 501system.cpu.commit.membars 0 # Number of memory barriers committed 502system.cpu.commit.branches 12326938 # Number of branches committed 503system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 533system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction 534system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction 535system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction 536system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction 537system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction 538system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 539system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 540system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction |
| 541system.cpu.commit.bw_lim_events 7026620 # number cycles where commit BW limit reached 542system.cpu.rob.rob_reads 455708112 # The number of ROB reads 543system.cpu.rob.rob_writes 648756933 # The number of ROB writes 544system.cpu.timesIdled 2654 # Number of times that the entire CPU went into an idle state and unscheduled itself 545system.cpu.idleCycles 204037 # Total number of cycles that the CPU has spent unscheduled due to idling | 541system.cpu.commit.bw_lim_events 7006769 # number cycles where commit BW limit reached 542system.cpu.rob.rob_reads 455802776 # The number of ROB reads 543system.cpu.rob.rob_writes 648723400 # The number of ROB writes 544system.cpu.timesIdled 2658 # Number of times that the entire CPU went into an idle state and unscheduled itself 545system.cpu.idleCycles 206131 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 546system.cpu.committedInsts 132071192 # Number of Instructions Simulated 547system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated | 546system.cpu.committedInsts 132071192 # Number of Instructions Simulated 547system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated |
| 548system.cpu.cpi 1.198555 # CPI: Cycles Per Instruction 549system.cpu.cpi_total 1.198555 # CPI: Total CPI of All Threads 550system.cpu.ipc 0.834338 # IPC: Instructions Per Cycle 551system.cpu.ipc_total 0.834338 # IPC: Total IPC of All Threads 552system.cpu.int_regfile_reads 448462774 # number of integer regfile reads 553system.cpu.int_regfile_writes 232558570 # number of integer regfile writes 554system.cpu.fp_regfile_reads 3214394 # number of floating regfile reads 555system.cpu.fp_regfile_writes 1998880 # number of floating regfile writes 556system.cpu.cc_regfile_reads 102524460 # number of cc regfile reads 557system.cpu.cc_regfile_writes 59518831 # number of cc regfile writes 558system.cpu.misc_regfile_reads 132416718 # number of misc regfile reads | 548system.cpu.cpi 1.199207 # CPI: Cycles Per Instruction 549system.cpu.cpi_total 1.199207 # CPI: Total CPI of All Threads 550system.cpu.ipc 0.833884 # IPC: Instructions Per Cycle 551system.cpu.ipc_total 0.833884 # IPC: Total IPC of All Threads 552system.cpu.int_regfile_reads 448507967 # number of integer regfile reads 553system.cpu.int_regfile_writes 232568909 # number of integer regfile writes 554system.cpu.fp_regfile_reads 3215393 # number of floating regfile reads 555system.cpu.fp_regfile_writes 1999198 # number of floating regfile writes 556system.cpu.cc_regfile_reads 102530516 # number of cc regfile reads 557system.cpu.cc_regfile_writes 59523273 # number of cc regfile writes 558system.cpu.misc_regfile_reads 132435302 # number of misc regfile reads |
| 559system.cpu.misc_regfile_writes 1689 # number of misc regfile writes | 559system.cpu.misc_regfile_writes 1689 # number of misc regfile writes |
| 560system.cpu.dcache.tags.replacements 53 # number of replacements 561system.cpu.dcache.tags.tagsinuse 1431.895248 # Cycle average of tags in use 562system.cpu.dcache.tags.total_refs 65702088 # Total number of references to valid blocks. 563system.cpu.dcache.tags.sampled_refs 1996 # Sample count of references to valid blocks. 564system.cpu.dcache.tags.avg_refs 32916.877756 # Average number of references to valid blocks. | 560system.cpu.dcache.tags.replacements 52 # number of replacements 561system.cpu.dcache.tags.tagsinuse 1432.092422 # Cycle average of tags in use 562system.cpu.dcache.tags.total_refs 65736813 # Total number of references to valid blocks. 563system.cpu.dcache.tags.sampled_refs 2001 # Sample count of references to valid blocks. 564system.cpu.dcache.tags.avg_refs 32851.980510 # Average number of references to valid blocks. |
| 565system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 565system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 566system.cpu.dcache.tags.occ_blocks::cpu.data 1431.895248 # Average occupied blocks per requestor 567system.cpu.dcache.tags.occ_percent::cpu.data 0.349584 # Average percentage of cache occupancy 568system.cpu.dcache.tags.occ_percent::total 0.349584 # Average percentage of cache occupancy 569system.cpu.dcache.tags.occ_task_id_blocks::1024 1943 # Occupied blocks per task id 570system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id | 566system.cpu.dcache.tags.occ_blocks::cpu.data 1432.092422 # Average occupied blocks per requestor 567system.cpu.dcache.tags.occ_percent::cpu.data 0.349632 # Average percentage of cache occupancy 568system.cpu.dcache.tags.occ_percent::total 0.349632 # Average percentage of cache occupancy 569system.cpu.dcache.tags.occ_task_id_blocks::1024 1949 # Occupied blocks per task id 570system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id |
| 571system.cpu.dcache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id | 571system.cpu.dcache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id |
| 572system.cpu.dcache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id | 572system.cpu.dcache.tags.age_task_id_blocks_1024::2 500 # Occupied blocks per task id |
| 573system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id | 573system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id |
| 574system.cpu.dcache.tags.age_task_id_blocks_1024::4 1395 # Occupied blocks per task id 575system.cpu.dcache.tags.occ_task_id_percent::1024 0.474365 # Percentage of cache occupancy per task id 576system.cpu.dcache.tags.tag_accesses 131411014 # Number of tag accesses 577system.cpu.dcache.tags.data_accesses 131411014 # Number of data accesses 578system.cpu.dcache.ReadReq_hits::cpu.data 45187780 # number of ReadReq hits 579system.cpu.dcache.ReadReq_hits::total 45187780 # number of ReadReq hits 580system.cpu.dcache.WriteReq_hits::cpu.data 20513887 # number of WriteReq hits 581system.cpu.dcache.WriteReq_hits::total 20513887 # number of WriteReq hits 582system.cpu.dcache.demand_hits::cpu.data 65701667 # number of demand (read+write) hits 583system.cpu.dcache.demand_hits::total 65701667 # number of demand (read+write) hits 584system.cpu.dcache.overall_hits::cpu.data 65701667 # number of overall hits 585system.cpu.dcache.overall_hits::total 65701667 # number of overall hits 586system.cpu.dcache.ReadReq_misses::cpu.data 998 # number of ReadReq misses 587system.cpu.dcache.ReadReq_misses::total 998 # number of ReadReq misses 588system.cpu.dcache.WriteReq_misses::cpu.data 1844 # number of WriteReq misses 589system.cpu.dcache.WriteReq_misses::total 1844 # number of WriteReq misses 590system.cpu.dcache.demand_misses::cpu.data 2842 # number of demand (read+write) misses 591system.cpu.dcache.demand_misses::total 2842 # number of demand (read+write) misses 592system.cpu.dcache.overall_misses::cpu.data 2842 # number of overall misses 593system.cpu.dcache.overall_misses::total 2842 # number of overall misses 594system.cpu.dcache.ReadReq_miss_latency::cpu.data 65947500 # number of ReadReq miss cycles 595system.cpu.dcache.ReadReq_miss_latency::total 65947500 # number of ReadReq miss cycles 596system.cpu.dcache.WriteReq_miss_latency::cpu.data 129226000 # number of WriteReq miss cycles 597system.cpu.dcache.WriteReq_miss_latency::total 129226000 # number of WriteReq miss cycles 598system.cpu.dcache.demand_miss_latency::cpu.data 195173500 # number of demand (read+write) miss cycles 599system.cpu.dcache.demand_miss_latency::total 195173500 # number of demand (read+write) miss cycles 600system.cpu.dcache.overall_miss_latency::cpu.data 195173500 # number of overall miss cycles 601system.cpu.dcache.overall_miss_latency::total 195173500 # number of overall miss cycles 602system.cpu.dcache.ReadReq_accesses::cpu.data 45188778 # number of ReadReq accesses(hits+misses) 603system.cpu.dcache.ReadReq_accesses::total 45188778 # number of ReadReq accesses(hits+misses) | 574system.cpu.dcache.tags.age_task_id_blocks_1024::4 1397 # Occupied blocks per task id 575system.cpu.dcache.tags.occ_task_id_percent::1024 0.475830 # Percentage of cache occupancy per task id 576system.cpu.dcache.tags.tag_accesses 131480483 # Number of tag accesses 577system.cpu.dcache.tags.data_accesses 131480483 # Number of data accesses 578system.cpu.dcache.ReadReq_hits::cpu.data 45222500 # number of ReadReq hits 579system.cpu.dcache.ReadReq_hits::total 45222500 # number of ReadReq hits 580system.cpu.dcache.WriteReq_hits::cpu.data 20513893 # number of WriteReq hits 581system.cpu.dcache.WriteReq_hits::total 20513893 # number of WriteReq hits 582system.cpu.dcache.demand_hits::cpu.data 65736393 # number of demand (read+write) hits 583system.cpu.dcache.demand_hits::total 65736393 # number of demand (read+write) hits 584system.cpu.dcache.overall_hits::cpu.data 65736393 # number of overall hits 585system.cpu.dcache.overall_hits::total 65736393 # number of overall hits 586system.cpu.dcache.ReadReq_misses::cpu.data 1010 # number of ReadReq misses 587system.cpu.dcache.ReadReq_misses::total 1010 # number of ReadReq misses 588system.cpu.dcache.WriteReq_misses::cpu.data 1838 # number of WriteReq misses 589system.cpu.dcache.WriteReq_misses::total 1838 # number of WriteReq misses 590system.cpu.dcache.demand_misses::cpu.data 2848 # number of demand (read+write) misses 591system.cpu.dcache.demand_misses::total 2848 # number of demand (read+write) misses 592system.cpu.dcache.overall_misses::cpu.data 2848 # number of overall misses 593system.cpu.dcache.overall_misses::total 2848 # number of overall misses 594system.cpu.dcache.ReadReq_miss_latency::cpu.data 65396000 # number of ReadReq miss cycles 595system.cpu.dcache.ReadReq_miss_latency::total 65396000 # number of ReadReq miss cycles 596system.cpu.dcache.WriteReq_miss_latency::cpu.data 129164500 # number of WriteReq miss cycles 597system.cpu.dcache.WriteReq_miss_latency::total 129164500 # number of WriteReq miss cycles 598system.cpu.dcache.demand_miss_latency::cpu.data 194560500 # number of demand (read+write) miss cycles 599system.cpu.dcache.demand_miss_latency::total 194560500 # number of demand (read+write) miss cycles 600system.cpu.dcache.overall_miss_latency::cpu.data 194560500 # number of overall miss cycles 601system.cpu.dcache.overall_miss_latency::total 194560500 # number of overall miss cycles 602system.cpu.dcache.ReadReq_accesses::cpu.data 45223510 # number of ReadReq accesses(hits+misses) 603system.cpu.dcache.ReadReq_accesses::total 45223510 # number of ReadReq accesses(hits+misses) |
| 604system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) 605system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) | 604system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) 605system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) |
| 606system.cpu.dcache.demand_accesses::cpu.data 65704509 # number of demand (read+write) accesses 607system.cpu.dcache.demand_accesses::total 65704509 # number of demand (read+write) accesses 608system.cpu.dcache.overall_accesses::cpu.data 65704509 # number of overall (read+write) accesses 609system.cpu.dcache.overall_accesses::total 65704509 # number of overall (read+write) accesses | 606system.cpu.dcache.demand_accesses::cpu.data 65739241 # number of demand (read+write) accesses 607system.cpu.dcache.demand_accesses::total 65739241 # number of demand (read+write) accesses 608system.cpu.dcache.overall_accesses::cpu.data 65739241 # number of overall (read+write) accesses 609system.cpu.dcache.overall_accesses::total 65739241 # number of overall (read+write) accesses |
| 610system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses 611system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses 612system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000090 # miss rate for WriteReq accesses 613system.cpu.dcache.WriteReq_miss_rate::total 0.000090 # miss rate for WriteReq accesses 614system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses 615system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses 616system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses 617system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses | 610system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses 611system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses 612system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000090 # miss rate for WriteReq accesses 613system.cpu.dcache.WriteReq_miss_rate::total 0.000090 # miss rate for WriteReq accesses 614system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses 615system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses 616system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses 617system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses |
| 618system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66079.659319 # average ReadReq miss latency 619system.cpu.dcache.ReadReq_avg_miss_latency::total 66079.659319 # average ReadReq miss latency 620system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70079.175705 # average WriteReq miss latency 621system.cpu.dcache.WriteReq_avg_miss_latency::total 70079.175705 # average WriteReq miss latency 622system.cpu.dcache.demand_avg_miss_latency::cpu.data 68674.700915 # average overall miss latency 623system.cpu.dcache.demand_avg_miss_latency::total 68674.700915 # average overall miss latency 624system.cpu.dcache.overall_avg_miss_latency::cpu.data 68674.700915 # average overall miss latency 625system.cpu.dcache.overall_avg_miss_latency::total 68674.700915 # average overall miss latency 626system.cpu.dcache.blocked_cycles::no_mshrs 656 # number of cycles access was blocked | 618system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64748.514851 # average ReadReq miss latency 619system.cpu.dcache.ReadReq_avg_miss_latency::total 64748.514851 # average ReadReq miss latency 620system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70274.483134 # average WriteReq miss latency 621system.cpu.dcache.WriteReq_avg_miss_latency::total 70274.483134 # average WriteReq miss latency 622system.cpu.dcache.demand_avg_miss_latency::cpu.data 68314.782303 # average overall miss latency 623system.cpu.dcache.demand_avg_miss_latency::total 68314.782303 # average overall miss latency 624system.cpu.dcache.overall_avg_miss_latency::cpu.data 68314.782303 # average overall miss latency 625system.cpu.dcache.overall_avg_miss_latency::total 68314.782303 # average overall miss latency 626system.cpu.dcache.blocked_cycles::no_mshrs 697 # number of cycles access was blocked |
| 627system.cpu.dcache.blocked_cycles::no_targets 70 # number of cycles access was blocked | 627system.cpu.dcache.blocked_cycles::no_targets 70 # number of cycles access was blocked |
| 628system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked | 628system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked |
| 629system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked | 629system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked |
| 630system.cpu.dcache.avg_blocked_cycles::no_mshrs 93.714286 # average number of cycles each access was blocked | 630system.cpu.dcache.avg_blocked_cycles::no_mshrs 87.125000 # average number of cycles each access was blocked |
| 631system.cpu.dcache.avg_blocked_cycles::no_targets 70 # average number of cycles each access was blocked 632system.cpu.dcache.fast_writes 0 # number of fast writes performed 633system.cpu.dcache.cache_copies 0 # number of cache copies performed | 631system.cpu.dcache.avg_blocked_cycles::no_targets 70 # average number of cycles each access was blocked 632system.cpu.dcache.fast_writes 0 # number of fast writes performed 633system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 634system.cpu.dcache.writebacks::writebacks 12 # number of writebacks 635system.cpu.dcache.writebacks::total 12 # number of writebacks 636system.cpu.dcache.ReadReq_mshr_hits::cpu.data 541 # number of ReadReq MSHR hits 637system.cpu.dcache.ReadReq_mshr_hits::total 541 # number of ReadReq MSHR hits | 634system.cpu.dcache.writebacks::writebacks 10 # number of writebacks 635system.cpu.dcache.writebacks::total 10 # number of writebacks 636system.cpu.dcache.ReadReq_mshr_hits::cpu.data 549 # number of ReadReq MSHR hits 637system.cpu.dcache.ReadReq_mshr_hits::total 549 # number of ReadReq MSHR hits |
| 638system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits 639system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits | 638system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits 639system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits |
| 640system.cpu.dcache.demand_mshr_hits::cpu.data 543 # number of demand (read+write) MSHR hits 641system.cpu.dcache.demand_mshr_hits::total 543 # number of demand (read+write) MSHR hits 642system.cpu.dcache.overall_mshr_hits::cpu.data 543 # number of overall MSHR hits 643system.cpu.dcache.overall_mshr_hits::total 543 # number of overall MSHR hits 644system.cpu.dcache.ReadReq_mshr_misses::cpu.data 457 # number of ReadReq MSHR misses 645system.cpu.dcache.ReadReq_mshr_misses::total 457 # number of ReadReq MSHR misses 646system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1842 # number of WriteReq MSHR misses 647system.cpu.dcache.WriteReq_mshr_misses::total 1842 # number of WriteReq MSHR misses 648system.cpu.dcache.demand_mshr_misses::cpu.data 2299 # number of demand (read+write) MSHR misses 649system.cpu.dcache.demand_mshr_misses::total 2299 # number of demand (read+write) MSHR misses 650system.cpu.dcache.overall_mshr_misses::cpu.data 2299 # number of overall MSHR misses 651system.cpu.dcache.overall_mshr_misses::total 2299 # number of overall MSHR misses 652system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36552500 # number of ReadReq MSHR miss cycles 653system.cpu.dcache.ReadReq_mshr_miss_latency::total 36552500 # number of ReadReq MSHR miss cycles 654system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127238000 # number of WriteReq MSHR miss cycles 655system.cpu.dcache.WriteReq_mshr_miss_latency::total 127238000 # number of WriteReq MSHR miss cycles 656system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163790500 # number of demand (read+write) MSHR miss cycles 657system.cpu.dcache.demand_mshr_miss_latency::total 163790500 # number of demand (read+write) MSHR miss cycles 658system.cpu.dcache.overall_mshr_miss_latency::cpu.data 163790500 # number of overall MSHR miss cycles 659system.cpu.dcache.overall_mshr_miss_latency::total 163790500 # number of overall MSHR miss cycles | 640system.cpu.dcache.demand_mshr_hits::cpu.data 551 # number of demand (read+write) MSHR hits 641system.cpu.dcache.demand_mshr_hits::total 551 # number of demand (read+write) MSHR hits 642system.cpu.dcache.overall_mshr_hits::cpu.data 551 # number of overall MSHR hits 643system.cpu.dcache.overall_mshr_hits::total 551 # number of overall MSHR hits 644system.cpu.dcache.ReadReq_mshr_misses::cpu.data 461 # number of ReadReq MSHR misses 645system.cpu.dcache.ReadReq_mshr_misses::total 461 # number of ReadReq MSHR misses 646system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1836 # number of WriteReq MSHR misses 647system.cpu.dcache.WriteReq_mshr_misses::total 1836 # number of WriteReq MSHR misses 648system.cpu.dcache.demand_mshr_misses::cpu.data 2297 # number of demand (read+write) MSHR misses 649system.cpu.dcache.demand_mshr_misses::total 2297 # number of demand (read+write) MSHR misses 650system.cpu.dcache.overall_mshr_misses::cpu.data 2297 # number of overall MSHR misses 651system.cpu.dcache.overall_mshr_misses::total 2297 # number of overall MSHR misses 652system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36137000 # number of ReadReq MSHR miss cycles 653system.cpu.dcache.ReadReq_mshr_miss_latency::total 36137000 # number of ReadReq MSHR miss cycles 654system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127182500 # number of WriteReq MSHR miss cycles 655system.cpu.dcache.WriteReq_mshr_miss_latency::total 127182500 # number of WriteReq MSHR miss cycles 656system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163319500 # number of demand (read+write) MSHR miss cycles 657system.cpu.dcache.demand_mshr_miss_latency::total 163319500 # number of demand (read+write) MSHR miss cycles 658system.cpu.dcache.overall_mshr_miss_latency::cpu.data 163319500 # number of overall MSHR miss cycles 659system.cpu.dcache.overall_mshr_miss_latency::total 163319500 # number of overall MSHR miss cycles |
| 660system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses 661system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses | 660system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses 661system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses |
| 662system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000090 # mshr miss rate for WriteReq accesses 663system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000090 # mshr miss rate for WriteReq accesses | 662system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses 663system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses |
| 664system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for demand accesses 665system.cpu.dcache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses 666system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for overall accesses 667system.cpu.dcache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses | 664system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for demand accesses 665system.cpu.dcache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses 666system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for overall accesses 667system.cpu.dcache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses |
| 668system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79983.588621 # average ReadReq mshr miss latency 669system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79983.588621 # average ReadReq mshr miss latency 670system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69076.004343 # average WriteReq mshr miss latency 671system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69076.004343 # average WriteReq mshr miss latency 672system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71244.236625 # average overall mshr miss latency 673system.cpu.dcache.demand_avg_mshr_miss_latency::total 71244.236625 # average overall mshr miss latency 674system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71244.236625 # average overall mshr miss latency 675system.cpu.dcache.overall_avg_mshr_miss_latency::total 71244.236625 # average overall mshr miss latency | 668system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78388.286334 # average ReadReq mshr miss latency 669system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78388.286334 # average ReadReq mshr miss latency 670system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69271.514161 # average WriteReq mshr miss latency 671system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69271.514161 # average WriteReq mshr miss latency 672system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71101.218981 # average overall mshr miss latency 673system.cpu.dcache.demand_avg_mshr_miss_latency::total 71101.218981 # average overall mshr miss latency 674system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71101.218981 # average overall mshr miss latency 675system.cpu.dcache.overall_avg_mshr_miss_latency::total 71101.218981 # average overall mshr miss latency |
| 676system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 676system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 677system.cpu.icache.tags.replacements 5044 # number of replacements 678system.cpu.icache.tags.tagsinuse 1638.951309 # Cycle average of tags in use 679system.cpu.icache.tags.total_refs 24246301 # Total number of references to valid blocks. 680system.cpu.icache.tags.sampled_refs 7022 # Sample count of references to valid blocks. 681system.cpu.icache.tags.avg_refs 3452.905298 # Average number of references to valid blocks. | 677system.cpu.icache.tags.replacements 4970 # number of replacements 678system.cpu.icache.tags.tagsinuse 1639.175035 # Cycle average of tags in use 679system.cpu.icache.tags.total_refs 24244955 # Total number of references to valid blocks. 680system.cpu.icache.tags.sampled_refs 6947 # Sample count of references to valid blocks. 681system.cpu.icache.tags.avg_refs 3489.989204 # Average number of references to valid blocks. |
| 682system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 682system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 683system.cpu.icache.tags.occ_blocks::cpu.inst 1638.951309 # Average occupied blocks per requestor 684system.cpu.icache.tags.occ_percent::cpu.inst 0.800269 # Average percentage of cache occupancy 685system.cpu.icache.tags.occ_percent::total 0.800269 # Average percentage of cache occupancy 686system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id 687system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id 688system.cpu.icache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id 689system.cpu.icache.tags.age_task_id_blocks_1024::2 874 # Occupied blocks per task id 690system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id 691system.cpu.icache.tags.age_task_id_blocks_1024::4 790 # Occupied blocks per task id 692system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id 693system.cpu.icache.tags.tag_accesses 48518920 # Number of tag accesses 694system.cpu.icache.tags.data_accesses 48518920 # Number of data accesses 695system.cpu.icache.ReadReq_hits::cpu.inst 24246303 # number of ReadReq hits 696system.cpu.icache.ReadReq_hits::total 24246303 # number of ReadReq hits 697system.cpu.icache.demand_hits::cpu.inst 24246303 # number of demand (read+write) hits 698system.cpu.icache.demand_hits::total 24246303 # number of demand (read+write) hits 699system.cpu.icache.overall_hits::cpu.inst 24246303 # number of overall hits 700system.cpu.icache.overall_hits::total 24246303 # number of overall hits 701system.cpu.icache.ReadReq_misses::cpu.inst 9495 # number of ReadReq misses 702system.cpu.icache.ReadReq_misses::total 9495 # number of ReadReq misses 703system.cpu.icache.demand_misses::cpu.inst 9495 # number of demand (read+write) misses 704system.cpu.icache.demand_misses::total 9495 # number of demand (read+write) misses 705system.cpu.icache.overall_misses::cpu.inst 9495 # number of overall misses 706system.cpu.icache.overall_misses::total 9495 # number of overall misses 707system.cpu.icache.ReadReq_miss_latency::cpu.inst 408233999 # number of ReadReq miss cycles 708system.cpu.icache.ReadReq_miss_latency::total 408233999 # number of ReadReq miss cycles 709system.cpu.icache.demand_miss_latency::cpu.inst 408233999 # number of demand (read+write) miss cycles 710system.cpu.icache.demand_miss_latency::total 408233999 # number of demand (read+write) miss cycles 711system.cpu.icache.overall_miss_latency::cpu.inst 408233999 # number of overall miss cycles 712system.cpu.icache.overall_miss_latency::total 408233999 # number of overall miss cycles 713system.cpu.icache.ReadReq_accesses::cpu.inst 24255798 # number of ReadReq accesses(hits+misses) 714system.cpu.icache.ReadReq_accesses::total 24255798 # number of ReadReq accesses(hits+misses) 715system.cpu.icache.demand_accesses::cpu.inst 24255798 # number of demand (read+write) accesses 716system.cpu.icache.demand_accesses::total 24255798 # number of demand (read+write) accesses 717system.cpu.icache.overall_accesses::cpu.inst 24255798 # number of overall (read+write) accesses 718system.cpu.icache.overall_accesses::total 24255798 # number of overall (read+write) accesses 719system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000391 # miss rate for ReadReq accesses 720system.cpu.icache.ReadReq_miss_rate::total 0.000391 # miss rate for ReadReq accesses 721system.cpu.icache.demand_miss_rate::cpu.inst 0.000391 # miss rate for demand accesses 722system.cpu.icache.demand_miss_rate::total 0.000391 # miss rate for demand accesses 723system.cpu.icache.overall_miss_rate::cpu.inst 0.000391 # miss rate for overall accesses 724system.cpu.icache.overall_miss_rate::total 0.000391 # miss rate for overall accesses 725system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42994.628647 # average ReadReq miss latency 726system.cpu.icache.ReadReq_avg_miss_latency::total 42994.628647 # average ReadReq miss latency 727system.cpu.icache.demand_avg_miss_latency::cpu.inst 42994.628647 # average overall miss latency 728system.cpu.icache.demand_avg_miss_latency::total 42994.628647 # average overall miss latency 729system.cpu.icache.overall_avg_miss_latency::cpu.inst 42994.628647 # average overall miss latency 730system.cpu.icache.overall_avg_miss_latency::total 42994.628647 # average overall miss latency 731system.cpu.icache.blocked_cycles::no_mshrs 791 # number of cycles access was blocked | 683system.cpu.icache.tags.occ_blocks::cpu.inst 1639.175035 # Average occupied blocks per requestor 684system.cpu.icache.tags.occ_percent::cpu.inst 0.800378 # Average percentage of cache occupancy 685system.cpu.icache.tags.occ_percent::total 0.800378 # Average percentage of cache occupancy 686system.cpu.icache.tags.occ_task_id_blocks::1024 1977 # Occupied blocks per task id 687system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id 688system.cpu.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id 689system.cpu.icache.tags.age_task_id_blocks_1024::2 870 # Occupied blocks per task id 690system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id 691system.cpu.icache.tags.age_task_id_blocks_1024::4 793 # Occupied blocks per task id 692system.cpu.icache.tags.occ_task_id_percent::1024 0.965332 # Percentage of cache occupancy per task id 693system.cpu.icache.tags.tag_accesses 48515969 # Number of tag accesses 694system.cpu.icache.tags.data_accesses 48515969 # Number of data accesses 695system.cpu.icache.ReadReq_hits::cpu.inst 24244955 # number of ReadReq hits 696system.cpu.icache.ReadReq_hits::total 24244955 # number of ReadReq hits 697system.cpu.icache.demand_hits::cpu.inst 24244955 # number of demand (read+write) hits 698system.cpu.icache.demand_hits::total 24244955 # number of demand (read+write) hits 699system.cpu.icache.overall_hits::cpu.inst 24244955 # number of overall hits 700system.cpu.icache.overall_hits::total 24244955 # number of overall hits 701system.cpu.icache.ReadReq_misses::cpu.inst 9408 # number of ReadReq misses 702system.cpu.icache.ReadReq_misses::total 9408 # number of ReadReq misses 703system.cpu.icache.demand_misses::cpu.inst 9408 # number of demand (read+write) misses 704system.cpu.icache.demand_misses::total 9408 # number of demand (read+write) misses 705system.cpu.icache.overall_misses::cpu.inst 9408 # number of overall misses 706system.cpu.icache.overall_misses::total 9408 # number of overall misses 707system.cpu.icache.ReadReq_miss_latency::cpu.inst 407324999 # number of ReadReq miss cycles 708system.cpu.icache.ReadReq_miss_latency::total 407324999 # number of ReadReq miss cycles 709system.cpu.icache.demand_miss_latency::cpu.inst 407324999 # number of demand (read+write) miss cycles 710system.cpu.icache.demand_miss_latency::total 407324999 # number of demand (read+write) miss cycles 711system.cpu.icache.overall_miss_latency::cpu.inst 407324999 # number of overall miss cycles 712system.cpu.icache.overall_miss_latency::total 407324999 # number of overall miss cycles 713system.cpu.icache.ReadReq_accesses::cpu.inst 24254363 # number of ReadReq accesses(hits+misses) 714system.cpu.icache.ReadReq_accesses::total 24254363 # number of ReadReq accesses(hits+misses) 715system.cpu.icache.demand_accesses::cpu.inst 24254363 # number of demand (read+write) accesses 716system.cpu.icache.demand_accesses::total 24254363 # number of demand (read+write) accesses 717system.cpu.icache.overall_accesses::cpu.inst 24254363 # number of overall (read+write) accesses 718system.cpu.icache.overall_accesses::total 24254363 # number of overall (read+write) accesses 719system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000388 # miss rate for ReadReq accesses 720system.cpu.icache.ReadReq_miss_rate::total 0.000388 # miss rate for ReadReq accesses 721system.cpu.icache.demand_miss_rate::cpu.inst 0.000388 # miss rate for demand accesses 722system.cpu.icache.demand_miss_rate::total 0.000388 # miss rate for demand accesses 723system.cpu.icache.overall_miss_rate::cpu.inst 0.000388 # miss rate for overall accesses 724system.cpu.icache.overall_miss_rate::total 0.000388 # miss rate for overall accesses 725system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43295.599384 # average ReadReq miss latency 726system.cpu.icache.ReadReq_avg_miss_latency::total 43295.599384 # average ReadReq miss latency 727system.cpu.icache.demand_avg_miss_latency::cpu.inst 43295.599384 # average overall miss latency 728system.cpu.icache.demand_avg_miss_latency::total 43295.599384 # average overall miss latency 729system.cpu.icache.overall_avg_miss_latency::cpu.inst 43295.599384 # average overall miss latency 730system.cpu.icache.overall_avg_miss_latency::total 43295.599384 # average overall miss latency 731system.cpu.icache.blocked_cycles::no_mshrs 788 # number of cycles access was blocked |
| 732system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 732system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 733system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked | 733system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked |
| 734system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 734system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 735system.cpu.icache.avg_blocked_cycles::no_mshrs 60.846154 # average number of cycles each access was blocked | 735system.cpu.icache.avg_blocked_cycles::no_mshrs 65.666667 # average number of cycles each access was blocked |
| 736system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 737system.cpu.icache.fast_writes 0 # number of fast writes performed 738system.cpu.icache.cache_copies 0 # number of cache copies performed | 736system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 737system.cpu.icache.fast_writes 0 # number of fast writes performed 738system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 739system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2168 # number of ReadReq MSHR hits 740system.cpu.icache.ReadReq_mshr_hits::total 2168 # number of ReadReq MSHR hits 741system.cpu.icache.demand_mshr_hits::cpu.inst 2168 # number of demand (read+write) MSHR hits 742system.cpu.icache.demand_mshr_hits::total 2168 # number of demand (read+write) MSHR hits 743system.cpu.icache.overall_mshr_hits::cpu.inst 2168 # number of overall MSHR hits 744system.cpu.icache.overall_mshr_hits::total 2168 # number of overall MSHR hits 745system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7327 # number of ReadReq MSHR misses 746system.cpu.icache.ReadReq_mshr_misses::total 7327 # number of ReadReq MSHR misses 747system.cpu.icache.demand_mshr_misses::cpu.inst 7327 # number of demand (read+write) MSHR misses 748system.cpu.icache.demand_mshr_misses::total 7327 # number of demand (read+write) MSHR misses 749system.cpu.icache.overall_mshr_misses::cpu.inst 7327 # number of overall MSHR misses 750system.cpu.icache.overall_mshr_misses::total 7327 # number of overall MSHR misses 751system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 310311499 # number of ReadReq MSHR miss cycles 752system.cpu.icache.ReadReq_mshr_miss_latency::total 310311499 # number of ReadReq MSHR miss cycles 753system.cpu.icache.demand_mshr_miss_latency::cpu.inst 310311499 # number of demand (read+write) MSHR miss cycles 754system.cpu.icache.demand_mshr_miss_latency::total 310311499 # number of demand (read+write) MSHR miss cycles 755system.cpu.icache.overall_mshr_miss_latency::cpu.inst 310311499 # number of overall MSHR miss cycles 756system.cpu.icache.overall_mshr_miss_latency::total 310311499 # number of overall MSHR miss cycles 757system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000302 # mshr miss rate for ReadReq accesses 758system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000302 # mshr miss rate for ReadReq accesses 759system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000302 # mshr miss rate for demand accesses 760system.cpu.icache.demand_mshr_miss_rate::total 0.000302 # mshr miss rate for demand accesses 761system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000302 # mshr miss rate for overall accesses 762system.cpu.icache.overall_mshr_miss_rate::total 0.000302 # mshr miss rate for overall accesses 763system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42351.780947 # average ReadReq mshr miss latency 764system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42351.780947 # average ReadReq mshr miss latency 765system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42351.780947 # average overall mshr miss latency 766system.cpu.icache.demand_avg_mshr_miss_latency::total 42351.780947 # average overall mshr miss latency 767system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42351.780947 # average overall mshr miss latency 768system.cpu.icache.overall_avg_mshr_miss_latency::total 42351.780947 # average overall mshr miss latency | 739system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2164 # number of ReadReq MSHR hits 740system.cpu.icache.ReadReq_mshr_hits::total 2164 # number of ReadReq MSHR hits 741system.cpu.icache.demand_mshr_hits::cpu.inst 2164 # number of demand (read+write) MSHR hits 742system.cpu.icache.demand_mshr_hits::total 2164 # number of demand (read+write) MSHR hits 743system.cpu.icache.overall_mshr_hits::cpu.inst 2164 # number of overall MSHR hits 744system.cpu.icache.overall_mshr_hits::total 2164 # number of overall MSHR hits 745system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7244 # number of ReadReq MSHR misses 746system.cpu.icache.ReadReq_mshr_misses::total 7244 # number of ReadReq MSHR misses 747system.cpu.icache.demand_mshr_misses::cpu.inst 7244 # number of demand (read+write) MSHR misses 748system.cpu.icache.demand_mshr_misses::total 7244 # number of demand (read+write) MSHR misses 749system.cpu.icache.overall_mshr_misses::cpu.inst 7244 # number of overall MSHR misses 750system.cpu.icache.overall_mshr_misses::total 7244 # number of overall MSHR misses 751system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 309481499 # number of ReadReq MSHR miss cycles 752system.cpu.icache.ReadReq_mshr_miss_latency::total 309481499 # number of ReadReq MSHR miss cycles 753system.cpu.icache.demand_mshr_miss_latency::cpu.inst 309481499 # number of demand (read+write) MSHR miss cycles 754system.cpu.icache.demand_mshr_miss_latency::total 309481499 # number of demand (read+write) MSHR miss cycles 755system.cpu.icache.overall_mshr_miss_latency::cpu.inst 309481499 # number of overall MSHR miss cycles 756system.cpu.icache.overall_mshr_miss_latency::total 309481499 # number of overall MSHR miss cycles 757system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for ReadReq accesses 758system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000299 # mshr miss rate for ReadReq accesses 759system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for demand accesses 760system.cpu.icache.demand_mshr_miss_rate::total 0.000299 # mshr miss rate for demand accesses 761system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for overall accesses 762system.cpu.icache.overall_mshr_miss_rate::total 0.000299 # mshr miss rate for overall accesses 763system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42722.459829 # average ReadReq mshr miss latency 764system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42722.459829 # average ReadReq mshr miss latency 765system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42722.459829 # average overall mshr miss latency 766system.cpu.icache.demand_avg_mshr_miss_latency::total 42722.459829 # average overall mshr miss latency 767system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42722.459829 # average overall mshr miss latency 768system.cpu.icache.overall_avg_mshr_miss_latency::total 42722.459829 # average overall mshr miss latency |
| 769system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 770system.cpu.l2cache.tags.replacements 0 # number of replacements | 769system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 770system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 771system.cpu.l2cache.tags.tagsinuse 2588.297524 # Cycle average of tags in use 772system.cpu.l2cache.tags.total_refs 8549 # Total number of references to valid blocks. 773system.cpu.l2cache.tags.sampled_refs 3882 # Sample count of references to valid blocks. 774system.cpu.l2cache.tags.avg_refs 2.202215 # Average number of references to valid blocks. | 771system.cpu.l2cache.tags.tagsinuse 2588.929088 # Cycle average of tags in use 772system.cpu.l2cache.tags.total_refs 8413 # Total number of references to valid blocks. 773system.cpu.l2cache.tags.sampled_refs 3873 # Sample count of references to valid blocks. 774system.cpu.l2cache.tags.avg_refs 2.172218 # Average number of references to valid blocks. |
| 775system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 775system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 776system.cpu.l2cache.tags.occ_blocks::writebacks 0.823385 # Average occupied blocks per requestor 777system.cpu.l2cache.tags.occ_blocks::cpu.inst 2282.748954 # Average occupied blocks per requestor 778system.cpu.l2cache.tags.occ_blocks::cpu.data 304.725185 # Average occupied blocks per requestor 779system.cpu.l2cache.tags.occ_percent::writebacks 0.000025 # Average percentage of cache occupancy 780system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069664 # Average percentage of cache occupancy 781system.cpu.l2cache.tags.occ_percent::cpu.data 0.009299 # Average percentage of cache occupancy 782system.cpu.l2cache.tags.occ_percent::total 0.078989 # Average percentage of cache occupancy 783system.cpu.l2cache.tags.occ_task_id_blocks::1024 3882 # Occupied blocks per task id 784system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 785system.cpu.l2cache.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id 786system.cpu.l2cache.tags.age_task_id_blocks_1024::2 994 # Occupied blocks per task id 787system.cpu.l2cache.tags.age_task_id_blocks_1024::3 40 # Occupied blocks per task id 788system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2615 # Occupied blocks per task id 789system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118469 # Percentage of cache occupancy per task id 790system.cpu.l2cache.tags.tag_accesses 119661 # Number of tag accesses 791system.cpu.l2cache.tags.data_accesses 119661 # Number of data accesses 792system.cpu.l2cache.Writeback_hits::writebacks 12 # number of Writeback hits 793system.cpu.l2cache.Writeback_hits::total 12 # number of Writeback hits 794system.cpu.l2cache.ReadExReq_hits::cpu.data 5 # number of ReadExReq hits 795system.cpu.l2cache.ReadExReq_hits::total 5 # number of ReadExReq hits 796system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3560 # number of ReadCleanReq hits 797system.cpu.l2cache.ReadCleanReq_hits::total 3560 # number of ReadCleanReq hits 798system.cpu.l2cache.ReadSharedReq_hits::cpu.data 39 # number of ReadSharedReq hits 799system.cpu.l2cache.ReadSharedReq_hits::total 39 # number of ReadSharedReq hits 800system.cpu.l2cache.demand_hits::cpu.inst 3560 # number of demand (read+write) hits 801system.cpu.l2cache.demand_hits::cpu.data 44 # number of demand (read+write) hits 802system.cpu.l2cache.demand_hits::total 3604 # number of demand (read+write) hits 803system.cpu.l2cache.overall_hits::cpu.inst 3560 # number of overall hits 804system.cpu.l2cache.overall_hits::cpu.data 44 # number of overall hits 805system.cpu.l2cache.overall_hits::total 3604 # number of overall hits 806system.cpu.l2cache.UpgradeReq_misses::cpu.data 303 # number of UpgradeReq misses 807system.cpu.l2cache.UpgradeReq_misses::total 303 # number of UpgradeReq misses | 776system.cpu.l2cache.tags.occ_blocks::writebacks 1.256976 # Average occupied blocks per requestor 777system.cpu.l2cache.tags.occ_blocks::cpu.inst 2282.894376 # Average occupied blocks per requestor 778system.cpu.l2cache.tags.occ_blocks::cpu.data 304.777736 # Average occupied blocks per requestor 779system.cpu.l2cache.tags.occ_percent::writebacks 0.000038 # Average percentage of cache occupancy 780system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069668 # Average percentage of cache occupancy 781system.cpu.l2cache.tags.occ_percent::cpu.data 0.009301 # Average percentage of cache occupancy 782system.cpu.l2cache.tags.occ_percent::total 0.079008 # Average percentage of cache occupancy 783system.cpu.l2cache.tags.occ_task_id_blocks::1024 3873 # Occupied blocks per task id 784system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id 785system.cpu.l2cache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id 786system.cpu.l2cache.tags.age_task_id_blocks_1024::2 989 # Occupied blocks per task id 787system.cpu.l2cache.tags.age_task_id_blocks_1024::3 39 # Occupied blocks per task id 788system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2616 # Occupied blocks per task id 789system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118195 # Percentage of cache occupancy per task id 790system.cpu.l2cache.tags.tag_accesses 118429 # Number of tag accesses 791system.cpu.l2cache.tags.data_accesses 118429 # Number of data accesses 792system.cpu.l2cache.Writeback_hits::writebacks 10 # number of Writeback hits 793system.cpu.l2cache.Writeback_hits::total 10 # number of Writeback hits 794system.cpu.l2cache.ReadExReq_hits::cpu.data 6 # number of ReadExReq hits 795system.cpu.l2cache.ReadExReq_hits::total 6 # number of ReadExReq hits 796system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3494 # number of ReadCleanReq hits 797system.cpu.l2cache.ReadCleanReq_hits::total 3494 # number of ReadCleanReq hits 798system.cpu.l2cache.ReadSharedReq_hits::cpu.data 40 # number of ReadSharedReq hits 799system.cpu.l2cache.ReadSharedReq_hits::total 40 # number of ReadSharedReq hits 800system.cpu.l2cache.demand_hits::cpu.inst 3494 # number of demand (read+write) hits 801system.cpu.l2cache.demand_hits::cpu.data 46 # number of demand (read+write) hits 802system.cpu.l2cache.demand_hits::total 3540 # number of demand (read+write) hits 803system.cpu.l2cache.overall_hits::cpu.inst 3494 # number of overall hits 804system.cpu.l2cache.overall_hits::cpu.data 46 # number of overall hits 805system.cpu.l2cache.overall_hits::total 3540 # number of overall hits 806system.cpu.l2cache.UpgradeReq_misses::cpu.data 296 # number of UpgradeReq misses 807system.cpu.l2cache.UpgradeReq_misses::total 296 # number of UpgradeReq misses |
| 808system.cpu.l2cache.ReadExReq_misses::cpu.data 1534 # number of ReadExReq misses 809system.cpu.l2cache.ReadExReq_misses::total 1534 # number of ReadExReq misses | 808system.cpu.l2cache.ReadExReq_misses::cpu.data 1534 # number of ReadExReq misses 809system.cpu.l2cache.ReadExReq_misses::total 1534 # number of ReadExReq misses |
| 810system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3462 # number of ReadCleanReq misses 811system.cpu.l2cache.ReadCleanReq_misses::total 3462 # number of ReadCleanReq misses 812system.cpu.l2cache.ReadSharedReq_misses::cpu.data 418 # number of ReadSharedReq misses 813system.cpu.l2cache.ReadSharedReq_misses::total 418 # number of ReadSharedReq misses 814system.cpu.l2cache.demand_misses::cpu.inst 3462 # number of demand (read+write) misses 815system.cpu.l2cache.demand_misses::cpu.data 1952 # number of demand (read+write) misses 816system.cpu.l2cache.demand_misses::total 5414 # number of demand (read+write) misses 817system.cpu.l2cache.overall_misses::cpu.inst 3462 # number of overall misses 818system.cpu.l2cache.overall_misses::cpu.data 1952 # number of overall misses 819system.cpu.l2cache.overall_misses::total 5414 # number of overall misses 820system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 115109000 # number of ReadExReq miss cycles 821system.cpu.l2cache.ReadExReq_miss_latency::total 115109000 # number of ReadExReq miss cycles 822system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 261483000 # number of ReadCleanReq miss cycles 823system.cpu.l2cache.ReadCleanReq_miss_latency::total 261483000 # number of ReadCleanReq miss cycles 824system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35445000 # number of ReadSharedReq miss cycles 825system.cpu.l2cache.ReadSharedReq_miss_latency::total 35445000 # number of ReadSharedReq miss cycles 826system.cpu.l2cache.demand_miss_latency::cpu.inst 261483000 # number of demand (read+write) miss cycles 827system.cpu.l2cache.demand_miss_latency::cpu.data 150554000 # number of demand (read+write) miss cycles 828system.cpu.l2cache.demand_miss_latency::total 412037000 # number of demand (read+write) miss cycles 829system.cpu.l2cache.overall_miss_latency::cpu.inst 261483000 # number of overall miss cycles 830system.cpu.l2cache.overall_miss_latency::cpu.data 150554000 # number of overall miss cycles 831system.cpu.l2cache.overall_miss_latency::total 412037000 # number of overall miss cycles 832system.cpu.l2cache.Writeback_accesses::writebacks 12 # number of Writeback accesses(hits+misses) 833system.cpu.l2cache.Writeback_accesses::total 12 # number of Writeback accesses(hits+misses) 834system.cpu.l2cache.UpgradeReq_accesses::cpu.data 303 # number of UpgradeReq accesses(hits+misses) 835system.cpu.l2cache.UpgradeReq_accesses::total 303 # number of UpgradeReq accesses(hits+misses) 836system.cpu.l2cache.ReadExReq_accesses::cpu.data 1539 # number of ReadExReq accesses(hits+misses) 837system.cpu.l2cache.ReadExReq_accesses::total 1539 # number of ReadExReq accesses(hits+misses) 838system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 7022 # number of ReadCleanReq accesses(hits+misses) 839system.cpu.l2cache.ReadCleanReq_accesses::total 7022 # number of ReadCleanReq accesses(hits+misses) 840system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 457 # number of ReadSharedReq accesses(hits+misses) 841system.cpu.l2cache.ReadSharedReq_accesses::total 457 # number of ReadSharedReq accesses(hits+misses) 842system.cpu.l2cache.demand_accesses::cpu.inst 7022 # number of demand (read+write) accesses 843system.cpu.l2cache.demand_accesses::cpu.data 1996 # number of demand (read+write) accesses 844system.cpu.l2cache.demand_accesses::total 9018 # number of demand (read+write) accesses 845system.cpu.l2cache.overall_accesses::cpu.inst 7022 # number of overall (read+write) accesses 846system.cpu.l2cache.overall_accesses::cpu.data 1996 # number of overall (read+write) accesses 847system.cpu.l2cache.overall_accesses::total 9018 # number of overall (read+write) accesses | 810system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3451 # number of ReadCleanReq misses 811system.cpu.l2cache.ReadCleanReq_misses::total 3451 # number of ReadCleanReq misses 812system.cpu.l2cache.ReadSharedReq_misses::cpu.data 421 # number of ReadSharedReq misses 813system.cpu.l2cache.ReadSharedReq_misses::total 421 # number of ReadSharedReq misses 814system.cpu.l2cache.demand_misses::cpu.inst 3451 # number of demand (read+write) misses 815system.cpu.l2cache.demand_misses::cpu.data 1955 # number of demand (read+write) misses 816system.cpu.l2cache.demand_misses::total 5406 # number of demand (read+write) misses 817system.cpu.l2cache.overall_misses::cpu.inst 3451 # number of overall misses 818system.cpu.l2cache.overall_misses::cpu.data 1955 # number of overall misses 819system.cpu.l2cache.overall_misses::total 5406 # number of overall misses 820system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 114989000 # number of ReadExReq miss cycles 821system.cpu.l2cache.ReadExReq_miss_latency::total 114989000 # number of ReadExReq miss cycles 822system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 261344500 # number of ReadCleanReq miss cycles 823system.cpu.l2cache.ReadCleanReq_miss_latency::total 261344500 # number of ReadCleanReq miss cycles 824system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 34980500 # number of ReadSharedReq miss cycles 825system.cpu.l2cache.ReadSharedReq_miss_latency::total 34980500 # number of ReadSharedReq miss cycles 826system.cpu.l2cache.demand_miss_latency::cpu.inst 261344500 # number of demand (read+write) miss cycles 827system.cpu.l2cache.demand_miss_latency::cpu.data 149969500 # number of demand (read+write) miss cycles 828system.cpu.l2cache.demand_miss_latency::total 411314000 # number of demand (read+write) miss cycles 829system.cpu.l2cache.overall_miss_latency::cpu.inst 261344500 # number of overall miss cycles 830system.cpu.l2cache.overall_miss_latency::cpu.data 149969500 # number of overall miss cycles 831system.cpu.l2cache.overall_miss_latency::total 411314000 # number of overall miss cycles 832system.cpu.l2cache.Writeback_accesses::writebacks 10 # number of Writeback accesses(hits+misses) 833system.cpu.l2cache.Writeback_accesses::total 10 # number of Writeback accesses(hits+misses) 834system.cpu.l2cache.UpgradeReq_accesses::cpu.data 296 # number of UpgradeReq accesses(hits+misses) 835system.cpu.l2cache.UpgradeReq_accesses::total 296 # number of UpgradeReq accesses(hits+misses) 836system.cpu.l2cache.ReadExReq_accesses::cpu.data 1540 # number of ReadExReq accesses(hits+misses) 837system.cpu.l2cache.ReadExReq_accesses::total 1540 # number of ReadExReq accesses(hits+misses) 838system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6945 # number of ReadCleanReq accesses(hits+misses) 839system.cpu.l2cache.ReadCleanReq_accesses::total 6945 # number of ReadCleanReq accesses(hits+misses) 840system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 461 # number of ReadSharedReq accesses(hits+misses) 841system.cpu.l2cache.ReadSharedReq_accesses::total 461 # number of ReadSharedReq accesses(hits+misses) 842system.cpu.l2cache.demand_accesses::cpu.inst 6945 # number of demand (read+write) accesses 843system.cpu.l2cache.demand_accesses::cpu.data 2001 # number of demand (read+write) accesses 844system.cpu.l2cache.demand_accesses::total 8946 # number of demand (read+write) accesses 845system.cpu.l2cache.overall_accesses::cpu.inst 6945 # number of overall (read+write) accesses 846system.cpu.l2cache.overall_accesses::cpu.data 2001 # number of overall (read+write) accesses 847system.cpu.l2cache.overall_accesses::total 8946 # number of overall (read+write) accesses |
| 848system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 849system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses | 848system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 849system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses |
| 850system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996751 # miss rate for ReadExReq accesses 851system.cpu.l2cache.ReadExReq_miss_rate::total 0.996751 # miss rate for ReadExReq accesses 852system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.493022 # miss rate for ReadCleanReq accesses 853system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.493022 # miss rate for ReadCleanReq accesses 854system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.914661 # miss rate for ReadSharedReq accesses 855system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.914661 # miss rate for ReadSharedReq accesses 856system.cpu.l2cache.demand_miss_rate::cpu.inst 0.493022 # miss rate for demand accesses 857system.cpu.l2cache.demand_miss_rate::cpu.data 0.977956 # miss rate for demand accesses 858system.cpu.l2cache.demand_miss_rate::total 0.600355 # miss rate for demand accesses 859system.cpu.l2cache.overall_miss_rate::cpu.inst 0.493022 # miss rate for overall accesses 860system.cpu.l2cache.overall_miss_rate::cpu.data 0.977956 # miss rate for overall accesses 861system.cpu.l2cache.overall_miss_rate::total 0.600355 # miss rate for overall accesses 862system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75038.461538 # average ReadExReq miss latency 863system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75038.461538 # average ReadExReq miss latency 864system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75529.462738 # average ReadCleanReq miss latency 865system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75529.462738 # average ReadCleanReq miss latency 866system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84796.650718 # average ReadSharedReq miss latency 867system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84796.650718 # average ReadSharedReq miss latency 868system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75529.462738 # average overall miss latency 869system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77128.073770 # average overall miss latency 870system.cpu.l2cache.demand_avg_miss_latency::total 76105.836720 # average overall miss latency 871system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75529.462738 # average overall miss latency 872system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77128.073770 # average overall miss latency 873system.cpu.l2cache.overall_avg_miss_latency::total 76105.836720 # average overall miss latency | 850system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996104 # miss rate for ReadExReq accesses 851system.cpu.l2cache.ReadExReq_miss_rate::total 0.996104 # miss rate for ReadExReq accesses 852system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.496904 # miss rate for ReadCleanReq accesses 853system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.496904 # miss rate for ReadCleanReq accesses 854system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.913232 # miss rate for ReadSharedReq accesses 855system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.913232 # miss rate for ReadSharedReq accesses 856system.cpu.l2cache.demand_miss_rate::cpu.inst 0.496904 # miss rate for demand accesses 857system.cpu.l2cache.demand_miss_rate::cpu.data 0.977011 # miss rate for demand accesses 858system.cpu.l2cache.demand_miss_rate::total 0.604292 # miss rate for demand accesses 859system.cpu.l2cache.overall_miss_rate::cpu.inst 0.496904 # miss rate for overall accesses 860system.cpu.l2cache.overall_miss_rate::cpu.data 0.977011 # miss rate for overall accesses 861system.cpu.l2cache.overall_miss_rate::total 0.604292 # miss rate for overall accesses 862system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74960.234681 # average ReadExReq miss latency 863system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74960.234681 # average ReadExReq miss latency 864system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75730.078238 # average ReadCleanReq miss latency 865system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75730.078238 # average ReadCleanReq miss latency 866system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83089.073634 # average ReadSharedReq miss latency 867system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83089.073634 # average ReadSharedReq miss latency 868system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75730.078238 # average overall miss latency 869system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76710.741688 # average overall miss latency 870system.cpu.l2cache.demand_avg_miss_latency::total 76084.720681 # average overall miss latency 871system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75730.078238 # average overall miss latency 872system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76710.741688 # average overall miss latency 873system.cpu.l2cache.overall_avg_miss_latency::total 76084.720681 # average overall miss latency |
| 874system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 875system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 876system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 877system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 878system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 879system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 880system.cpu.l2cache.fast_writes 0 # number of fast writes performed 881system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 874system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 875system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 876system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 877system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 878system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 879system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 880system.cpu.l2cache.fast_writes 0 # number of fast writes performed 881system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 882system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 303 # number of UpgradeReq MSHR misses 883system.cpu.l2cache.UpgradeReq_mshr_misses::total 303 # number of UpgradeReq MSHR misses | 882system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 296 # number of UpgradeReq MSHR misses 883system.cpu.l2cache.UpgradeReq_mshr_misses::total 296 # number of UpgradeReq MSHR misses |
| 884system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1534 # number of ReadExReq MSHR misses 885system.cpu.l2cache.ReadExReq_mshr_misses::total 1534 # number of ReadExReq MSHR misses | 884system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1534 # number of ReadExReq MSHR misses 885system.cpu.l2cache.ReadExReq_mshr_misses::total 1534 # number of ReadExReq MSHR misses |
| 886system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3462 # number of ReadCleanReq MSHR misses 887system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3462 # number of ReadCleanReq MSHR misses 888system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 418 # number of ReadSharedReq MSHR misses 889system.cpu.l2cache.ReadSharedReq_mshr_misses::total 418 # number of ReadSharedReq MSHR misses 890system.cpu.l2cache.demand_mshr_misses::cpu.inst 3462 # number of demand (read+write) MSHR misses 891system.cpu.l2cache.demand_mshr_misses::cpu.data 1952 # number of demand (read+write) MSHR misses 892system.cpu.l2cache.demand_mshr_misses::total 5414 # number of demand (read+write) MSHR misses 893system.cpu.l2cache.overall_mshr_misses::cpu.inst 3462 # number of overall MSHR misses 894system.cpu.l2cache.overall_mshr_misses::cpu.data 1952 # number of overall MSHR misses 895system.cpu.l2cache.overall_mshr_misses::total 5414 # number of overall MSHR misses 896system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6283500 # number of UpgradeReq MSHR miss cycles 897system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6283500 # number of UpgradeReq MSHR miss cycles 898system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 99769000 # number of ReadExReq MSHR miss cycles 899system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 99769000 # number of ReadExReq MSHR miss cycles 900system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 226893000 # number of ReadCleanReq MSHR miss cycles 901system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 226893000 # number of ReadCleanReq MSHR miss cycles 902system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31265000 # number of ReadSharedReq MSHR miss cycles 903system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31265000 # number of ReadSharedReq MSHR miss cycles 904system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 226893000 # number of demand (read+write) MSHR miss cycles 905system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131034000 # number of demand (read+write) MSHR miss cycles 906system.cpu.l2cache.demand_mshr_miss_latency::total 357927000 # number of demand (read+write) MSHR miss cycles 907system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 226893000 # number of overall MSHR miss cycles 908system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131034000 # number of overall MSHR miss cycles 909system.cpu.l2cache.overall_mshr_miss_latency::total 357927000 # number of overall MSHR miss cycles | 886system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3451 # number of ReadCleanReq MSHR misses 887system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3451 # number of ReadCleanReq MSHR misses 888system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 421 # number of ReadSharedReq MSHR misses 889system.cpu.l2cache.ReadSharedReq_mshr_misses::total 421 # number of ReadSharedReq MSHR misses 890system.cpu.l2cache.demand_mshr_misses::cpu.inst 3451 # number of demand (read+write) MSHR misses 891system.cpu.l2cache.demand_mshr_misses::cpu.data 1955 # number of demand (read+write) MSHR misses 892system.cpu.l2cache.demand_mshr_misses::total 5406 # number of demand (read+write) MSHR misses 893system.cpu.l2cache.overall_mshr_misses::cpu.inst 3451 # number of overall MSHR misses 894system.cpu.l2cache.overall_mshr_misses::cpu.data 1955 # number of overall MSHR misses 895system.cpu.l2cache.overall_mshr_misses::total 5406 # number of overall MSHR misses 896system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6416500 # number of UpgradeReq MSHR miss cycles 897system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6416500 # number of UpgradeReq MSHR miss cycles 898system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 99649000 # number of ReadExReq MSHR miss cycles 899system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 99649000 # number of ReadExReq MSHR miss cycles 900system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 226844500 # number of ReadCleanReq MSHR miss cycles 901system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 226844500 # number of ReadCleanReq MSHR miss cycles 902system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30770500 # number of ReadSharedReq MSHR miss cycles 903system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30770500 # number of ReadSharedReq MSHR miss cycles 904system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 226844500 # number of demand (read+write) MSHR miss cycles 905system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 130419500 # number of demand (read+write) MSHR miss cycles 906system.cpu.l2cache.demand_mshr_miss_latency::total 357264000 # number of demand (read+write) MSHR miss cycles 907system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 226844500 # number of overall MSHR miss cycles 908system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 130419500 # number of overall MSHR miss cycles 909system.cpu.l2cache.overall_mshr_miss_latency::total 357264000 # number of overall MSHR miss cycles |
| 910system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 911system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses | 910system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 911system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses |
| 912system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996751 # mshr miss rate for ReadExReq accesses 913system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996751 # mshr miss rate for ReadExReq accesses 914system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.493022 # mshr miss rate for ReadCleanReq accesses 915system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.493022 # mshr miss rate for ReadCleanReq accesses 916system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.914661 # mshr miss rate for ReadSharedReq accesses 917system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.914661 # mshr miss rate for ReadSharedReq accesses 918system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.493022 # mshr miss rate for demand accesses 919system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.977956 # mshr miss rate for demand accesses 920system.cpu.l2cache.demand_mshr_miss_rate::total 0.600355 # mshr miss rate for demand accesses 921system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.493022 # mshr miss rate for overall accesses 922system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.977956 # mshr miss rate for overall accesses 923system.cpu.l2cache.overall_mshr_miss_rate::total 0.600355 # mshr miss rate for overall accesses 924system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20737.623762 # average UpgradeReq mshr miss latency 925system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20737.623762 # average UpgradeReq mshr miss latency 926system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65038.461538 # average ReadExReq mshr miss latency 927system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65038.461538 # average ReadExReq mshr miss latency 928system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65538.128250 # average ReadCleanReq mshr miss latency 929system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65538.128250 # average ReadCleanReq mshr miss latency 930system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74796.650718 # average ReadSharedReq mshr miss latency 931system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74796.650718 # average ReadSharedReq mshr miss latency 932system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65538.128250 # average overall mshr miss latency 933system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67128.073770 # average overall mshr miss latency 934system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66111.377909 # average overall mshr miss latency 935system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65538.128250 # average overall mshr miss latency 936system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67128.073770 # average overall mshr miss latency 937system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66111.377909 # average overall mshr miss latency | 912system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996104 # mshr miss rate for ReadExReq accesses 913system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996104 # mshr miss rate for ReadExReq accesses 914system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.496904 # mshr miss rate for ReadCleanReq accesses 915system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.496904 # mshr miss rate for ReadCleanReq accesses 916system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.913232 # mshr miss rate for ReadSharedReq accesses 917system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.913232 # mshr miss rate for ReadSharedReq accesses 918system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.496904 # mshr miss rate for demand accesses 919system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.977011 # mshr miss rate for demand accesses 920system.cpu.l2cache.demand_mshr_miss_rate::total 0.604292 # mshr miss rate for demand accesses 921system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496904 # mshr miss rate for overall accesses 922system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.977011 # mshr miss rate for overall accesses 923system.cpu.l2cache.overall_mshr_miss_rate::total 0.604292 # mshr miss rate for overall accesses 924system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21677.364865 # average UpgradeReq mshr miss latency 925system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21677.364865 # average UpgradeReq mshr miss latency 926system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64960.234681 # average ReadExReq mshr miss latency 927system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64960.234681 # average ReadExReq mshr miss latency 928system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65732.975949 # average ReadCleanReq mshr miss latency 929system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65732.975949 # average ReadCleanReq mshr miss latency 930system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73089.073634 # average ReadSharedReq mshr miss latency 931system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73089.073634 # average ReadSharedReq mshr miss latency 932system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65732.975949 # average overall mshr miss latency 933system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66710.741688 # average overall mshr miss latency 934system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66086.570477 # average overall mshr miss latency 935system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65732.975949 # average overall mshr miss latency 936system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66710.741688 # average overall mshr miss latency 937system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66086.570477 # average overall mshr miss latency |
| 938system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 938system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 939system.cpu.toL2Bus.trans_dist::ReadResp 7781 # Transaction distribution 940system.cpu.toL2Bus.trans_dist::Writeback 12 # Transaction distribution 941system.cpu.toL2Bus.trans_dist::CleanEvict 4947 # Transaction distribution 942system.cpu.toL2Bus.trans_dist::UpgradeReq 303 # Transaction distribution 943system.cpu.toL2Bus.trans_dist::UpgradeResp 303 # Transaction distribution 944system.cpu.toL2Bus.trans_dist::ReadExReq 1539 # Transaction distribution 945system.cpu.toL2Bus.trans_dist::ReadExResp 1539 # Transaction distribution 946system.cpu.toL2Bus.trans_dist::ReadCleanReq 7327 # Transaction distribution 947system.cpu.toL2Bus.trans_dist::ReadSharedReq 457 # Transaction distribution 948system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19253 # Packet count per connected master and slave (bytes) 949system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4650 # Packet count per connected master and slave (bytes) 950system.cpu.toL2Bus.pkt_count::total 23903 # Packet count per connected master and slave (bytes) 951system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 449216 # Cumulative packet size per connected master and slave (bytes) 952system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128512 # Cumulative packet size per connected master and slave (bytes) 953system.cpu.toL2Bus.pkt_size::total 577728 # Cumulative packet size per connected master and slave (bytes) 954system.cpu.toL2Bus.snoops 305 # Total snoops (count) 955system.cpu.toL2Bus.snoop_fanout::samples 14723 # Request fanout histogram 956system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 957system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram | 939system.cpu.toL2Bus.snoop_filter.tot_requests 14563 # Total number of requests made to the snoop filter. 940system.cpu.toL2Bus.snoop_filter.hit_single_requests 5344 # Number of requests hitting in the snoop filter with a single holder of the requested data. 941system.cpu.toL2Bus.snoop_filter.hit_multi_requests 433 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 942system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 943system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 944system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 945system.cpu.toL2Bus.trans_dist::ReadResp 7704 # Transaction distribution 946system.cpu.toL2Bus.trans_dist::Writeback 10 # Transaction distribution 947system.cpu.toL2Bus.trans_dist::CleanEvict 4875 # Transaction distribution 948system.cpu.toL2Bus.trans_dist::UpgradeReq 296 # Transaction distribution 949system.cpu.toL2Bus.trans_dist::UpgradeResp 296 # Transaction distribution 950system.cpu.toL2Bus.trans_dist::ReadExReq 1540 # Transaction distribution 951system.cpu.toL2Bus.trans_dist::ReadExResp 1540 # Transaction distribution 952system.cpu.toL2Bus.trans_dist::ReadCleanReq 7244 # Transaction distribution 953system.cpu.toL2Bus.trans_dist::ReadSharedReq 461 # Transaction distribution 954system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19022 # Packet count per connected master and slave (bytes) 955system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4645 # Packet count per connected master and slave (bytes) 956system.cpu.toL2Bus.pkt_count::total 23667 # Packet count per connected master and slave (bytes) 957system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 444416 # Cumulative packet size per connected master and slave (bytes) 958system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128704 # Cumulative packet size per connected master and slave (bytes) 959system.cpu.toL2Bus.pkt_size::total 573120 # Cumulative packet size per connected master and slave (bytes) 960system.cpu.toL2Bus.snoops 299 # Total snoops (count) 961system.cpu.toL2Bus.snoop_fanout::samples 14563 # Request fanout histogram 962system.cpu.toL2Bus.snoop_fanout::mean 0.061251 # Request fanout histogram 963system.cpu.toL2Bus.snoop_fanout::stdev 0.239799 # Request fanout histogram |
| 958system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 964system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 959system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 960system.cpu.toL2Bus.snoop_fanout::1 14723 100.00% 100.00% # Request fanout histogram | 965system.cpu.toL2Bus.snoop_fanout::0 13671 93.87% 93.87% # Request fanout histogram 966system.cpu.toL2Bus.snoop_fanout::1 892 6.13% 100.00% # Request fanout histogram |
| 961system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 962system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 967system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 968system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 963system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram | 969system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| 964system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 970system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 965system.cpu.toL2Bus.snoop_fanout::total 14723 # Request fanout histogram 966system.cpu.toL2Bus.reqLayer0.occupancy 7373500 # Layer occupancy (ticks) | 971system.cpu.toL2Bus.snoop_fanout::total 14563 # Request fanout histogram 972system.cpu.toL2Bus.reqLayer0.occupancy 7291500 # Layer occupancy (ticks) |
| 967system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 973system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 968system.cpu.toL2Bus.respLayer0.occupancy 10986000 # Layer occupancy (ticks) | 974system.cpu.toL2Bus.respLayer0.occupancy 10864500 # Layer occupancy (ticks) |
| 969system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 975system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 970system.cpu.toL2Bus.respLayer1.occupancy 3145500 # Layer occupancy (ticks) | 976system.cpu.toL2Bus.respLayer1.occupancy 3149999 # Layer occupancy (ticks) |
| 971system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 977system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 972system.membus.trans_dist::ReadResp 3877 # Transaction distribution 973system.membus.trans_dist::UpgradeReq 303 # Transaction distribution 974system.membus.trans_dist::UpgradeResp 303 # Transaction distribution | 978system.membus.trans_dist::ReadResp 3871 # Transaction distribution 979system.membus.trans_dist::UpgradeReq 296 # Transaction distribution 980system.membus.trans_dist::UpgradeResp 296 # Transaction distribution |
| 975system.membus.trans_dist::ReadExReq 1534 # Transaction distribution 976system.membus.trans_dist::ReadExResp 1534 # Transaction distribution | 981system.membus.trans_dist::ReadExReq 1534 # Transaction distribution 982system.membus.trans_dist::ReadExResp 1534 # Transaction distribution |
| 977system.membus.trans_dist::ReadSharedReq 3879 # Transaction distribution 978system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11430 # Packet count per connected master and slave (bytes) 979system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11430 # Packet count per connected master and slave (bytes) 980system.membus.pkt_count::total 11430 # Packet count per connected master and slave (bytes) 981system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 346304 # Cumulative packet size per connected master and slave (bytes) 982system.membus.pkt_size_system.cpu.l2cache.mem_side::total 346304 # Cumulative packet size per connected master and slave (bytes) 983system.membus.pkt_size::total 346304 # Cumulative packet size per connected master and slave (bytes) | 983system.membus.trans_dist::ReadSharedReq 3871 # Transaction distribution 984system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11402 # Packet count per connected master and slave (bytes) 985system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11402 # Packet count per connected master and slave (bytes) 986system.membus.pkt_count::total 11402 # Packet count per connected master and slave (bytes) 987system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 345920 # Cumulative packet size per connected master and slave (bytes) 988system.membus.pkt_size_system.cpu.l2cache.mem_side::total 345920 # Cumulative packet size per connected master and slave (bytes) 989system.membus.pkt_size::total 345920 # Cumulative packet size per connected master and slave (bytes) |
| 984system.membus.snoops 0 # Total snoops (count) | 990system.membus.snoops 0 # Total snoops (count) |
| 985system.membus.snoop_fanout::samples 5716 # Request fanout histogram | 991system.membus.snoop_fanout::samples 5701 # Request fanout histogram |
| 986system.membus.snoop_fanout::mean 0 # Request fanout histogram 987system.membus.snoop_fanout::stdev 0 # Request fanout histogram 988system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 992system.membus.snoop_fanout::mean 0 # Request fanout histogram 993system.membus.snoop_fanout::stdev 0 # Request fanout histogram 994system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 989system.membus.snoop_fanout::0 5716 100.00% 100.00% # Request fanout histogram | 995system.membus.snoop_fanout::0 5701 100.00% 100.00% # Request fanout histogram |
| 990system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 991system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 992system.membus.snoop_fanout::min_value 0 # Request fanout histogram 993system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 996system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 997system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 998system.membus.snoop_fanout::min_value 0 # Request fanout histogram 999system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 994system.membus.snoop_fanout::total 5716 # Request fanout histogram 995system.membus.reqLayer0.occupancy 7099000 # Layer occupancy (ticks) | 1000system.membus.snoop_fanout::total 5701 # Request fanout histogram 1001system.membus.reqLayer0.occupancy 6922500 # Layer occupancy (ticks) |
| 996system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1002system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 997system.membus.respLayer1.occupancy 29276697 # Layer occupancy (ticks) | 1003system.membus.respLayer1.occupancy 29231454 # Layer occupancy (ticks) |
| 998system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 999 1000---------- End Simulation Statistics ---------- | 1004system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 1005 1006---------- End Simulation Statistics ---------- |