| stats.txt (10726:8a20e2a1562d) | stats.txt (10736:4433fb00fa7d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.148669 # Number of seconds simulated 4sim_ticks 148668850500 # Number of ticks simulated 5final_tick 148668850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 82634 # Simulator instruction rate (inst/s) 8host_op_rate 138502 # Simulator op (including micro ops) rate (op/s) --- 525 unchanged lines hidden (view full) --- 534system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction 535system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction 536system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction 537system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction 538system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 539system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 540system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction 541system.cpu.commit.bw_lim_events 6920063 # number cycles where commit BW limit reached | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.148669 # Number of seconds simulated 4sim_ticks 148668850500 # Number of ticks simulated 5final_tick 148668850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 82634 # Simulator instruction rate (inst/s) 8host_op_rate 138502 # Simulator op (including micro ops) rate (op/s) --- 525 unchanged lines hidden (view full) --- 534system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction 535system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction 536system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction 537system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction 538system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 539system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 540system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction 541system.cpu.commit.bw_lim_events 6920063 # number cycles where commit BW limit reached |
| 542system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | |
| 543system.cpu.rob.rob_reads 615300578 # The number of ROB reads 544system.cpu.rob.rob_writes 699132843 # The number of ROB writes 545system.cpu.timesIdled 3156 # Number of times that the entire CPU went into an idle state and unscheduled itself 546system.cpu.idleCycles 199760 # Total number of cycles that the CPU has spent unscheduled due to idling 547system.cpu.committedInsts 132071192 # Number of Instructions Simulated 548system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated 549system.cpu.cpi 2.251344 # CPI: Cycles Per Instruction 550system.cpu.cpi_total 2.251344 # CPI: Total CPI of All Threads --- 443 unchanged lines hidden --- | 542system.cpu.rob.rob_reads 615300578 # The number of ROB reads 543system.cpu.rob.rob_writes 699132843 # The number of ROB writes 544system.cpu.timesIdled 3156 # Number of times that the entire CPU went into an idle state and unscheduled itself 545system.cpu.idleCycles 199760 # Total number of cycles that the CPU has spent unscheduled due to idling 546system.cpu.committedInsts 132071192 # Number of Instructions Simulated 547system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated 548system.cpu.cpi 2.251344 # CPI: Cycles Per Instruction 549system.cpu.cpi_total 2.251344 # CPI: Total CPI of All Threads --- 443 unchanged lines hidden --- |