| stats.txt (10488:7c27480a5031) | stats.txt (10628:c9b7e0c69f88) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.148694 # Number of seconds simulated 4sim_ticks 148694012000 # Number of ticks simulated 5final_tick 148694012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.148652 # Number of seconds simulated 4sim_ticks 148652306000 # Number of ticks simulated 5final_tick 148652306000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 81223 # Simulator instruction rate (inst/s) 8host_op_rate 136137 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 91445548 # Simulator tick rate (ticks/s) 10host_mem_usage 288088 # Number of bytes of host memory used 11host_seconds 1626.04 # Real time elapsed on the host | 7host_inst_rate 83185 # Simulator instruction rate (inst/s) 8host_op_rate 139426 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 93628996 # Simulator tick rate (ticks/s) 10host_mem_usage 346568 # Number of bytes of host memory used 11host_seconds 1587.67 # Real time elapsed on the host |
| 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221363384 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221363384 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 223936 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 125888 # Number of bytes read from this memory 18system.physmem.bytes_read::total 349824 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 223936 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 223936 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 3499 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1967 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 5466 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1506019 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 846625 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 2352643 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1506019 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1506019 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1506019 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 846625 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 2352643 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 5466 # Number of read requests accepted | 16system.physmem.bytes_read::cpu.inst 224768 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 125696 # Number of bytes read from this memory 18system.physmem.bytes_read::total 350464 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 224768 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 224768 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 3512 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1964 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 5476 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1512038 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 845570 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 2357609 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1512038 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1512038 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1512038 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 845570 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 2357609 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 5476 # Number of read requests accepted |
| 33system.physmem.writeReqs 0 # Number of write requests accepted | 33system.physmem.writeReqs 0 # Number of write requests accepted |
| 34system.physmem.readBursts 5466 # Number of DRAM read bursts, including those serviced by the write queue | 34system.physmem.readBursts 5476 # Number of DRAM read bursts, including those serviced by the write queue |
| 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 36system.physmem.bytesReadDRAM 349824 # Total number of bytes read from DRAM | 36system.physmem.bytesReadDRAM 350464 # Total number of bytes read from DRAM |
| 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 39system.physmem.bytesReadSys 349824 # Total read bytes from the system interface side | 39system.physmem.bytesReadSys 350464 # Total read bytes from the system interface side |
| 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one | 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| 43system.physmem.neitherReadNorWriteReqs 296 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 294 # Per bank write bursts 45system.physmem.perBankRdBursts::1 361 # Per bank write bursts 46system.physmem.perBankRdBursts::2 463 # Per bank write bursts 47system.physmem.perBankRdBursts::3 372 # Per bank write bursts 48system.physmem.perBankRdBursts::4 337 # Per bank write bursts 49system.physmem.perBankRdBursts::5 332 # Per bank write bursts | 43system.physmem.neitherReadNorWriteReqs 324 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 295 # Per bank write bursts 45system.physmem.perBankRdBursts::1 363 # Per bank write bursts 46system.physmem.perBankRdBursts::2 461 # Per bank write bursts 47system.physmem.perBankRdBursts::3 370 # Per bank write bursts 48system.physmem.perBankRdBursts::4 335 # Per bank write bursts 49system.physmem.perBankRdBursts::5 334 # Per bank write bursts |
| 50system.physmem.perBankRdBursts::6 400 # Per bank write bursts | 50system.physmem.perBankRdBursts::6 400 # Per bank write bursts |
| 51system.physmem.perBankRdBursts::7 384 # Per bank write bursts 52system.physmem.perBankRdBursts::8 341 # Per bank write bursts 53system.physmem.perBankRdBursts::9 282 # Per bank write bursts 54system.physmem.perBankRdBursts::10 235 # Per bank write bursts 55system.physmem.perBankRdBursts::11 262 # Per bank write bursts 56system.physmem.perBankRdBursts::12 222 # Per bank write bursts 57system.physmem.perBankRdBursts::13 508 # Per bank write bursts | 51system.physmem.perBankRdBursts::7 383 # Per bank write bursts 52system.physmem.perBankRdBursts::8 340 # Per bank write bursts 53system.physmem.perBankRdBursts::9 286 # Per bank write bursts 54system.physmem.perBankRdBursts::10 236 # Per bank write bursts 55system.physmem.perBankRdBursts::11 261 # Per bank write bursts 56system.physmem.perBankRdBursts::12 219 # Per bank write bursts 57system.physmem.perBankRdBursts::13 509 # Per bank write bursts |
| 58system.physmem.perBankRdBursts::14 392 # Per bank write bursts | 58system.physmem.perBankRdBursts::14 392 # Per bank write bursts |
| 59system.physmem.perBankRdBursts::15 281 # Per bank write bursts | 59system.physmem.perBankRdBursts::15 292 # Per bank write bursts |
| 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 148693969000 # Total gap between requests | 78system.physmem.totGap 148652208500 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 85system.physmem.readPktSize::6 5466 # Read request sizes (log2) | 85system.physmem.readPktSize::6 5476 # Read request sizes (log2) |
| 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) | 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 93system.physmem.rdQLenPdf::0 4370 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 896 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 174 # What read queue length does an incoming req see | 93system.physmem.rdQLenPdf::0 4366 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 909 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 176 # What read queue length does an incoming req see |
| 96system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see | 96system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see |
| 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see | 97system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see |
| 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 75 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 75 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 189system.physmem.bytesPerActivate::samples 1125 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 309.532444 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 178.678629 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 328.994757 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 454 40.36% 40.36% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 235 20.89% 61.24% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 101 8.98% 70.22% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 52 4.62% 74.84% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 60 5.33% 80.18% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 59 5.24% 85.42% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 19 1.69% 87.11% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 20 1.78% 88.89% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 125 11.11% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 1125 # Bytes accessed per row activation 203system.physmem.totQLat 38946250 # Total ticks spent queuing 204system.physmem.totMemAccLat 141433750 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 27330000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 7125.18 # Average queueing delay per DRAM burst | 189system.physmem.bytesPerActivate::samples 1147 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 304.265039 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 175.960981 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 326.625541 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 464 40.45% 40.45% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 245 21.36% 61.81% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 104 9.07% 70.88% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 57 4.97% 75.85% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 54 4.71% 80.56% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 57 4.97% 85.53% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 24 2.09% 87.62% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 15 1.31% 88.93% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 127 11.07% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 1147 # Bytes accessed per row activation 203system.physmem.totQLat 37377750 # Total ticks spent queuing 204system.physmem.totMemAccLat 140052750 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 27380000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 6825.74 # Average queueing delay per DRAM burst |
| 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 208system.physmem.avgMemAccLat 25875.18 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 2.35 # Average DRAM read bandwidth in MiByte/s | 208system.physmem.avgMemAccLat 25575.74 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 2.36 # Average DRAM read bandwidth in MiByte/s |
| 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 211system.physmem.avgRdBWSys 2.35 # Average system read bandwidth in MiByte/s | 211system.physmem.avgRdBWSys 2.36 # Average system read bandwidth in MiByte/s |
| 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.02 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.02 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 217system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing | 217system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing |
| 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 219system.physmem.readRowHits 4331 # Number of row buffer hits during reads | 219system.physmem.readRowHits 4321 # Number of row buffer hits during reads |
| 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 221system.physmem.readRowHitRate 79.24 # Row buffer hit rate for reads | 221system.physmem.readRowHitRate 78.91 # Row buffer hit rate for reads |
| 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 223system.physmem.avgGap 27203433.77 # Average gap between requests 224system.physmem.pageHitRate 79.24 # Row buffer hit rate, read and write combined 225system.physmem.memoryStateTime::IDLE 142073657250 # Time in different power states 226system.physmem.memoryStateTime::REF 4964960000 # Time in different power states 227system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 228system.physmem.memoryStateTime::ACT 1647900000 # Time in different power states 229system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 230system.physmem.actEnergy::0 4982040 # Energy for activate commands per rank (pJ) 231system.physmem.actEnergy::1 3500280 # Energy for activate commands per rank (pJ) 232system.physmem.preEnergy::0 2718375 # Energy for precharge commands per rank (pJ) 233system.physmem.preEnergy::1 1909875 # Energy for precharge commands per rank (pJ) 234system.physmem.readEnergy::0 22776000 # Energy for read commands per rank (pJ) 235system.physmem.readEnergy::1 19507800 # Energy for read commands per rank (pJ) 236system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) 237system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) 238system.physmem.refreshEnergy::0 9711461760 # Energy for refresh commands per rank (pJ) 239system.physmem.refreshEnergy::1 9711461760 # Energy for refresh commands per rank (pJ) 240system.physmem.actBackEnergy::0 4022315865 # Energy for active background per rank (pJ) 241system.physmem.actBackEnergy::1 3825718020 # Energy for active background per rank (pJ) 242system.physmem.preBackEnergy::0 85683555000 # Energy for precharge background per rank (pJ) 243system.physmem.preBackEnergy::1 85856009250 # Energy for precharge background per rank (pJ) 244system.physmem.totalEnergy::0 99447809040 # Total energy per rank (pJ) 245system.physmem.totalEnergy::1 99418106985 # Total energy per rank (pJ) 246system.physmem.averagePower::0 668.842205 # Core power per rank (mW) 247system.physmem.averagePower::1 668.642442 # Core power per rank (mW) 248system.membus.trans_dist::ReadReq 3933 # Transaction distribution 249system.membus.trans_dist::ReadResp 3932 # Transaction distribution 250system.membus.trans_dist::UpgradeReq 296 # Transaction distribution 251system.membus.trans_dist::UpgradeResp 296 # Transaction distribution 252system.membus.trans_dist::ReadExReq 1533 # Transaction distribution 253system.membus.trans_dist::ReadExResp 1533 # Transaction distribution 254system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11523 # Packet count per connected master and slave (bytes) 255system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11523 # Packet count per connected master and slave (bytes) 256system.membus.pkt_count::total 11523 # Packet count per connected master and slave (bytes) 257system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 349760 # Cumulative packet size per connected master and slave (bytes) 258system.membus.pkt_size_system.cpu.l2cache.mem_side::total 349760 # Cumulative packet size per connected master and slave (bytes) 259system.membus.pkt_size::total 349760 # Cumulative packet size per connected master and slave (bytes) 260system.membus.snoops 0 # Total snoops (count) 261system.membus.snoop_fanout::samples 5762 # Request fanout histogram 262system.membus.snoop_fanout::mean 0 # Request fanout histogram 263system.membus.snoop_fanout::stdev 0 # Request fanout histogram 264system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 265system.membus.snoop_fanout::0 5762 100.00% 100.00% # Request fanout histogram 266system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 267system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 268system.membus.snoop_fanout::min_value 0 # Request fanout histogram 269system.membus.snoop_fanout::max_value 0 # Request fanout histogram 270system.membus.snoop_fanout::total 5762 # Request fanout histogram 271system.membus.reqLayer0.occupancy 7167000 # Layer occupancy (ticks) 272system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 273system.membus.respLayer1.occupancy 51861454 # Layer occupancy (ticks) 274system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 275system.cpu_clk_domain.clock 500 # Clock period in ticks 276system.cpu.branchPred.lookups 22382097 # Number of BP lookups 277system.cpu.branchPred.condPredicted 22382097 # Number of conditional branches predicted 278system.cpu.branchPred.condIncorrect 1553409 # Number of conditional branches incorrect 279system.cpu.branchPred.BTBLookups 14143770 # Number of BTB lookups 280system.cpu.branchPred.BTBHits 13239374 # Number of BTB hits | 223system.physmem.avgGap 27146130.11 # Average gap between requests 224system.physmem.pageHitRate 78.91 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 5072760 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 2767875 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 22791600 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 9708918960 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 4015280925 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 85666359000 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 99421191120 # Total energy per rank (pJ) 233system.physmem_0.averagePower 668.838371 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 142511183750 # Time in different power states 235system.physmem_0.memoryStateTime::REF 4963660000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 237system.physmem_0.memoryStateTime::ACT 1172773250 # Time in different power states 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.physmem_1.actEnergy 3575880 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 1951125 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 19585800 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 9708918960 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 3861811845 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 85800972750 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 99396816360 # Total energy per rank (pJ) 247system.physmem_1.averagePower 668.674456 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 142739163750 # Time in different power states 249system.physmem_1.memoryStateTime::REF 4963660000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 947728750 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.cpu.branchPred.lookups 22375930 # Number of BP lookups 254system.cpu.branchPred.condPredicted 22375930 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 1550820 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 14142904 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 13245564 # Number of BTB hits |
| 281system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 282system.cpu.branchPred.BTBHitPct 93.605694 # BTB Hit Percentage 283system.cpu.branchPred.usedRAS 1523861 # Number of times the RAS was used to get a target. 284system.cpu.branchPred.RASInCorrect 22060 # Number of incorrect RAS predictions. | 259system.cpu.branchPred.BTBHitPct 93.655193 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 1524021 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 21798 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 285system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 286system.cpu.workload.num_syscalls 400 # Number of system calls | 263system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 264system.cpu.workload.num_syscalls 400 # Number of system calls |
| 287system.cpu.numCycles 297388032 # number of cpu cycles simulated | 265system.cpu.numCycles 297304620 # number of cpu cycles simulated |
| 288system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 289system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 266system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 267system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 290system.cpu.fetch.icacheStallCycles 27880008 # Number of cycles fetch is stalled on an Icache miss 291system.cpu.fetch.Insts 249058784 # Number of instructions fetch has processed 292system.cpu.fetch.Branches 22382097 # Number of branches that fetch encountered 293system.cpu.fetch.predictedBranches 14763235 # Number of branches that fetch has predicted taken 294system.cpu.fetch.Cycles 267434691 # Number of cycles fetch has run and was not squashing or blocked 295system.cpu.fetch.SquashCycles 3695049 # Number of cycles fetch has spent squashing 296system.cpu.fetch.TlbCycles 15 # Number of cycles fetch has spent waiting for tlb 297system.cpu.fetch.MiscStallCycles 4561 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 298system.cpu.fetch.PendingTrapStallCycles 42381 # Number of stall cycles due to pending traps | 268system.cpu.fetch.icacheStallCycles 27866919 # Number of cycles fetch is stalled on an Icache miss 269system.cpu.fetch.Insts 248846814 # Number of instructions fetch has processed 270system.cpu.fetch.Branches 22375930 # Number of branches that fetch encountered 271system.cpu.fetch.predictedBranches 14769585 # Number of branches that fetch has predicted taken 272system.cpu.fetch.Cycles 267364531 # Number of cycles fetch has run and was not squashing or blocked 273system.cpu.fetch.SquashCycles 3698749 # Number of cycles fetch has spent squashing 274system.cpu.fetch.TlbCycles 56 # Number of cycles fetch has spent waiting for tlb 275system.cpu.fetch.MiscStallCycles 4550 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 276system.cpu.fetch.PendingTrapStallCycles 42690 # Number of stall cycles due to pending traps |
| 299system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions | 277system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions |
| 300system.cpu.fetch.IcacheWaitRetryStallCycles 113 # Number of stall cycles due to full MSHR 301system.cpu.fetch.CacheLines 26649696 # Number of cache lines fetched 302system.cpu.fetch.IcacheSquashes 257275 # Number of outstanding Icache misses that were squashed 303system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed 304system.cpu.fetch.rateDist::samples 297209306 # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::mean 1.380725 # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::stdev 2.789359 # Number of instructions fetched each cycle (Total) | 278system.cpu.fetch.IcacheWaitRetryStallCycles 111 # Number of stall cycles due to full MSHR 279system.cpu.fetch.CacheLines 26638460 # Number of cache lines fetched 280system.cpu.fetch.IcacheSquashes 257102 # Number of outstanding Icache misses that were squashed 281system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed 282system.cpu.fetch.rateDist::samples 297128244 # Number of instructions fetched each cycle (Total) 283system.cpu.fetch.rateDist::mean 1.381645 # Number of instructions fetched each cycle (Total) 284system.cpu.fetch.rateDist::stdev 2.790124 # Number of instructions fetched each cycle (Total) |
| 307system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 285system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 308system.cpu.fetch.rateDist::0 229177022 77.11% 77.11% # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::1 5084587 1.71% 78.82% # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::2 4138437 1.39% 80.21% # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::3 4791887 1.61% 81.83% # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::4 4876855 1.64% 83.47% # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::5 5109175 1.72% 85.19% # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::6 5334492 1.79% 86.98% # Number of instructions fetched each cycle (Total) 315system.cpu.fetch.rateDist::7 4008000 1.35% 88.33% # Number of instructions fetched each cycle (Total) 316system.cpu.fetch.rateDist::8 34688851 11.67% 100.00% # Number of instructions fetched each cycle (Total) | 286system.cpu.fetch.rateDist::0 229068376 77.09% 77.09% # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::1 5099613 1.72% 78.81% # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::2 4127262 1.39% 80.20% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::3 4784384 1.61% 81.81% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::4 4893969 1.65% 83.46% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::5 5110538 1.72% 85.18% # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::6 5334476 1.80% 86.97% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::7 3994023 1.34% 88.32% # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.rateDist::8 34715603 11.68% 100.00% # Number of instructions fetched each cycle (Total) |
| 317system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 318system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 295system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 320system.cpu.fetch.rateDist::total 297209306 # Number of instructions fetched each cycle (Total) 321system.cpu.fetch.branchRate 0.075262 # Number of branch fetches per cycle 322system.cpu.fetch.rate 0.837488 # Number of inst fetches per cycle 323system.cpu.decode.IdleCycles 16317003 # Number of cycles decode is idle 324system.cpu.decode.BlockedCycles 231094890 # Number of cycles decode is blocked 325system.cpu.decode.RunCycles 26094955 # Number of cycles decode is running 326system.cpu.decode.UnblockCycles 21854934 # Number of cycles decode is unblocking 327system.cpu.decode.SquashCycles 1847524 # Number of cycles decode is squashing 328system.cpu.decode.DecodedInsts 359064274 # Number of instructions handled by decode 329system.cpu.rename.SquashCycles 1847524 # Number of cycles rename is squashing 330system.cpu.rename.IdleCycles 24114798 # Number of cycles rename is idle 331system.cpu.rename.BlockCycles 162761005 # Number of cycles rename is blocking 332system.cpu.rename.serializeStallCycles 33475 # count of cycles rename stalled for serializing inst 333system.cpu.rename.RunCycles 38241804 # Number of cycles rename is running 334system.cpu.rename.UnblockCycles 70210700 # Number of cycles rename is unblocking 335system.cpu.rename.RenamedInsts 350324590 # Number of instructions processed by rename 336system.cpu.rename.ROBFullEvents 42142 # Number of times rename has blocked due to ROB full 337system.cpu.rename.IQFullEvents 61992199 # Number of times rename has blocked due to IQ full 338system.cpu.rename.LQFullEvents 7946895 # Number of times rename has blocked due to LQ full 339system.cpu.rename.SQFullEvents 152925 # Number of times rename has blocked due to SQ full 340system.cpu.rename.RenamedOperands 405428411 # Number of destination operands rename has renamed 341system.cpu.rename.RenameLookups 972465740 # Number of register rename lookups that rename has made 342system.cpu.rename.int_rename_lookups 641794462 # Number of integer rename lookups 343system.cpu.rename.fp_rename_lookups 4665474 # Number of floating rename lookups | 298system.cpu.fetch.rateDist::total 297128244 # Number of instructions fetched each cycle (Total) 299system.cpu.fetch.branchRate 0.075263 # Number of branch fetches per cycle 300system.cpu.fetch.rate 0.837010 # Number of inst fetches per cycle 301system.cpu.decode.IdleCycles 16329336 # Number of cycles decode is idle 302system.cpu.decode.BlockedCycles 230975824 # Number of cycles decode is blocked 303system.cpu.decode.RunCycles 26113582 # Number of cycles decode is running 304system.cpu.decode.UnblockCycles 21860128 # Number of cycles decode is unblocking 305system.cpu.decode.SquashCycles 1849374 # Number of cycles decode is squashing 306system.cpu.decode.DecodedInsts 359242894 # Number of instructions handled by decode 307system.cpu.rename.SquashCycles 1849374 # Number of cycles rename is squashing 308system.cpu.rename.IdleCycles 24118008 # Number of cycles rename is idle 309system.cpu.rename.BlockCycles 162656356 # Number of cycles rename is blocking 310system.cpu.rename.serializeStallCycles 38273 # count of cycles rename stalled for serializing inst 311system.cpu.rename.RunCycles 38263619 # Number of cycles rename is running 312system.cpu.rename.UnblockCycles 70202614 # Number of cycles rename is unblocking 313system.cpu.rename.RenamedInsts 350538626 # Number of instructions processed by rename 314system.cpu.rename.ROBFullEvents 41453 # Number of times rename has blocked due to ROB full 315system.cpu.rename.IQFullEvents 61947521 # Number of times rename has blocked due to IQ full 316system.cpu.rename.LQFullEvents 7945702 # Number of times rename has blocked due to LQ full 317system.cpu.rename.SQFullEvents 153558 # Number of times rename has blocked due to SQ full 318system.cpu.rename.RenamedOperands 405817730 # Number of destination operands rename has renamed 319system.cpu.rename.RenameLookups 972424276 # Number of register rename lookups that rename has made 320system.cpu.rename.int_rename_lookups 641996744 # Number of integer rename lookups 321system.cpu.rename.fp_rename_lookups 4657501 # Number of floating rename lookups |
| 344system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed | 322system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed |
| 345system.cpu.rename.UndoneMaps 145998961 # Number of HB maps that are undone due to squashing 346system.cpu.rename.serializingInsts 2154 # count of serializing insts renamed 347system.cpu.rename.tempSerializingInsts 2076 # count of temporary serializing insts renamed 348system.cpu.rename.skidInsts 128653734 # count of insts added to the skid buffer 349system.cpu.memDep0.insertedLoads 89733483 # Number of loads inserted to the mem dependence unit. 350system.cpu.memDep0.insertedStores 32018253 # Number of stores inserted to the mem dependence unit. 351system.cpu.memDep0.conflictingLoads 63985001 # Number of conflicting loads. 352system.cpu.memDep0.conflictingStores 21567740 # Number of conflicting stores. 353system.cpu.iq.iqInstsAdded 341091248 # Number of instructions added to the IQ (excludes non-spec) 354system.cpu.iq.iqNonSpecInstsAdded 4877 # Number of non-speculative instructions added to the IQ 355system.cpu.iq.iqInstsIssued 266696686 # Number of instructions issued 356system.cpu.iq.iqSquashedInstsIssued 73290 # Number of squashed instructions issued 357system.cpu.iq.iqSquashedInstsExamined 119329162 # Number of squashed instructions iterated over during squash; mainly for profiling 358system.cpu.iq.iqSquashedOperandsExamined 250439001 # Number of squashed operands that are examined and possibly removed from graph 359system.cpu.iq.iqSquashedNonSpecRemoved 3632 # Number of squashed non-spec instructions that were removed 360system.cpu.iq.issued_per_cycle::samples 297209306 # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::mean 0.897336 # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::stdev 1.363195 # Number of insts issued each cycle | 323system.cpu.rename.UndoneMaps 146388280 # Number of HB maps that are undone due to squashing 324system.cpu.rename.serializingInsts 2397 # count of serializing insts renamed 325system.cpu.rename.tempSerializingInsts 2322 # count of temporary serializing insts renamed 326system.cpu.rename.skidInsts 128546417 # count of insts added to the skid buffer 327system.cpu.memDep0.insertedLoads 89512895 # Number of loads inserted to the mem dependence unit. 328system.cpu.memDep0.insertedStores 32023027 # Number of stores inserted to the mem dependence unit. 329system.cpu.memDep0.conflictingLoads 63891013 # Number of conflicting loads. 330system.cpu.memDep0.conflictingStores 21581901 # Number of conflicting stores. 331system.cpu.iq.iqInstsAdded 341300793 # Number of instructions added to the IQ (excludes non-spec) 332system.cpu.iq.iqNonSpecInstsAdded 5145 # Number of non-speculative instructions added to the IQ 333system.cpu.iq.iqInstsIssued 266928835 # Number of instructions issued 334system.cpu.iq.iqSquashedInstsIssued 76764 # Number of squashed instructions issued 335system.cpu.iq.iqSquashedInstsExamined 119543073 # Number of squashed instructions iterated over during squash; mainly for profiling 336system.cpu.iq.iqSquashedOperandsExamined 250225997 # Number of squashed operands that are examined and possibly removed from graph 337system.cpu.iq.iqSquashedNonSpecRemoved 3900 # Number of squashed non-spec instructions that were removed 338system.cpu.iq.issued_per_cycle::samples 297128244 # Number of insts issued each cycle 339system.cpu.iq.issued_per_cycle::mean 0.898362 # Number of insts issued each cycle 340system.cpu.iq.issued_per_cycle::stdev 1.364631 # Number of insts issued each cycle |
| 363system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 341system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 364system.cpu.iq.issued_per_cycle::0 171484109 57.70% 57.70% # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::1 54269493 18.26% 75.96% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::2 33638460 11.32% 87.28% # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::3 19147986 6.44% 93.72% # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::4 10817239 3.64% 97.36% # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::5 4351297 1.46% 98.82% # Number of insts issued each cycle 370system.cpu.iq.issued_per_cycle::6 2217356 0.75% 99.57% # Number of insts issued each cycle 371system.cpu.iq.issued_per_cycle::7 890190 0.30% 99.87% # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::8 393176 0.13% 100.00% # Number of insts issued each cycle | 342system.cpu.iq.issued_per_cycle::0 171384973 57.68% 57.68% # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::1 54250707 18.26% 75.94% # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::2 33605057 11.31% 87.25% # Number of insts issued each cycle 345system.cpu.iq.issued_per_cycle::3 19187938 6.46% 93.71% # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::4 10808168 3.64% 97.34% # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::5 4369052 1.47% 98.81% # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::6 2227260 0.75% 99.56% # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::7 898004 0.30% 99.87% # Number of insts issued each cycle 350system.cpu.iq.issued_per_cycle::8 397085 0.13% 100.00% # Number of insts issued each cycle |
| 373system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 374system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 375system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 351system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 352system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 353system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 376system.cpu.iq.issued_per_cycle::total 297209306 # Number of insts issued each cycle | 354system.cpu.iq.issued_per_cycle::total 297128244 # Number of insts issued each cycle |
| 377system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 355system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 378system.cpu.iq.fu_full::IntAlu 237582 7.35% 7.35% # attempts to use FU when none available 379system.cpu.iq.fu_full::IntMult 0 0.00% 7.35% # attempts to use FU when none available 380system.cpu.iq.fu_full::IntDiv 0 0.00% 7.35% # attempts to use FU when none available 381system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.35% # attempts to use FU when none available 382system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.35% # attempts to use FU when none available 383system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.35% # attempts to use FU when none available 384system.cpu.iq.fu_full::FloatMult 0 0.00% 7.35% # attempts to use FU when none available 385system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.35% # attempts to use FU when none available 386system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.35% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.35% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.35% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.35% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.35% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.35% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.35% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdMult 0 0.00% 7.35% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.35% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdShift 0 0.00% 7.35% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.35% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.35% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.35% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.35% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.35% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.35% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.35% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.35% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.35% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.35% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.35% # attempts to use FU when none available 407system.cpu.iq.fu_full::MemRead 2582537 79.93% 87.28% # attempts to use FU when none available 408system.cpu.iq.fu_full::MemWrite 410926 12.72% 100.00% # attempts to use FU when none available | 356system.cpu.iq.fu_full::IntAlu 240256 7.42% 7.42% # attempts to use FU when none available 357system.cpu.iq.fu_full::IntMult 0 0.00% 7.42% # attempts to use FU when none available 358system.cpu.iq.fu_full::IntDiv 0 0.00% 7.42% # attempts to use FU when none available 359system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.42% # attempts to use FU when none available 360system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.42% # attempts to use FU when none available 361system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.42% # attempts to use FU when none available 362system.cpu.iq.fu_full::FloatMult 0 0.00% 7.42% # attempts to use FU when none available 363system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.42% # attempts to use FU when none available 364system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.42% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.42% # attempts to use FU when none available 366system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.42% # attempts to use FU when none available 367system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.42% # attempts to use FU when none available 368system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.42% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.42% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.42% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdMult 0 0.00% 7.42% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.42% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdShift 0 0.00% 7.42% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.42% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.42% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.42% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.42% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.42% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.42% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.42% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.42% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.42% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.42% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.42% # attempts to use FU when none available 385system.cpu.iq.fu_full::MemRead 2591676 80.04% 87.46% # attempts to use FU when none available 386system.cpu.iq.fu_full::MemWrite 406020 12.54% 100.00% # attempts to use FU when none available |
| 409system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 410system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 387system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 388system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 411system.cpu.iq.FU_type_0::No_OpClass 1211351 0.45% 0.45% # Type of FU issued 412system.cpu.iq.FU_type_0::IntAlu 167148119 62.67% 63.13% # Type of FU issued 413system.cpu.iq.FU_type_0::IntMult 789126 0.30% 63.42% # Type of FU issued 414system.cpu.iq.FU_type_0::IntDiv 7035938 2.64% 66.06% # Type of FU issued 415system.cpu.iq.FU_type_0::FloatAdd 1214032 0.46% 66.52% # Type of FU issued 416system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.52% # Type of FU issued 417system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.52% # Type of FU issued 418system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.52% # Type of FU issued 419system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.52% # Type of FU issued 420system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.52% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.52% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.52% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.52% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.52% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.52% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.52% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.52% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.52% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.52% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.52% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.52% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.52% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.52% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.52% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.52% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.52% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.52% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.52% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.52% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.52% # Type of FU issued 441system.cpu.iq.FU_type_0::MemRead 66518900 24.94% 91.46% # Type of FU issued 442system.cpu.iq.FU_type_0::MemWrite 22779220 8.54% 100.00% # Type of FU issued | 389system.cpu.iq.FU_type_0::No_OpClass 1211341 0.45% 0.45% # Type of FU issued 390system.cpu.iq.FU_type_0::IntAlu 167360520 62.70% 63.15% # Type of FU issued 391system.cpu.iq.FU_type_0::IntMult 793230 0.30% 63.45% # Type of FU issued 392system.cpu.iq.FU_type_0::IntDiv 7036198 2.64% 66.09% # Type of FU issued 393system.cpu.iq.FU_type_0::FloatAdd 1213739 0.45% 66.54% # Type of FU issued 394system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.54% # Type of FU issued 395system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.54% # Type of FU issued 396system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.54% # Type of FU issued 397system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.54% # Type of FU issued 398system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.54% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.54% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.54% # Type of FU issued 401system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.54% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.54% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.54% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.54% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.54% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.54% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.54% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.54% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.54% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.54% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.54% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.54% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.54% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.54% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.54% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.54% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.54% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.54% # Type of FU issued 419system.cpu.iq.FU_type_0::MemRead 66512723 24.92% 91.46% # Type of FU issued 420system.cpu.iq.FU_type_0::MemWrite 22801084 8.54% 100.00% # Type of FU issued |
| 443system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 444system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 421system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 422system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 445system.cpu.iq.FU_type_0::total 266696686 # Type of FU issued 446system.cpu.iq.rate 0.896797 # Inst issue rate 447system.cpu.iq.fu_busy_cnt 3231045 # FU busy when requested 448system.cpu.iq.fu_busy_rate 0.012115 # FU busy rate (busy events/executed inst) 449system.cpu.iq.int_inst_queue_reads 828907957 # Number of integer instruction queue reads 450system.cpu.iq.int_inst_queue_writes 456425026 # Number of integer instruction queue writes 451system.cpu.iq.int_inst_queue_wakeup_accesses 260744620 # Number of integer instruction queue wakeup accesses 452system.cpu.iq.fp_inst_queue_reads 4999056 # Number of floating instruction queue reads 453system.cpu.iq.fp_inst_queue_writes 4321531 # Number of floating instruction queue writes 454system.cpu.iq.fp_inst_queue_wakeup_accesses 2398079 # Number of floating instruction queue wakeup accesses 455system.cpu.iq.int_alu_accesses 266200144 # Number of integer alu accesses 456system.cpu.iq.fp_alu_accesses 2516236 # Number of floating point alu accesses 457system.cpu.iew.lsq.thread0.forwLoads 18853700 # Number of loads that had data forwarded from stores | 423system.cpu.iq.FU_type_0::total 266928835 # Type of FU issued 424system.cpu.iq.rate 0.897829 # Inst issue rate 425system.cpu.iq.fu_busy_cnt 3237952 # FU busy when requested 426system.cpu.iq.fu_busy_rate 0.012130 # FU busy rate (busy events/executed inst) 427system.cpu.iq.int_inst_queue_reads 829304993 # Number of integer instruction queue reads 428system.cpu.iq.int_inst_queue_writes 456859927 # Number of integer instruction queue writes 429system.cpu.iq.int_inst_queue_wakeup_accesses 261005005 # Number of integer instruction queue wakeup accesses 430system.cpu.iq.fp_inst_queue_reads 4995637 # Number of floating instruction queue reads 431system.cpu.iq.fp_inst_queue_writes 4315017 # Number of floating instruction queue writes 432system.cpu.iq.fp_inst_queue_wakeup_accesses 2397122 # Number of floating instruction queue wakeup accesses 433system.cpu.iq.int_alu_accesses 266441955 # Number of integer alu accesses 434system.cpu.iq.fp_alu_accesses 2513491 # Number of floating point alu accesses 435system.cpu.iew.lsq.thread0.forwLoads 18899538 # Number of loads that had data forwarded from stores |
| 458system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 436system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 459system.cpu.iew.lsq.thread0.squashedLoads 33083896 # Number of loads squashed 460system.cpu.iew.lsq.thread0.ignoredResponses 14048 # Number of memory responses ignored because the instruction is squashed 461system.cpu.iew.lsq.thread0.memOrderViolation 327034 # Number of memory ordering violations 462system.cpu.iew.lsq.thread0.squashedStores 11502536 # Number of stores squashed | 437system.cpu.iew.lsq.thread0.squashedLoads 32863308 # Number of loads squashed 438system.cpu.iew.lsq.thread0.ignoredResponses 14004 # Number of memory responses ignored because the instruction is squashed 439system.cpu.iew.lsq.thread0.memOrderViolation 331776 # Number of memory ordering violations 440system.cpu.iew.lsq.thread0.squashedStores 11507310 # Number of stores squashed |
| 463system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 464system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 441system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 442system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 465system.cpu.iew.lsq.thread0.rescheduledLoads 52807 # Number of loads that were rescheduled 466system.cpu.iew.lsq.thread0.cacheBlocked 19 # Number of times an access to memory failed due to the cache being blocked | 443system.cpu.iew.lsq.thread0.rescheduledLoads 52520 # Number of loads that were rescheduled 444system.cpu.iew.lsq.thread0.cacheBlocked 17 # Number of times an access to memory failed due to the cache being blocked |
| 467system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 445system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 468system.cpu.iew.iewSquashCycles 1847524 # Number of cycles IEW is squashing 469system.cpu.iew.iewBlockCycles 126225383 # Number of cycles IEW is blocking 470system.cpu.iew.iewUnblockCycles 5553775 # Number of cycles IEW is unblocking 471system.cpu.iew.iewDispatchedInsts 341096125 # Number of instructions dispatched to IQ 472system.cpu.iew.iewDispSquashedInsts 111900 # Number of squashed instructions skipped by dispatch 473system.cpu.iew.iewDispLoadInsts 89733483 # Number of dispatched load instructions 474system.cpu.iew.iewDispStoreInsts 32018253 # Number of dispatched store instructions 475system.cpu.iew.iewDispNonSpecInsts 2073 # Number of dispatched non-speculative instructions 476system.cpu.iew.iewIQFullEvents 2221761 # Number of times the IQ has become full, causing a stall 477system.cpu.iew.iewLSQFullEvents 397558 # Number of times the LSQ has become full, causing a stall 478system.cpu.iew.memOrderViolationEvents 327034 # Number of memory order violations 479system.cpu.iew.predictedTakenIncorrect 687554 # Number of branches that were predicted taken incorrectly 480system.cpu.iew.predictedNotTakenIncorrect 924641 # Number of branches that were predicted not taken incorrectly 481system.cpu.iew.branchMispredicts 1612195 # Number of branch mispredicts detected at execute 482system.cpu.iew.iewExecutedInsts 264577830 # Number of executed instructions 483system.cpu.iew.iewExecLoadInsts 65651803 # Number of load instructions executed 484system.cpu.iew.iewExecSquashedInsts 2118856 # Number of squashed instructions skipped in execute | 446system.cpu.iew.iewSquashCycles 1849374 # Number of cycles IEW is squashing 447system.cpu.iew.iewBlockCycles 126083228 # Number of cycles IEW is blocking 448system.cpu.iew.iewUnblockCycles 5521965 # Number of cycles IEW is unblocking 449system.cpu.iew.iewDispatchedInsts 341305938 # Number of instructions dispatched to IQ 450system.cpu.iew.iewDispSquashedInsts 113234 # Number of squashed instructions skipped by dispatch 451system.cpu.iew.iewDispLoadInsts 89512895 # Number of dispatched load instructions 452system.cpu.iew.iewDispStoreInsts 32023027 # Number of dispatched store instructions 453system.cpu.iew.iewDispNonSpecInsts 2291 # Number of dispatched non-speculative instructions 454system.cpu.iew.iewIQFullEvents 2224383 # Number of times the IQ has become full, causing a stall 455system.cpu.iew.iewLSQFullEvents 364956 # Number of times the LSQ has become full, causing a stall 456system.cpu.iew.memOrderViolationEvents 331776 # Number of memory order violations 457system.cpu.iew.predictedTakenIncorrect 682604 # Number of branches that were predicted taken incorrectly 458system.cpu.iew.predictedNotTakenIncorrect 926974 # Number of branches that were predicted not taken incorrectly 459system.cpu.iew.branchMispredicts 1609578 # Number of branch mispredicts detected at execute 460system.cpu.iew.iewExecutedInsts 264820941 # Number of executed instructions 461system.cpu.iew.iewExecLoadInsts 65644877 # Number of load instructions executed 462system.cpu.iew.iewExecSquashedInsts 2107894 # Number of squashed instructions skipped in execute |
| 485system.cpu.iew.exec_swp 0 # number of swp insts executed 486system.cpu.iew.exec_nop 0 # number of nop insts executed | 463system.cpu.iew.exec_swp 0 # number of swp insts executed 464system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 487system.cpu.iew.exec_refs 88227876 # number of memory reference insts executed 488system.cpu.iew.exec_branches 14574542 # Number of branches executed 489system.cpu.iew.exec_stores 22576073 # Number of stores executed 490system.cpu.iew.exec_rate 0.889672 # Inst execution rate 491system.cpu.iew.wb_sent 263857804 # cumulative count of insts sent to commit 492system.cpu.iew.wb_count 263142699 # cumulative count of insts written-back 493system.cpu.iew.wb_producers 208771445 # num instructions producing a value 494system.cpu.iew.wb_consumers 376756650 # num instructions consuming a value | 465system.cpu.iew.exec_refs 88243318 # number of memory reference insts executed 466system.cpu.iew.exec_branches 14594562 # Number of branches executed 467system.cpu.iew.exec_stores 22598441 # Number of stores executed 468system.cpu.iew.exec_rate 0.890739 # Inst execution rate 469system.cpu.iew.wb_sent 264116022 # cumulative count of insts sent to commit 470system.cpu.iew.wb_count 263402127 # cumulative count of insts written-back 471system.cpu.iew.wb_producers 208929627 # num instructions producing a value 472system.cpu.iew.wb_consumers 376950815 # num instructions consuming a value |
| 495system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 473system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 496system.cpu.iew.wb_rate 0.884846 # insts written-back per cycle 497system.cpu.iew.wb_fanout 0.554128 # average fanout of values written-back | 474system.cpu.iew.wb_rate 0.885967 # insts written-back per cycle 475system.cpu.iew.wb_fanout 0.554262 # average fanout of values written-back |
| 498system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 476system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 499system.cpu.commit.commitSquashedInsts 119784082 # The number of squashed insts skipped by commit | 477system.cpu.commit.commitSquashedInsts 119991036 # The number of squashed insts skipped by commit |
| 500system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards | 478system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards |
| 501system.cpu.commit.branchMispredicts 1557714 # The number of times a branch was mispredicted 502system.cpu.commit.committed_per_cycle::samples 280934178 # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::mean 0.787955 # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::stdev 1.593006 # Number of insts commited each cycle | 479system.cpu.commit.branchMispredicts 1555160 # The number of times a branch was mispredicted 480system.cpu.commit.committed_per_cycle::samples 280815934 # Number of insts commited each cycle 481system.cpu.commit.committed_per_cycle::mean 0.788286 # Number of insts commited each cycle 482system.cpu.commit.committed_per_cycle::stdev 1.594389 # Number of insts commited each cycle |
| 505system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 483system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 506system.cpu.commit.committed_per_cycle::0 181002455 64.43% 64.43% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::1 57799506 20.57% 85.00% # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::2 14236358 5.07% 90.07% # Number of insts commited each cycle 509system.cpu.commit.committed_per_cycle::3 11930779 4.25% 94.32% # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::4 4218902 1.50% 95.82% # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::5 2886432 1.03% 96.85% # Number of insts commited each cycle 512system.cpu.commit.committed_per_cycle::6 918195 0.33% 97.17% # Number of insts commited each cycle 513system.cpu.commit.committed_per_cycle::7 1050521 0.37% 97.55% # Number of insts commited each cycle 514system.cpu.commit.committed_per_cycle::8 6891030 2.45% 100.00% # Number of insts commited each cycle | 484system.cpu.commit.committed_per_cycle::0 180962849 64.44% 64.44% # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::1 57749972 20.57% 85.01% # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::2 14199777 5.06% 90.06% # Number of insts commited each cycle 487system.cpu.commit.committed_per_cycle::3 11927311 4.25% 94.31% # Number of insts commited each cycle 488system.cpu.commit.committed_per_cycle::4 4203723 1.50% 95.81% # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::5 2893126 1.03% 96.84% # Number of insts commited each cycle 490system.cpu.commit.committed_per_cycle::6 916943 0.33% 97.16% # Number of insts commited each cycle 491system.cpu.commit.committed_per_cycle::7 1048119 0.37% 97.54% # Number of insts commited each cycle 492system.cpu.commit.committed_per_cycle::8 6914114 2.46% 100.00% # Number of insts commited each cycle |
| 515system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 516system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 517system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 493system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 494system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 495system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 518system.cpu.commit.committed_per_cycle::total 280934178 # Number of insts commited each cycle | 496system.cpu.commit.committed_per_cycle::total 280815934 # Number of insts commited each cycle |
| 519system.cpu.commit.committedInsts 132071192 # Number of instructions committed 520system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed 521system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 522system.cpu.commit.refs 77165304 # Number of memory references committed 523system.cpu.commit.loads 56649587 # Number of loads committed 524system.cpu.commit.membars 0 # Number of memory barriers committed 525system.cpu.commit.branches 12326938 # Number of branches committed 526system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 556system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction 557system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction 558system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction 559system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction 560system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction 561system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 562system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 563system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction | 497system.cpu.commit.committedInsts 132071192 # Number of instructions committed 498system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed 499system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 500system.cpu.commit.refs 77165304 # Number of memory references committed 501system.cpu.commit.loads 56649587 # Number of loads committed 502system.cpu.commit.membars 0 # Number of memory barriers committed 503system.cpu.commit.branches 12326938 # Number of branches committed 504system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 534system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction 535system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction 536system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction 537system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction 538system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction 539system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 540system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 541system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction |
| 564system.cpu.commit.bw_lim_events 6891030 # number cycles where commit BW limit reached | 542system.cpu.commit.bw_lim_events 6914114 # number cycles where commit BW limit reached |
| 565system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 543system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 566system.cpu.rob.rob_reads 615190614 # The number of ROB reads 567system.cpu.rob.rob_writes 698614569 # The number of ROB writes 568system.cpu.timesIdled 3122 # Number of times that the entire CPU went into an idle state and unscheduled itself 569system.cpu.idleCycles 178726 # Total number of cycles that the CPU has spent unscheduled due to idling | 544system.cpu.rob.rob_reads 615256240 # The number of ROB reads 545system.cpu.rob.rob_writes 699066092 # The number of ROB writes 546system.cpu.timesIdled 3079 # Number of times that the entire CPU went into an idle state and unscheduled itself 547system.cpu.idleCycles 176376 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 570system.cpu.committedInsts 132071192 # Number of Instructions Simulated 571system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated | 548system.cpu.committedInsts 132071192 # Number of Instructions Simulated 549system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated |
| 572system.cpu.cpi 2.251725 # CPI: Cycles Per Instruction 573system.cpu.cpi_total 2.251725 # CPI: Total CPI of All Threads 574system.cpu.ipc 0.444104 # IPC: Instructions Per Cycle 575system.cpu.ipc_total 0.444104 # IPC: Total IPC of All Threads 576system.cpu.int_regfile_reads 456362005 # number of integer regfile reads 577system.cpu.int_regfile_writes 239113538 # number of integer regfile writes 578system.cpu.fp_regfile_reads 3275482 # number of floating regfile reads 579system.cpu.fp_regfile_writes 2058196 # number of floating regfile writes 580system.cpu.cc_regfile_reads 102983282 # number of cc regfile reads 581system.cpu.cc_regfile_writes 60177632 # number of cc regfile writes 582system.cpu.misc_regfile_reads 136798826 # number of misc regfile reads | 550system.cpu.cpi 2.251094 # CPI: Cycles Per Instruction 551system.cpu.cpi_total 2.251094 # CPI: Total CPI of All Threads 552system.cpu.ipc 0.444229 # IPC: Instructions Per Cycle 553system.cpu.ipc_total 0.444229 # IPC: Total IPC of All Threads 554system.cpu.int_regfile_reads 456513966 # number of integer regfile reads 555system.cpu.int_regfile_writes 239334814 # number of integer regfile writes 556system.cpu.fp_regfile_reads 3274089 # number of floating regfile reads 557system.cpu.fp_regfile_writes 2057271 # number of floating regfile writes 558system.cpu.cc_regfile_reads 102998380 # number of cc regfile reads 559system.cpu.cc_regfile_writes 60202762 # number of cc regfile writes 560system.cpu.misc_regfile_reads 136901121 # number of misc regfile reads |
| 583system.cpu.misc_regfile_writes 1689 # number of misc regfile writes | 561system.cpu.misc_regfile_writes 1689 # number of misc regfile writes |
| 584system.cpu.toL2Bus.trans_dist::ReadReq 8736 # Transaction distribution 585system.cpu.toL2Bus.trans_dist::ReadResp 8734 # Transaction distribution 586system.cpu.toL2Bus.trans_dist::Writeback 10 # Transaction distribution 587system.cpu.toL2Bus.trans_dist::UpgradeReq 299 # Transaction distribution 588system.cpu.toL2Bus.trans_dist::UpgradeResp 299 # Transaction distribution 589system.cpu.toL2Bus.trans_dist::ReadExReq 1538 # Transaction distribution 590system.cpu.toL2Bus.trans_dist::ReadExResp 1538 # Transaction distribution 591system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16221 # Packet count per connected master and slave (bytes) 592system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4632 # Packet count per connected master and slave (bytes) 593system.cpu.toL2Bus.pkt_count::total 20853 # Packet count per connected master and slave (bytes) 594system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 509376 # Cumulative packet size per connected master and slave (bytes) 595system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129408 # Cumulative packet size per connected master and slave (bytes) 596system.cpu.toL2Bus.pkt_size::total 638784 # Cumulative packet size per connected master and slave (bytes) 597system.cpu.toL2Bus.snoops 301 # Total snoops (count) 598system.cpu.toL2Bus.snoop_fanout::samples 10583 # Request fanout histogram 599system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram 600system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 601system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 602system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 603system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 604system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 605system.cpu.toL2Bus.snoop_fanout::3 10583 100.00% 100.00% # Request fanout histogram 606system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 607system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 608system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 609system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 610system.cpu.toL2Bus.snoop_fanout::total 10583 # Request fanout histogram 611system.cpu.toL2Bus.reqLayer0.occupancy 5301999 # Layer occupancy (ticks) 612system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 613system.cpu.toL2Bus.respLayer0.occupancy 12991249 # Layer occupancy (ticks) 614system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 615system.cpu.toL2Bus.respLayer1.occupancy 3546296 # Layer occupancy (ticks) 616system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 617system.cpu.icache.tags.replacements 5983 # number of replacements 618system.cpu.icache.tags.tagsinuse 1649.665059 # Cycle average of tags in use 619system.cpu.icache.tags.total_refs 26639065 # Total number of references to valid blocks. 620system.cpu.icache.tags.sampled_refs 7962 # Sample count of references to valid blocks. 621system.cpu.icache.tags.avg_refs 3345.775559 # Average number of references to valid blocks. | 562system.cpu.dcache.tags.replacements 52 # number of replacements 563system.cpu.dcache.tags.tagsinuse 1443.647680 # Cycle average of tags in use 564system.cpu.dcache.tags.total_refs 67095165 # Total number of references to valid blocks. 565system.cpu.dcache.tags.sampled_refs 2013 # Sample count of references to valid blocks. 566system.cpu.dcache.tags.avg_refs 33330.931446 # Average number of references to valid blocks. 567system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 568system.cpu.dcache.tags.occ_blocks::cpu.data 1443.647680 # Average occupied blocks per requestor 569system.cpu.dcache.tags.occ_percent::cpu.data 0.352453 # Average percentage of cache occupancy 570system.cpu.dcache.tags.occ_percent::total 0.352453 # Average percentage of cache occupancy 571system.cpu.dcache.tags.occ_task_id_blocks::1024 1961 # Occupied blocks per task id 572system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 573system.cpu.dcache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id 574system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id 575system.cpu.dcache.tags.age_task_id_blocks_1024::3 441 # Occupied blocks per task id 576system.cpu.dcache.tags.age_task_id_blocks_1024::4 1405 # Occupied blocks per task id 577system.cpu.dcache.tags.occ_task_id_percent::1024 0.478760 # Percentage of cache occupancy per task id 578system.cpu.dcache.tags.tag_accesses 134197329 # Number of tag accesses 579system.cpu.dcache.tags.data_accesses 134197329 # Number of data accesses 580system.cpu.dcache.ReadReq_hits::cpu.data 46580786 # number of ReadReq hits 581system.cpu.dcache.ReadReq_hits::total 46580786 # number of ReadReq hits 582system.cpu.dcache.WriteReq_hits::cpu.data 20513865 # number of WriteReq hits 583system.cpu.dcache.WriteReq_hits::total 20513865 # number of WriteReq hits 584system.cpu.dcache.demand_hits::cpu.data 67094651 # number of demand (read+write) hits 585system.cpu.dcache.demand_hits::total 67094651 # number of demand (read+write) hits 586system.cpu.dcache.overall_hits::cpu.data 67094651 # number of overall hits 587system.cpu.dcache.overall_hits::total 67094651 # number of overall hits 588system.cpu.dcache.ReadReq_misses::cpu.data 1141 # number of ReadReq misses 589system.cpu.dcache.ReadReq_misses::total 1141 # number of ReadReq misses 590system.cpu.dcache.WriteReq_misses::cpu.data 1866 # number of WriteReq misses 591system.cpu.dcache.WriteReq_misses::total 1866 # number of WriteReq misses 592system.cpu.dcache.demand_misses::cpu.data 3007 # number of demand (read+write) misses 593system.cpu.dcache.demand_misses::total 3007 # number of demand (read+write) misses 594system.cpu.dcache.overall_misses::cpu.data 3007 # number of overall misses 595system.cpu.dcache.overall_misses::total 3007 # number of overall misses 596system.cpu.dcache.ReadReq_miss_latency::cpu.data 64283437 # number of ReadReq miss cycles 597system.cpu.dcache.ReadReq_miss_latency::total 64283437 # number of ReadReq miss cycles 598system.cpu.dcache.WriteReq_miss_latency::cpu.data 116004574 # number of WriteReq miss cycles 599system.cpu.dcache.WriteReq_miss_latency::total 116004574 # number of WriteReq miss cycles 600system.cpu.dcache.demand_miss_latency::cpu.data 180288011 # number of demand (read+write) miss cycles 601system.cpu.dcache.demand_miss_latency::total 180288011 # number of demand (read+write) miss cycles 602system.cpu.dcache.overall_miss_latency::cpu.data 180288011 # number of overall miss cycles 603system.cpu.dcache.overall_miss_latency::total 180288011 # number of overall miss cycles 604system.cpu.dcache.ReadReq_accesses::cpu.data 46581927 # number of ReadReq accesses(hits+misses) 605system.cpu.dcache.ReadReq_accesses::total 46581927 # number of ReadReq accesses(hits+misses) 606system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) 607system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) 608system.cpu.dcache.demand_accesses::cpu.data 67097658 # number of demand (read+write) accesses 609system.cpu.dcache.demand_accesses::total 67097658 # number of demand (read+write) accesses 610system.cpu.dcache.overall_accesses::cpu.data 67097658 # number of overall (read+write) accesses 611system.cpu.dcache.overall_accesses::total 67097658 # number of overall (read+write) accesses 612system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses 613system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses 614system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000091 # miss rate for WriteReq accesses 615system.cpu.dcache.WriteReq_miss_rate::total 0.000091 # miss rate for WriteReq accesses 616system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 # miss rate for demand accesses 617system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses 618system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses 619system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses 620system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56339.559159 # average ReadReq miss latency 621system.cpu.dcache.ReadReq_avg_miss_latency::total 56339.559159 # average ReadReq miss latency 622system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62167.510182 # average WriteReq miss latency 623system.cpu.dcache.WriteReq_avg_miss_latency::total 62167.510182 # average WriteReq miss latency 624system.cpu.dcache.demand_avg_miss_latency::cpu.data 59956.106086 # average overall miss latency 625system.cpu.dcache.demand_avg_miss_latency::total 59956.106086 # average overall miss latency 626system.cpu.dcache.overall_avg_miss_latency::cpu.data 59956.106086 # average overall miss latency 627system.cpu.dcache.overall_avg_miss_latency::total 59956.106086 # average overall miss latency 628system.cpu.dcache.blocked_cycles::no_mshrs 248 # number of cycles access was blocked 629system.cpu.dcache.blocked_cycles::no_targets 50 # number of cycles access was blocked 630system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked 631system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked 632system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.600000 # average number of cycles each access was blocked 633system.cpu.dcache.avg_blocked_cycles::no_targets 50 # average number of cycles each access was blocked 634system.cpu.dcache.fast_writes 0 # number of fast writes performed 635system.cpu.dcache.cache_copies 0 # number of cache copies performed 636system.cpu.dcache.writebacks::writebacks 10 # number of writebacks 637system.cpu.dcache.writebacks::total 10 # number of writebacks 638system.cpu.dcache.ReadReq_mshr_hits::cpu.data 666 # number of ReadReq MSHR hits 639system.cpu.dcache.ReadReq_mshr_hits::total 666 # number of ReadReq MSHR hits 640system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits 641system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits 642system.cpu.dcache.demand_mshr_hits::cpu.data 667 # number of demand (read+write) MSHR hits 643system.cpu.dcache.demand_mshr_hits::total 667 # number of demand (read+write) MSHR hits 644system.cpu.dcache.overall_mshr_hits::cpu.data 667 # number of overall MSHR hits 645system.cpu.dcache.overall_mshr_hits::total 667 # number of overall MSHR hits 646system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses 647system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses 648system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1865 # number of WriteReq MSHR misses 649system.cpu.dcache.WriteReq_mshr_misses::total 1865 # number of WriteReq MSHR misses 650system.cpu.dcache.demand_mshr_misses::cpu.data 2340 # number of demand (read+write) MSHR misses 651system.cpu.dcache.demand_mshr_misses::total 2340 # number of demand (read+write) MSHR misses 652system.cpu.dcache.overall_mshr_misses::cpu.data 2340 # number of overall MSHR misses 653system.cpu.dcache.overall_mshr_misses::total 2340 # number of overall MSHR misses 654system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33671000 # number of ReadReq MSHR miss cycles 655system.cpu.dcache.ReadReq_mshr_miss_latency::total 33671000 # number of ReadReq MSHR miss cycles 656system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 111589176 # number of WriteReq MSHR miss cycles 657system.cpu.dcache.WriteReq_mshr_miss_latency::total 111589176 # number of WriteReq MSHR miss cycles 658system.cpu.dcache.demand_mshr_miss_latency::cpu.data 145260176 # number of demand (read+write) MSHR miss cycles 659system.cpu.dcache.demand_mshr_miss_latency::total 145260176 # number of demand (read+write) MSHR miss cycles 660system.cpu.dcache.overall_mshr_miss_latency::cpu.data 145260176 # number of overall MSHR miss cycles 661system.cpu.dcache.overall_mshr_miss_latency::total 145260176 # number of overall MSHR miss cycles 662system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses 663system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses 664system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000091 # mshr miss rate for WriteReq accesses 665system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000091 # mshr miss rate for WriteReq accesses 666system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for demand accesses 667system.cpu.dcache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses 668system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for overall accesses 669system.cpu.dcache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses 670system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70886.315789 # average ReadReq mshr miss latency 671system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70886.315789 # average ReadReq mshr miss latency 672system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59833.338338 # average WriteReq mshr miss latency 673system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59833.338338 # average WriteReq mshr miss latency 674system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62076.998291 # average overall mshr miss latency 675system.cpu.dcache.demand_avg_mshr_miss_latency::total 62076.998291 # average overall mshr miss latency 676system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62076.998291 # average overall mshr miss latency 677system.cpu.dcache.overall_avg_mshr_miss_latency::total 62076.998291 # average overall mshr miss latency 678system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 679system.cpu.icache.tags.replacements 5851 # number of replacements 680system.cpu.icache.tags.tagsinuse 1641.461746 # Cycle average of tags in use 681system.cpu.icache.tags.total_refs 26627917 # Total number of references to valid blocks. 682system.cpu.icache.tags.sampled_refs 7830 # Sample count of references to valid blocks. 683system.cpu.icache.tags.avg_refs 3400.755683 # Average number of references to valid blocks. |
| 622system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 684system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 623system.cpu.icache.tags.occ_blocks::cpu.inst 1649.665059 # Average occupied blocks per requestor 624system.cpu.icache.tags.occ_percent::cpu.inst 0.805501 # Average percentage of cache occupancy 625system.cpu.icache.tags.occ_percent::total 0.805501 # Average percentage of cache occupancy | 685system.cpu.icache.tags.occ_blocks::cpu.inst 1641.461746 # Average occupied blocks per requestor 686system.cpu.icache.tags.occ_percent::cpu.inst 0.801495 # Average percentage of cache occupancy 687system.cpu.icache.tags.occ_percent::total 0.801495 # Average percentage of cache occupancy |
| 626system.cpu.icache.tags.occ_task_id_blocks::1024 1979 # Occupied blocks per task id | 688system.cpu.icache.tags.occ_task_id_blocks::1024 1979 # Occupied blocks per task id |
| 627system.cpu.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id 628system.cpu.icache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id 629system.cpu.icache.tags.age_task_id_blocks_1024::2 796 # Occupied blocks per task id 630system.cpu.icache.tags.age_task_id_blocks_1024::3 127 # Occupied blocks per task id 631system.cpu.icache.tags.age_task_id_blocks_1024::4 790 # Occupied blocks per task id | 689system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id 690system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id 691system.cpu.icache.tags.age_task_id_blocks_1024::2 813 # Occupied blocks per task id 692system.cpu.icache.tags.age_task_id_blocks_1024::3 142 # Occupied blocks per task id 693system.cpu.icache.tags.age_task_id_blocks_1024::4 767 # Occupied blocks per task id |
| 632system.cpu.icache.tags.occ_task_id_percent::1024 0.966309 # Percentage of cache occupancy per task id | 694system.cpu.icache.tags.occ_task_id_percent::1024 0.966309 # Percentage of cache occupancy per task id |
| 633system.cpu.icache.tags.tag_accesses 53307648 # Number of tag accesses 634system.cpu.icache.tags.data_accesses 53307648 # Number of data accesses 635system.cpu.icache.ReadReq_hits::cpu.inst 26639065 # number of ReadReq hits 636system.cpu.icache.ReadReq_hits::total 26639065 # number of ReadReq hits 637system.cpu.icache.demand_hits::cpu.inst 26639065 # number of demand (read+write) hits 638system.cpu.icache.demand_hits::total 26639065 # number of demand (read+write) hits 639system.cpu.icache.overall_hits::cpu.inst 26639065 # number of overall hits 640system.cpu.icache.overall_hits::total 26639065 # number of overall hits 641system.cpu.icache.ReadReq_misses::cpu.inst 10629 # number of ReadReq misses 642system.cpu.icache.ReadReq_misses::total 10629 # number of ReadReq misses 643system.cpu.icache.demand_misses::cpu.inst 10629 # number of demand (read+write) misses 644system.cpu.icache.demand_misses::total 10629 # number of demand (read+write) misses 645system.cpu.icache.overall_misses::cpu.inst 10629 # number of overall misses 646system.cpu.icache.overall_misses::total 10629 # number of overall misses 647system.cpu.icache.ReadReq_miss_latency::cpu.inst 394374749 # number of ReadReq miss cycles 648system.cpu.icache.ReadReq_miss_latency::total 394374749 # number of ReadReq miss cycles 649system.cpu.icache.demand_miss_latency::cpu.inst 394374749 # number of demand (read+write) miss cycles 650system.cpu.icache.demand_miss_latency::total 394374749 # number of demand (read+write) miss cycles 651system.cpu.icache.overall_miss_latency::cpu.inst 394374749 # number of overall miss cycles 652system.cpu.icache.overall_miss_latency::total 394374749 # number of overall miss cycles 653system.cpu.icache.ReadReq_accesses::cpu.inst 26649694 # number of ReadReq accesses(hits+misses) 654system.cpu.icache.ReadReq_accesses::total 26649694 # number of ReadReq accesses(hits+misses) 655system.cpu.icache.demand_accesses::cpu.inst 26649694 # number of demand (read+write) accesses 656system.cpu.icache.demand_accesses::total 26649694 # number of demand (read+write) accesses 657system.cpu.icache.overall_accesses::cpu.inst 26649694 # number of overall (read+write) accesses 658system.cpu.icache.overall_accesses::total 26649694 # number of overall (read+write) accesses 659system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000399 # miss rate for ReadReq accesses 660system.cpu.icache.ReadReq_miss_rate::total 0.000399 # miss rate for ReadReq accesses 661system.cpu.icache.demand_miss_rate::cpu.inst 0.000399 # miss rate for demand accesses 662system.cpu.icache.demand_miss_rate::total 0.000399 # miss rate for demand accesses 663system.cpu.icache.overall_miss_rate::cpu.inst 0.000399 # miss rate for overall accesses 664system.cpu.icache.overall_miss_rate::total 0.000399 # miss rate for overall accesses 665system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37103.655000 # average ReadReq miss latency 666system.cpu.icache.ReadReq_avg_miss_latency::total 37103.655000 # average ReadReq miss latency 667system.cpu.icache.demand_avg_miss_latency::cpu.inst 37103.655000 # average overall miss latency 668system.cpu.icache.demand_avg_miss_latency::total 37103.655000 # average overall miss latency 669system.cpu.icache.overall_avg_miss_latency::cpu.inst 37103.655000 # average overall miss latency 670system.cpu.icache.overall_avg_miss_latency::total 37103.655000 # average overall miss latency 671system.cpu.icache.blocked_cycles::no_mshrs 1302 # number of cycles access was blocked | 695system.cpu.icache.tags.tag_accesses 53285074 # Number of tag accesses 696system.cpu.icache.tags.data_accesses 53285074 # Number of data accesses 697system.cpu.icache.ReadReq_hits::cpu.inst 26627919 # number of ReadReq hits 698system.cpu.icache.ReadReq_hits::total 26627919 # number of ReadReq hits 699system.cpu.icache.demand_hits::cpu.inst 26627919 # number of demand (read+write) hits 700system.cpu.icache.demand_hits::total 26627919 # number of demand (read+write) hits 701system.cpu.icache.overall_hits::cpu.inst 26627919 # number of overall hits 702system.cpu.icache.overall_hits::total 26627919 # number of overall hits 703system.cpu.icache.ReadReq_misses::cpu.inst 10540 # number of ReadReq misses 704system.cpu.icache.ReadReq_misses::total 10540 # number of ReadReq misses 705system.cpu.icache.demand_misses::cpu.inst 10540 # number of demand (read+write) misses 706system.cpu.icache.demand_misses::total 10540 # number of demand (read+write) misses 707system.cpu.icache.overall_misses::cpu.inst 10540 # number of overall misses 708system.cpu.icache.overall_misses::total 10540 # number of overall misses 709system.cpu.icache.ReadReq_miss_latency::cpu.inst 391405749 # number of ReadReq miss cycles 710system.cpu.icache.ReadReq_miss_latency::total 391405749 # number of ReadReq miss cycles 711system.cpu.icache.demand_miss_latency::cpu.inst 391405749 # number of demand (read+write) miss cycles 712system.cpu.icache.demand_miss_latency::total 391405749 # number of demand (read+write) miss cycles 713system.cpu.icache.overall_miss_latency::cpu.inst 391405749 # number of overall miss cycles 714system.cpu.icache.overall_miss_latency::total 391405749 # number of overall miss cycles 715system.cpu.icache.ReadReq_accesses::cpu.inst 26638459 # number of ReadReq accesses(hits+misses) 716system.cpu.icache.ReadReq_accesses::total 26638459 # number of ReadReq accesses(hits+misses) 717system.cpu.icache.demand_accesses::cpu.inst 26638459 # number of demand (read+write) accesses 718system.cpu.icache.demand_accesses::total 26638459 # number of demand (read+write) accesses 719system.cpu.icache.overall_accesses::cpu.inst 26638459 # number of overall (read+write) accesses 720system.cpu.icache.overall_accesses::total 26638459 # number of overall (read+write) accesses 721system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000396 # miss rate for ReadReq accesses 722system.cpu.icache.ReadReq_miss_rate::total 0.000396 # miss rate for ReadReq accesses 723system.cpu.icache.demand_miss_rate::cpu.inst 0.000396 # miss rate for demand accesses 724system.cpu.icache.demand_miss_rate::total 0.000396 # miss rate for demand accesses 725system.cpu.icache.overall_miss_rate::cpu.inst 0.000396 # miss rate for overall accesses 726system.cpu.icache.overall_miss_rate::total 0.000396 # miss rate for overall accesses 727system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37135.270304 # average ReadReq miss latency 728system.cpu.icache.ReadReq_avg_miss_latency::total 37135.270304 # average ReadReq miss latency 729system.cpu.icache.demand_avg_miss_latency::cpu.inst 37135.270304 # average overall miss latency 730system.cpu.icache.demand_avg_miss_latency::total 37135.270304 # average overall miss latency 731system.cpu.icache.overall_avg_miss_latency::cpu.inst 37135.270304 # average overall miss latency 732system.cpu.icache.overall_avg_miss_latency::total 37135.270304 # average overall miss latency 733system.cpu.icache.blocked_cycles::no_mshrs 1286 # number of cycles access was blocked |
| 672system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 734system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 673system.cpu.icache.blocked::no_mshrs 30 # number of cycles access was blocked | 735system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked |
| 674system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 736system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 675system.cpu.icache.avg_blocked_cycles::no_mshrs 43.400000 # average number of cycles each access was blocked | 737system.cpu.icache.avg_blocked_cycles::no_mshrs 49.461538 # average number of cycles each access was blocked |
| 676system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 677system.cpu.icache.fast_writes 0 # number of fast writes performed 678system.cpu.icache.cache_copies 0 # number of cache copies performed | 738system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 739system.cpu.icache.fast_writes 0 # number of fast writes performed 740system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 679system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2367 # number of ReadReq MSHR hits 680system.cpu.icache.ReadReq_mshr_hits::total 2367 # number of ReadReq MSHR hits 681system.cpu.icache.demand_mshr_hits::cpu.inst 2367 # number of demand (read+write) MSHR hits 682system.cpu.icache.demand_mshr_hits::total 2367 # number of demand (read+write) MSHR hits 683system.cpu.icache.overall_mshr_hits::cpu.inst 2367 # number of overall MSHR hits 684system.cpu.icache.overall_mshr_hits::total 2367 # number of overall MSHR hits 685system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8262 # number of ReadReq MSHR misses 686system.cpu.icache.ReadReq_mshr_misses::total 8262 # number of ReadReq MSHR misses 687system.cpu.icache.demand_mshr_misses::cpu.inst 8262 # number of demand (read+write) MSHR misses 688system.cpu.icache.demand_mshr_misses::total 8262 # number of demand (read+write) MSHR misses 689system.cpu.icache.overall_mshr_misses::cpu.inst 8262 # number of overall MSHR misses 690system.cpu.icache.overall_mshr_misses::total 8262 # number of overall MSHR misses 691system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 293853251 # number of ReadReq MSHR miss cycles 692system.cpu.icache.ReadReq_mshr_miss_latency::total 293853251 # number of ReadReq MSHR miss cycles 693system.cpu.icache.demand_mshr_miss_latency::cpu.inst 293853251 # number of demand (read+write) MSHR miss cycles 694system.cpu.icache.demand_mshr_miss_latency::total 293853251 # number of demand (read+write) MSHR miss cycles 695system.cpu.icache.overall_mshr_miss_latency::cpu.inst 293853251 # number of overall MSHR miss cycles 696system.cpu.icache.overall_mshr_miss_latency::total 293853251 # number of overall MSHR miss cycles 697system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000310 # mshr miss rate for ReadReq accesses 698system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000310 # mshr miss rate for ReadReq accesses 699system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000310 # mshr miss rate for demand accesses 700system.cpu.icache.demand_mshr_miss_rate::total 0.000310 # mshr miss rate for demand accesses 701system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000310 # mshr miss rate for overall accesses 702system.cpu.icache.overall_mshr_miss_rate::total 0.000310 # mshr miss rate for overall accesses 703system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35566.842290 # average ReadReq mshr miss latency 704system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35566.842290 # average ReadReq mshr miss latency 705system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35566.842290 # average overall mshr miss latency 706system.cpu.icache.demand_avg_mshr_miss_latency::total 35566.842290 # average overall mshr miss latency 707system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35566.842290 # average overall mshr miss latency 708system.cpu.icache.overall_avg_mshr_miss_latency::total 35566.842290 # average overall mshr miss latency | 741system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2383 # number of ReadReq MSHR hits 742system.cpu.icache.ReadReq_mshr_hits::total 2383 # number of ReadReq MSHR hits 743system.cpu.icache.demand_mshr_hits::cpu.inst 2383 # number of demand (read+write) MSHR hits 744system.cpu.icache.demand_mshr_hits::total 2383 # number of demand (read+write) MSHR hits 745system.cpu.icache.overall_mshr_hits::cpu.inst 2383 # number of overall MSHR hits 746system.cpu.icache.overall_mshr_hits::total 2383 # number of overall MSHR hits 747system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8157 # number of ReadReq MSHR misses 748system.cpu.icache.ReadReq_mshr_misses::total 8157 # number of ReadReq MSHR misses 749system.cpu.icache.demand_mshr_misses::cpu.inst 8157 # number of demand (read+write) MSHR misses 750system.cpu.icache.demand_mshr_misses::total 8157 # number of demand (read+write) MSHR misses 751system.cpu.icache.overall_mshr_misses::cpu.inst 8157 # number of overall MSHR misses 752system.cpu.icache.overall_mshr_misses::total 8157 # number of overall MSHR misses 753system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 292444251 # number of ReadReq MSHR miss cycles 754system.cpu.icache.ReadReq_mshr_miss_latency::total 292444251 # number of ReadReq MSHR miss cycles 755system.cpu.icache.demand_mshr_miss_latency::cpu.inst 292444251 # number of demand (read+write) MSHR miss cycles 756system.cpu.icache.demand_mshr_miss_latency::total 292444251 # number of demand (read+write) MSHR miss cycles 757system.cpu.icache.overall_mshr_miss_latency::cpu.inst 292444251 # number of overall MSHR miss cycles 758system.cpu.icache.overall_mshr_miss_latency::total 292444251 # number of overall MSHR miss cycles 759system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000306 # mshr miss rate for ReadReq accesses 760system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000306 # mshr miss rate for ReadReq accesses 761system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000306 # mshr miss rate for demand accesses 762system.cpu.icache.demand_mshr_miss_rate::total 0.000306 # mshr miss rate for demand accesses 763system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000306 # mshr miss rate for overall accesses 764system.cpu.icache.overall_mshr_miss_rate::total 0.000306 # mshr miss rate for overall accesses 765system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35851.937109 # average ReadReq mshr miss latency 766system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35851.937109 # average ReadReq mshr miss latency 767system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35851.937109 # average overall mshr miss latency 768system.cpu.icache.demand_avg_mshr_miss_latency::total 35851.937109 # average overall mshr miss latency 769system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35851.937109 # average overall mshr miss latency 770system.cpu.icache.overall_avg_mshr_miss_latency::total 35851.937109 # average overall mshr miss latency |
| 709system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 710system.cpu.l2cache.tags.replacements 0 # number of replacements | 771system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 772system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 711system.cpu.l2cache.tags.tagsinuse 2653.963036 # Cycle average of tags in use 712system.cpu.l2cache.tags.total_refs 4507 # Total number of references to valid blocks. 713system.cpu.l2cache.tags.sampled_refs 3933 # Sample count of references to valid blocks. 714system.cpu.l2cache.tags.avg_refs 1.145945 # Average number of references to valid blocks. | 773system.cpu.l2cache.tags.tagsinuse 2637.518864 # Cycle average of tags in use 774system.cpu.l2cache.tags.total_refs 4367 # Total number of references to valid blocks. 775system.cpu.l2cache.tags.sampled_refs 3944 # Sample count of references to valid blocks. 776system.cpu.l2cache.tags.avg_refs 1.107252 # Average number of references to valid blocks. |
| 715system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 777system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 716system.cpu.l2cache.tags.occ_blocks::writebacks 1.072767 # Average occupied blocks per requestor 717system.cpu.l2cache.tags.occ_blocks::cpu.inst 2333.691994 # Average occupied blocks per requestor 718system.cpu.l2cache.tags.occ_blocks::cpu.data 319.198275 # Average occupied blocks per requestor 719system.cpu.l2cache.tags.occ_percent::writebacks 0.000033 # Average percentage of cache occupancy 720system.cpu.l2cache.tags.occ_percent::cpu.inst 0.071219 # Average percentage of cache occupancy 721system.cpu.l2cache.tags.occ_percent::cpu.data 0.009741 # Average percentage of cache occupancy 722system.cpu.l2cache.tags.occ_percent::total 0.080993 # Average percentage of cache occupancy 723system.cpu.l2cache.tags.occ_task_id_blocks::1024 3933 # Occupied blocks per task id 724system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 725system.cpu.l2cache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id 726system.cpu.l2cache.tags.age_task_id_blocks_1024::2 904 # Occupied blocks per task id 727system.cpu.l2cache.tags.age_task_id_blocks_1024::3 148 # Occupied blocks per task id 728system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2687 # Occupied blocks per task id 729system.cpu.l2cache.tags.occ_task_id_percent::1024 0.120026 # Percentage of cache occupancy per task id 730system.cpu.l2cache.tags.tag_accesses 87730 # Number of tag accesses 731system.cpu.l2cache.tags.data_accesses 87730 # Number of data accesses 732system.cpu.l2cache.ReadReq_hits::cpu.inst 4461 # number of ReadReq hits 733system.cpu.l2cache.ReadReq_hits::cpu.data 40 # number of ReadReq hits 734system.cpu.l2cache.ReadReq_hits::total 4501 # number of ReadReq hits | 778system.cpu.l2cache.tags.occ_blocks::writebacks 1.637738 # Average occupied blocks per requestor 779system.cpu.l2cache.tags.occ_blocks::cpu.inst 2323.101405 # Average occupied blocks per requestor 780system.cpu.l2cache.tags.occ_blocks::cpu.data 312.779722 # Average occupied blocks per requestor 781system.cpu.l2cache.tags.occ_percent::writebacks 0.000050 # Average percentage of cache occupancy 782system.cpu.l2cache.tags.occ_percent::cpu.inst 0.070895 # Average percentage of cache occupancy 783system.cpu.l2cache.tags.occ_percent::cpu.data 0.009545 # Average percentage of cache occupancy 784system.cpu.l2cache.tags.occ_percent::total 0.080491 # Average percentage of cache occupancy 785system.cpu.l2cache.tags.occ_task_id_blocks::1024 3944 # Occupied blocks per task id 786system.cpu.l2cache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 787system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id 788system.cpu.l2cache.tags.age_task_id_blocks_1024::2 920 # Occupied blocks per task id 789system.cpu.l2cache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id 790system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2666 # Occupied blocks per task id 791system.cpu.l2cache.tags.occ_task_id_percent::1024 0.120361 # Percentage of cache occupancy per task id 792system.cpu.l2cache.tags.tag_accesses 86925 # Number of tag accesses 793system.cpu.l2cache.tags.data_accesses 86925 # Number of data accesses 794system.cpu.l2cache.ReadReq_hits::cpu.inst 4317 # number of ReadReq hits 795system.cpu.l2cache.ReadReq_hits::cpu.data 44 # number of ReadReq hits 796system.cpu.l2cache.ReadReq_hits::total 4361 # number of ReadReq hits |
| 735system.cpu.l2cache.Writeback_hits::writebacks 10 # number of Writeback hits 736system.cpu.l2cache.Writeback_hits::total 10 # number of Writeback hits 737system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits 738system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits 739system.cpu.l2cache.ReadExReq_hits::cpu.data 5 # number of ReadExReq hits 740system.cpu.l2cache.ReadExReq_hits::total 5 # number of ReadExReq hits | 797system.cpu.l2cache.Writeback_hits::writebacks 10 # number of Writeback hits 798system.cpu.l2cache.Writeback_hits::total 10 # number of Writeback hits 799system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits 800system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits 801system.cpu.l2cache.ReadExReq_hits::cpu.data 5 # number of ReadExReq hits 802system.cpu.l2cache.ReadExReq_hits::total 5 # number of ReadExReq hits |
| 741system.cpu.l2cache.demand_hits::cpu.inst 4461 # number of demand (read+write) hits 742system.cpu.l2cache.demand_hits::cpu.data 45 # number of demand (read+write) hits 743system.cpu.l2cache.demand_hits::total 4506 # number of demand (read+write) hits 744system.cpu.l2cache.overall_hits::cpu.inst 4461 # number of overall hits 745system.cpu.l2cache.overall_hits::cpu.data 45 # number of overall hits 746system.cpu.l2cache.overall_hits::total 4506 # number of overall hits 747system.cpu.l2cache.ReadReq_misses::cpu.inst 3500 # number of ReadReq misses 748system.cpu.l2cache.ReadReq_misses::cpu.data 434 # number of ReadReq misses 749system.cpu.l2cache.ReadReq_misses::total 3934 # number of ReadReq misses 750system.cpu.l2cache.UpgradeReq_misses::cpu.data 296 # number of UpgradeReq misses 751system.cpu.l2cache.UpgradeReq_misses::total 296 # number of UpgradeReq misses | 803system.cpu.l2cache.demand_hits::cpu.inst 4317 # number of demand (read+write) hits 804system.cpu.l2cache.demand_hits::cpu.data 49 # number of demand (read+write) hits 805system.cpu.l2cache.demand_hits::total 4366 # number of demand (read+write) hits 806system.cpu.l2cache.overall_hits::cpu.inst 4317 # number of overall hits 807system.cpu.l2cache.overall_hits::cpu.data 49 # number of overall hits 808system.cpu.l2cache.overall_hits::total 4366 # number of overall hits 809system.cpu.l2cache.ReadReq_misses::cpu.inst 3513 # number of ReadReq misses 810system.cpu.l2cache.ReadReq_misses::cpu.data 431 # number of ReadReq misses 811system.cpu.l2cache.ReadReq_misses::total 3944 # number of ReadReq misses 812system.cpu.l2cache.UpgradeReq_misses::cpu.data 324 # number of UpgradeReq misses 813system.cpu.l2cache.UpgradeReq_misses::total 324 # number of UpgradeReq misses |
| 752system.cpu.l2cache.ReadExReq_misses::cpu.data 1533 # number of ReadExReq misses 753system.cpu.l2cache.ReadExReq_misses::total 1533 # number of ReadExReq misses | 814system.cpu.l2cache.ReadExReq_misses::cpu.data 1533 # number of ReadExReq misses 815system.cpu.l2cache.ReadExReq_misses::total 1533 # number of ReadExReq misses |
| 754system.cpu.l2cache.demand_misses::cpu.inst 3500 # number of demand (read+write) misses 755system.cpu.l2cache.demand_misses::cpu.data 1967 # number of demand (read+write) misses 756system.cpu.l2cache.demand_misses::total 5467 # number of demand (read+write) misses 757system.cpu.l2cache.overall_misses::cpu.inst 3500 # number of overall misses 758system.cpu.l2cache.overall_misses::cpu.data 1967 # number of overall misses 759system.cpu.l2cache.overall_misses::total 5467 # number of overall misses 760system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 240675250 # number of ReadReq miss cycles 761system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32902250 # number of ReadReq miss cycles 762system.cpu.l2cache.ReadReq_miss_latency::total 273577500 # number of ReadReq miss cycles 763system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 103297250 # number of ReadExReq miss cycles 764system.cpu.l2cache.ReadExReq_miss_latency::total 103297250 # number of ReadExReq miss cycles 765system.cpu.l2cache.demand_miss_latency::cpu.inst 240675250 # number of demand (read+write) miss cycles 766system.cpu.l2cache.demand_miss_latency::cpu.data 136199500 # number of demand (read+write) miss cycles 767system.cpu.l2cache.demand_miss_latency::total 376874750 # number of demand (read+write) miss cycles 768system.cpu.l2cache.overall_miss_latency::cpu.inst 240675250 # number of overall miss cycles 769system.cpu.l2cache.overall_miss_latency::cpu.data 136199500 # number of overall miss cycles 770system.cpu.l2cache.overall_miss_latency::total 376874750 # number of overall miss cycles 771system.cpu.l2cache.ReadReq_accesses::cpu.inst 7961 # number of ReadReq accesses(hits+misses) 772system.cpu.l2cache.ReadReq_accesses::cpu.data 474 # number of ReadReq accesses(hits+misses) 773system.cpu.l2cache.ReadReq_accesses::total 8435 # number of ReadReq accesses(hits+misses) | 816system.cpu.l2cache.demand_misses::cpu.inst 3513 # number of demand (read+write) misses 817system.cpu.l2cache.demand_misses::cpu.data 1964 # number of demand (read+write) misses 818system.cpu.l2cache.demand_misses::total 5477 # number of demand (read+write) misses 819system.cpu.l2cache.overall_misses::cpu.inst 3513 # number of overall misses 820system.cpu.l2cache.overall_misses::cpu.data 1964 # number of overall misses 821system.cpu.l2cache.overall_misses::total 5477 # number of overall misses 822system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 240782500 # number of ReadReq miss cycles 823system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32741000 # number of ReadReq miss cycles 824system.cpu.l2cache.ReadReq_miss_latency::total 273523500 # number of ReadReq miss cycles 825system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 102420500 # number of ReadExReq miss cycles 826system.cpu.l2cache.ReadExReq_miss_latency::total 102420500 # number of ReadExReq miss cycles 827system.cpu.l2cache.demand_miss_latency::cpu.inst 240782500 # number of demand (read+write) miss cycles 828system.cpu.l2cache.demand_miss_latency::cpu.data 135161500 # number of demand (read+write) miss cycles 829system.cpu.l2cache.demand_miss_latency::total 375944000 # number of demand (read+write) miss cycles 830system.cpu.l2cache.overall_miss_latency::cpu.inst 240782500 # number of overall miss cycles 831system.cpu.l2cache.overall_miss_latency::cpu.data 135161500 # number of overall miss cycles 832system.cpu.l2cache.overall_miss_latency::total 375944000 # number of overall miss cycles 833system.cpu.l2cache.ReadReq_accesses::cpu.inst 7830 # number of ReadReq accesses(hits+misses) 834system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) 835system.cpu.l2cache.ReadReq_accesses::total 8305 # number of ReadReq accesses(hits+misses) |
| 774system.cpu.l2cache.Writeback_accesses::writebacks 10 # number of Writeback accesses(hits+misses) 775system.cpu.l2cache.Writeback_accesses::total 10 # number of Writeback accesses(hits+misses) | 836system.cpu.l2cache.Writeback_accesses::writebacks 10 # number of Writeback accesses(hits+misses) 837system.cpu.l2cache.Writeback_accesses::total 10 # number of Writeback accesses(hits+misses) |
| 776system.cpu.l2cache.UpgradeReq_accesses::cpu.data 299 # number of UpgradeReq accesses(hits+misses) 777system.cpu.l2cache.UpgradeReq_accesses::total 299 # number of UpgradeReq accesses(hits+misses) | 838system.cpu.l2cache.UpgradeReq_accesses::cpu.data 327 # number of UpgradeReq accesses(hits+misses) 839system.cpu.l2cache.UpgradeReq_accesses::total 327 # number of UpgradeReq accesses(hits+misses) |
| 778system.cpu.l2cache.ReadExReq_accesses::cpu.data 1538 # number of ReadExReq accesses(hits+misses) 779system.cpu.l2cache.ReadExReq_accesses::total 1538 # number of ReadExReq accesses(hits+misses) | 840system.cpu.l2cache.ReadExReq_accesses::cpu.data 1538 # number of ReadExReq accesses(hits+misses) 841system.cpu.l2cache.ReadExReq_accesses::total 1538 # number of ReadExReq accesses(hits+misses) |
| 780system.cpu.l2cache.demand_accesses::cpu.inst 7961 # number of demand (read+write) accesses 781system.cpu.l2cache.demand_accesses::cpu.data 2012 # number of demand (read+write) accesses 782system.cpu.l2cache.demand_accesses::total 9973 # number of demand (read+write) accesses 783system.cpu.l2cache.overall_accesses::cpu.inst 7961 # number of overall (read+write) accesses 784system.cpu.l2cache.overall_accesses::cpu.data 2012 # number of overall (read+write) accesses 785system.cpu.l2cache.overall_accesses::total 9973 # number of overall (read+write) accesses 786system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.439643 # miss rate for ReadReq accesses 787system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.915612 # miss rate for ReadReq accesses 788system.cpu.l2cache.ReadReq_miss_rate::total 0.466390 # miss rate for ReadReq accesses 789system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989967 # miss rate for UpgradeReq accesses 790system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989967 # miss rate for UpgradeReq accesses | 842system.cpu.l2cache.demand_accesses::cpu.inst 7830 # number of demand (read+write) accesses 843system.cpu.l2cache.demand_accesses::cpu.data 2013 # number of demand (read+write) accesses 844system.cpu.l2cache.demand_accesses::total 9843 # number of demand (read+write) accesses 845system.cpu.l2cache.overall_accesses::cpu.inst 7830 # number of overall (read+write) accesses 846system.cpu.l2cache.overall_accesses::cpu.data 2013 # number of overall (read+write) accesses 847system.cpu.l2cache.overall_accesses::total 9843 # number of overall (read+write) accesses 848system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.448659 # miss rate for ReadReq accesses 849system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.907368 # miss rate for ReadReq accesses 850system.cpu.l2cache.ReadReq_miss_rate::total 0.474895 # miss rate for ReadReq accesses 851system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990826 # miss rate for UpgradeReq accesses 852system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990826 # miss rate for UpgradeReq accesses |
| 791system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996749 # miss rate for ReadExReq accesses 792system.cpu.l2cache.ReadExReq_miss_rate::total 0.996749 # miss rate for ReadExReq accesses | 853system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996749 # miss rate for ReadExReq accesses 854system.cpu.l2cache.ReadExReq_miss_rate::total 0.996749 # miss rate for ReadExReq accesses |
| 793system.cpu.l2cache.demand_miss_rate::cpu.inst 0.439643 # miss rate for demand accesses 794system.cpu.l2cache.demand_miss_rate::cpu.data 0.977634 # miss rate for demand accesses 795system.cpu.l2cache.demand_miss_rate::total 0.548180 # miss rate for demand accesses 796system.cpu.l2cache.overall_miss_rate::cpu.inst 0.439643 # miss rate for overall accesses 797system.cpu.l2cache.overall_miss_rate::cpu.data 0.977634 # miss rate for overall accesses 798system.cpu.l2cache.overall_miss_rate::total 0.548180 # miss rate for overall accesses 799system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68764.357143 # average ReadReq miss latency 800system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75811.635945 # average ReadReq miss latency 801system.cpu.l2cache.ReadReq_avg_miss_latency::total 69541.814947 # average ReadReq miss latency 802system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67382.420091 # average ReadExReq miss latency 803system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67382.420091 # average ReadExReq miss latency 804system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68764.357143 # average overall miss latency 805system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69242.247077 # average overall miss latency 806system.cpu.l2cache.demand_avg_miss_latency::total 68936.299616 # average overall miss latency 807system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68764.357143 # average overall miss latency 808system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69242.247077 # average overall miss latency 809system.cpu.l2cache.overall_avg_miss_latency::total 68936.299616 # average overall miss latency | 855system.cpu.l2cache.demand_miss_rate::cpu.inst 0.448659 # miss rate for demand accesses 856system.cpu.l2cache.demand_miss_rate::cpu.data 0.975658 # miss rate for demand accesses 857system.cpu.l2cache.demand_miss_rate::total 0.556436 # miss rate for demand accesses 858system.cpu.l2cache.overall_miss_rate::cpu.inst 0.448659 # miss rate for overall accesses 859system.cpu.l2cache.overall_miss_rate::cpu.data 0.975658 # miss rate for overall accesses 860system.cpu.l2cache.overall_miss_rate::total 0.556436 # miss rate for overall accesses 861system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68540.421292 # average ReadReq miss latency 862system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75965.197216 # average ReadReq miss latency 863system.cpu.l2cache.ReadReq_avg_miss_latency::total 69351.800203 # average ReadReq miss latency 864system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66810.502283 # average ReadExReq miss latency 865system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66810.502283 # average ReadExReq miss latency 866system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68540.421292 # average overall miss latency 867system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68819.501018 # average overall miss latency 868system.cpu.l2cache.demand_avg_miss_latency::total 68640.496622 # average overall miss latency 869system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68540.421292 # average overall miss latency 870system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68819.501018 # average overall miss latency 871system.cpu.l2cache.overall_avg_miss_latency::total 68640.496622 # average overall miss latency |
| 810system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 811system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 812system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 813system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 814system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 815system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 816system.cpu.l2cache.fast_writes 0 # number of fast writes performed 817system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 872system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 873system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 874system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 875system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 876system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 877system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 878system.cpu.l2cache.fast_writes 0 # number of fast writes performed 879system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 818system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3500 # number of ReadReq MSHR misses 819system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 434 # number of ReadReq MSHR misses 820system.cpu.l2cache.ReadReq_mshr_misses::total 3934 # number of ReadReq MSHR misses 821system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 296 # number of UpgradeReq MSHR misses 822system.cpu.l2cache.UpgradeReq_mshr_misses::total 296 # number of UpgradeReq MSHR misses | 880system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3513 # number of ReadReq MSHR misses 881system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 431 # number of ReadReq MSHR misses 882system.cpu.l2cache.ReadReq_mshr_misses::total 3944 # number of ReadReq MSHR misses 883system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 324 # number of UpgradeReq MSHR misses 884system.cpu.l2cache.UpgradeReq_mshr_misses::total 324 # number of UpgradeReq MSHR misses |
| 823system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1533 # number of ReadExReq MSHR misses 824system.cpu.l2cache.ReadExReq_mshr_misses::total 1533 # number of ReadExReq MSHR misses | 885system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1533 # number of ReadExReq MSHR misses 886system.cpu.l2cache.ReadExReq_mshr_misses::total 1533 # number of ReadExReq MSHR misses |
| 825system.cpu.l2cache.demand_mshr_misses::cpu.inst 3500 # number of demand (read+write) MSHR misses 826system.cpu.l2cache.demand_mshr_misses::cpu.data 1967 # number of demand (read+write) MSHR misses 827system.cpu.l2cache.demand_mshr_misses::total 5467 # number of demand (read+write) MSHR misses 828system.cpu.l2cache.overall_mshr_misses::cpu.inst 3500 # number of overall MSHR misses 829system.cpu.l2cache.overall_mshr_misses::cpu.data 1967 # number of overall MSHR misses 830system.cpu.l2cache.overall_mshr_misses::total 5467 # number of overall MSHR misses 831system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 196802250 # number of ReadReq MSHR miss cycles 832system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27518750 # number of ReadReq MSHR miss cycles 833system.cpu.l2cache.ReadReq_mshr_miss_latency::total 224321000 # number of ReadReq MSHR miss cycles 834system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2960795 # number of UpgradeReq MSHR miss cycles 835system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2960795 # number of UpgradeReq MSHR miss cycles 836system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 83847750 # number of ReadExReq MSHR miss cycles 837system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 83847750 # number of ReadExReq MSHR miss cycles 838system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 196802250 # number of demand (read+write) MSHR miss cycles 839system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 111366500 # number of demand (read+write) MSHR miss cycles 840system.cpu.l2cache.demand_mshr_miss_latency::total 308168750 # number of demand (read+write) MSHR miss cycles 841system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 196802250 # number of overall MSHR miss cycles 842system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 111366500 # number of overall MSHR miss cycles 843system.cpu.l2cache.overall_mshr_miss_latency::total 308168750 # number of overall MSHR miss cycles 844system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.439643 # mshr miss rate for ReadReq accesses 845system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.915612 # mshr miss rate for ReadReq accesses 846system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.466390 # mshr miss rate for ReadReq accesses 847system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989967 # mshr miss rate for UpgradeReq accesses 848system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989967 # mshr miss rate for UpgradeReq accesses | 887system.cpu.l2cache.demand_mshr_misses::cpu.inst 3513 # number of demand (read+write) MSHR misses 888system.cpu.l2cache.demand_mshr_misses::cpu.data 1964 # number of demand (read+write) MSHR misses 889system.cpu.l2cache.demand_mshr_misses::total 5477 # number of demand (read+write) MSHR misses 890system.cpu.l2cache.overall_mshr_misses::cpu.inst 3513 # number of overall MSHR misses 891system.cpu.l2cache.overall_mshr_misses::cpu.data 1964 # number of overall MSHR misses 892system.cpu.l2cache.overall_mshr_misses::total 5477 # number of overall MSHR misses 893system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 196758000 # number of ReadReq MSHR miss cycles 894system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27393000 # number of ReadReq MSHR miss cycles 895system.cpu.l2cache.ReadReq_mshr_miss_latency::total 224151000 # number of ReadReq MSHR miss cycles 896system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3240823 # number of UpgradeReq MSHR miss cycles 897system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3240823 # number of UpgradeReq MSHR miss cycles 898system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 83086000 # number of ReadExReq MSHR miss cycles 899system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 83086000 # number of ReadExReq MSHR miss cycles 900system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 196758000 # number of demand (read+write) MSHR miss cycles 901system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 110479000 # number of demand (read+write) MSHR miss cycles 902system.cpu.l2cache.demand_mshr_miss_latency::total 307237000 # number of demand (read+write) MSHR miss cycles 903system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 196758000 # number of overall MSHR miss cycles 904system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 110479000 # number of overall MSHR miss cycles 905system.cpu.l2cache.overall_mshr_miss_latency::total 307237000 # number of overall MSHR miss cycles 906system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.448659 # mshr miss rate for ReadReq accesses 907system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.907368 # mshr miss rate for ReadReq accesses 908system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.474895 # mshr miss rate for ReadReq accesses 909system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990826 # mshr miss rate for UpgradeReq accesses 910system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990826 # mshr miss rate for UpgradeReq accesses |
| 849system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996749 # mshr miss rate for ReadExReq accesses 850system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996749 # mshr miss rate for ReadExReq accesses | 911system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996749 # mshr miss rate for ReadExReq accesses 912system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996749 # mshr miss rate for ReadExReq accesses |
| 851system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.439643 # mshr miss rate for demand accesses 852system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.977634 # mshr miss rate for demand accesses 853system.cpu.l2cache.demand_mshr_miss_rate::total 0.548180 # mshr miss rate for demand accesses 854system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.439643 # mshr miss rate for overall accesses 855system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.977634 # mshr miss rate for overall accesses 856system.cpu.l2cache.overall_mshr_miss_rate::total 0.548180 # mshr miss rate for overall accesses 857system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56229.214286 # average ReadReq mshr miss latency 858system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63407.258065 # average ReadReq mshr miss latency 859system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57021.098119 # average ReadReq mshr miss latency 860system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.685811 # average UpgradeReq mshr miss latency 861system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.685811 # average UpgradeReq mshr miss latency 862system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54695.205479 # average ReadExReq mshr miss latency 863system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54695.205479 # average ReadExReq mshr miss latency 864system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56229.214286 # average overall mshr miss latency 865system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56617.437722 # average overall mshr miss latency 866system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56368.895189 # average overall mshr miss latency 867system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56229.214286 # average overall mshr miss latency 868system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56617.437722 # average overall mshr miss latency 869system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56368.895189 # average overall mshr miss latency | 913system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.448659 # mshr miss rate for demand accesses 914system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.975658 # mshr miss rate for demand accesses 915system.cpu.l2cache.demand_mshr_miss_rate::total 0.556436 # mshr miss rate for demand accesses 916system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.448659 # mshr miss rate for overall accesses 917system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.975658 # mshr miss rate for overall accesses 918system.cpu.l2cache.overall_mshr_miss_rate::total 0.556436 # mshr miss rate for overall accesses 919system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56008.539710 # average ReadReq mshr miss latency 920system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63556.844548 # average ReadReq mshr miss latency 921system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56833.417850 # average ReadReq mshr miss latency 922system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.540123 # average UpgradeReq mshr miss latency 923system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.540123 # average UpgradeReq mshr miss latency 924system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54198.303979 # average ReadExReq mshr miss latency 925system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54198.303979 # average ReadExReq mshr miss latency 926system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56008.539710 # average overall mshr miss latency 927system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56252.036660 # average overall mshr miss latency 928system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56095.855395 # average overall mshr miss latency 929system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56008.539710 # average overall mshr miss latency 930system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56252.036660 # average overall mshr miss latency 931system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56095.855395 # average overall mshr miss latency |
| 870system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 932system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 871system.cpu.dcache.tags.replacements 52 # number of replacements 872system.cpu.dcache.tags.tagsinuse 1451.665096 # Cycle average of tags in use 873system.cpu.dcache.tags.total_refs 67147234 # Total number of references to valid blocks. 874system.cpu.dcache.tags.sampled_refs 2012 # Sample count of references to valid blocks. 875system.cpu.dcache.tags.avg_refs 33373.376740 # Average number of references to valid blocks. 876system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 877system.cpu.dcache.tags.occ_blocks::cpu.data 1451.665096 # Average occupied blocks per requestor 878system.cpu.dcache.tags.occ_percent::cpu.data 0.354410 # Average percentage of cache occupancy 879system.cpu.dcache.tags.occ_percent::total 0.354410 # Average percentage of cache occupancy 880system.cpu.dcache.tags.occ_task_id_blocks::1024 1960 # Occupied blocks per task id 881system.cpu.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 882system.cpu.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 883system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id 884system.cpu.dcache.tags.age_task_id_blocks_1024::3 434 # Occupied blocks per task id 885system.cpu.dcache.tags.age_task_id_blocks_1024::4 1416 # Occupied blocks per task id 886system.cpu.dcache.tags.occ_task_id_percent::1024 0.478516 # Percentage of cache occupancy per task id 887system.cpu.dcache.tags.tag_accesses 134301424 # Number of tag accesses 888system.cpu.dcache.tags.data_accesses 134301424 # Number of data accesses 889system.cpu.dcache.ReadReq_hits::cpu.data 46632911 # number of ReadReq hits 890system.cpu.dcache.ReadReq_hits::total 46632911 # number of ReadReq hits 891system.cpu.dcache.WriteReq_hits::cpu.data 20513893 # number of WriteReq hits 892system.cpu.dcache.WriteReq_hits::total 20513893 # number of WriteReq hits 893system.cpu.dcache.demand_hits::cpu.data 67146804 # number of demand (read+write) hits 894system.cpu.dcache.demand_hits::total 67146804 # number of demand (read+write) hits 895system.cpu.dcache.overall_hits::cpu.data 67146804 # number of overall hits 896system.cpu.dcache.overall_hits::total 67146804 # number of overall hits 897system.cpu.dcache.ReadReq_misses::cpu.data 1064 # number of ReadReq misses 898system.cpu.dcache.ReadReq_misses::total 1064 # number of ReadReq misses 899system.cpu.dcache.WriteReq_misses::cpu.data 1838 # number of WriteReq misses 900system.cpu.dcache.WriteReq_misses::total 1838 # number of WriteReq misses 901system.cpu.dcache.demand_misses::cpu.data 2902 # number of demand (read+write) misses 902system.cpu.dcache.demand_misses::total 2902 # number of demand (read+write) misses 903system.cpu.dcache.overall_misses::cpu.data 2902 # number of overall misses 904system.cpu.dcache.overall_misses::total 2902 # number of overall misses 905system.cpu.dcache.ReadReq_miss_latency::cpu.data 63689380 # number of ReadReq miss cycles 906system.cpu.dcache.ReadReq_miss_latency::total 63689380 # number of ReadReq miss cycles 907system.cpu.dcache.WriteReq_miss_latency::cpu.data 116173296 # number of WriteReq miss cycles 908system.cpu.dcache.WriteReq_miss_latency::total 116173296 # number of WriteReq miss cycles 909system.cpu.dcache.demand_miss_latency::cpu.data 179862676 # number of demand (read+write) miss cycles 910system.cpu.dcache.demand_miss_latency::total 179862676 # number of demand (read+write) miss cycles 911system.cpu.dcache.overall_miss_latency::cpu.data 179862676 # number of overall miss cycles 912system.cpu.dcache.overall_miss_latency::total 179862676 # number of overall miss cycles 913system.cpu.dcache.ReadReq_accesses::cpu.data 46633975 # number of ReadReq accesses(hits+misses) 914system.cpu.dcache.ReadReq_accesses::total 46633975 # number of ReadReq accesses(hits+misses) 915system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) 916system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) 917system.cpu.dcache.demand_accesses::cpu.data 67149706 # number of demand (read+write) accesses 918system.cpu.dcache.demand_accesses::total 67149706 # number of demand (read+write) accesses 919system.cpu.dcache.overall_accesses::cpu.data 67149706 # number of overall (read+write) accesses 920system.cpu.dcache.overall_accesses::total 67149706 # number of overall (read+write) accesses 921system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses 922system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses 923system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000090 # miss rate for WriteReq accesses 924system.cpu.dcache.WriteReq_miss_rate::total 0.000090 # miss rate for WriteReq accesses 925system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses 926system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses 927system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses 928system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses 929system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59858.439850 # average ReadReq miss latency 930system.cpu.dcache.ReadReq_avg_miss_latency::total 59858.439850 # average ReadReq miss latency 931system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63206.363439 # average WriteReq miss latency 932system.cpu.dcache.WriteReq_avg_miss_latency::total 63206.363439 # average WriteReq miss latency 933system.cpu.dcache.demand_avg_miss_latency::cpu.data 61978.868367 # average overall miss latency 934system.cpu.dcache.demand_avg_miss_latency::total 61978.868367 # average overall miss latency 935system.cpu.dcache.overall_avg_miss_latency::cpu.data 61978.868367 # average overall miss latency 936system.cpu.dcache.overall_avg_miss_latency::total 61978.868367 # average overall miss latency 937system.cpu.dcache.blocked_cycles::no_mshrs 303 # number of cycles access was blocked 938system.cpu.dcache.blocked_cycles::no_targets 50 # number of cycles access was blocked 939system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked 940system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked 941system.cpu.dcache.avg_blocked_cycles::no_mshrs 60.600000 # average number of cycles each access was blocked 942system.cpu.dcache.avg_blocked_cycles::no_targets 50 # average number of cycles each access was blocked 943system.cpu.dcache.fast_writes 0 # number of fast writes performed 944system.cpu.dcache.cache_copies 0 # number of cache copies performed 945system.cpu.dcache.writebacks::writebacks 10 # number of writebacks 946system.cpu.dcache.writebacks::total 10 # number of writebacks 947system.cpu.dcache.ReadReq_mshr_hits::cpu.data 590 # number of ReadReq MSHR hits 948system.cpu.dcache.ReadReq_mshr_hits::total 590 # number of ReadReq MSHR hits 949system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits 950system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits 951system.cpu.dcache.demand_mshr_hits::cpu.data 591 # number of demand (read+write) MSHR hits 952system.cpu.dcache.demand_mshr_hits::total 591 # number of demand (read+write) MSHR hits 953system.cpu.dcache.overall_mshr_hits::cpu.data 591 # number of overall MSHR hits 954system.cpu.dcache.overall_mshr_hits::total 591 # number of overall MSHR hits 955system.cpu.dcache.ReadReq_mshr_misses::cpu.data 474 # number of ReadReq MSHR misses 956system.cpu.dcache.ReadReq_mshr_misses::total 474 # number of ReadReq MSHR misses 957system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1837 # number of WriteReq MSHR misses 958system.cpu.dcache.WriteReq_mshr_misses::total 1837 # number of WriteReq MSHR misses 959system.cpu.dcache.demand_mshr_misses::cpu.data 2311 # number of demand (read+write) MSHR misses 960system.cpu.dcache.demand_mshr_misses::total 2311 # number of demand (read+write) MSHR misses 961system.cpu.dcache.overall_mshr_misses::cpu.data 2311 # number of overall MSHR misses 962system.cpu.dcache.overall_mshr_misses::total 2311 # number of overall MSHR misses 963system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33789250 # number of ReadReq MSHR miss cycles 964system.cpu.dcache.ReadReq_mshr_miss_latency::total 33789250 # number of ReadReq MSHR miss cycles 965system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 111812454 # number of WriteReq MSHR miss cycles 966system.cpu.dcache.WriteReq_mshr_miss_latency::total 111812454 # number of WriteReq MSHR miss cycles 967system.cpu.dcache.demand_mshr_miss_latency::cpu.data 145601704 # number of demand (read+write) MSHR miss cycles 968system.cpu.dcache.demand_mshr_miss_latency::total 145601704 # number of demand (read+write) MSHR miss cycles 969system.cpu.dcache.overall_mshr_miss_latency::cpu.data 145601704 # number of overall MSHR miss cycles 970system.cpu.dcache.overall_mshr_miss_latency::total 145601704 # number of overall MSHR miss cycles 971system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses 972system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses 973system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000090 # mshr miss rate for WriteReq accesses 974system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000090 # mshr miss rate for WriteReq accesses 975system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for demand accesses 976system.cpu.dcache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses 977system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for overall accesses 978system.cpu.dcache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses 979system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71285.337553 # average ReadReq mshr miss latency 980system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71285.337553 # average ReadReq mshr miss latency 981system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60866.877518 # average WriteReq mshr miss latency 982system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60866.877518 # average WriteReq mshr miss latency 983system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63003.766335 # average overall mshr miss latency 984system.cpu.dcache.demand_avg_mshr_miss_latency::total 63003.766335 # average overall mshr miss latency 985system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63003.766335 # average overall mshr miss latency 986system.cpu.dcache.overall_avg_mshr_miss_latency::total 63003.766335 # average overall mshr miss latency 987system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 933system.cpu.toL2Bus.trans_dist::ReadReq 8632 # Transaction distribution 934system.cpu.toL2Bus.trans_dist::ReadResp 8631 # Transaction distribution 935system.cpu.toL2Bus.trans_dist::Writeback 10 # Transaction distribution 936system.cpu.toL2Bus.trans_dist::UpgradeReq 327 # Transaction distribution 937system.cpu.toL2Bus.trans_dist::UpgradeResp 327 # Transaction distribution 938system.cpu.toL2Bus.trans_dist::ReadExReq 1538 # Transaction distribution 939system.cpu.toL2Bus.trans_dist::ReadExResp 1538 # Transaction distribution 940system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15986 # Packet count per connected master and slave (bytes) 941system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4690 # Packet count per connected master and slave (bytes) 942system.cpu.toL2Bus.pkt_count::total 20676 # Packet count per connected master and slave (bytes) 943system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 501056 # Cumulative packet size per connected master and slave (bytes) 944system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129472 # Cumulative packet size per connected master and slave (bytes) 945system.cpu.toL2Bus.pkt_size::total 630528 # Cumulative packet size per connected master and slave (bytes) 946system.cpu.toL2Bus.snoops 327 # Total snoops (count) 947system.cpu.toL2Bus.snoop_fanout::samples 10507 # Request fanout histogram 948system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram 949system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 950system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 951system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 952system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 953system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 954system.cpu.toL2Bus.snoop_fanout::3 10507 100.00% 100.00% # Request fanout histogram 955system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 956system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 957system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 958system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 959system.cpu.toL2Bus.snoop_fanout::total 10507 # Request fanout histogram 960system.cpu.toL2Bus.reqLayer0.occupancy 5263999 # Layer occupancy (ticks) 961system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 962system.cpu.toL2Bus.respLayer0.occupancy 12826749 # Layer occupancy (ticks) 963system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 964system.cpu.toL2Bus.respLayer1.occupancy 3560824 # Layer occupancy (ticks) 965system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 966system.membus.trans_dist::ReadReq 3943 # Transaction distribution 967system.membus.trans_dist::ReadResp 3943 # Transaction distribution 968system.membus.trans_dist::UpgradeReq 324 # Transaction distribution 969system.membus.trans_dist::UpgradeResp 324 # Transaction distribution 970system.membus.trans_dist::ReadExReq 1533 # Transaction distribution 971system.membus.trans_dist::ReadExResp 1533 # Transaction distribution 972system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11600 # Packet count per connected master and slave (bytes) 973system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11600 # Packet count per connected master and slave (bytes) 974system.membus.pkt_count::total 11600 # Packet count per connected master and slave (bytes) 975system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 350464 # Cumulative packet size per connected master and slave (bytes) 976system.membus.pkt_size_system.cpu.l2cache.mem_side::total 350464 # Cumulative packet size per connected master and slave (bytes) 977system.membus.pkt_size::total 350464 # Cumulative packet size per connected master and slave (bytes) 978system.membus.snoops 0 # Total snoops (count) 979system.membus.snoop_fanout::samples 5800 # Request fanout histogram 980system.membus.snoop_fanout::mean 0 # Request fanout histogram 981system.membus.snoop_fanout::stdev 0 # Request fanout histogram 982system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 983system.membus.snoop_fanout::0 5800 100.00% 100.00% # Request fanout histogram 984system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 985system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 986system.membus.snoop_fanout::min_value 0 # Request fanout histogram 987system.membus.snoop_fanout::max_value 0 # Request fanout histogram 988system.membus.snoop_fanout::total 5800 # Request fanout histogram 989system.membus.reqLayer0.occupancy 7074000 # Layer occupancy (ticks) 990system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 991system.membus.respLayer1.occupancy 51890176 # Layer occupancy (ticks) 992system.membus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 988 989---------- End Simulation Statistics ---------- | 993 994---------- End Simulation Statistics ---------- |