| stats.txt (10352:5f1f92bf76ee) | stats.txt (10409:8c80b91944c5) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.148587 # Number of seconds simulated 4sim_ticks 148587085500 # Number of ticks simulated 5final_tick 148587085500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.148694 # Number of seconds simulated 4sim_ticks 148694012000 # Number of ticks simulated 5final_tick 148694012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 101386 # Simulator instruction rate (inst/s) 8host_op_rate 169932 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 114064202 # Simulator tick rate (ticks/s) 10host_mem_usage 285092 # Number of bytes of host memory used 11host_seconds 1302.66 # Real time elapsed on the host | 7host_inst_rate 84654 # Simulator instruction rate (inst/s) 8host_op_rate 141888 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 95308980 # Simulator tick rate (ticks/s) 10host_mem_usage 341916 # Number of bytes of host memory used 11host_seconds 1560.13 # Real time elapsed on the host |
| 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221363384 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221363384 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 225472 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 125440 # Number of bytes read from this memory 18system.physmem.bytes_read::total 350912 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 225472 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 225472 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 3523 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1960 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 5483 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1517440 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 844219 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 2361659 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1517440 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1517440 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1517440 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 844219 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 2361659 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 5483 # Number of read requests accepted | 16system.physmem.bytes_read::cpu.inst 223936 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 125888 # Number of bytes read from this memory 18system.physmem.bytes_read::total 349824 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 223936 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 223936 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 3499 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1967 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 5466 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1506019 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 846625 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 2352643 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1506019 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1506019 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1506019 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 846625 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 2352643 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 5466 # Number of read requests accepted |
| 33system.physmem.writeReqs 0 # Number of write requests accepted | 33system.physmem.writeReqs 0 # Number of write requests accepted |
| 34system.physmem.readBursts 5483 # Number of DRAM read bursts, including those serviced by the write queue | 34system.physmem.readBursts 5466 # Number of DRAM read bursts, including those serviced by the write queue |
| 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 36system.physmem.bytesReadDRAM 350912 # Total number of bytes read from DRAM | 36system.physmem.bytesReadDRAM 349824 # Total number of bytes read from DRAM |
| 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 39system.physmem.bytesReadSys 350912 # Total read bytes from the system interface side | 39system.physmem.bytesReadSys 349824 # Total read bytes from the system interface side |
| 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one | 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| 43system.physmem.neitherReadNorWriteReqs 350 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 310 # Per bank write bursts 45system.physmem.perBankRdBursts::1 352 # Per bank write bursts 46system.physmem.perBankRdBursts::2 465 # Per bank write bursts 47system.physmem.perBankRdBursts::3 360 # Per bank write bursts 48system.physmem.perBankRdBursts::4 334 # Per bank write bursts 49system.physmem.perBankRdBursts::5 328 # Per bank write bursts | 43system.physmem.neitherReadNorWriteReqs 296 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 294 # Per bank write bursts 45system.physmem.perBankRdBursts::1 361 # Per bank write bursts 46system.physmem.perBankRdBursts::2 463 # Per bank write bursts 47system.physmem.perBankRdBursts::3 372 # Per bank write bursts 48system.physmem.perBankRdBursts::4 337 # Per bank write bursts 49system.physmem.perBankRdBursts::5 332 # Per bank write bursts |
| 50system.physmem.perBankRdBursts::6 400 # Per bank write bursts | 50system.physmem.perBankRdBursts::6 400 # Per bank write bursts |
| 51system.physmem.perBankRdBursts::7 386 # Per bank write bursts | 51system.physmem.perBankRdBursts::7 384 # Per bank write bursts |
| 52system.physmem.perBankRdBursts::8 341 # Per bank write bursts | 52system.physmem.perBankRdBursts::8 341 # Per bank write bursts |
| 53system.physmem.perBankRdBursts::9 281 # Per bank write bursts 54system.physmem.perBankRdBursts::10 278 # Per bank write bursts 55system.physmem.perBankRdBursts::11 258 # Per bank write bursts 56system.physmem.perBankRdBursts::12 226 # Per bank write bursts 57system.physmem.perBankRdBursts::13 469 # Per bank write bursts 58system.physmem.perBankRdBursts::14 405 # Per bank write bursts 59system.physmem.perBankRdBursts::15 290 # Per bank write bursts | 53system.physmem.perBankRdBursts::9 282 # Per bank write bursts 54system.physmem.perBankRdBursts::10 235 # Per bank write bursts 55system.physmem.perBankRdBursts::11 262 # Per bank write bursts 56system.physmem.perBankRdBursts::12 222 # Per bank write bursts 57system.physmem.perBankRdBursts::13 508 # Per bank write bursts 58system.physmem.perBankRdBursts::14 392 # Per bank write bursts 59system.physmem.perBankRdBursts::15 281 # Per bank write bursts |
| 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 148587005000 # Total gap between requests | 78system.physmem.totGap 148693969000 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 85system.physmem.readPktSize::6 5483 # Read request sizes (log2) | 85system.physmem.readPktSize::6 5466 # Read request sizes (log2) |
| 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) | 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 93system.physmem.rdQLenPdf::0 4379 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 915 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 165 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see | 93system.physmem.rdQLenPdf::0 4370 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 896 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 174 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see |
| 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 76 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 76 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 189system.physmem.bytesPerActivate::samples 1137 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 307.616535 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 177.186204 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 330.211340 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 456 40.11% 40.11% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 252 22.16% 62.27% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 97 8.53% 70.80% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 50 4.40% 75.20% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 53 4.66% 79.86% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 61 5.36% 85.22% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 21 1.85% 87.07% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 17 1.50% 88.57% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 130 11.43% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 1137 # Bytes accessed per row activation 203system.physmem.totQLat 38062500 # Total ticks spent queuing 204system.physmem.totMemAccLat 140868750 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 27415000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 6941.91 # Average queueing delay per DRAM burst | 189system.physmem.bytesPerActivate::samples 1125 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 309.532444 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 178.678629 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 328.994757 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 454 40.36% 40.36% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 235 20.89% 61.24% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 101 8.98% 70.22% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 52 4.62% 74.84% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 60 5.33% 80.18% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 59 5.24% 85.42% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 19 1.69% 87.11% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 20 1.78% 88.89% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 125 11.11% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 1125 # Bytes accessed per row activation 203system.physmem.totQLat 38946250 # Total ticks spent queuing 204system.physmem.totMemAccLat 141433750 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 27330000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 7125.18 # Average queueing delay per DRAM burst |
| 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 208system.physmem.avgMemAccLat 25691.91 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 2.36 # Average DRAM read bandwidth in MiByte/s | 208system.physmem.avgMemAccLat 25875.18 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 2.35 # Average DRAM read bandwidth in MiByte/s |
| 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 211system.physmem.avgRdBWSys 2.36 # Average system read bandwidth in MiByte/s | 211system.physmem.avgRdBWSys 2.35 # Average system read bandwidth in MiByte/s |
| 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.02 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.02 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 217system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing | 217system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing |
| 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 219system.physmem.readRowHits 4339 # Number of row buffer hits during reads | 219system.physmem.readRowHits 4331 # Number of row buffer hits during reads |
| 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 221system.physmem.readRowHitRate 79.14 # Row buffer hit rate for reads | 221system.physmem.readRowHitRate 79.24 # Row buffer hit rate for reads |
| 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 223system.physmem.avgGap 27099581.43 # Average gap between requests 224system.physmem.pageHitRate 79.14 # Row buffer hit rate, read and write combined 225system.physmem.memoryStateTime::IDLE 141978840750 # Time in different power states 226system.physmem.memoryStateTime::REF 4961580000 # Time in different power states | 223system.physmem.avgGap 27203433.77 # Average gap between requests 224system.physmem.pageHitRate 79.24 # Row buffer hit rate, read and write combined 225system.physmem.memoryStateTime::IDLE 142073657250 # Time in different power states 226system.physmem.memoryStateTime::REF 4964960000 # Time in different power states |
| 227system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 227system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 228system.physmem.memoryStateTime::ACT 1644861750 # Time in different power states | 228system.physmem.memoryStateTime::ACT 1647900000 # Time in different power states |
| 229system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 229system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 230system.membus.throughput 2361659 # Throughput (bytes/s) 231system.membus.trans_dist::ReadReq 3951 # Transaction distribution 232system.membus.trans_dist::ReadResp 3951 # Transaction distribution 233system.membus.trans_dist::UpgradeReq 350 # Transaction distribution 234system.membus.trans_dist::UpgradeResp 350 # Transaction distribution 235system.membus.trans_dist::ReadExReq 1532 # Transaction distribution 236system.membus.trans_dist::ReadExResp 1532 # Transaction distribution 237system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11666 # Packet count per connected master and slave (bytes) 238system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11666 # Packet count per connected master and slave (bytes) 239system.membus.pkt_count::total 11666 # Packet count per connected master and slave (bytes) 240system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 350912 # Cumulative packet size per connected master and slave (bytes) 241system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 350912 # Cumulative packet size per connected master and slave (bytes) 242system.membus.tot_pkt_size::total 350912 # Cumulative packet size per connected master and slave (bytes) 243system.membus.data_through_bus 350912 # Total data (bytes) 244system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 245system.membus.reqLayer0.occupancy 7101000 # Layer occupancy (ticks) | 230system.membus.trans_dist::ReadReq 3933 # Transaction distribution 231system.membus.trans_dist::ReadResp 3932 # Transaction distribution 232system.membus.trans_dist::UpgradeReq 296 # Transaction distribution 233system.membus.trans_dist::UpgradeResp 296 # Transaction distribution 234system.membus.trans_dist::ReadExReq 1533 # Transaction distribution 235system.membus.trans_dist::ReadExResp 1533 # Transaction distribution 236system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11523 # Packet count per connected master and slave (bytes) 237system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11523 # Packet count per connected master and slave (bytes) 238system.membus.pkt_count::total 11523 # Packet count per connected master and slave (bytes) 239system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 349760 # Cumulative packet size per connected master and slave (bytes) 240system.membus.pkt_size_system.cpu.l2cache.mem_side::total 349760 # Cumulative packet size per connected master and slave (bytes) 241system.membus.pkt_size::total 349760 # Cumulative packet size per connected master and slave (bytes) 242system.membus.snoops 0 # Total snoops (count) 243system.membus.snoop_fanout::samples 5762 # Request fanout histogram 244system.membus.snoop_fanout::mean 0 # Request fanout histogram 245system.membus.snoop_fanout::stdev 0 # Request fanout histogram 246system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 247system.membus.snoop_fanout::0 5762 100.00% 100.00% # Request fanout histogram 248system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 249system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 250system.membus.snoop_fanout::min_value 0 # Request fanout histogram 251system.membus.snoop_fanout::max_value 0 # Request fanout histogram 252system.membus.snoop_fanout::total 5762 # Request fanout histogram 253system.membus.reqLayer0.occupancy 7167000 # Layer occupancy (ticks) |
| 246system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 254system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 247system.membus.respLayer1.occupancy 51987900 # Layer occupancy (ticks) | 255system.membus.respLayer1.occupancy 51861454 # Layer occupancy (ticks) |
| 248system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 249system.cpu_clk_domain.clock 500 # Clock period in ticks | 256system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 257system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 250system.cpu.branchPred.lookups 22396239 # Number of BP lookups 251system.cpu.branchPred.condPredicted 22396239 # Number of conditional branches predicted 252system.cpu.branchPred.condIncorrect 1554538 # Number of conditional branches incorrect 253system.cpu.branchPred.BTBLookups 14104442 # Number of BTB lookups 254system.cpu.branchPred.BTBHits 13258278 # Number of BTB hits | 258system.cpu.branchPred.lookups 22382097 # Number of BP lookups 259system.cpu.branchPred.condPredicted 22382097 # Number of conditional branches predicted 260system.cpu.branchPred.condIncorrect 1553409 # Number of conditional branches incorrect 261system.cpu.branchPred.BTBLookups 14143770 # Number of BTB lookups 262system.cpu.branchPred.BTBHits 13239374 # Number of BTB hits |
| 255system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 263system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 256system.cpu.branchPred.BTBHitPct 94.000727 # BTB Hit Percentage 257system.cpu.branchPred.usedRAS 1524438 # Number of times the RAS was used to get a target. 258system.cpu.branchPred.RASInCorrect 22257 # Number of incorrect RAS predictions. | 264system.cpu.branchPred.BTBHitPct 93.605694 # BTB Hit Percentage 265system.cpu.branchPred.usedRAS 1523861 # Number of times the RAS was used to get a target. 266system.cpu.branchPred.RASInCorrect 22060 # Number of incorrect RAS predictions. |
| 259system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 260system.cpu.workload.num_syscalls 400 # Number of system calls | 267system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 268system.cpu.workload.num_syscalls 400 # Number of system calls |
| 261system.cpu.numCycles 297174180 # number of cpu cycles simulated | 269system.cpu.numCycles 297388032 # number of cpu cycles simulated |
| 262system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 263system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 270system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 271system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 264system.cpu.fetch.icacheStallCycles 27916282 # Number of cycles fetch is stalled on an Icache miss 265system.cpu.fetch.Insts 249227309 # Number of instructions fetch has processed 266system.cpu.fetch.Branches 22396239 # Number of branches that fetch encountered 267system.cpu.fetch.predictedBranches 14782716 # Number of branches that fetch has predicted taken 268system.cpu.fetch.Cycles 267173177 # Number of cycles fetch has run and was not squashing or blocked 269system.cpu.fetch.SquashCycles 3706948 # Number of cycles fetch has spent squashing 270system.cpu.fetch.TlbCycles 35 # Number of cycles fetch has spent waiting for tlb 271system.cpu.fetch.MiscStallCycles 5683 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 272system.cpu.fetch.PendingTrapStallCycles 49787 # Number of stall cycles due to pending traps | 272system.cpu.fetch.icacheStallCycles 27880008 # Number of cycles fetch is stalled on an Icache miss 273system.cpu.fetch.Insts 249058784 # Number of instructions fetch has processed 274system.cpu.fetch.Branches 22382097 # Number of branches that fetch encountered 275system.cpu.fetch.predictedBranches 14763235 # Number of branches that fetch has predicted taken 276system.cpu.fetch.Cycles 267434691 # Number of cycles fetch has run and was not squashing or blocked 277system.cpu.fetch.SquashCycles 3695048 # Number of cycles fetch has spent squashing 278system.cpu.fetch.TlbCycles 15 # Number of cycles fetch has spent waiting for tlb 279system.cpu.fetch.MiscStallCycles 4561 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 280system.cpu.fetch.PendingTrapStallCycles 42381 # Number of stall cycles due to pending traps |
| 273system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions | 281system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions |
| 274system.cpu.fetch.IcacheWaitRetryStallCycles 112 # Number of stall cycles due to full MSHR 275system.cpu.fetch.CacheLines 26681234 # Number of cache lines fetched 276system.cpu.fetch.IcacheSquashes 258392 # Number of outstanding Icache misses that were squashed 277system.cpu.fetch.rateDist::samples 296998563 # Number of instructions fetched each cycle (Total) 278system.cpu.fetch.rateDist::mean 1.383031 # Number of instructions fetched each cycle (Total) 279system.cpu.fetch.rateDist::stdev 2.791258 # Number of instructions fetched each cycle (Total) | 282system.cpu.fetch.IcacheWaitRetryStallCycles 113 # Number of stall cycles due to full MSHR 283system.cpu.fetch.CacheLines 26649696 # Number of cache lines fetched 284system.cpu.fetch.IcacheSquashes 257275 # Number of outstanding Icache misses that were squashed 285system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed 286system.cpu.fetch.rateDist::samples 297209306 # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::mean 1.380725 # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::stdev 2.789359 # Number of instructions fetched each cycle (Total) |
| 280system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 289system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 281system.cpu.fetch.rateDist::0 228914394 77.08% 77.08% # Number of instructions fetched each cycle (Total) 282system.cpu.fetch.rateDist::1 5078121 1.71% 78.79% # Number of instructions fetched each cycle (Total) 283system.cpu.fetch.rateDist::2 4142401 1.39% 80.18% # Number of instructions fetched each cycle (Total) 284system.cpu.fetch.rateDist::3 4790312 1.61% 81.79% # Number of instructions fetched each cycle (Total) 285system.cpu.fetch.rateDist::4 4897925 1.65% 83.44% # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::5 5093198 1.71% 85.16% # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::6 5344969 1.80% 86.96% # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::7 4001055 1.35% 88.30% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::8 34736188 11.70% 100.00% # Number of instructions fetched each cycle (Total) | 290system.cpu.fetch.rateDist::0 229177022 77.11% 77.11% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::1 5084587 1.71% 78.82% # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::2 4138437 1.39% 80.21% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::3 4791887 1.61% 81.83% # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.rateDist::4 4876855 1.64% 83.47% # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.rateDist::5 5109175 1.72% 85.19% # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::6 5334492 1.79% 86.98% # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::7 4008000 1.35% 88.33% # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.rateDist::8 34688851 11.67% 100.00% # Number of instructions fetched each cycle (Total) |
| 290system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 299system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 293system.cpu.fetch.rateDist::total 296998563 # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.branchRate 0.075364 # Number of branch fetches per cycle 295system.cpu.fetch.rate 0.838657 # Number of inst fetches per cycle 296system.cpu.decode.IdleCycles 16354452 # Number of cycles decode is idle 297system.cpu.decode.BlockedCycles 230786837 # Number of cycles decode is blocked 298system.cpu.decode.RunCycles 26168548 # Number of cycles decode is running 299system.cpu.decode.UnblockCycles 21835252 # Number of cycles decode is unblocking 300system.cpu.decode.SquashCycles 1853474 # Number of cycles decode is squashing 301system.cpu.decode.DecodedInsts 359377278 # Number of instructions handled by decode 302system.cpu.rename.SquashCycles 1853474 # Number of cycles rename is squashing 303system.cpu.rename.IdleCycles 24140537 # Number of cycles rename is idle 304system.cpu.rename.BlockCycles 162592213 # Number of cycles rename is blocking 305system.cpu.rename.serializeStallCycles 34818 # count of cycles rename stalled for serializing inst 306system.cpu.rename.RunCycles 38296584 # Number of cycles rename is running 307system.cpu.rename.UnblockCycles 70080937 # Number of cycles rename is unblocking 308system.cpu.rename.RenamedInsts 350637562 # Number of instructions processed by rename 309system.cpu.rename.ROBFullEvents 41127 # Number of times rename has blocked due to ROB full 310system.cpu.rename.IQFullEvents 61846506 # Number of times rename has blocked due to IQ full 311system.cpu.rename.LQFullEvents 7943239 # Number of times rename has blocked due to LQ full 312system.cpu.rename.SQFullEvents 152837 # Number of times rename has blocked due to SQ full 313system.cpu.rename.RenamedOperands 405833434 # Number of destination operands rename has renamed 314system.cpu.rename.RenameLookups 972943751 # Number of register rename lookups that rename has made 315system.cpu.rename.int_rename_lookups 642292546 # Number of integer rename lookups 316system.cpu.rename.fp_rename_lookups 4668888 # Number of floating rename lookups | 302system.cpu.fetch.rateDist::total 297209306 # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.branchRate 0.075262 # Number of branch fetches per cycle 304system.cpu.fetch.rate 0.837488 # Number of inst fetches per cycle 305system.cpu.decode.IdleCycles 16317003 # Number of cycles decode is idle 306system.cpu.decode.BlockedCycles 231094890 # Number of cycles decode is blocked 307system.cpu.decode.RunCycles 26094955 # Number of cycles decode is running 308system.cpu.decode.UnblockCycles 21854934 # Number of cycles decode is unblocking 309system.cpu.decode.SquashCycles 1847524 # Number of cycles decode is squashing 310system.cpu.decode.DecodedInsts 359064274 # Number of instructions handled by decode 311system.cpu.rename.SquashCycles 1847524 # Number of cycles rename is squashing 312system.cpu.rename.IdleCycles 24114798 # Number of cycles rename is idle 313system.cpu.rename.BlockCycles 162761005 # Number of cycles rename is blocking 314system.cpu.rename.serializeStallCycles 33475 # count of cycles rename stalled for serializing inst 315system.cpu.rename.RunCycles 38241804 # Number of cycles rename is running 316system.cpu.rename.UnblockCycles 70210700 # Number of cycles rename is unblocking 317system.cpu.rename.RenamedInsts 350324590 # Number of instructions processed by rename 318system.cpu.rename.ROBFullEvents 42142 # Number of times rename has blocked due to ROB full 319system.cpu.rename.IQFullEvents 61992199 # Number of times rename has blocked due to IQ full 320system.cpu.rename.LQFullEvents 7946895 # Number of times rename has blocked due to LQ full 321system.cpu.rename.SQFullEvents 152925 # Number of times rename has blocked due to SQ full 322system.cpu.rename.RenamedOperands 405428411 # Number of destination operands rename has renamed 323system.cpu.rename.RenameLookups 972465740 # Number of register rename lookups that rename has made 324system.cpu.rename.int_rename_lookups 641794462 # Number of integer rename lookups 325system.cpu.rename.fp_rename_lookups 4665474 # Number of floating rename lookups |
| 317system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed | 326system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed |
| 318system.cpu.rename.UndoneMaps 146403984 # Number of HB maps that are undone due to squashing 319system.cpu.rename.serializingInsts 2369 # count of serializing insts renamed 320system.cpu.rename.tempSerializingInsts 2300 # count of temporary serializing insts renamed 321system.cpu.rename.skidInsts 128426201 # count of insts added to the skid buffer 322system.cpu.memDep0.insertedLoads 89689525 # Number of loads inserted to the mem dependence unit. 323system.cpu.memDep0.insertedStores 32027647 # Number of stores inserted to the mem dependence unit. 324system.cpu.memDep0.conflictingLoads 63947531 # Number of conflicting loads. 325system.cpu.memDep0.conflictingStores 21534219 # Number of conflicting stores. 326system.cpu.iq.iqInstsAdded 341381240 # Number of instructions added to the IQ (excludes non-spec) 327system.cpu.iq.iqNonSpecInstsAdded 5216 # Number of non-speculative instructions added to the IQ 328system.cpu.iq.iqInstsIssued 266882213 # Number of instructions issued 329system.cpu.iq.iqSquashedInstsIssued 74332 # Number of squashed instructions issued 330system.cpu.iq.iqSquashedInstsExamined 119621882 # Number of squashed instructions iterated over during squash; mainly for profiling 331system.cpu.iq.iqSquashedOperandsExamined 250682367 # Number of squashed operands that are examined and possibly removed from graph 332system.cpu.iq.iqSquashedNonSpecRemoved 3971 # Number of squashed non-spec instructions that were removed 333system.cpu.iq.issued_per_cycle::samples 296998563 # Number of insts issued each cycle 334system.cpu.iq.issued_per_cycle::mean 0.898598 # Number of insts issued each cycle 335system.cpu.iq.issued_per_cycle::stdev 1.365381 # Number of insts issued each cycle | 327system.cpu.rename.UndoneMaps 145998961 # Number of HB maps that are undone due to squashing 328system.cpu.rename.serializingInsts 2154 # count of serializing insts renamed 329system.cpu.rename.tempSerializingInsts 2076 # count of temporary serializing insts renamed 330system.cpu.rename.skidInsts 128653734 # count of insts added to the skid buffer 331system.cpu.memDep0.insertedLoads 89733483 # Number of loads inserted to the mem dependence unit. 332system.cpu.memDep0.insertedStores 32018253 # Number of stores inserted to the mem dependence unit. 333system.cpu.memDep0.conflictingLoads 63985001 # Number of conflicting loads. 334system.cpu.memDep0.conflictingStores 21567740 # Number of conflicting stores. 335system.cpu.iq.iqInstsAdded 341091248 # Number of instructions added to the IQ (excludes non-spec) 336system.cpu.iq.iqNonSpecInstsAdded 4877 # Number of non-speculative instructions added to the IQ 337system.cpu.iq.iqInstsIssued 266696686 # Number of instructions issued 338system.cpu.iq.iqSquashedInstsIssued 73290 # Number of squashed instructions issued 339system.cpu.iq.iqSquashedInstsExamined 119329162 # Number of squashed instructions iterated over during squash; mainly for profiling 340system.cpu.iq.iqSquashedOperandsExamined 250439001 # Number of squashed operands that are examined and possibly removed from graph 341system.cpu.iq.iqSquashedNonSpecRemoved 3632 # Number of squashed non-spec instructions that were removed 342system.cpu.iq.issued_per_cycle::samples 297209306 # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::mean 0.897336 # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::stdev 1.363195 # Number of insts issued each cycle |
| 336system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 345system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 337system.cpu.iq.issued_per_cycle::0 171353571 57.70% 57.70% # Number of insts issued each cycle 338system.cpu.iq.issued_per_cycle::1 54179431 18.24% 75.94% # Number of insts issued each cycle 339system.cpu.iq.issued_per_cycle::2 33564937 11.30% 87.24% # Number of insts issued each cycle 340system.cpu.iq.issued_per_cycle::3 19156299 6.45% 93.69% # Number of insts issued each cycle 341system.cpu.iq.issued_per_cycle::4 10836839 3.65% 97.34% # Number of insts issued each cycle 342system.cpu.iq.issued_per_cycle::5 4376133 1.47% 98.81% # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::6 2240693 0.75% 99.57% # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::7 893448 0.30% 99.87% # Number of insts issued each cycle 345system.cpu.iq.issued_per_cycle::8 397212 0.13% 100.00% # Number of insts issued each cycle | 346system.cpu.iq.issued_per_cycle::0 171484109 57.70% 57.70% # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::1 54269493 18.26% 75.96% # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::2 33638460 11.32% 87.28% # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::3 19147986 6.44% 93.72% # Number of insts issued each cycle 350system.cpu.iq.issued_per_cycle::4 10817239 3.64% 97.36% # Number of insts issued each cycle 351system.cpu.iq.issued_per_cycle::5 4351297 1.46% 98.82% # Number of insts issued each cycle 352system.cpu.iq.issued_per_cycle::6 2217356 0.75% 99.57% # Number of insts issued each cycle 353system.cpu.iq.issued_per_cycle::7 890190 0.30% 99.87% # Number of insts issued each cycle 354system.cpu.iq.issued_per_cycle::8 393176 0.13% 100.00% # Number of insts issued each cycle |
| 346system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 355system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 349system.cpu.iq.issued_per_cycle::total 296998563 # Number of insts issued each cycle | 358system.cpu.iq.issued_per_cycle::total 297209306 # Number of insts issued each cycle |
| 350system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 359system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 351system.cpu.iq.fu_full::IntAlu 240121 7.41% 7.41% # attempts to use FU when none available 352system.cpu.iq.fu_full::IntMult 0 0.00% 7.41% # attempts to use FU when none available 353system.cpu.iq.fu_full::IntDiv 0 0.00% 7.41% # attempts to use FU when none available 354system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.41% # attempts to use FU when none available 355system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.41% # attempts to use FU when none available 356system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.41% # attempts to use FU when none available 357system.cpu.iq.fu_full::FloatMult 0 0.00% 7.41% # attempts to use FU when none available 358system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.41% # attempts to use FU when none available 359system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.41% # attempts to use FU when none available 360system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.41% # attempts to use FU when none available 361system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.41% # attempts to use FU when none available 362system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.41% # attempts to use FU when none available 363system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.41% # attempts to use FU when none available 364system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.41% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.41% # attempts to use FU when none available 366system.cpu.iq.fu_full::SimdMult 0 0.00% 7.41% # attempts to use FU when none available 367system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.41% # attempts to use FU when none available 368system.cpu.iq.fu_full::SimdShift 0 0.00% 7.41% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.41% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.41% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.41% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.41% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.41% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.41% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.41% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.41% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.41% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.41% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.41% # attempts to use FU when none available 380system.cpu.iq.fu_full::MemRead 2588686 79.93% 87.34% # attempts to use FU when none available 381system.cpu.iq.fu_full::MemWrite 410086 12.66% 100.00% # attempts to use FU when none available | 360system.cpu.iq.fu_full::IntAlu 237582 7.35% 7.35% # attempts to use FU when none available 361system.cpu.iq.fu_full::IntMult 0 0.00% 7.35% # attempts to use FU when none available 362system.cpu.iq.fu_full::IntDiv 0 0.00% 7.35% # attempts to use FU when none available 363system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.35% # attempts to use FU when none available 364system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.35% # attempts to use FU when none available 365system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.35% # attempts to use FU when none available 366system.cpu.iq.fu_full::FloatMult 0 0.00% 7.35% # attempts to use FU when none available 367system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.35% # attempts to use FU when none available 368system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.35% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.35% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.35% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.35% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.35% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.35% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.35% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdMult 0 0.00% 7.35% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.35% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdShift 0 0.00% 7.35% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.35% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.35% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.35% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.35% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.35% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.35% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.35% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.35% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.35% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.35% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.35% # attempts to use FU when none available 389system.cpu.iq.fu_full::MemRead 2582537 79.93% 87.28% # attempts to use FU when none available 390system.cpu.iq.fu_full::MemWrite 410926 12.72% 100.00% # attempts to use FU when none available |
| 382system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 383system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 391system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 392system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 384system.cpu.iq.FU_type_0::No_OpClass 1211280 0.45% 0.45% # Type of FU issued 385system.cpu.iq.FU_type_0::IntAlu 167297217 62.69% 63.14% # Type of FU issued 386system.cpu.iq.FU_type_0::IntMult 790659 0.30% 63.44% # Type of FU issued 387system.cpu.iq.FU_type_0::IntDiv 7035808 2.64% 66.07% # Type of FU issued 388system.cpu.iq.FU_type_0::FloatAdd 1214833 0.46% 66.53% # Type of FU issued 389system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.53% # Type of FU issued 390system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.53% # Type of FU issued 391system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.53% # Type of FU issued 392system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.53% # Type of FU issued 393system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.53% # Type of FU issued 394system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.53% # Type of FU issued 395system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.53% # Type of FU issued 396system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.53% # Type of FU issued 397system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.53% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.53% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.53% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.53% # Type of FU issued 401system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.53% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.53% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.53% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.53% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.53% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.53% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.53% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.53% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.53% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.53% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.53% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.53% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.53% # Type of FU issued 414system.cpu.iq.FU_type_0::MemRead 66531787 24.93% 91.46% # Type of FU issued 415system.cpu.iq.FU_type_0::MemWrite 22800629 8.54% 100.00% # Type of FU issued | 393system.cpu.iq.FU_type_0::No_OpClass 1211351 0.45% 0.45% # Type of FU issued 394system.cpu.iq.FU_type_0::IntAlu 167148119 62.67% 63.13% # Type of FU issued 395system.cpu.iq.FU_type_0::IntMult 789126 0.30% 63.42% # Type of FU issued 396system.cpu.iq.FU_type_0::IntDiv 7035938 2.64% 66.06% # Type of FU issued 397system.cpu.iq.FU_type_0::FloatAdd 1214032 0.46% 66.52% # Type of FU issued 398system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.52% # Type of FU issued 399system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.52% # Type of FU issued 400system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.52% # Type of FU issued 401system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.52% # Type of FU issued 402system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.52% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.52% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.52% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.52% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.52% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.52% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.52% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.52% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.52% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.52% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.52% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.52% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.52% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.52% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.52% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.52% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.52% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.52% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.52% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.52% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.52% # Type of FU issued 423system.cpu.iq.FU_type_0::MemRead 66518900 24.94% 91.46% # Type of FU issued 424system.cpu.iq.FU_type_0::MemWrite 22779220 8.54% 100.00% # Type of FU issued |
| 416system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 417system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 425system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 426system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 418system.cpu.iq.FU_type_0::total 266882213 # Type of FU issued 419system.cpu.iq.rate 0.898067 # Inst issue rate 420system.cpu.iq.fu_busy_cnt 3238893 # FU busy when requested 421system.cpu.iq.fu_busy_rate 0.012136 # FU busy rate (busy events/executed inst) 422system.cpu.iq.int_inst_queue_reads 829077263 # Number of integer instruction queue reads 423system.cpu.iq.int_inst_queue_writes 457002634 # Number of integer instruction queue writes 424system.cpu.iq.int_inst_queue_wakeup_accesses 260953197 # Number of integer instruction queue wakeup accesses 425system.cpu.iq.fp_inst_queue_reads 4998951 # Number of floating instruction queue reads 426system.cpu.iq.fp_inst_queue_writes 4330787 # Number of floating instruction queue writes 427system.cpu.iq.fp_inst_queue_wakeup_accesses 2399211 # Number of floating instruction queue wakeup accesses 428system.cpu.iq.int_alu_accesses 266394178 # Number of integer alu accesses 429system.cpu.iq.fp_alu_accesses 2515648 # Number of floating point alu accesses 430system.cpu.iew.lsq.thread0.forwLoads 18924906 # Number of loads that had data forwarded from stores | 427system.cpu.iq.FU_type_0::total 266696686 # Type of FU issued 428system.cpu.iq.rate 0.896797 # Inst issue rate 429system.cpu.iq.fu_busy_cnt 3231045 # FU busy when requested 430system.cpu.iq.fu_busy_rate 0.012115 # FU busy rate (busy events/executed inst) 431system.cpu.iq.int_inst_queue_reads 828907957 # Number of integer instruction queue reads 432system.cpu.iq.int_inst_queue_writes 456425026 # Number of integer instruction queue writes 433system.cpu.iq.int_inst_queue_wakeup_accesses 260744620 # Number of integer instruction queue wakeup accesses 434system.cpu.iq.fp_inst_queue_reads 4999056 # Number of floating instruction queue reads 435system.cpu.iq.fp_inst_queue_writes 4321531 # Number of floating instruction queue writes 436system.cpu.iq.fp_inst_queue_wakeup_accesses 2398079 # Number of floating instruction queue wakeup accesses 437system.cpu.iq.int_alu_accesses 266200144 # Number of integer alu accesses 438system.cpu.iq.fp_alu_accesses 2516236 # Number of floating point alu accesses 439system.cpu.iew.lsq.thread0.forwLoads 18853700 # Number of loads that had data forwarded from stores |
| 431system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 440system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 432system.cpu.iew.lsq.thread0.squashedLoads 33039938 # Number of loads squashed 433system.cpu.iew.lsq.thread0.ignoredResponses 13805 # Number of memory responses ignored because the instruction is squashed 434system.cpu.iew.lsq.thread0.memOrderViolation 330906 # Number of memory ordering violations 435system.cpu.iew.lsq.thread0.squashedStores 11511930 # Number of stores squashed | 441system.cpu.iew.lsq.thread0.squashedLoads 33083896 # Number of loads squashed 442system.cpu.iew.lsq.thread0.ignoredResponses 14048 # Number of memory responses ignored because the instruction is squashed 443system.cpu.iew.lsq.thread0.memOrderViolation 327034 # Number of memory ordering violations 444system.cpu.iew.lsq.thread0.squashedStores 11502536 # Number of stores squashed |
| 436system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 437system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 445system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 446system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 438system.cpu.iew.lsq.thread0.rescheduledLoads 51585 # Number of loads that were rescheduled | 447system.cpu.iew.lsq.thread0.rescheduledLoads 52807 # Number of loads that were rescheduled |
| 439system.cpu.iew.lsq.thread0.cacheBlocked 19 # Number of times an access to memory failed due to the cache being blocked 440system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 448system.cpu.iew.lsq.thread0.cacheBlocked 19 # Number of times an access to memory failed due to the cache being blocked 449system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 441system.cpu.iew.iewSquashCycles 1853474 # Number of cycles IEW is squashing 442system.cpu.iew.iewBlockCycles 126194753 # Number of cycles IEW is blocking 443system.cpu.iew.iewUnblockCycles 5535533 # Number of cycles IEW is unblocking 444system.cpu.iew.iewDispatchedInsts 341386456 # Number of instructions dispatched to IQ 445system.cpu.iew.iewDispSquashedInsts 110817 # Number of squashed instructions skipped by dispatch 446system.cpu.iew.iewDispLoadInsts 89689525 # Number of dispatched load instructions 447system.cpu.iew.iewDispStoreInsts 32027647 # Number of dispatched store instructions 448system.cpu.iew.iewDispNonSpecInsts 2236 # Number of dispatched non-speculative instructions 449system.cpu.iew.iewIQFullEvents 2225894 # Number of times the IQ has become full, causing a stall 450system.cpu.iew.iewLSQFullEvents 376853 # Number of times the LSQ has become full, causing a stall 451system.cpu.iew.memOrderViolationEvents 330906 # Number of memory order violations 452system.cpu.iew.predictedTakenIncorrect 685400 # Number of branches that were predicted taken incorrectly 453system.cpu.iew.predictedNotTakenIncorrect 928719 # Number of branches that were predicted not taken incorrectly 454system.cpu.iew.branchMispredicts 1614119 # Number of branch mispredicts detected at execute 455system.cpu.iew.iewExecutedInsts 264771892 # Number of executed instructions 456system.cpu.iew.iewExecLoadInsts 65665679 # Number of load instructions executed 457system.cpu.iew.iewExecSquashedInsts 2110321 # Number of squashed instructions skipped in execute | 450system.cpu.iew.iewSquashCycles 1847524 # Number of cycles IEW is squashing 451system.cpu.iew.iewBlockCycles 126225383 # Number of cycles IEW is blocking 452system.cpu.iew.iewUnblockCycles 5553775 # Number of cycles IEW is unblocking 453system.cpu.iew.iewDispatchedInsts 341096125 # Number of instructions dispatched to IQ 454system.cpu.iew.iewDispSquashedInsts 111900 # Number of squashed instructions skipped by dispatch 455system.cpu.iew.iewDispLoadInsts 89733483 # Number of dispatched load instructions 456system.cpu.iew.iewDispStoreInsts 32018253 # Number of dispatched store instructions 457system.cpu.iew.iewDispNonSpecInsts 2073 # Number of dispatched non-speculative instructions 458system.cpu.iew.iewIQFullEvents 2221761 # Number of times the IQ has become full, causing a stall 459system.cpu.iew.iewLSQFullEvents 397558 # Number of times the LSQ has become full, causing a stall 460system.cpu.iew.memOrderViolationEvents 327034 # Number of memory order violations 461system.cpu.iew.predictedTakenIncorrect 687554 # Number of branches that were predicted taken incorrectly 462system.cpu.iew.predictedNotTakenIncorrect 924641 # Number of branches that were predicted not taken incorrectly 463system.cpu.iew.branchMispredicts 1612195 # Number of branch mispredicts detected at execute 464system.cpu.iew.iewExecutedInsts 264577830 # Number of executed instructions 465system.cpu.iew.iewExecLoadInsts 65651803 # Number of load instructions executed 466system.cpu.iew.iewExecSquashedInsts 2118856 # Number of squashed instructions skipped in execute |
| 458system.cpu.iew.exec_swp 0 # number of swp insts executed 459system.cpu.iew.exec_nop 0 # number of nop insts executed | 467system.cpu.iew.exec_swp 0 # number of swp insts executed 468system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 460system.cpu.iew.exec_refs 88263450 # number of memory reference insts executed 461system.cpu.iew.exec_branches 14588563 # Number of branches executed 462system.cpu.iew.exec_stores 22597771 # Number of stores executed 463system.cpu.iew.exec_rate 0.890965 # Inst execution rate 464system.cpu.iew.wb_sent 264070010 # cumulative count of insts sent to commit 465system.cpu.iew.wb_count 263352408 # cumulative count of insts written-back 466system.cpu.iew.wb_producers 208938306 # num instructions producing a value 467system.cpu.iew.wb_consumers 376948521 # num instructions consuming a value | 469system.cpu.iew.exec_refs 88227876 # number of memory reference insts executed 470system.cpu.iew.exec_branches 14574542 # Number of branches executed 471system.cpu.iew.exec_stores 22576073 # Number of stores executed 472system.cpu.iew.exec_rate 0.889672 # Inst execution rate 473system.cpu.iew.wb_sent 263857804 # cumulative count of insts sent to commit 474system.cpu.iew.wb_count 263142699 # cumulative count of insts written-back 475system.cpu.iew.wb_producers 208771445 # num instructions producing a value 476system.cpu.iew.wb_consumers 376756650 # num instructions consuming a value |
| 468system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 477system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 469system.cpu.iew.wb_rate 0.886189 # insts written-back per cycle 470system.cpu.iew.wb_fanout 0.554289 # average fanout of values written-back | 478system.cpu.iew.wb_rate 0.884846 # insts written-back per cycle 479system.cpu.iew.wb_fanout 0.554128 # average fanout of values written-back |
| 471system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 480system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 472system.cpu.commit.commitSquashedInsts 120072652 # The number of squashed insts skipped by commit | 481system.cpu.commit.commitSquashedInsts 119784082 # The number of squashed insts skipped by commit |
| 473system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards | 482system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards |
| 474system.cpu.commit.branchMispredicts 1559859 # The number of times a branch was mispredicted 475system.cpu.commit.committed_per_cycle::samples 280678389 # Number of insts commited each cycle 476system.cpu.commit.committed_per_cycle::mean 0.788673 # Number of insts commited each cycle 477system.cpu.commit.committed_per_cycle::stdev 1.596070 # Number of insts commited each cycle | 483system.cpu.commit.branchMispredicts 1557714 # The number of times a branch was mispredicted 484system.cpu.commit.committed_per_cycle::samples 280934179 # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::mean 0.787955 # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::stdev 1.593006 # Number of insts commited each cycle |
| 478system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 487system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 479system.cpu.commit.committed_per_cycle::0 180909203 64.45% 64.45% # Number of insts commited each cycle 480system.cpu.commit.committed_per_cycle::1 57692004 20.55% 85.01% # Number of insts commited each cycle 481system.cpu.commit.committed_per_cycle::2 14189338 5.06% 90.06% # Number of insts commited each cycle 482system.cpu.commit.committed_per_cycle::3 11904368 4.24% 94.31% # Number of insts commited each cycle 483system.cpu.commit.committed_per_cycle::4 4187159 1.49% 95.80% # Number of insts commited each cycle 484system.cpu.commit.committed_per_cycle::5 2885597 1.03% 96.83% # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::6 913299 0.33% 97.15% # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::7 1056183 0.38% 97.53% # Number of insts commited each cycle 487system.cpu.commit.committed_per_cycle::8 6941238 2.47% 100.00% # Number of insts commited each cycle | 488system.cpu.commit.committed_per_cycle::0 181002456 64.43% 64.43% # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::1 57799506 20.57% 85.00% # Number of insts commited each cycle 490system.cpu.commit.committed_per_cycle::2 14236358 5.07% 90.07% # Number of insts commited each cycle 491system.cpu.commit.committed_per_cycle::3 11930779 4.25% 94.32% # Number of insts commited each cycle 492system.cpu.commit.committed_per_cycle::4 4218902 1.50% 95.82% # Number of insts commited each cycle 493system.cpu.commit.committed_per_cycle::5 2886432 1.03% 96.85% # Number of insts commited each cycle 494system.cpu.commit.committed_per_cycle::6 918195 0.33% 97.17% # Number of insts commited each cycle 495system.cpu.commit.committed_per_cycle::7 1050521 0.37% 97.55% # Number of insts commited each cycle 496system.cpu.commit.committed_per_cycle::8 6891030 2.45% 100.00% # Number of insts commited each cycle |
| 488system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 490system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 497system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 499system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 491system.cpu.commit.committed_per_cycle::total 280678389 # Number of insts commited each cycle | 500system.cpu.commit.committed_per_cycle::total 280934179 # Number of insts commited each cycle |
| 492system.cpu.commit.committedInsts 132071192 # Number of instructions committed 493system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed 494system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 495system.cpu.commit.refs 77165304 # Number of memory references committed 496system.cpu.commit.loads 56649587 # Number of loads committed 497system.cpu.commit.membars 0 # Number of memory barriers committed 498system.cpu.commit.branches 12326938 # Number of branches committed 499system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 529system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction 530system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction 531system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction 532system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction 533system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction 534system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 535system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 536system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction | 501system.cpu.commit.committedInsts 132071192 # Number of instructions committed 502system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed 503system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 504system.cpu.commit.refs 77165304 # Number of memory references committed 505system.cpu.commit.loads 56649587 # Number of loads committed 506system.cpu.commit.membars 0 # Number of memory barriers committed 507system.cpu.commit.branches 12326938 # Number of branches committed 508system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 538system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction 539system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction 540system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction 541system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction 542system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction 543system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 544system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 545system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction |
| 537system.cpu.commit.bw_lim_events 6941238 # number cycles where commit BW limit reached | 546system.cpu.commit.bw_lim_events 6891030 # number cycles where commit BW limit reached |
| 538system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 547system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 539system.cpu.rob.rob_reads 615173187 # The number of ROB reads 540system.cpu.rob.rob_writes 699236981 # The number of ROB writes 541system.cpu.timesIdled 3132 # Number of times that the entire CPU went into an idle state and unscheduled itself 542system.cpu.idleCycles 175617 # Total number of cycles that the CPU has spent unscheduled due to idling | 548system.cpu.rob.rob_reads 615190615 # The number of ROB reads 549system.cpu.rob.rob_writes 698614568 # The number of ROB writes 550system.cpu.timesIdled 3122 # Number of times that the entire CPU went into an idle state and unscheduled itself 551system.cpu.idleCycles 178726 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 543system.cpu.committedInsts 132071192 # Number of Instructions Simulated 544system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated | 552system.cpu.committedInsts 132071192 # Number of Instructions Simulated 553system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated |
| 545system.cpu.cpi 2.250106 # CPI: Cycles Per Instruction 546system.cpu.cpi_total 2.250106 # CPI: Total CPI of All Threads 547system.cpu.ipc 0.444424 # IPC: Instructions Per Cycle 548system.cpu.ipc_total 0.444424 # IPC: Total IPC of All Threads 549system.cpu.int_regfile_reads 456530694 # number of integer regfile reads 550system.cpu.int_regfile_writes 239288826 # number of integer regfile writes 551system.cpu.fp_regfile_reads 3276715 # number of floating regfile reads 552system.cpu.fp_regfile_writes 2059644 # number of floating regfile writes 553system.cpu.cc_regfile_reads 102986535 # number of cc regfile reads 554system.cpu.cc_regfile_writes 60205049 # number of cc regfile writes 555system.cpu.misc_regfile_reads 136896298 # number of misc regfile reads | 554system.cpu.cpi 2.251725 # CPI: Cycles Per Instruction 555system.cpu.cpi_total 2.251725 # CPI: Total CPI of All Threads 556system.cpu.ipc 0.444104 # IPC: Instructions Per Cycle 557system.cpu.ipc_total 0.444104 # IPC: Total IPC of All Threads 558system.cpu.int_regfile_reads 456361988 # number of integer regfile reads 559system.cpu.int_regfile_writes 239113538 # number of integer regfile writes 560system.cpu.fp_regfile_reads 3275482 # number of floating regfile reads 561system.cpu.fp_regfile_writes 2058196 # number of floating regfile writes 562system.cpu.cc_regfile_reads 102983282 # number of cc regfile reads 563system.cpu.cc_regfile_writes 60177632 # number of cc regfile writes 564system.cpu.misc_regfile_reads 136798826 # number of misc regfile reads |
| 556system.cpu.misc_regfile_writes 1689 # number of misc regfile writes | 565system.cpu.misc_regfile_writes 1689 # number of misc regfile writes |
| 557system.cpu.toL2Bus.throughput 4492019 # Throughput (bytes/s) 558system.cpu.toL2Bus.trans_dist::ReadReq 8845 # Transaction distribution 559system.cpu.toL2Bus.trans_dist::ReadResp 8844 # Transaction distribution 560system.cpu.toL2Bus.trans_dist::Writeback 38 # Transaction distribution 561system.cpu.toL2Bus.trans_dist::UpgradeReq 353 # Transaction distribution 562system.cpu.toL2Bus.trans_dist::UpgradeResp 353 # Transaction distribution 563system.cpu.toL2Bus.trans_dist::ReadExReq 1547 # Transaction distribution 564system.cpu.toL2Bus.trans_dist::ReadExResp 1547 # Transaction distribution 565system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16361 # Packet count per connected master and slave (bytes) 566system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4810 # Packet count per connected master and slave (bytes) 567system.cpu.toL2Bus.pkt_count::total 21171 # Packet count per connected master and slave (bytes) 568system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 512128 # Cumulative packet size per connected master and slave (bytes) 569system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 132544 # Cumulative packet size per connected master and slave (bytes) 570system.cpu.toL2Bus.tot_pkt_size::total 644672 # Cumulative packet size per connected master and slave (bytes) 571system.cpu.toL2Bus.data_through_bus 644672 # Total data (bytes) 572system.cpu.toL2Bus.snoop_data_through_bus 22784 # Total snoop data (bytes) 573system.cpu.toL2Bus.reqLayer0.occupancy 5429500 # Layer occupancy (ticks) | 566system.cpu.toL2Bus.trans_dist::ReadReq 8736 # Transaction distribution 567system.cpu.toL2Bus.trans_dist::ReadResp 8734 # Transaction distribution 568system.cpu.toL2Bus.trans_dist::Writeback 10 # Transaction distribution 569system.cpu.toL2Bus.trans_dist::UpgradeReq 299 # Transaction distribution 570system.cpu.toL2Bus.trans_dist::UpgradeResp 299 # Transaction distribution 571system.cpu.toL2Bus.trans_dist::ReadExReq 1538 # Transaction distribution 572system.cpu.toL2Bus.trans_dist::ReadExResp 1538 # Transaction distribution 573system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16221 # Packet count per connected master and slave (bytes) 574system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4632 # Packet count per connected master and slave (bytes) 575system.cpu.toL2Bus.pkt_count::total 20853 # Packet count per connected master and slave (bytes) 576system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 509376 # Cumulative packet size per connected master and slave (bytes) 577system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129408 # Cumulative packet size per connected master and slave (bytes) 578system.cpu.toL2Bus.pkt_size::total 638784 # Cumulative packet size per connected master and slave (bytes) 579system.cpu.toL2Bus.snoops 301 # Total snoops (count) 580system.cpu.toL2Bus.snoop_fanout::samples 10583 # Request fanout histogram 581system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram 582system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 583system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 584system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 585system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 586system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 587system.cpu.toL2Bus.snoop_fanout::3 10583 100.00% 100.00% # Request fanout histogram 588system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 589system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 590system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 591system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 592system.cpu.toL2Bus.snoop_fanout::total 10583 # Request fanout histogram 593system.cpu.toL2Bus.reqLayer0.occupancy 5301999 # Layer occupancy (ticks) |
| 574system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 594system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 575system.cpu.toL2Bus.respLayer0.occupancy 13138750 # Layer occupancy (ticks) | 595system.cpu.toL2Bus.respLayer0.occupancy 12991249 # Layer occupancy (ticks) |
| 576system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 596system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 577system.cpu.toL2Bus.respLayer1.occupancy 3605850 # Layer occupancy (ticks) | 597system.cpu.toL2Bus.respLayer1.occupancy 3546296 # Layer occupancy (ticks) |
| 578system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 598system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 579system.cpu.icache.tags.replacements 6027 # number of replacements 580system.cpu.icache.tags.tagsinuse 1644.648933 # Cycle average of tags in use 581system.cpu.icache.tags.total_refs 26670487 # Total number of references to valid blocks. 582system.cpu.icache.tags.sampled_refs 8006 # Sample count of references to valid blocks. 583system.cpu.icache.tags.avg_refs 3331.312391 # Average number of references to valid blocks. | 599system.cpu.icache.tags.replacements 5983 # number of replacements 600system.cpu.icache.tags.tagsinuse 1649.665059 # Cycle average of tags in use 601system.cpu.icache.tags.total_refs 26639065 # Total number of references to valid blocks. 602system.cpu.icache.tags.sampled_refs 7962 # Sample count of references to valid blocks. 603system.cpu.icache.tags.avg_refs 3345.775559 # Average number of references to valid blocks. |
| 584system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 604system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 585system.cpu.icache.tags.occ_blocks::cpu.inst 1644.648933 # Average occupied blocks per requestor 586system.cpu.icache.tags.occ_percent::cpu.inst 0.803051 # Average percentage of cache occupancy 587system.cpu.icache.tags.occ_percent::total 0.803051 # Average percentage of cache occupancy | 605system.cpu.icache.tags.occ_blocks::cpu.inst 1649.665059 # Average occupied blocks per requestor 606system.cpu.icache.tags.occ_percent::cpu.inst 0.805501 # Average percentage of cache occupancy 607system.cpu.icache.tags.occ_percent::total 0.805501 # Average percentage of cache occupancy |
| 588system.cpu.icache.tags.occ_task_id_blocks::1024 1979 # Occupied blocks per task id | 608system.cpu.icache.tags.occ_task_id_blocks::1024 1979 # Occupied blocks per task id |
| 589system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id 590system.cpu.icache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id 591system.cpu.icache.tags.age_task_id_blocks_1024::2 791 # Occupied blocks per task id 592system.cpu.icache.tags.age_task_id_blocks_1024::3 137 # Occupied blocks per task id 593system.cpu.icache.tags.age_task_id_blocks_1024::4 758 # Occupied blocks per task id | 609system.cpu.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id 610system.cpu.icache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id 611system.cpu.icache.tags.age_task_id_blocks_1024::2 796 # Occupied blocks per task id 612system.cpu.icache.tags.age_task_id_blocks_1024::3 127 # Occupied blocks per task id 613system.cpu.icache.tags.age_task_id_blocks_1024::4 790 # Occupied blocks per task id |
| 594system.cpu.icache.tags.occ_task_id_percent::1024 0.966309 # Percentage of cache occupancy per task id | 614system.cpu.icache.tags.occ_task_id_percent::1024 0.966309 # Percentage of cache occupancy per task id |
| 595system.cpu.icache.tags.tag_accesses 53370822 # Number of tag accesses 596system.cpu.icache.tags.data_accesses 53370822 # Number of data accesses 597system.cpu.icache.ReadReq_hits::cpu.inst 26670487 # number of ReadReq hits 598system.cpu.icache.ReadReq_hits::total 26670487 # number of ReadReq hits 599system.cpu.icache.demand_hits::cpu.inst 26670487 # number of demand (read+write) hits 600system.cpu.icache.demand_hits::total 26670487 # number of demand (read+write) hits 601system.cpu.icache.overall_hits::cpu.inst 26670487 # number of overall hits 602system.cpu.icache.overall_hits::total 26670487 # number of overall hits 603system.cpu.icache.ReadReq_misses::cpu.inst 10745 # number of ReadReq misses 604system.cpu.icache.ReadReq_misses::total 10745 # number of ReadReq misses 605system.cpu.icache.demand_misses::cpu.inst 10745 # number of demand (read+write) misses 606system.cpu.icache.demand_misses::total 10745 # number of demand (read+write) misses 607system.cpu.icache.overall_misses::cpu.inst 10745 # number of overall misses 608system.cpu.icache.overall_misses::total 10745 # number of overall misses 609system.cpu.icache.ReadReq_miss_latency::cpu.inst 397133250 # number of ReadReq miss cycles 610system.cpu.icache.ReadReq_miss_latency::total 397133250 # number of ReadReq miss cycles 611system.cpu.icache.demand_miss_latency::cpu.inst 397133250 # number of demand (read+write) miss cycles 612system.cpu.icache.demand_miss_latency::total 397133250 # number of demand (read+write) miss cycles 613system.cpu.icache.overall_miss_latency::cpu.inst 397133250 # number of overall miss cycles 614system.cpu.icache.overall_miss_latency::total 397133250 # number of overall miss cycles 615system.cpu.icache.ReadReq_accesses::cpu.inst 26681232 # number of ReadReq accesses(hits+misses) 616system.cpu.icache.ReadReq_accesses::total 26681232 # number of ReadReq accesses(hits+misses) 617system.cpu.icache.demand_accesses::cpu.inst 26681232 # number of demand (read+write) accesses 618system.cpu.icache.demand_accesses::total 26681232 # number of demand (read+write) accesses 619system.cpu.icache.overall_accesses::cpu.inst 26681232 # number of overall (read+write) accesses 620system.cpu.icache.overall_accesses::total 26681232 # number of overall (read+write) accesses 621system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000403 # miss rate for ReadReq accesses 622system.cpu.icache.ReadReq_miss_rate::total 0.000403 # miss rate for ReadReq accesses 623system.cpu.icache.demand_miss_rate::cpu.inst 0.000403 # miss rate for demand accesses 624system.cpu.icache.demand_miss_rate::total 0.000403 # miss rate for demand accesses 625system.cpu.icache.overall_miss_rate::cpu.inst 0.000403 # miss rate for overall accesses 626system.cpu.icache.overall_miss_rate::total 0.000403 # miss rate for overall accesses 627system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36959.818520 # average ReadReq miss latency 628system.cpu.icache.ReadReq_avg_miss_latency::total 36959.818520 # average ReadReq miss latency 629system.cpu.icache.demand_avg_miss_latency::cpu.inst 36959.818520 # average overall miss latency 630system.cpu.icache.demand_avg_miss_latency::total 36959.818520 # average overall miss latency 631system.cpu.icache.overall_avg_miss_latency::cpu.inst 36959.818520 # average overall miss latency 632system.cpu.icache.overall_avg_miss_latency::total 36959.818520 # average overall miss latency 633system.cpu.icache.blocked_cycles::no_mshrs 1215 # number of cycles access was blocked | 615system.cpu.icache.tags.tag_accesses 53307648 # Number of tag accesses 616system.cpu.icache.tags.data_accesses 53307648 # Number of data accesses 617system.cpu.icache.ReadReq_hits::cpu.inst 26639065 # number of ReadReq hits 618system.cpu.icache.ReadReq_hits::total 26639065 # number of ReadReq hits 619system.cpu.icache.demand_hits::cpu.inst 26639065 # number of demand (read+write) hits 620system.cpu.icache.demand_hits::total 26639065 # number of demand (read+write) hits 621system.cpu.icache.overall_hits::cpu.inst 26639065 # number of overall hits 622system.cpu.icache.overall_hits::total 26639065 # number of overall hits 623system.cpu.icache.ReadReq_misses::cpu.inst 10629 # number of ReadReq misses 624system.cpu.icache.ReadReq_misses::total 10629 # number of ReadReq misses 625system.cpu.icache.demand_misses::cpu.inst 10629 # number of demand (read+write) misses 626system.cpu.icache.demand_misses::total 10629 # number of demand (read+write) misses 627system.cpu.icache.overall_misses::cpu.inst 10629 # number of overall misses 628system.cpu.icache.overall_misses::total 10629 # number of overall misses 629system.cpu.icache.ReadReq_miss_latency::cpu.inst 394374749 # number of ReadReq miss cycles 630system.cpu.icache.ReadReq_miss_latency::total 394374749 # number of ReadReq miss cycles 631system.cpu.icache.demand_miss_latency::cpu.inst 394374749 # number of demand (read+write) miss cycles 632system.cpu.icache.demand_miss_latency::total 394374749 # number of demand (read+write) miss cycles 633system.cpu.icache.overall_miss_latency::cpu.inst 394374749 # number of overall miss cycles 634system.cpu.icache.overall_miss_latency::total 394374749 # number of overall miss cycles 635system.cpu.icache.ReadReq_accesses::cpu.inst 26649694 # number of ReadReq accesses(hits+misses) 636system.cpu.icache.ReadReq_accesses::total 26649694 # number of ReadReq accesses(hits+misses) 637system.cpu.icache.demand_accesses::cpu.inst 26649694 # number of demand (read+write) accesses 638system.cpu.icache.demand_accesses::total 26649694 # number of demand (read+write) accesses 639system.cpu.icache.overall_accesses::cpu.inst 26649694 # number of overall (read+write) accesses 640system.cpu.icache.overall_accesses::total 26649694 # number of overall (read+write) accesses 641system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000399 # miss rate for ReadReq accesses 642system.cpu.icache.ReadReq_miss_rate::total 0.000399 # miss rate for ReadReq accesses 643system.cpu.icache.demand_miss_rate::cpu.inst 0.000399 # miss rate for demand accesses 644system.cpu.icache.demand_miss_rate::total 0.000399 # miss rate for demand accesses 645system.cpu.icache.overall_miss_rate::cpu.inst 0.000399 # miss rate for overall accesses 646system.cpu.icache.overall_miss_rate::total 0.000399 # miss rate for overall accesses 647system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37103.655000 # average ReadReq miss latency 648system.cpu.icache.ReadReq_avg_miss_latency::total 37103.655000 # average ReadReq miss latency 649system.cpu.icache.demand_avg_miss_latency::cpu.inst 37103.655000 # average overall miss latency 650system.cpu.icache.demand_avg_miss_latency::total 37103.655000 # average overall miss latency 651system.cpu.icache.overall_avg_miss_latency::cpu.inst 37103.655000 # average overall miss latency 652system.cpu.icache.overall_avg_miss_latency::total 37103.655000 # average overall miss latency 653system.cpu.icache.blocked_cycles::no_mshrs 1302 # number of cycles access was blocked |
| 634system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 654system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 635system.cpu.icache.blocked::no_mshrs 29 # number of cycles access was blocked | 655system.cpu.icache.blocked::no_mshrs 30 # number of cycles access was blocked |
| 636system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 656system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 637system.cpu.icache.avg_blocked_cycles::no_mshrs 41.896552 # average number of cycles each access was blocked | 657system.cpu.icache.avg_blocked_cycles::no_mshrs 43.400000 # average number of cycles each access was blocked |
| 638system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 639system.cpu.icache.fast_writes 0 # number of fast writes performed 640system.cpu.icache.cache_copies 0 # number of cache copies performed | 658system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 659system.cpu.icache.fast_writes 0 # number of fast writes performed 660system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 641system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2386 # number of ReadReq MSHR hits 642system.cpu.icache.ReadReq_mshr_hits::total 2386 # number of ReadReq MSHR hits 643system.cpu.icache.demand_mshr_hits::cpu.inst 2386 # number of demand (read+write) MSHR hits 644system.cpu.icache.demand_mshr_hits::total 2386 # number of demand (read+write) MSHR hits 645system.cpu.icache.overall_mshr_hits::cpu.inst 2386 # number of overall MSHR hits 646system.cpu.icache.overall_mshr_hits::total 2386 # number of overall MSHR hits 647system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8359 # number of ReadReq MSHR misses 648system.cpu.icache.ReadReq_mshr_misses::total 8359 # number of ReadReq MSHR misses 649system.cpu.icache.demand_mshr_misses::cpu.inst 8359 # number of demand (read+write) MSHR misses 650system.cpu.icache.demand_mshr_misses::total 8359 # number of demand (read+write) MSHR misses 651system.cpu.icache.overall_mshr_misses::cpu.inst 8359 # number of overall MSHR misses 652system.cpu.icache.overall_mshr_misses::total 8359 # number of overall MSHR misses 653system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 294698250 # number of ReadReq MSHR miss cycles 654system.cpu.icache.ReadReq_mshr_miss_latency::total 294698250 # number of ReadReq MSHR miss cycles 655system.cpu.icache.demand_mshr_miss_latency::cpu.inst 294698250 # number of demand (read+write) MSHR miss cycles 656system.cpu.icache.demand_mshr_miss_latency::total 294698250 # number of demand (read+write) MSHR miss cycles 657system.cpu.icache.overall_mshr_miss_latency::cpu.inst 294698250 # number of overall MSHR miss cycles 658system.cpu.icache.overall_mshr_miss_latency::total 294698250 # number of overall MSHR miss cycles 659system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses 660system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses 661system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses 662system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses 663system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses 664system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses 665system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35255.203972 # average ReadReq mshr miss latency 666system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35255.203972 # average ReadReq mshr miss latency 667system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35255.203972 # average overall mshr miss latency 668system.cpu.icache.demand_avg_mshr_miss_latency::total 35255.203972 # average overall mshr miss latency 669system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35255.203972 # average overall mshr miss latency 670system.cpu.icache.overall_avg_mshr_miss_latency::total 35255.203972 # average overall mshr miss latency | 661system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2367 # number of ReadReq MSHR hits 662system.cpu.icache.ReadReq_mshr_hits::total 2367 # number of ReadReq MSHR hits 663system.cpu.icache.demand_mshr_hits::cpu.inst 2367 # number of demand (read+write) MSHR hits 664system.cpu.icache.demand_mshr_hits::total 2367 # number of demand (read+write) MSHR hits 665system.cpu.icache.overall_mshr_hits::cpu.inst 2367 # number of overall MSHR hits 666system.cpu.icache.overall_mshr_hits::total 2367 # number of overall MSHR hits 667system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8262 # number of ReadReq MSHR misses 668system.cpu.icache.ReadReq_mshr_misses::total 8262 # number of ReadReq MSHR misses 669system.cpu.icache.demand_mshr_misses::cpu.inst 8262 # number of demand (read+write) MSHR misses 670system.cpu.icache.demand_mshr_misses::total 8262 # number of demand (read+write) MSHR misses 671system.cpu.icache.overall_mshr_misses::cpu.inst 8262 # number of overall MSHR misses 672system.cpu.icache.overall_mshr_misses::total 8262 # number of overall MSHR misses 673system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 293853251 # number of ReadReq MSHR miss cycles 674system.cpu.icache.ReadReq_mshr_miss_latency::total 293853251 # number of ReadReq MSHR miss cycles 675system.cpu.icache.demand_mshr_miss_latency::cpu.inst 293853251 # number of demand (read+write) MSHR miss cycles 676system.cpu.icache.demand_mshr_miss_latency::total 293853251 # number of demand (read+write) MSHR miss cycles 677system.cpu.icache.overall_mshr_miss_latency::cpu.inst 293853251 # number of overall MSHR miss cycles 678system.cpu.icache.overall_mshr_miss_latency::total 293853251 # number of overall MSHR miss cycles 679system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000310 # mshr miss rate for ReadReq accesses 680system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000310 # mshr miss rate for ReadReq accesses 681system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000310 # mshr miss rate for demand accesses 682system.cpu.icache.demand_mshr_miss_rate::total 0.000310 # mshr miss rate for demand accesses 683system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000310 # mshr miss rate for overall accesses 684system.cpu.icache.overall_mshr_miss_rate::total 0.000310 # mshr miss rate for overall accesses 685system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35566.842290 # average ReadReq mshr miss latency 686system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35566.842290 # average ReadReq mshr miss latency 687system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35566.842290 # average overall mshr miss latency 688system.cpu.icache.demand_avg_mshr_miss_latency::total 35566.842290 # average overall mshr miss latency 689system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35566.842290 # average overall mshr miss latency 690system.cpu.icache.overall_avg_mshr_miss_latency::total 35566.842290 # average overall mshr miss latency |
| 671system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 672system.cpu.l2cache.tags.replacements 0 # number of replacements | 691system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 692system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 673system.cpu.l2cache.tags.tagsinuse 2642.321417 # Cycle average of tags in use 674system.cpu.l2cache.tags.total_refs 4553 # Total number of references to valid blocks. 675system.cpu.l2cache.tags.sampled_refs 3966 # Sample count of references to valid blocks. 676system.cpu.l2cache.tags.avg_refs 1.148008 # Average number of references to valid blocks. | 693system.cpu.l2cache.tags.tagsinuse 2653.963036 # Cycle average of tags in use 694system.cpu.l2cache.tags.total_refs 4507 # Total number of references to valid blocks. 695system.cpu.l2cache.tags.sampled_refs 3933 # Sample count of references to valid blocks. 696system.cpu.l2cache.tags.avg_refs 1.145945 # Average number of references to valid blocks. |
| 677system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 697system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 678system.cpu.l2cache.tags.occ_blocks::writebacks 1.703258 # Average occupied blocks per requestor 679system.cpu.l2cache.tags.occ_blocks::cpu.inst 2327.129547 # Average occupied blocks per requestor 680system.cpu.l2cache.tags.occ_blocks::cpu.data 313.488612 # Average occupied blocks per requestor 681system.cpu.l2cache.tags.occ_percent::writebacks 0.000052 # Average percentage of cache occupancy 682system.cpu.l2cache.tags.occ_percent::cpu.inst 0.071018 # Average percentage of cache occupancy 683system.cpu.l2cache.tags.occ_percent::cpu.data 0.009567 # Average percentage of cache occupancy 684system.cpu.l2cache.tags.occ_percent::total 0.080637 # Average percentage of cache occupancy 685system.cpu.l2cache.tags.occ_task_id_blocks::1024 3966 # Occupied blocks per task id 686system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 687system.cpu.l2cache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id 688system.cpu.l2cache.tags.age_task_id_blocks_1024::2 899 # Occupied blocks per task id 689system.cpu.l2cache.tags.age_task_id_blocks_1024::3 158 # Occupied blocks per task id 690system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2676 # Occupied blocks per task id 691system.cpu.l2cache.tags.occ_task_id_percent::1024 0.121033 # Percentage of cache occupancy per task id 692system.cpu.l2cache.tags.tag_accesses 88932 # Number of tag accesses 693system.cpu.l2cache.tags.data_accesses 88932 # Number of data accesses 694system.cpu.l2cache.ReadReq_hits::cpu.inst 4479 # number of ReadReq hits 695system.cpu.l2cache.ReadReq_hits::cpu.data 58 # number of ReadReq hits 696system.cpu.l2cache.ReadReq_hits::total 4537 # number of ReadReq hits 697system.cpu.l2cache.Writeback_hits::writebacks 38 # number of Writeback hits 698system.cpu.l2cache.Writeback_hits::total 38 # number of Writeback hits | 698system.cpu.l2cache.tags.occ_blocks::writebacks 1.072767 # Average occupied blocks per requestor 699system.cpu.l2cache.tags.occ_blocks::cpu.inst 2333.691994 # Average occupied blocks per requestor 700system.cpu.l2cache.tags.occ_blocks::cpu.data 319.198275 # Average occupied blocks per requestor 701system.cpu.l2cache.tags.occ_percent::writebacks 0.000033 # Average percentage of cache occupancy 702system.cpu.l2cache.tags.occ_percent::cpu.inst 0.071219 # Average percentage of cache occupancy 703system.cpu.l2cache.tags.occ_percent::cpu.data 0.009741 # Average percentage of cache occupancy 704system.cpu.l2cache.tags.occ_percent::total 0.080993 # Average percentage of cache occupancy 705system.cpu.l2cache.tags.occ_task_id_blocks::1024 3933 # Occupied blocks per task id 706system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 707system.cpu.l2cache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id 708system.cpu.l2cache.tags.age_task_id_blocks_1024::2 904 # Occupied blocks per task id 709system.cpu.l2cache.tags.age_task_id_blocks_1024::3 148 # Occupied blocks per task id 710system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2687 # Occupied blocks per task id 711system.cpu.l2cache.tags.occ_task_id_percent::1024 0.120026 # Percentage of cache occupancy per task id 712system.cpu.l2cache.tags.tag_accesses 87730 # Number of tag accesses 713system.cpu.l2cache.tags.data_accesses 87730 # Number of data accesses 714system.cpu.l2cache.ReadReq_hits::cpu.inst 4461 # number of ReadReq hits 715system.cpu.l2cache.ReadReq_hits::cpu.data 40 # number of ReadReq hits 716system.cpu.l2cache.ReadReq_hits::total 4501 # number of ReadReq hits 717system.cpu.l2cache.Writeback_hits::writebacks 10 # number of Writeback hits 718system.cpu.l2cache.Writeback_hits::total 10 # number of Writeback hits |
| 699system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits 700system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits | 719system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits 720system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits |
| 701system.cpu.l2cache.ReadExReq_hits::cpu.data 15 # number of ReadExReq hits 702system.cpu.l2cache.ReadExReq_hits::total 15 # number of ReadExReq hits 703system.cpu.l2cache.demand_hits::cpu.inst 4479 # number of demand (read+write) hits 704system.cpu.l2cache.demand_hits::cpu.data 73 # number of demand (read+write) hits 705system.cpu.l2cache.demand_hits::total 4552 # number of demand (read+write) hits 706system.cpu.l2cache.overall_hits::cpu.inst 4479 # number of overall hits 707system.cpu.l2cache.overall_hits::cpu.data 73 # number of overall hits 708system.cpu.l2cache.overall_hits::total 4552 # number of overall hits 709system.cpu.l2cache.ReadReq_misses::cpu.inst 3524 # number of ReadReq misses 710system.cpu.l2cache.ReadReq_misses::cpu.data 428 # number of ReadReq misses 711system.cpu.l2cache.ReadReq_misses::total 3952 # number of ReadReq misses 712system.cpu.l2cache.UpgradeReq_misses::cpu.data 350 # number of UpgradeReq misses 713system.cpu.l2cache.UpgradeReq_misses::total 350 # number of UpgradeReq misses 714system.cpu.l2cache.ReadExReq_misses::cpu.data 1532 # number of ReadExReq misses 715system.cpu.l2cache.ReadExReq_misses::total 1532 # number of ReadExReq misses 716system.cpu.l2cache.demand_misses::cpu.inst 3524 # number of demand (read+write) misses 717system.cpu.l2cache.demand_misses::cpu.data 1960 # number of demand (read+write) misses 718system.cpu.l2cache.demand_misses::total 5484 # number of demand (read+write) misses 719system.cpu.l2cache.overall_misses::cpu.inst 3524 # number of overall misses 720system.cpu.l2cache.overall_misses::cpu.data 1960 # number of overall misses 721system.cpu.l2cache.overall_misses::total 5484 # number of overall misses 722system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 241181750 # number of ReadReq miss cycles 723system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32748250 # number of ReadReq miss cycles 724system.cpu.l2cache.ReadReq_miss_latency::total 273930000 # number of ReadReq miss cycles 725system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 103353250 # number of ReadExReq miss cycles 726system.cpu.l2cache.ReadExReq_miss_latency::total 103353250 # number of ReadExReq miss cycles 727system.cpu.l2cache.demand_miss_latency::cpu.inst 241181750 # number of demand (read+write) miss cycles 728system.cpu.l2cache.demand_miss_latency::cpu.data 136101500 # number of demand (read+write) miss cycles 729system.cpu.l2cache.demand_miss_latency::total 377283250 # number of demand (read+write) miss cycles 730system.cpu.l2cache.overall_miss_latency::cpu.inst 241181750 # number of overall miss cycles 731system.cpu.l2cache.overall_miss_latency::cpu.data 136101500 # number of overall miss cycles 732system.cpu.l2cache.overall_miss_latency::total 377283250 # number of overall miss cycles 733system.cpu.l2cache.ReadReq_accesses::cpu.inst 8003 # number of ReadReq accesses(hits+misses) 734system.cpu.l2cache.ReadReq_accesses::cpu.data 486 # number of ReadReq accesses(hits+misses) 735system.cpu.l2cache.ReadReq_accesses::total 8489 # number of ReadReq accesses(hits+misses) 736system.cpu.l2cache.Writeback_accesses::writebacks 38 # number of Writeback accesses(hits+misses) 737system.cpu.l2cache.Writeback_accesses::total 38 # number of Writeback accesses(hits+misses) 738system.cpu.l2cache.UpgradeReq_accesses::cpu.data 353 # number of UpgradeReq accesses(hits+misses) 739system.cpu.l2cache.UpgradeReq_accesses::total 353 # number of UpgradeReq accesses(hits+misses) 740system.cpu.l2cache.ReadExReq_accesses::cpu.data 1547 # number of ReadExReq accesses(hits+misses) 741system.cpu.l2cache.ReadExReq_accesses::total 1547 # number of ReadExReq accesses(hits+misses) 742system.cpu.l2cache.demand_accesses::cpu.inst 8003 # number of demand (read+write) accesses 743system.cpu.l2cache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses 744system.cpu.l2cache.demand_accesses::total 10036 # number of demand (read+write) accesses 745system.cpu.l2cache.overall_accesses::cpu.inst 8003 # number of overall (read+write) accesses 746system.cpu.l2cache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses 747system.cpu.l2cache.overall_accesses::total 10036 # number of overall (read+write) accesses 748system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.440335 # miss rate for ReadReq accesses 749system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.880658 # miss rate for ReadReq accesses 750system.cpu.l2cache.ReadReq_miss_rate::total 0.465544 # miss rate for ReadReq accesses 751system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991501 # miss rate for UpgradeReq accesses 752system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991501 # miss rate for UpgradeReq accesses 753system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.990304 # miss rate for ReadExReq accesses 754system.cpu.l2cache.ReadExReq_miss_rate::total 0.990304 # miss rate for ReadExReq accesses 755system.cpu.l2cache.demand_miss_rate::cpu.inst 0.440335 # miss rate for demand accesses 756system.cpu.l2cache.demand_miss_rate::cpu.data 0.964092 # miss rate for demand accesses 757system.cpu.l2cache.demand_miss_rate::total 0.546433 # miss rate for demand accesses 758system.cpu.l2cache.overall_miss_rate::cpu.inst 0.440335 # miss rate for overall accesses 759system.cpu.l2cache.overall_miss_rate::cpu.data 0.964092 # miss rate for overall accesses 760system.cpu.l2cache.overall_miss_rate::total 0.546433 # miss rate for overall accesses 761system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68439.770148 # average ReadReq miss latency 762system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76514.602804 # average ReadReq miss latency 763system.cpu.l2cache.ReadReq_avg_miss_latency::total 69314.271255 # average ReadReq miss latency 764system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67462.956919 # average ReadExReq miss latency 765system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67462.956919 # average ReadExReq miss latency 766system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68439.770148 # average overall miss latency 767system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69439.540816 # average overall miss latency 768system.cpu.l2cache.demand_avg_miss_latency::total 68797.091539 # average overall miss latency 769system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68439.770148 # average overall miss latency 770system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69439.540816 # average overall miss latency 771system.cpu.l2cache.overall_avg_miss_latency::total 68797.091539 # average overall miss latency | 721system.cpu.l2cache.ReadExReq_hits::cpu.data 5 # number of ReadExReq hits 722system.cpu.l2cache.ReadExReq_hits::total 5 # number of ReadExReq hits 723system.cpu.l2cache.demand_hits::cpu.inst 4461 # number of demand (read+write) hits 724system.cpu.l2cache.demand_hits::cpu.data 45 # number of demand (read+write) hits 725system.cpu.l2cache.demand_hits::total 4506 # number of demand (read+write) hits 726system.cpu.l2cache.overall_hits::cpu.inst 4461 # number of overall hits 727system.cpu.l2cache.overall_hits::cpu.data 45 # number of overall hits 728system.cpu.l2cache.overall_hits::total 4506 # number of overall hits 729system.cpu.l2cache.ReadReq_misses::cpu.inst 3500 # number of ReadReq misses 730system.cpu.l2cache.ReadReq_misses::cpu.data 434 # number of ReadReq misses 731system.cpu.l2cache.ReadReq_misses::total 3934 # number of ReadReq misses 732system.cpu.l2cache.UpgradeReq_misses::cpu.data 296 # number of UpgradeReq misses 733system.cpu.l2cache.UpgradeReq_misses::total 296 # number of UpgradeReq misses 734system.cpu.l2cache.ReadExReq_misses::cpu.data 1533 # number of ReadExReq misses 735system.cpu.l2cache.ReadExReq_misses::total 1533 # number of ReadExReq misses 736system.cpu.l2cache.demand_misses::cpu.inst 3500 # number of demand (read+write) misses 737system.cpu.l2cache.demand_misses::cpu.data 1967 # number of demand (read+write) misses 738system.cpu.l2cache.demand_misses::total 5467 # number of demand (read+write) misses 739system.cpu.l2cache.overall_misses::cpu.inst 3500 # number of overall misses 740system.cpu.l2cache.overall_misses::cpu.data 1967 # number of overall misses 741system.cpu.l2cache.overall_misses::total 5467 # number of overall misses 742system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 240675250 # number of ReadReq miss cycles 743system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32902250 # number of ReadReq miss cycles 744system.cpu.l2cache.ReadReq_miss_latency::total 273577500 # number of ReadReq miss cycles 745system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 103297250 # number of ReadExReq miss cycles 746system.cpu.l2cache.ReadExReq_miss_latency::total 103297250 # number of ReadExReq miss cycles 747system.cpu.l2cache.demand_miss_latency::cpu.inst 240675250 # number of demand (read+write) miss cycles 748system.cpu.l2cache.demand_miss_latency::cpu.data 136199500 # number of demand (read+write) miss cycles 749system.cpu.l2cache.demand_miss_latency::total 376874750 # number of demand (read+write) miss cycles 750system.cpu.l2cache.overall_miss_latency::cpu.inst 240675250 # number of overall miss cycles 751system.cpu.l2cache.overall_miss_latency::cpu.data 136199500 # number of overall miss cycles 752system.cpu.l2cache.overall_miss_latency::total 376874750 # number of overall miss cycles 753system.cpu.l2cache.ReadReq_accesses::cpu.inst 7961 # number of ReadReq accesses(hits+misses) 754system.cpu.l2cache.ReadReq_accesses::cpu.data 474 # number of ReadReq accesses(hits+misses) 755system.cpu.l2cache.ReadReq_accesses::total 8435 # number of ReadReq accesses(hits+misses) 756system.cpu.l2cache.Writeback_accesses::writebacks 10 # number of Writeback accesses(hits+misses) 757system.cpu.l2cache.Writeback_accesses::total 10 # number of Writeback accesses(hits+misses) 758system.cpu.l2cache.UpgradeReq_accesses::cpu.data 299 # number of UpgradeReq accesses(hits+misses) 759system.cpu.l2cache.UpgradeReq_accesses::total 299 # number of UpgradeReq accesses(hits+misses) 760system.cpu.l2cache.ReadExReq_accesses::cpu.data 1538 # number of ReadExReq accesses(hits+misses) 761system.cpu.l2cache.ReadExReq_accesses::total 1538 # number of ReadExReq accesses(hits+misses) 762system.cpu.l2cache.demand_accesses::cpu.inst 7961 # number of demand (read+write) accesses 763system.cpu.l2cache.demand_accesses::cpu.data 2012 # number of demand (read+write) accesses 764system.cpu.l2cache.demand_accesses::total 9973 # number of demand (read+write) accesses 765system.cpu.l2cache.overall_accesses::cpu.inst 7961 # number of overall (read+write) accesses 766system.cpu.l2cache.overall_accesses::cpu.data 2012 # number of overall (read+write) accesses 767system.cpu.l2cache.overall_accesses::total 9973 # number of overall (read+write) accesses 768system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.439643 # miss rate for ReadReq accesses 769system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.915612 # miss rate for ReadReq accesses 770system.cpu.l2cache.ReadReq_miss_rate::total 0.466390 # miss rate for ReadReq accesses 771system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989967 # miss rate for UpgradeReq accesses 772system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989967 # miss rate for UpgradeReq accesses 773system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996749 # miss rate for ReadExReq accesses 774system.cpu.l2cache.ReadExReq_miss_rate::total 0.996749 # miss rate for ReadExReq accesses 775system.cpu.l2cache.demand_miss_rate::cpu.inst 0.439643 # miss rate for demand accesses 776system.cpu.l2cache.demand_miss_rate::cpu.data 0.977634 # miss rate for demand accesses 777system.cpu.l2cache.demand_miss_rate::total 0.548180 # miss rate for demand accesses 778system.cpu.l2cache.overall_miss_rate::cpu.inst 0.439643 # miss rate for overall accesses 779system.cpu.l2cache.overall_miss_rate::cpu.data 0.977634 # miss rate for overall accesses 780system.cpu.l2cache.overall_miss_rate::total 0.548180 # miss rate for overall accesses 781system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68764.357143 # average ReadReq miss latency 782system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75811.635945 # average ReadReq miss latency 783system.cpu.l2cache.ReadReq_avg_miss_latency::total 69541.814947 # average ReadReq miss latency 784system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67382.420091 # average ReadExReq miss latency 785system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67382.420091 # average ReadExReq miss latency 786system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68764.357143 # average overall miss latency 787system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69242.247077 # average overall miss latency 788system.cpu.l2cache.demand_avg_miss_latency::total 68936.299616 # average overall miss latency 789system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68764.357143 # average overall miss latency 790system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69242.247077 # average overall miss latency 791system.cpu.l2cache.overall_avg_miss_latency::total 68936.299616 # average overall miss latency |
| 772system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 773system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 774system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 775system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 776system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 777system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 778system.cpu.l2cache.fast_writes 0 # number of fast writes performed 779system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 792system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 793system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 794system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 795system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 796system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 797system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 798system.cpu.l2cache.fast_writes 0 # number of fast writes performed 799system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 780system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3524 # number of ReadReq MSHR misses 781system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 428 # number of ReadReq MSHR misses 782system.cpu.l2cache.ReadReq_mshr_misses::total 3952 # number of ReadReq MSHR misses 783system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 350 # number of UpgradeReq MSHR misses 784system.cpu.l2cache.UpgradeReq_mshr_misses::total 350 # number of UpgradeReq MSHR misses 785system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1532 # number of ReadExReq MSHR misses 786system.cpu.l2cache.ReadExReq_mshr_misses::total 1532 # number of ReadExReq MSHR misses 787system.cpu.l2cache.demand_mshr_misses::cpu.inst 3524 # number of demand (read+write) MSHR misses 788system.cpu.l2cache.demand_mshr_misses::cpu.data 1960 # number of demand (read+write) MSHR misses 789system.cpu.l2cache.demand_mshr_misses::total 5484 # number of demand (read+write) MSHR misses 790system.cpu.l2cache.overall_mshr_misses::cpu.inst 3524 # number of overall MSHR misses 791system.cpu.l2cache.overall_mshr_misses::cpu.data 1960 # number of overall MSHR misses 792system.cpu.l2cache.overall_mshr_misses::total 5484 # number of overall MSHR misses 793system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 197010750 # number of ReadReq MSHR miss cycles 794system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27426750 # number of ReadReq MSHR miss cycles 795system.cpu.l2cache.ReadReq_mshr_miss_latency::total 224437500 # number of ReadReq MSHR miss cycles 796system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3500350 # number of UpgradeReq MSHR miss cycles 797system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3500350 # number of UpgradeReq MSHR miss cycles 798system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 84053250 # number of ReadExReq MSHR miss cycles 799system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 84053250 # number of ReadExReq MSHR miss cycles 800system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 197010750 # number of demand (read+write) MSHR miss cycles 801system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 111480000 # number of demand (read+write) MSHR miss cycles 802system.cpu.l2cache.demand_mshr_miss_latency::total 308490750 # number of demand (read+write) MSHR miss cycles 803system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 197010750 # number of overall MSHR miss cycles 804system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 111480000 # number of overall MSHR miss cycles 805system.cpu.l2cache.overall_mshr_miss_latency::total 308490750 # number of overall MSHR miss cycles 806system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.440335 # mshr miss rate for ReadReq accesses 807system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.880658 # mshr miss rate for ReadReq accesses 808system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.465544 # mshr miss rate for ReadReq accesses 809system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991501 # mshr miss rate for UpgradeReq accesses 810system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991501 # mshr miss rate for UpgradeReq accesses 811system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.990304 # mshr miss rate for ReadExReq accesses 812system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.990304 # mshr miss rate for ReadExReq accesses 813system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.440335 # mshr miss rate for demand accesses 814system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964092 # mshr miss rate for demand accesses 815system.cpu.l2cache.demand_mshr_miss_rate::total 0.546433 # mshr miss rate for demand accesses 816system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.440335 # mshr miss rate for overall accesses 817system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964092 # mshr miss rate for overall accesses 818system.cpu.l2cache.overall_mshr_miss_rate::total 0.546433 # mshr miss rate for overall accesses 819system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55905.434166 # average ReadReq mshr miss latency 820system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64081.191589 # average ReadReq mshr miss latency 821system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56790.865385 # average ReadReq mshr miss latency 822system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 823system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 824system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54865.045692 # average ReadExReq mshr miss latency 825system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54865.045692 # average ReadExReq mshr miss latency 826system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55905.434166 # average overall mshr miss latency 827system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56877.551020 # average overall mshr miss latency 828system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56252.871991 # average overall mshr miss latency 829system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55905.434166 # average overall mshr miss latency 830system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56877.551020 # average overall mshr miss latency 831system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56252.871991 # average overall mshr miss latency | 800system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3500 # number of ReadReq MSHR misses 801system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 434 # number of ReadReq MSHR misses 802system.cpu.l2cache.ReadReq_mshr_misses::total 3934 # number of ReadReq MSHR misses 803system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 296 # number of UpgradeReq MSHR misses 804system.cpu.l2cache.UpgradeReq_mshr_misses::total 296 # number of UpgradeReq MSHR misses 805system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1533 # number of ReadExReq MSHR misses 806system.cpu.l2cache.ReadExReq_mshr_misses::total 1533 # number of ReadExReq MSHR misses 807system.cpu.l2cache.demand_mshr_misses::cpu.inst 3500 # number of demand (read+write) MSHR misses 808system.cpu.l2cache.demand_mshr_misses::cpu.data 1967 # number of demand (read+write) MSHR misses 809system.cpu.l2cache.demand_mshr_misses::total 5467 # number of demand (read+write) MSHR misses 810system.cpu.l2cache.overall_mshr_misses::cpu.inst 3500 # number of overall MSHR misses 811system.cpu.l2cache.overall_mshr_misses::cpu.data 1967 # number of overall MSHR misses 812system.cpu.l2cache.overall_mshr_misses::total 5467 # number of overall MSHR misses 813system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 196802250 # number of ReadReq MSHR miss cycles 814system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27518750 # number of ReadReq MSHR miss cycles 815system.cpu.l2cache.ReadReq_mshr_miss_latency::total 224321000 # number of ReadReq MSHR miss cycles 816system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2960795 # number of UpgradeReq MSHR miss cycles 817system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2960795 # number of UpgradeReq MSHR miss cycles 818system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 83847750 # number of ReadExReq MSHR miss cycles 819system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 83847750 # number of ReadExReq MSHR miss cycles 820system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 196802250 # number of demand (read+write) MSHR miss cycles 821system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 111366500 # number of demand (read+write) MSHR miss cycles 822system.cpu.l2cache.demand_mshr_miss_latency::total 308168750 # number of demand (read+write) MSHR miss cycles 823system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 196802250 # number of overall MSHR miss cycles 824system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 111366500 # number of overall MSHR miss cycles 825system.cpu.l2cache.overall_mshr_miss_latency::total 308168750 # number of overall MSHR miss cycles 826system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.439643 # mshr miss rate for ReadReq accesses 827system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.915612 # mshr miss rate for ReadReq accesses 828system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.466390 # mshr miss rate for ReadReq accesses 829system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989967 # mshr miss rate for UpgradeReq accesses 830system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989967 # mshr miss rate for UpgradeReq accesses 831system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996749 # mshr miss rate for ReadExReq accesses 832system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996749 # mshr miss rate for ReadExReq accesses 833system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.439643 # mshr miss rate for demand accesses 834system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.977634 # mshr miss rate for demand accesses 835system.cpu.l2cache.demand_mshr_miss_rate::total 0.548180 # mshr miss rate for demand accesses 836system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.439643 # mshr miss rate for overall accesses 837system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.977634 # mshr miss rate for overall accesses 838system.cpu.l2cache.overall_mshr_miss_rate::total 0.548180 # mshr miss rate for overall accesses 839system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56229.214286 # average ReadReq mshr miss latency 840system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63407.258065 # average ReadReq mshr miss latency 841system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57021.098119 # average ReadReq mshr miss latency 842system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.685811 # average UpgradeReq mshr miss latency 843system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.685811 # average UpgradeReq mshr miss latency 844system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54695.205479 # average ReadExReq mshr miss latency 845system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54695.205479 # average ReadExReq mshr miss latency 846system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56229.214286 # average overall mshr miss latency 847system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56617.437722 # average overall mshr miss latency 848system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56368.895189 # average overall mshr miss latency 849system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56229.214286 # average overall mshr miss latency 850system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56617.437722 # average overall mshr miss latency 851system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56368.895189 # average overall mshr miss latency |
| 832system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 852system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 833system.cpu.dcache.tags.replacements 91 # number of replacements 834system.cpu.dcache.tags.tagsinuse 1449.080763 # Cycle average of tags in use 835system.cpu.dcache.tags.total_refs 67091510 # Total number of references to valid blocks. 836system.cpu.dcache.tags.sampled_refs 2033 # Sample count of references to valid blocks. 837system.cpu.dcache.tags.avg_refs 33001.234629 # Average number of references to valid blocks. | 853system.cpu.dcache.tags.replacements 52 # number of replacements 854system.cpu.dcache.tags.tagsinuse 1451.665096 # Cycle average of tags in use 855system.cpu.dcache.tags.total_refs 67147234 # Total number of references to valid blocks. 856system.cpu.dcache.tags.sampled_refs 2012 # Sample count of references to valid blocks. 857system.cpu.dcache.tags.avg_refs 33373.376740 # Average number of references to valid blocks. |
| 838system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 858system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 839system.cpu.dcache.tags.occ_blocks::cpu.data 1449.080763 # Average occupied blocks per requestor 840system.cpu.dcache.tags.occ_percent::cpu.data 0.353779 # Average percentage of cache occupancy 841system.cpu.dcache.tags.occ_percent::total 0.353779 # Average percentage of cache occupancy 842system.cpu.dcache.tags.occ_task_id_blocks::1024 1942 # Occupied blocks per task id 843system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id 844system.cpu.dcache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id 845system.cpu.dcache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id 846system.cpu.dcache.tags.age_task_id_blocks_1024::3 432 # Occupied blocks per task id 847system.cpu.dcache.tags.age_task_id_blocks_1024::4 1397 # Occupied blocks per task id 848system.cpu.dcache.tags.occ_task_id_percent::1024 0.474121 # Percentage of cache occupancy per task id 849system.cpu.dcache.tags.tag_accesses 134190055 # Number of tag accesses 850system.cpu.dcache.tags.data_accesses 134190055 # Number of data accesses 851system.cpu.dcache.ReadReq_hits::cpu.data 46577118 # number of ReadReq hits 852system.cpu.dcache.ReadReq_hits::total 46577118 # number of ReadReq hits 853system.cpu.dcache.WriteReq_hits::cpu.data 20513830 # number of WriteReq hits 854system.cpu.dcache.WriteReq_hits::total 20513830 # number of WriteReq hits 855system.cpu.dcache.demand_hits::cpu.data 67090948 # number of demand (read+write) hits 856system.cpu.dcache.demand_hits::total 67090948 # number of demand (read+write) hits 857system.cpu.dcache.overall_hits::cpu.data 67090948 # number of overall hits 858system.cpu.dcache.overall_hits::total 67090948 # number of overall hits 859system.cpu.dcache.ReadReq_misses::cpu.data 1162 # number of ReadReq misses 860system.cpu.dcache.ReadReq_misses::total 1162 # number of ReadReq misses 861system.cpu.dcache.WriteReq_misses::cpu.data 1901 # number of WriteReq misses 862system.cpu.dcache.WriteReq_misses::total 1901 # number of WriteReq misses 863system.cpu.dcache.demand_misses::cpu.data 3063 # number of demand (read+write) misses 864system.cpu.dcache.demand_misses::total 3063 # number of demand (read+write) misses 865system.cpu.dcache.overall_misses::cpu.data 3063 # number of overall misses 866system.cpu.dcache.overall_misses::total 3063 # number of overall misses 867system.cpu.dcache.ReadReq_miss_latency::cpu.data 64753959 # number of ReadReq miss cycles 868system.cpu.dcache.ReadReq_miss_latency::total 64753959 # number of ReadReq miss cycles 869system.cpu.dcache.WriteReq_miss_latency::cpu.data 117721350 # number of WriteReq miss cycles 870system.cpu.dcache.WriteReq_miss_latency::total 117721350 # number of WriteReq miss cycles 871system.cpu.dcache.demand_miss_latency::cpu.data 182475309 # number of demand (read+write) miss cycles 872system.cpu.dcache.demand_miss_latency::total 182475309 # number of demand (read+write) miss cycles 873system.cpu.dcache.overall_miss_latency::cpu.data 182475309 # number of overall miss cycles 874system.cpu.dcache.overall_miss_latency::total 182475309 # number of overall miss cycles 875system.cpu.dcache.ReadReq_accesses::cpu.data 46578280 # number of ReadReq accesses(hits+misses) 876system.cpu.dcache.ReadReq_accesses::total 46578280 # number of ReadReq accesses(hits+misses) | 859system.cpu.dcache.tags.occ_blocks::cpu.data 1451.665096 # Average occupied blocks per requestor 860system.cpu.dcache.tags.occ_percent::cpu.data 0.354410 # Average percentage of cache occupancy 861system.cpu.dcache.tags.occ_percent::total 0.354410 # Average percentage of cache occupancy 862system.cpu.dcache.tags.occ_task_id_blocks::1024 1960 # Occupied blocks per task id 863system.cpu.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 864system.cpu.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 865system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id 866system.cpu.dcache.tags.age_task_id_blocks_1024::3 434 # Occupied blocks per task id 867system.cpu.dcache.tags.age_task_id_blocks_1024::4 1416 # Occupied blocks per task id 868system.cpu.dcache.tags.occ_task_id_percent::1024 0.478516 # Percentage of cache occupancy per task id 869system.cpu.dcache.tags.tag_accesses 134301424 # Number of tag accesses 870system.cpu.dcache.tags.data_accesses 134301424 # Number of data accesses 871system.cpu.dcache.ReadReq_hits::cpu.data 46632911 # number of ReadReq hits 872system.cpu.dcache.ReadReq_hits::total 46632911 # number of ReadReq hits 873system.cpu.dcache.WriteReq_hits::cpu.data 20513893 # number of WriteReq hits 874system.cpu.dcache.WriteReq_hits::total 20513893 # number of WriteReq hits 875system.cpu.dcache.demand_hits::cpu.data 67146804 # number of demand (read+write) hits 876system.cpu.dcache.demand_hits::total 67146804 # number of demand (read+write) hits 877system.cpu.dcache.overall_hits::cpu.data 67146804 # number of overall hits 878system.cpu.dcache.overall_hits::total 67146804 # number of overall hits 879system.cpu.dcache.ReadReq_misses::cpu.data 1064 # number of ReadReq misses 880system.cpu.dcache.ReadReq_misses::total 1064 # number of ReadReq misses 881system.cpu.dcache.WriteReq_misses::cpu.data 1838 # number of WriteReq misses 882system.cpu.dcache.WriteReq_misses::total 1838 # number of WriteReq misses 883system.cpu.dcache.demand_misses::cpu.data 2902 # number of demand (read+write) misses 884system.cpu.dcache.demand_misses::total 2902 # number of demand (read+write) misses 885system.cpu.dcache.overall_misses::cpu.data 2902 # number of overall misses 886system.cpu.dcache.overall_misses::total 2902 # number of overall misses 887system.cpu.dcache.ReadReq_miss_latency::cpu.data 63689380 # number of ReadReq miss cycles 888system.cpu.dcache.ReadReq_miss_latency::total 63689380 # number of ReadReq miss cycles 889system.cpu.dcache.WriteReq_miss_latency::cpu.data 116173296 # number of WriteReq miss cycles 890system.cpu.dcache.WriteReq_miss_latency::total 116173296 # number of WriteReq miss cycles 891system.cpu.dcache.demand_miss_latency::cpu.data 179862676 # number of demand (read+write) miss cycles 892system.cpu.dcache.demand_miss_latency::total 179862676 # number of demand (read+write) miss cycles 893system.cpu.dcache.overall_miss_latency::cpu.data 179862676 # number of overall miss cycles 894system.cpu.dcache.overall_miss_latency::total 179862676 # number of overall miss cycles 895system.cpu.dcache.ReadReq_accesses::cpu.data 46633975 # number of ReadReq accesses(hits+misses) 896system.cpu.dcache.ReadReq_accesses::total 46633975 # number of ReadReq accesses(hits+misses) |
| 877system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) 878system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) | 897system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) 898system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) |
| 879system.cpu.dcache.demand_accesses::cpu.data 67094011 # number of demand (read+write) accesses 880system.cpu.dcache.demand_accesses::total 67094011 # number of demand (read+write) accesses 881system.cpu.dcache.overall_accesses::cpu.data 67094011 # number of overall (read+write) accesses 882system.cpu.dcache.overall_accesses::total 67094011 # number of overall (read+write) accesses 883system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses 884system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses 885system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000093 # miss rate for WriteReq accesses 886system.cpu.dcache.WriteReq_miss_rate::total 0.000093 # miss rate for WriteReq accesses 887system.cpu.dcache.demand_miss_rate::cpu.data 0.000046 # miss rate for demand accesses 888system.cpu.dcache.demand_miss_rate::total 0.000046 # miss rate for demand accesses 889system.cpu.dcache.overall_miss_rate::cpu.data 0.000046 # miss rate for overall accesses 890system.cpu.dcache.overall_miss_rate::total 0.000046 # miss rate for overall accesses 891system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55726.298623 # average ReadReq miss latency 892system.cpu.dcache.ReadReq_avg_miss_latency::total 55726.298623 # average ReadReq miss latency 893system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61926.012625 # average WriteReq miss latency 894system.cpu.dcache.WriteReq_avg_miss_latency::total 61926.012625 # average WriteReq miss latency 895system.cpu.dcache.demand_avg_miss_latency::cpu.data 59574.047992 # average overall miss latency 896system.cpu.dcache.demand_avg_miss_latency::total 59574.047992 # average overall miss latency 897system.cpu.dcache.overall_avg_miss_latency::cpu.data 59574.047992 # average overall miss latency 898system.cpu.dcache.overall_avg_miss_latency::total 59574.047992 # average overall miss latency | 899system.cpu.dcache.demand_accesses::cpu.data 67149706 # number of demand (read+write) accesses 900system.cpu.dcache.demand_accesses::total 67149706 # number of demand (read+write) accesses 901system.cpu.dcache.overall_accesses::cpu.data 67149706 # number of overall (read+write) accesses 902system.cpu.dcache.overall_accesses::total 67149706 # number of overall (read+write) accesses 903system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses 904system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses 905system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000090 # miss rate for WriteReq accesses 906system.cpu.dcache.WriteReq_miss_rate::total 0.000090 # miss rate for WriteReq accesses 907system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses 908system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses 909system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses 910system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses 911system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59858.439850 # average ReadReq miss latency 912system.cpu.dcache.ReadReq_avg_miss_latency::total 59858.439850 # average ReadReq miss latency 913system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63206.363439 # average WriteReq miss latency 914system.cpu.dcache.WriteReq_avg_miss_latency::total 63206.363439 # average WriteReq miss latency 915system.cpu.dcache.demand_avg_miss_latency::cpu.data 61978.868367 # average overall miss latency 916system.cpu.dcache.demand_avg_miss_latency::total 61978.868367 # average overall miss latency 917system.cpu.dcache.overall_avg_miss_latency::cpu.data 61978.868367 # average overall miss latency 918system.cpu.dcache.overall_avg_miss_latency::total 61978.868367 # average overall miss latency |
| 899system.cpu.dcache.blocked_cycles::no_mshrs 303 # number of cycles access was blocked 900system.cpu.dcache.blocked_cycles::no_targets 50 # number of cycles access was blocked 901system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked 902system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked 903system.cpu.dcache.avg_blocked_cycles::no_mshrs 60.600000 # average number of cycles each access was blocked 904system.cpu.dcache.avg_blocked_cycles::no_targets 50 # average number of cycles each access was blocked 905system.cpu.dcache.fast_writes 0 # number of fast writes performed 906system.cpu.dcache.cache_copies 0 # number of cache copies performed | 919system.cpu.dcache.blocked_cycles::no_mshrs 303 # number of cycles access was blocked 920system.cpu.dcache.blocked_cycles::no_targets 50 # number of cycles access was blocked 921system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked 922system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked 923system.cpu.dcache.avg_blocked_cycles::no_mshrs 60.600000 # average number of cycles each access was blocked 924system.cpu.dcache.avg_blocked_cycles::no_targets 50 # average number of cycles each access was blocked 925system.cpu.dcache.fast_writes 0 # number of fast writes performed 926system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 907system.cpu.dcache.writebacks::writebacks 38 # number of writebacks 908system.cpu.dcache.writebacks::total 38 # number of writebacks 909system.cpu.dcache.ReadReq_mshr_hits::cpu.data 676 # number of ReadReq MSHR hits 910system.cpu.dcache.ReadReq_mshr_hits::total 676 # number of ReadReq MSHR hits | 927system.cpu.dcache.writebacks::writebacks 10 # number of writebacks 928system.cpu.dcache.writebacks::total 10 # number of writebacks 929system.cpu.dcache.ReadReq_mshr_hits::cpu.data 590 # number of ReadReq MSHR hits 930system.cpu.dcache.ReadReq_mshr_hits::total 590 # number of ReadReq MSHR hits |
| 911system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits 912system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits | 931system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits 932system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits |
| 913system.cpu.dcache.demand_mshr_hits::cpu.data 677 # number of demand (read+write) MSHR hits 914system.cpu.dcache.demand_mshr_hits::total 677 # number of demand (read+write) MSHR hits 915system.cpu.dcache.overall_mshr_hits::cpu.data 677 # number of overall MSHR hits 916system.cpu.dcache.overall_mshr_hits::total 677 # number of overall MSHR hits 917system.cpu.dcache.ReadReq_mshr_misses::cpu.data 486 # number of ReadReq MSHR misses 918system.cpu.dcache.ReadReq_mshr_misses::total 486 # number of ReadReq MSHR misses 919system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1900 # number of WriteReq MSHR misses 920system.cpu.dcache.WriteReq_mshr_misses::total 1900 # number of WriteReq MSHR misses 921system.cpu.dcache.demand_mshr_misses::cpu.data 2386 # number of demand (read+write) MSHR misses 922system.cpu.dcache.demand_mshr_misses::total 2386 # number of demand (read+write) MSHR misses 923system.cpu.dcache.overall_mshr_misses::cpu.data 2386 # number of overall MSHR misses 924system.cpu.dcache.overall_mshr_misses::total 2386 # number of overall MSHR misses 925system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33826250 # number of ReadReq MSHR miss cycles 926system.cpu.dcache.ReadReq_mshr_miss_latency::total 33826250 # number of ReadReq MSHR miss cycles 927system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 113234400 # number of WriteReq MSHR miss cycles 928system.cpu.dcache.WriteReq_mshr_miss_latency::total 113234400 # number of WriteReq MSHR miss cycles 929system.cpu.dcache.demand_mshr_miss_latency::cpu.data 147060650 # number of demand (read+write) MSHR miss cycles 930system.cpu.dcache.demand_mshr_miss_latency::total 147060650 # number of demand (read+write) MSHR miss cycles 931system.cpu.dcache.overall_mshr_miss_latency::cpu.data 147060650 # number of overall MSHR miss cycles 932system.cpu.dcache.overall_mshr_miss_latency::total 147060650 # number of overall MSHR miss cycles | 933system.cpu.dcache.demand_mshr_hits::cpu.data 591 # number of demand (read+write) MSHR hits 934system.cpu.dcache.demand_mshr_hits::total 591 # number of demand (read+write) MSHR hits 935system.cpu.dcache.overall_mshr_hits::cpu.data 591 # number of overall MSHR hits 936system.cpu.dcache.overall_mshr_hits::total 591 # number of overall MSHR hits 937system.cpu.dcache.ReadReq_mshr_misses::cpu.data 474 # number of ReadReq MSHR misses 938system.cpu.dcache.ReadReq_mshr_misses::total 474 # number of ReadReq MSHR misses 939system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1837 # number of WriteReq MSHR misses 940system.cpu.dcache.WriteReq_mshr_misses::total 1837 # number of WriteReq MSHR misses 941system.cpu.dcache.demand_mshr_misses::cpu.data 2311 # number of demand (read+write) MSHR misses 942system.cpu.dcache.demand_mshr_misses::total 2311 # number of demand (read+write) MSHR misses 943system.cpu.dcache.overall_mshr_misses::cpu.data 2311 # number of overall MSHR misses 944system.cpu.dcache.overall_mshr_misses::total 2311 # number of overall MSHR misses 945system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33789250 # number of ReadReq MSHR miss cycles 946system.cpu.dcache.ReadReq_mshr_miss_latency::total 33789250 # number of ReadReq MSHR miss cycles 947system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 111812454 # number of WriteReq MSHR miss cycles 948system.cpu.dcache.WriteReq_mshr_miss_latency::total 111812454 # number of WriteReq MSHR miss cycles 949system.cpu.dcache.demand_mshr_miss_latency::cpu.data 145601704 # number of demand (read+write) MSHR miss cycles 950system.cpu.dcache.demand_mshr_miss_latency::total 145601704 # number of demand (read+write) MSHR miss cycles 951system.cpu.dcache.overall_mshr_miss_latency::cpu.data 145601704 # number of overall MSHR miss cycles 952system.cpu.dcache.overall_mshr_miss_latency::total 145601704 # number of overall MSHR miss cycles |
| 933system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses 934system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses | 953system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses 954system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses |
| 935system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000093 # mshr miss rate for WriteReq accesses 936system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000093 # mshr miss rate for WriteReq accesses 937system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000036 # mshr miss rate for demand accesses 938system.cpu.dcache.demand_mshr_miss_rate::total 0.000036 # mshr miss rate for demand accesses 939system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000036 # mshr miss rate for overall accesses 940system.cpu.dcache.overall_mshr_miss_rate::total 0.000036 # mshr miss rate for overall accesses 941system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69601.337449 # average ReadReq mshr miss latency 942system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69601.337449 # average ReadReq mshr miss latency 943system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59597.052632 # average WriteReq mshr miss latency 944system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59597.052632 # average WriteReq mshr miss latency 945system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61634.807209 # average overall mshr miss latency 946system.cpu.dcache.demand_avg_mshr_miss_latency::total 61634.807209 # average overall mshr miss latency 947system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61634.807209 # average overall mshr miss latency 948system.cpu.dcache.overall_avg_mshr_miss_latency::total 61634.807209 # average overall mshr miss latency | 955system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000090 # mshr miss rate for WriteReq accesses 956system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000090 # mshr miss rate for WriteReq accesses 957system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for demand accesses 958system.cpu.dcache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses 959system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for overall accesses 960system.cpu.dcache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses 961system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71285.337553 # average ReadReq mshr miss latency 962system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71285.337553 # average ReadReq mshr miss latency 963system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60866.877518 # average WriteReq mshr miss latency 964system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60866.877518 # average WriteReq mshr miss latency 965system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63003.766335 # average overall mshr miss latency 966system.cpu.dcache.demand_avg_mshr_miss_latency::total 63003.766335 # average overall mshr miss latency 967system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63003.766335 # average overall mshr miss latency 968system.cpu.dcache.overall_avg_mshr_miss_latency::total 63003.766335 # average overall mshr miss latency |
| 949system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 950 951---------- End Simulation Statistics ---------- | 969system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 970 971---------- End Simulation Statistics ---------- |