| stats.txt (10230:a2bb75a474fd) | stats.txt (10242:cb4e86c17767) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.144620 # Number of seconds simulated 4sim_ticks 144620050000 # Number of ticks simulated 5final_tick 144620050000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.145783 # Number of seconds simulated 4sim_ticks 145782984000 # Number of ticks simulated 5final_tick 145782984000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 65513 # Simulator instruction rate (inst/s) 8host_op_rate 109805 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 71737347 # Simulator tick rate (ticks/s) 10host_mem_usage 319696 # Number of bytes of host memory used 11host_seconds 2015.97 # Real time elapsed on the host | 7host_inst_rate 75578 # Simulator instruction rate (inst/s) 8host_op_rate 126676 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 83424852 # Simulator tick rate (ticks/s) 10host_mem_usage 276072 # Number of bytes of host memory used 11host_seconds 1747.48 # Real time elapsed on the host |
| 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221363384 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221363384 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 217216 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 125440 # Number of bytes read from this memory 18system.physmem.bytes_read::total 342656 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 217216 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 217216 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 3394 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1960 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 5354 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1501977 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 867376 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 2369353 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1501977 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1501977 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1501977 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 867376 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 2369353 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 5356 # Number of read requests accepted | 16system.physmem.bytes_read::cpu.inst 219712 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 125824 # Number of bytes read from this memory 18system.physmem.bytes_read::total 345536 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 219712 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 219712 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 3433 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1966 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 5399 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1507117 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 863091 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 2370208 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1507117 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1507117 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1507117 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 863091 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 2370208 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 5399 # Number of read requests accepted |
| 33system.physmem.writeReqs 0 # Number of write requests accepted | 33system.physmem.writeReqs 0 # Number of write requests accepted |
| 34system.physmem.readBursts 5356 # Number of DRAM read bursts, including those serviced by the write queue | 34system.physmem.readBursts 5399 # Number of DRAM read bursts, including those serviced by the write queue |
| 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 36system.physmem.bytesReadDRAM 342784 # Total number of bytes read from DRAM | 36system.physmem.bytesReadDRAM 345536 # Total number of bytes read from DRAM |
| 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 39system.physmem.bytesReadSys 342784 # Total read bytes from the system interface side | 39system.physmem.bytesReadSys 345536 # Total read bytes from the system interface side |
| 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one | 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| 43system.physmem.neitherReadNorWriteReqs 131 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 288 # Per bank write bursts 45system.physmem.perBankRdBursts::1 358 # Per bank write bursts 46system.physmem.perBankRdBursts::2 449 # Per bank write bursts 47system.physmem.perBankRdBursts::3 356 # Per bank write bursts 48system.physmem.perBankRdBursts::4 330 # Per bank write bursts 49system.physmem.perBankRdBursts::5 328 # Per bank write bursts 50system.physmem.perBankRdBursts::6 400 # Per bank write bursts 51system.physmem.perBankRdBursts::7 378 # Per bank write bursts | 43system.physmem.neitherReadNorWriteReqs 225 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 296 # Per bank write bursts 45system.physmem.perBankRdBursts::1 360 # Per bank write bursts 46system.physmem.perBankRdBursts::2 450 # Per bank write bursts 47system.physmem.perBankRdBursts::3 362 # Per bank write bursts 48system.physmem.perBankRdBursts::4 334 # Per bank write bursts 49system.physmem.perBankRdBursts::5 327 # Per bank write bursts 50system.physmem.perBankRdBursts::6 402 # Per bank write bursts 51system.physmem.perBankRdBursts::7 379 # Per bank write bursts |
| 52system.physmem.perBankRdBursts::8 340 # Per bank write bursts | 52system.physmem.perBankRdBursts::8 340 # Per bank write bursts |
| 53system.physmem.perBankRdBursts::9 277 # Per bank write bursts 54system.physmem.perBankRdBursts::10 231 # Per bank write bursts 55system.physmem.perBankRdBursts::11 276 # Per bank write bursts 56system.physmem.perBankRdBursts::12 208 # Per bank write bursts 57system.physmem.perBankRdBursts::13 466 # Per bank write bursts 58system.physmem.perBankRdBursts::14 385 # Per bank write bursts 59system.physmem.perBankRdBursts::15 286 # Per bank write bursts | 53system.physmem.perBankRdBursts::9 280 # Per bank write bursts 54system.physmem.perBankRdBursts::10 232 # Per bank write bursts 55system.physmem.perBankRdBursts::11 283 # Per bank write bursts 56system.physmem.perBankRdBursts::12 213 # Per bank write bursts 57system.physmem.perBankRdBursts::13 468 # Per bank write bursts 58system.physmem.perBankRdBursts::14 388 # Per bank write bursts 59system.physmem.perBankRdBursts::15 285 # Per bank write bursts |
| 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 144620007000 # Total gap between requests | 78system.physmem.totGap 145782934000 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 85system.physmem.readPktSize::6 5356 # Read request sizes (log2) | 85system.physmem.readPktSize::6 5399 # Read request sizes (log2) |
| 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) | 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 93system.physmem.rdQLenPdf::0 4298 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 873 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 161 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see | 93system.physmem.rdQLenPdf::0 4350 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 862 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 162 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see |
| 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see --- 74 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see --- 74 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 189system.physmem.bytesPerActivate::samples 1043 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 326.933845 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 193.223116 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 334.208962 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 368 35.28% 35.28% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 248 23.78% 59.06% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 102 9.78% 68.84% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 58 5.56% 74.40% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 42 4.03% 78.43% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 59 5.66% 84.08% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 17 1.63% 85.71% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 23 2.21% 87.92% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 126 12.08% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 1043 # Bytes accessed per row activation 203system.physmem.totQLat 35519000 # Total ticks spent queuing 204system.physmem.totMemAccLat 135944000 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 26780000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 6631.63 # Average queueing delay per DRAM burst | 189system.physmem.bytesPerActivate::samples 1099 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 313.768881 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 183.938334 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 327.481688 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 421 38.31% 38.31% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 241 21.93% 60.24% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 100 9.10% 69.34% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 65 5.91% 75.25% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 56 5.10% 80.35% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 54 4.91% 85.26% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 19 1.73% 86.99% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 20 1.82% 88.81% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 123 11.19% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 1099 # Bytes accessed per row activation 203system.physmem.totQLat 41267750 # Total ticks spent queuing 204system.physmem.totMemAccLat 142499000 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 26995000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 7643.59 # Average queueing delay per DRAM burst |
| 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 208system.physmem.avgMemAccLat 25381.63 # Average memory access latency per DRAM burst | 208system.physmem.avgMemAccLat 26393.59 # Average memory access latency per DRAM burst |
| 209system.physmem.avgRdBW 2.37 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 2.37 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.02 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 209system.physmem.avgRdBW 2.37 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 2.37 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.02 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 217system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing | 217system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing |
| 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 219system.physmem.readRowHits 4304 # Number of row buffer hits during reads | 219system.physmem.readRowHits 4296 # Number of row buffer hits during reads |
| 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 221system.physmem.readRowHitRate 80.36 # Row buffer hit rate for reads | 221system.physmem.readRowHitRate 79.57 # Row buffer hit rate for reads |
| 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 223system.physmem.avgGap 27001494.96 # Average gap between requests 224system.physmem.pageHitRate 80.36 # Row buffer hit rate, read and write combined 225system.physmem.memoryStateTime::IDLE 138334279250 # Time in different power states 226system.physmem.memoryStateTime::REF 4828980000 # Time in different power states | 223system.physmem.avgGap 27001839.97 # Average gap between requests 224system.physmem.pageHitRate 79.57 # Row buffer hit rate, read and write combined 225system.physmem.memoryStateTime::IDLE 139294402000 # Time in different power states 226system.physmem.memoryStateTime::REF 4867980000 # Time in different power states |
| 227system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 227system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 228system.physmem.memoryStateTime::ACT 1451861250 # Time in different power states | 228system.physmem.memoryStateTime::ACT 1619857750 # Time in different power states |
| 229system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 229system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 230system.membus.throughput 2368911 # Throughput (bytes/s) 231system.membus.trans_dist::ReadReq 3823 # Transaction distribution 232system.membus.trans_dist::ReadResp 3820 # Transaction distribution 233system.membus.trans_dist::UpgradeReq 131 # Transaction distribution 234system.membus.trans_dist::UpgradeResp 131 # Transaction distribution 235system.membus.trans_dist::ReadExReq 1533 # Transaction distribution 236system.membus.trans_dist::ReadExResp 1533 # Transaction distribution 237system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10971 # Packet count per connected master and slave (bytes) 238system.membus.pkt_count_system.cpu.l2cache.mem_side::total 10971 # Packet count per connected master and slave (bytes) 239system.membus.pkt_count::total 10971 # Packet count per connected master and slave (bytes) 240system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 342592 # Cumulative packet size per connected master and slave (bytes) 241system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342592 # Cumulative packet size per connected master and slave (bytes) 242system.membus.tot_pkt_size::total 342592 # Cumulative packet size per connected master and slave (bytes) 243system.membus.data_through_bus 342592 # Total data (bytes) | 230system.membus.throughput 2370208 # Throughput (bytes/s) 231system.membus.trans_dist::ReadReq 3862 # Transaction distribution 232system.membus.trans_dist::ReadResp 3862 # Transaction distribution 233system.membus.trans_dist::UpgradeReq 225 # Transaction distribution 234system.membus.trans_dist::UpgradeResp 225 # Transaction distribution 235system.membus.trans_dist::ReadExReq 1537 # Transaction distribution 236system.membus.trans_dist::ReadExResp 1537 # Transaction distribution 237system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11248 # Packet count per connected master and slave (bytes) 238system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11248 # Packet count per connected master and slave (bytes) 239system.membus.pkt_count::total 11248 # Packet count per connected master and slave (bytes) 240system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 345536 # Cumulative packet size per connected master and slave (bytes) 241system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 345536 # Cumulative packet size per connected master and slave (bytes) 242system.membus.tot_pkt_size::total 345536 # Cumulative packet size per connected master and slave (bytes) 243system.membus.data_through_bus 345536 # Total data (bytes) |
| 244system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 244system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 245system.membus.reqLayer0.occupancy 6960500 # Layer occupancy (ticks) | 245system.membus.reqLayer0.occupancy 6776000 # Layer occupancy (ticks) |
| 246system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 246system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 247system.membus.respLayer1.occupancy 50659869 # Layer occupancy (ticks) | 247system.membus.respLayer1.occupancy 50906775 # Layer occupancy (ticks) |
| 248system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 249system.cpu_clk_domain.clock 500 # Clock period in ticks | 248system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 249system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 250system.cpu.branchPred.lookups 18663045 # Number of BP lookups 251system.cpu.branchPred.condPredicted 18663045 # Number of conditional branches predicted 252system.cpu.branchPred.condIncorrect 1489785 # Number of conditional branches incorrect 253system.cpu.branchPred.BTBLookups 11444584 # Number of BTB lookups 254system.cpu.branchPred.BTBHits 10797822 # Number of BTB hits | 250system.cpu.branchPred.lookups 19251245 # Number of BP lookups 251system.cpu.branchPred.condPredicted 19251245 # Number of conditional branches predicted 252system.cpu.branchPred.condIncorrect 1503864 # Number of conditional branches incorrect 253system.cpu.branchPred.BTBLookups 11794147 # Number of BTB lookups 254system.cpu.branchPred.BTBHits 11185323 # Number of BTB hits |
| 255system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 255system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 256system.cpu.branchPred.BTBHitPct 94.348750 # BTB Hit Percentage 257system.cpu.branchPred.usedRAS 1319901 # Number of times the RAS was used to get a target. 258system.cpu.branchPred.RASInCorrect 22895 # Number of incorrect RAS predictions. | 256system.cpu.branchPred.BTBHitPct 94.837914 # BTB Hit Percentage 257system.cpu.branchPred.usedRAS 1363914 # Number of times the RAS was used to get a target. 258system.cpu.branchPred.RASInCorrect 22896 # Number of incorrect RAS predictions. |
| 259system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 260system.cpu.workload.num_syscalls 400 # Number of system calls | 259system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 260system.cpu.workload.num_syscalls 400 # Number of system calls |
| 261system.cpu.numCycles 289523031 # number of cpu cycles simulated | 261system.cpu.numCycles 291881234 # number of cpu cycles simulated |
| 262system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 263system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 262system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 263system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 264system.cpu.fetch.icacheStallCycles 23473938 # Number of cycles fetch is stalled on an Icache miss 265system.cpu.fetch.Insts 206858197 # Number of instructions fetch has processed 266system.cpu.fetch.Branches 18663045 # Number of branches that fetch encountered 267system.cpu.fetch.predictedBranches 12117723 # Number of branches that fetch has predicted taken 268system.cpu.fetch.Cycles 54247835 # Number of cycles fetch has run and was not squashing or blocked 269system.cpu.fetch.SquashCycles 15552938 # Number of cycles fetch has spent squashing 270system.cpu.fetch.BlockedCycles 178336695 # Number of cycles fetch has spent blocked 271system.cpu.fetch.MiscStallCycles 1340 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 272system.cpu.fetch.PendingTrapStallCycles 7706 # Number of stall cycles due to pending traps 273system.cpu.fetch.IcacheWaitRetryStallCycles 24 # Number of stall cycles due to full MSHR 274system.cpu.fetch.CacheLines 22368694 # Number of cache lines fetched 275system.cpu.fetch.IcacheSquashes 223698 # Number of outstanding Icache misses that were squashed 276system.cpu.fetch.rateDist::samples 269869756 # Number of instructions fetched each cycle (Total) 277system.cpu.fetch.rateDist::mean 1.267902 # Number of instructions fetched each cycle (Total) 278system.cpu.fetch.rateDist::stdev 2.756065 # Number of instructions fetched each cycle (Total) | 264system.cpu.fetch.icacheStallCycles 24212208 # Number of cycles fetch is stalled on an Icache miss 265system.cpu.fetch.Insts 214052436 # Number of instructions fetch has processed 266system.cpu.fetch.Branches 19251245 # Number of branches that fetch encountered 267system.cpu.fetch.predictedBranches 12549237 # Number of branches that fetch has predicted taken 268system.cpu.fetch.Cycles 55985392 # Number of cycles fetch has run and was not squashing or blocked 269system.cpu.fetch.SquashCycles 16840264 # Number of cycles fetch has spent squashing 270system.cpu.fetch.BlockedCycles 177008858 # Number of cycles fetch has spent blocked 271system.cpu.fetch.MiscStallCycles 1283 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 272system.cpu.fetch.PendingTrapStallCycles 7024 # Number of stall cycles due to pending traps 273system.cpu.fetch.IcacheWaitRetryStallCycles 65 # Number of stall cycles due to full MSHR 274system.cpu.fetch.CacheLines 23136044 # Number of cache lines fetched 275system.cpu.fetch.IcacheSquashes 282405 # Number of outstanding Icache misses that were squashed 276system.cpu.fetch.rateDist::samples 272277792 # Number of instructions fetched each cycle (Total) 277system.cpu.fetch.rateDist::mean 1.296795 # Number of instructions fetched each cycle (Total) 278system.cpu.fetch.rateDist::stdev 2.780007 # Number of instructions fetched each cycle (Total) |
| 279system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 279system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 280system.cpu.fetch.rateDist::0 217061517 80.43% 80.43% # Number of instructions fetched each cycle (Total) 281system.cpu.fetch.rateDist::1 2847740 1.06% 81.49% # Number of instructions fetched each cycle (Total) 282system.cpu.fetch.rateDist::2 2315002 0.86% 82.35% # Number of instructions fetched each cycle (Total) 283system.cpu.fetch.rateDist::3 2640494 0.98% 83.32% # Number of instructions fetched each cycle (Total) 284system.cpu.fetch.rateDist::4 3217056 1.19% 84.52% # Number of instructions fetched each cycle (Total) 285system.cpu.fetch.rateDist::5 3387561 1.26% 85.77% # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::6 3839682 1.42% 87.19% # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::7 2560696 0.95% 88.14% # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::8 32000008 11.86% 100.00% # Number of instructions fetched each cycle (Total) | 280system.cpu.fetch.rateDist::0 217778926 79.98% 79.98% # Number of instructions fetched each cycle (Total) 281system.cpu.fetch.rateDist::1 2920418 1.07% 81.06% # Number of instructions fetched each cycle (Total) 282system.cpu.fetch.rateDist::2 2383762 0.88% 81.93% # Number of instructions fetched each cycle (Total) 283system.cpu.fetch.rateDist::3 2729411 1.00% 82.93% # Number of instructions fetched each cycle (Total) 284system.cpu.fetch.rateDist::4 3335214 1.22% 84.16% # Number of instructions fetched each cycle (Total) 285system.cpu.fetch.rateDist::5 3498463 1.28% 85.44% # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::6 4001053 1.47% 86.91% # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::7 2671434 0.98% 87.90% # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::8 32959111 12.10% 100.00% # Number of instructions fetched each cycle (Total) |
| 289system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 289system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 292system.cpu.fetch.rateDist::total 269869756 # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.branchRate 0.064461 # Number of branch fetches per cycle 294system.cpu.fetch.rate 0.714479 # Number of inst fetches per cycle 295system.cpu.decode.IdleCycles 36939117 # Number of cycles decode is idle 296system.cpu.decode.BlockedCycles 167279649 # Number of cycles decode is blocked 297system.cpu.decode.RunCycles 41594778 # Number of cycles decode is running 298system.cpu.decode.UnblockCycles 10253994 # Number of cycles decode is unblocking 299system.cpu.decode.SquashCycles 13802218 # Number of cycles decode is squashing 300system.cpu.decode.DecodedInsts 336245393 # Number of instructions handled by decode 301system.cpu.rename.SquashCycles 13802218 # Number of cycles rename is squashing 302system.cpu.rename.IdleCycles 45020160 # Number of cycles rename is idle 303system.cpu.rename.BlockCycles 116775107 # Number of cycles rename is blocking 304system.cpu.rename.serializeStallCycles 31642 # count of cycles rename stalled for serializing inst 305system.cpu.rename.RunCycles 42714880 # Number of cycles rename is running 306system.cpu.rename.UnblockCycles 51525749 # Number of cycles rename is unblocking 307system.cpu.rename.RenamedInsts 329872428 # Number of instructions processed by rename 308system.cpu.rename.ROBFullEvents 11092 # Number of times rename has blocked due to ROB full 309system.cpu.rename.IQFullEvents 26167242 # Number of times rename has blocked due to IQ full 310system.cpu.rename.LSQFullEvents 22759273 # Number of times rename has blocked due to LSQ full 311system.cpu.rename.RenamedOperands 382595093 # Number of destination operands rename has renamed 312system.cpu.rename.RenameLookups 918331708 # Number of register rename lookups that rename has made 313system.cpu.rename.int_rename_lookups 606342575 # Number of integer rename lookups 314system.cpu.rename.fp_rename_lookups 4133173 # Number of floating rename lookups | 292system.cpu.fetch.rateDist::total 272277792 # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.branchRate 0.065956 # Number of branch fetches per cycle 294system.cpu.fetch.rate 0.733355 # Number of inst fetches per cycle 295system.cpu.decode.IdleCycles 35864450 # Number of cycles decode is idle 296system.cpu.decode.BlockedCycles 167881983 # Number of cycles decode is blocked 297system.cpu.decode.RunCycles 44786392 # Number of cycles decode is running 298system.cpu.decode.UnblockCycles 8682005 # Number of cycles decode is unblocking 299system.cpu.decode.SquashCycles 15062962 # Number of cycles decode is squashing 300system.cpu.decode.DecodedInsts 346567500 # Number of instructions handled by decode 301system.cpu.rename.SquashCycles 15062962 # Number of cycles rename is squashing 302system.cpu.rename.IdleCycles 42671339 # Number of cycles rename is idle 303system.cpu.rename.BlockCycles 116778023 # Number of cycles rename is blocking 304system.cpu.rename.serializeStallCycles 37081 # count of cycles rename stalled for serializing inst 305system.cpu.rename.RunCycles 45654825 # Number of cycles rename is running 306system.cpu.rename.UnblockCycles 52073562 # Number of cycles rename is unblocking 307system.cpu.rename.RenamedInsts 340013592 # Number of instructions processed by rename 308system.cpu.rename.ROBFullEvents 22387 # Number of times rename has blocked due to ROB full 309system.cpu.rename.IQFullEvents 45742154 # Number of times rename has blocked due to IQ full 310system.cpu.rename.LQFullEvents 5966467 # Number of times rename has blocked due to LQ full 311system.cpu.rename.SQFullEvents 137065 # Number of times rename has blocked due to SQ full 312system.cpu.rename.RenamedOperands 393960742 # Number of destination operands rename has renamed 313system.cpu.rename.RenameLookups 945391670 # Number of register rename lookups that rename has made 314system.cpu.rename.int_rename_lookups 624205941 # Number of integer rename lookups 315system.cpu.rename.fp_rename_lookups 4453971 # Number of floating rename lookups |
| 315system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed | 316system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed |
| 316system.cpu.rename.UndoneMaps 123165643 # Number of HB maps that are undone due to squashing 317system.cpu.rename.serializingInsts 2073 # count of serializing insts renamed 318system.cpu.rename.tempSerializingInsts 2073 # count of temporary serializing insts renamed 319system.cpu.rename.skidInsts 105277588 # count of insts added to the skid buffer 320system.cpu.memDep0.insertedLoads 84554246 # Number of loads inserted to the mem dependence unit. 321system.cpu.memDep0.insertedStores 30134710 # Number of stores inserted to the mem dependence unit. 322system.cpu.memDep0.conflictingLoads 58533931 # Number of conflicting loads. 323system.cpu.memDep0.conflictingStores 19035455 # Number of conflicting stores. 324system.cpu.iq.iqInstsAdded 322937953 # Number of instructions added to the IQ (excludes non-spec) 325system.cpu.iq.iqNonSpecInstsAdded 4364 # Number of non-speculative instructions added to the IQ 326system.cpu.iq.iqInstsIssued 260608849 # Number of instructions issued 327system.cpu.iq.iqSquashedInstsIssued 112553 # Number of squashed instructions issued 328system.cpu.iq.iqSquashedInstsExamined 101196304 # Number of squashed instructions iterated over during squash; mainly for profiling 329system.cpu.iq.iqSquashedOperandsExamined 210593531 # Number of squashed operands that are examined and possibly removed from graph 330system.cpu.iq.iqSquashedNonSpecRemoved 3119 # Number of squashed non-spec instructions that were removed 331system.cpu.iq.issued_per_cycle::samples 269869756 # Number of insts issued each cycle 332system.cpu.iq.issued_per_cycle::mean 0.965684 # Number of insts issued each cycle 333system.cpu.iq.issued_per_cycle::stdev 1.342187 # Number of insts issued each cycle | 317system.cpu.rename.UndoneMaps 134531292 # Number of HB maps that are undone due to squashing 318system.cpu.rename.serializingInsts 2243 # count of serializing insts renamed 319system.cpu.rename.tempSerializingInsts 2238 # count of temporary serializing insts renamed 320system.cpu.rename.skidInsts 90830827 # count of insts added to the skid buffer 321system.cpu.memDep0.insertedLoads 87006444 # Number of loads inserted to the mem dependence unit. 322system.cpu.memDep0.insertedStores 31074157 # Number of stores inserted to the mem dependence unit. 323system.cpu.memDep0.conflictingLoads 61167406 # Number of conflicting loads. 324system.cpu.memDep0.conflictingStores 20316475 # Number of conflicting stores. 325system.cpu.iq.iqInstsAdded 332092429 # Number of instructions added to the IQ (excludes non-spec) 326system.cpu.iq.iqNonSpecInstsAdded 4572 # Number of non-speculative instructions added to the IQ 327system.cpu.iq.iqInstsIssued 263265541 # Number of instructions issued 328system.cpu.iq.iqSquashedInstsIssued 182587 # Number of squashed instructions issued 329system.cpu.iq.iqSquashedInstsExamined 110344895 # Number of squashed instructions iterated over during squash; mainly for profiling 330system.cpu.iq.iqSquashedOperandsExamined 231927910 # Number of squashed operands that are examined and possibly removed from graph 331system.cpu.iq.iqSquashedNonSpecRemoved 3327 # Number of squashed non-spec instructions that were removed 332system.cpu.iq.issued_per_cycle::samples 272277792 # Number of insts issued each cycle 333system.cpu.iq.issued_per_cycle::mean 0.966901 # Number of insts issued each cycle 334system.cpu.iq.issued_per_cycle::stdev 1.357293 # Number of insts issued each cycle |
| 334system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 335system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 335system.cpu.iq.issued_per_cycle::0 143519297 53.18% 53.18% # Number of insts issued each cycle 336system.cpu.iq.issued_per_cycle::1 55647203 20.62% 73.80% # Number of insts issued each cycle 337system.cpu.iq.issued_per_cycle::2 34229884 12.68% 86.48% # Number of insts issued each cycle 338system.cpu.iq.issued_per_cycle::3 19073202 7.07% 93.55% # Number of insts issued each cycle 339system.cpu.iq.issued_per_cycle::4 10874136 4.03% 97.58% # Number of insts issued each cycle 340system.cpu.iq.issued_per_cycle::5 4113724 1.52% 99.11% # Number of insts issued each cycle 341system.cpu.iq.issued_per_cycle::6 1802263 0.67% 99.77% # Number of insts issued each cycle 342system.cpu.iq.issued_per_cycle::7 476846 0.18% 99.95% # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::8 133201 0.05% 100.00% # Number of insts issued each cycle | 336system.cpu.iq.issued_per_cycle::0 146114169 53.66% 53.66% # Number of insts issued each cycle 337system.cpu.iq.issued_per_cycle::1 54798888 20.13% 73.79% # Number of insts issued each cycle 338system.cpu.iq.issued_per_cycle::2 34241976 12.58% 86.37% # Number of insts issued each cycle 339system.cpu.iq.issued_per_cycle::3 18986540 6.97% 93.34% # Number of insts issued each cycle 340system.cpu.iq.issued_per_cycle::4 11181244 4.11% 97.45% # Number of insts issued each cycle 341system.cpu.iq.issued_per_cycle::5 4283756 1.57% 99.02% # Number of insts issued each cycle 342system.cpu.iq.issued_per_cycle::6 1956251 0.72% 99.74% # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::7 577925 0.21% 99.95% # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::8 137043 0.05% 100.00% # Number of insts issued each cycle |
| 344system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 345system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 345system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 347system.cpu.iq.issued_per_cycle::total 269869756 # Number of insts issued each cycle | 348system.cpu.iq.issued_per_cycle::total 272277792 # Number of insts issued each cycle |
| 348system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 349system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 349system.cpu.iq.fu_full::IntAlu 125646 4.63% 4.63% # attempts to use FU when none available 350system.cpu.iq.fu_full::IntMult 0 0.00% 4.63% # attempts to use FU when none available 351system.cpu.iq.fu_full::IntDiv 0 0.00% 4.63% # attempts to use FU when none available 352system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.63% # attempts to use FU when none available 353system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.63% # attempts to use FU when none available 354system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.63% # attempts to use FU when none available 355system.cpu.iq.fu_full::FloatMult 0 0.00% 4.63% # attempts to use FU when none available 356system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.63% # attempts to use FU when none available 357system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.63% # attempts to use FU when none available 358system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.63% # attempts to use FU when none available 359system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.63% # attempts to use FU when none available 360system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.63% # attempts to use FU when none available 361system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.63% # attempts to use FU when none available 362system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.63% # attempts to use FU when none available 363system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.63% # attempts to use FU when none available 364system.cpu.iq.fu_full::SimdMult 0 0.00% 4.63% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.63% # attempts to use FU when none available 366system.cpu.iq.fu_full::SimdShift 0 0.00% 4.63% # attempts to use FU when none available 367system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.63% # attempts to use FU when none available 368system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.63% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.63% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.63% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.63% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.63% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.63% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.63% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.63% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.63% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.63% # attempts to use FU when none available 378system.cpu.iq.fu_full::MemRead 2288183 84.39% 89.02% # attempts to use FU when none available 379system.cpu.iq.fu_full::MemWrite 297636 10.98% 100.00% # attempts to use FU when none available | 350system.cpu.iq.fu_full::IntAlu 142962 5.08% 5.08% # attempts to use FU when none available 351system.cpu.iq.fu_full::IntMult 0 0.00% 5.08% # attempts to use FU when none available 352system.cpu.iq.fu_full::IntDiv 0 0.00% 5.08% # attempts to use FU when none available 353system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.08% # attempts to use FU when none available 354system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.08% # attempts to use FU when none available 355system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.08% # attempts to use FU when none available 356system.cpu.iq.fu_full::FloatMult 0 0.00% 5.08% # attempts to use FU when none available 357system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.08% # attempts to use FU when none available 358system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.08% # attempts to use FU when none available 359system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.08% # attempts to use FU when none available 360system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.08% # attempts to use FU when none available 361system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.08% # attempts to use FU when none available 362system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.08% # attempts to use FU when none available 363system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.08% # attempts to use FU when none available 364system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.08% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdMult 0 0.00% 5.08% # attempts to use FU when none available 366system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.08% # attempts to use FU when none available 367system.cpu.iq.fu_full::SimdShift 0 0.00% 5.08% # attempts to use FU when none available 368system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.08% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.08% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.08% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.08% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.08% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.08% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.08% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.08% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.08% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.08% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.08% # attempts to use FU when none available 379system.cpu.iq.fu_full::MemRead 2337044 83.10% 88.19% # attempts to use FU when none available 380system.cpu.iq.fu_full::MemWrite 332186 11.81% 100.00% # attempts to use FU when none available |
| 380system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 381system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 381system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 382system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 382system.cpu.iq.FU_type_0::No_OpClass 1210826 0.46% 0.46% # Type of FU issued 383system.cpu.iq.FU_type_0::IntAlu 162119129 62.21% 62.67% # Type of FU issued 384system.cpu.iq.FU_type_0::IntMult 788294 0.30% 62.97% # Type of FU issued 385system.cpu.iq.FU_type_0::IntDiv 7035677 2.70% 65.67% # Type of FU issued 386system.cpu.iq.FU_type_0::FloatAdd 1444684 0.55% 66.23% # Type of FU issued 387system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.23% # Type of FU issued 388system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.23% # Type of FU issued 389system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.23% # Type of FU issued 390system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.23% # Type of FU issued 391system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.23% # Type of FU issued 392system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.23% # Type of FU issued 393system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.23% # Type of FU issued 394system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.23% # Type of FU issued 395system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.23% # Type of FU issued 396system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.23% # Type of FU issued 397system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.23% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.23% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.23% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.23% # Type of FU issued 401system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.23% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.23% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.23% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.23% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.23% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.23% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.23% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.23% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.23% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.23% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.23% # Type of FU issued 412system.cpu.iq.FU_type_0::MemRead 65441941 25.11% 91.34% # Type of FU issued 413system.cpu.iq.FU_type_0::MemWrite 22568298 8.66% 100.00% # Type of FU issued | 383system.cpu.iq.FU_type_0::No_OpClass 1210901 0.46% 0.46% # Type of FU issued 384system.cpu.iq.FU_type_0::IntAlu 164273729 62.40% 62.86% # Type of FU issued 385system.cpu.iq.FU_type_0::IntMult 789732 0.30% 63.16% # Type of FU issued 386system.cpu.iq.FU_type_0::IntDiv 7035869 2.67% 65.83% # Type of FU issued 387system.cpu.iq.FU_type_0::FloatAdd 1461918 0.56% 66.39% # Type of FU issued 388system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.39% # Type of FU issued 389system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.39% # Type of FU issued 390system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.39% # Type of FU issued 391system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.39% # Type of FU issued 392system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.39% # Type of FU issued 393system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.39% # Type of FU issued 394system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.39% # Type of FU issued 395system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.39% # Type of FU issued 396system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.39% # Type of FU issued 397system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.39% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.39% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.39% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.39% # Type of FU issued 401system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.39% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.39% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.39% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.39% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.39% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.39% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.39% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.39% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.39% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.39% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.39% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.39% # Type of FU issued 413system.cpu.iq.FU_type_0::MemRead 65849141 25.01% 91.40% # Type of FU issued 414system.cpu.iq.FU_type_0::MemWrite 22644251 8.60% 100.00% # Type of FU issued |
| 414system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 415system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 415system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 416system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 416system.cpu.iq.FU_type_0::total 260608849 # Type of FU issued 417system.cpu.iq.rate 0.900132 # Inst issue rate 418system.cpu.iq.fu_busy_cnt 2711465 # FU busy when requested 419system.cpu.iq.fu_busy_rate 0.010404 # FU busy rate (busy events/executed inst) 420system.cpu.iq.int_inst_queue_reads 789025856 # Number of integer instruction queue reads 421system.cpu.iq.int_inst_queue_writes 420800342 # Number of integer instruction queue writes 422system.cpu.iq.int_inst_queue_wakeup_accesses 255248449 # Number of integer instruction queue wakeup accesses 423system.cpu.iq.fp_inst_queue_reads 4885616 # Number of floating instruction queue reads 424system.cpu.iq.fp_inst_queue_writes 3622403 # Number of floating instruction queue writes 425system.cpu.iq.fp_inst_queue_wakeup_accesses 2349194 # Number of floating instruction queue wakeup accesses 426system.cpu.iq.int_alu_accesses 259650836 # Number of integer alu accesses 427system.cpu.iq.fp_alu_accesses 2458652 # Number of floating point alu accesses 428system.cpu.iew.lsq.thread0.forwLoads 18874838 # Number of loads that had data forwarded from stores | 417system.cpu.iq.FU_type_0::total 263265541 # Type of FU issued 418system.cpu.iq.rate 0.901961 # Inst issue rate 419system.cpu.iq.fu_busy_cnt 2812192 # FU busy when requested 420system.cpu.iq.fu_busy_rate 0.010682 # FU busy rate (busy events/executed inst) 421system.cpu.iq.int_inst_queue_reads 796857032 # Number of integer instruction queue reads 422system.cpu.iq.int_inst_queue_writes 438700759 # Number of integer instruction queue writes 423system.cpu.iq.int_inst_queue_wakeup_accesses 257701720 # Number of integer instruction queue wakeup accesses 424system.cpu.iq.fp_inst_queue_reads 4946621 # Number of floating instruction queue reads 425system.cpu.iq.fp_inst_queue_writes 4039797 # Number of floating instruction queue writes 426system.cpu.iq.fp_inst_queue_wakeup_accesses 2377852 # Number of floating instruction queue wakeup accesses 427system.cpu.iq.int_alu_accesses 262377827 # Number of integer alu accesses 428system.cpu.iq.fp_alu_accesses 2489005 # Number of floating point alu accesses 429system.cpu.iew.lsq.thread0.forwLoads 18800853 # Number of loads that had data forwarded from stores |
| 429system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 430system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 430system.cpu.iew.lsq.thread0.squashedLoads 27904659 # Number of loads squashed 431system.cpu.iew.lsq.thread0.ignoredResponses 26471 # Number of memory responses ignored because the instruction is squashed 432system.cpu.iew.lsq.thread0.memOrderViolation 289699 # Number of memory ordering violations 433system.cpu.iew.lsq.thread0.squashedStores 9618993 # Number of stores squashed | 431system.cpu.iew.lsq.thread0.squashedLoads 30356857 # Number of loads squashed 432system.cpu.iew.lsq.thread0.ignoredResponses 18134 # Number of memory responses ignored because the instruction is squashed 433system.cpu.iew.lsq.thread0.memOrderViolation 304082 # Number of memory ordering violations 434system.cpu.iew.lsq.thread0.squashedStores 10558440 # Number of stores squashed |
| 434system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 435system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 435system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 436system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 436system.cpu.iew.lsq.thread0.rescheduledLoads 50123 # Number of loads that were rescheduled 437system.cpu.iew.lsq.thread0.cacheBlocked 17 # Number of times an access to memory failed due to the cache being blocked | 437system.cpu.iew.lsq.thread0.rescheduledLoads 49872 # Number of loads that were rescheduled 438system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked |
| 438system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 439system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 439system.cpu.iew.iewSquashCycles 13802218 # Number of cycles IEW is squashing 440system.cpu.iew.iewBlockCycles 85051562 # Number of cycles IEW is blocking 441system.cpu.iew.iewUnblockCycles 5443180 # Number of cycles IEW is unblocking 442system.cpu.iew.iewDispatchedInsts 322942317 # Number of instructions dispatched to IQ 443system.cpu.iew.iewDispSquashedInsts 133815 # Number of squashed instructions skipped by dispatch 444system.cpu.iew.iewDispLoadInsts 84554246 # Number of dispatched load instructions 445system.cpu.iew.iewDispStoreInsts 30134710 # Number of dispatched store instructions 446system.cpu.iew.iewDispNonSpecInsts 2043 # Number of dispatched non-speculative instructions 447system.cpu.iew.iewIQFullEvents 2682047 # Number of times the IQ has become full, causing a stall 448system.cpu.iew.iewLSQFullEvents 14716 # Number of times the LSQ has become full, causing a stall 449system.cpu.iew.memOrderViolationEvents 289699 # Number of memory order violations 450system.cpu.iew.predictedTakenIncorrect 640019 # Number of branches that were predicted taken incorrectly 451system.cpu.iew.predictedNotTakenIncorrect 900364 # Number of branches that were predicted not taken incorrectly 452system.cpu.iew.branchMispredicts 1540383 # Number of branch mispredicts detected at execute 453system.cpu.iew.iewExecutedInsts 258834349 # Number of executed instructions 454system.cpu.iew.iewExecLoadInsts 64663337 # Number of load instructions executed 455system.cpu.iew.iewExecSquashedInsts 1774500 # Number of squashed instructions skipped in execute | 440system.cpu.iew.iewSquashCycles 15062962 # Number of cycles IEW is squashing 441system.cpu.iew.iewBlockCycles 84436601 # Number of cycles IEW is blocking 442system.cpu.iew.iewUnblockCycles 5827541 # Number of cycles IEW is unblocking 443system.cpu.iew.iewDispatchedInsts 332097001 # Number of instructions dispatched to IQ 444system.cpu.iew.iewDispSquashedInsts 93155 # Number of squashed instructions skipped by dispatch 445system.cpu.iew.iewDispLoadInsts 87006444 # Number of dispatched load instructions 446system.cpu.iew.iewDispStoreInsts 31074157 # Number of dispatched store instructions 447system.cpu.iew.iewDispNonSpecInsts 2159 # Number of dispatched non-speculative instructions 448system.cpu.iew.iewIQFullEvents 2868922 # Number of times the IQ has become full, causing a stall 449system.cpu.iew.iewLSQFullEvents 287074 # Number of times the LSQ has become full, causing a stall 450system.cpu.iew.memOrderViolationEvents 304082 # Number of memory order violations 451system.cpu.iew.predictedTakenIncorrect 649398 # Number of branches that were predicted taken incorrectly 452system.cpu.iew.predictedNotTakenIncorrect 907392 # Number of branches that were predicted not taken incorrectly 453system.cpu.iew.branchMispredicts 1556790 # Number of branch mispredicts detected at execute 454system.cpu.iew.iewExecutedInsts 261390422 # Number of executed instructions 455system.cpu.iew.iewExecLoadInsts 65051182 # Number of load instructions executed 456system.cpu.iew.iewExecSquashedInsts 1875119 # Number of squashed instructions skipped in execute |
| 456system.cpu.iew.exec_swp 0 # number of swp insts executed 457system.cpu.iew.exec_nop 0 # number of nop insts executed | 457system.cpu.iew.exec_swp 0 # number of swp insts executed 458system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 458system.cpu.iew.exec_refs 87028906 # number of memory reference insts executed 459system.cpu.iew.exec_branches 14271418 # Number of branches executed 460system.cpu.iew.exec_stores 22365569 # Number of stores executed 461system.cpu.iew.exec_rate 0.894003 # Inst execution rate 462system.cpu.iew.wb_sent 258197839 # cumulative count of insts sent to commit 463system.cpu.iew.wb_count 257597643 # cumulative count of insts written-back 464system.cpu.iew.wb_producers 206027195 # num instructions producing a value 465system.cpu.iew.wb_consumers 369217293 # num instructions consuming a value | 459system.cpu.iew.exec_refs 87491108 # number of memory reference insts executed 460system.cpu.iew.exec_branches 14410736 # Number of branches executed 461system.cpu.iew.exec_stores 22439926 # Number of stores executed 462system.cpu.iew.exec_rate 0.895537 # Inst execution rate 463system.cpu.iew.wb_sent 260730148 # cumulative count of insts sent to commit 464system.cpu.iew.wb_count 260079572 # cumulative count of insts written-back 465system.cpu.iew.wb_producers 208603284 # num instructions producing a value 466system.cpu.iew.wb_consumers 373821854 # num instructions consuming a value |
| 466system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 467system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 467system.cpu.iew.wb_rate 0.889731 # insts written-back per cycle 468system.cpu.iew.wb_fanout 0.558011 # average fanout of values written-back | 468system.cpu.iew.wb_rate 0.891046 # insts written-back per cycle 469system.cpu.iew.wb_fanout 0.558029 # average fanout of values written-back |
| 469system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 470system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 470system.cpu.commit.commitSquashedInsts 101647922 # The number of squashed insts skipped by commit | 471system.cpu.commit.commitSquashedInsts 110904752 # The number of squashed insts skipped by commit |
| 471system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards | 472system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards |
| 472system.cpu.commit.branchMispredicts 1490935 # The number of times a branch was mispredicted 473system.cpu.commit.committed_per_cycle::samples 256067538 # Number of insts commited each cycle 474system.cpu.commit.committed_per_cycle::mean 0.864473 # Number of insts commited each cycle 475system.cpu.commit.committed_per_cycle::stdev 1.651889 # Number of insts commited each cycle | 473system.cpu.commit.branchMispredicts 1504927 # The number of times a branch was mispredicted 474system.cpu.commit.committed_per_cycle::samples 257214830 # Number of insts commited each cycle 475system.cpu.commit.committed_per_cycle::mean 0.860617 # Number of insts commited each cycle 476system.cpu.commit.committed_per_cycle::stdev 1.643182 # Number of insts commited each cycle |
| 476system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 477system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 477system.cpu.commit.committed_per_cycle::0 156617936 61.16% 61.16% # Number of insts commited each cycle 478system.cpu.commit.committed_per_cycle::1 57255270 22.36% 83.52% # Number of insts commited each cycle 479system.cpu.commit.committed_per_cycle::2 14082261 5.50% 89.02% # Number of insts commited each cycle 480system.cpu.commit.committed_per_cycle::3 12088609 4.72% 93.74% # Number of insts commited each cycle 481system.cpu.commit.committed_per_cycle::4 4189643 1.64% 95.38% # Number of insts commited each cycle 482system.cpu.commit.committed_per_cycle::5 2964480 1.16% 96.54% # Number of insts commited each cycle 483system.cpu.commit.committed_per_cycle::6 903129 0.35% 96.89% # Number of insts commited each cycle 484system.cpu.commit.committed_per_cycle::7 1051661 0.41% 97.30% # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::8 6914549 2.70% 100.00% # Number of insts commited each cycle | 478system.cpu.commit.committed_per_cycle::0 157256344 61.14% 61.14% # Number of insts commited each cycle 479system.cpu.commit.committed_per_cycle::1 57715541 22.44% 83.58% # Number of insts commited each cycle 480system.cpu.commit.committed_per_cycle::2 14223073 5.53% 89.11% # Number of insts commited each cycle 481system.cpu.commit.committed_per_cycle::3 12060500 4.69% 93.80% # Number of insts commited each cycle 482system.cpu.commit.committed_per_cycle::4 4224463 1.64% 95.44% # Number of insts commited each cycle 483system.cpu.commit.committed_per_cycle::5 2956145 1.15% 96.59% # Number of insts commited each cycle 484system.cpu.commit.committed_per_cycle::6 920096 0.36% 96.94% # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::7 1048300 0.41% 97.35% # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::8 6810368 2.65% 100.00% # Number of insts commited each cycle |
| 486system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 487system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 488system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 487system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 488system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 489system.cpu.commit.committed_per_cycle::total 256067538 # Number of insts commited each cycle | 490system.cpu.commit.committed_per_cycle::total 257214830 # Number of insts commited each cycle |
| 490system.cpu.commit.committedInsts 132071192 # Number of instructions committed 491system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed 492system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 493system.cpu.commit.refs 77165304 # Number of memory references committed 494system.cpu.commit.loads 56649587 # Number of loads committed 495system.cpu.commit.membars 0 # Number of memory barriers committed 496system.cpu.commit.branches 12326938 # Number of branches committed 497system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 527system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction 528system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction 529system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction 530system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction 531system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction 532system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 533system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 534system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction | 491system.cpu.commit.committedInsts 132071192 # Number of instructions committed 492system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed 493system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 494system.cpu.commit.refs 77165304 # Number of memory references committed 495system.cpu.commit.loads 56649587 # Number of loads committed 496system.cpu.commit.membars 0 # Number of memory barriers committed 497system.cpu.commit.branches 12326938 # Number of branches committed 498system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 528system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction 529system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction 530system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction 531system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction 532system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction 533system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 534system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 535system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction |
| 535system.cpu.commit.bw_lim_events 6914549 # number cycles where commit BW limit reached | 536system.cpu.commit.bw_lim_events 6810368 # number cycles where commit BW limit reached |
| 536system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 537system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 537system.cpu.rob.rob_reads 572164295 # The number of ROB reads 538system.cpu.rob.rob_writes 659850863 # The number of ROB writes 539system.cpu.timesIdled 5930649 # Number of times that the entire CPU went into an idle state and unscheduled itself 540system.cpu.idleCycles 19653275 # Total number of cycles that the CPU has spent unscheduled due to idling | 538system.cpu.rob.rob_reads 582672598 # The number of ROB reads 539system.cpu.rob.rob_writes 679632792 # The number of ROB writes 540system.cpu.timesIdled 5976195 # Number of times that the entire CPU went into an idle state and unscheduled itself 541system.cpu.idleCycles 19603442 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 541system.cpu.committedInsts 132071192 # Number of Instructions Simulated 542system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated | 542system.cpu.committedInsts 132071192 # Number of Instructions Simulated 543system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated |
| 543system.cpu.cpi 2.192174 # CPI: Cycles Per Instruction 544system.cpu.cpi_total 2.192174 # CPI: Total CPI of All Threads 545system.cpu.ipc 0.456168 # IPC: Instructions Per Cycle 546system.cpu.ipc_total 0.456168 # IPC: Total IPC of All Threads 547system.cpu.int_regfile_reads 451375343 # number of integer regfile reads 548system.cpu.int_regfile_writes 234032598 # number of integer regfile writes 549system.cpu.fp_regfile_reads 3213912 # number of floating regfile reads 550system.cpu.fp_regfile_writes 2009037 # number of floating regfile writes 551system.cpu.cc_regfile_reads 102846049 # number of cc regfile reads 552system.cpu.cc_regfile_writes 59805449 # number of cc regfile writes 553system.cpu.misc_regfile_reads 133386978 # number of misc regfile reads | 544system.cpu.cpi 2.210030 # CPI: Cycles Per Instruction 545system.cpu.cpi_total 2.210030 # CPI: Total CPI of All Threads 546system.cpu.ipc 0.452483 # IPC: Instructions Per Cycle 547system.cpu.ipc_total 0.452483 # IPC: Total IPC of All Threads 548system.cpu.int_regfile_reads 453366407 # number of integer regfile reads 549system.cpu.int_regfile_writes 236319036 # number of integer regfile writes 550system.cpu.fp_regfile_reads 3248620 # number of floating regfile reads 551system.cpu.fp_regfile_writes 2037591 # number of floating regfile writes 552system.cpu.cc_regfile_reads 102911292 # number of cc regfile reads 553system.cpu.cc_regfile_writes 59928663 # number of cc regfile writes 554system.cpu.misc_regfile_reads 134914047 # number of misc regfile reads |
| 554system.cpu.misc_regfile_writes 1689 # number of misc regfile writes | 555system.cpu.misc_regfile_writes 1689 # number of misc regfile writes |
| 555system.cpu.toL2Bus.throughput 3852301 # Throughput (bytes/s) 556system.cpu.toL2Bus.trans_dist::ReadReq 7156 # Transaction distribution 557system.cpu.toL2Bus.trans_dist::ReadResp 7153 # Transaction distribution | 556system.cpu.toL2Bus.throughput 4027905 # Throughput (bytes/s) 557system.cpu.toL2Bus.trans_dist::ReadReq 7620 # Transaction distribution 558system.cpu.toL2Bus.trans_dist::ReadResp 7618 # Transaction distribution |
| 558system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution | 559system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution |
| 559system.cpu.toL2Bus.trans_dist::UpgradeReq 132 # Transaction distribution 560system.cpu.toL2Bus.trans_dist::UpgradeResp 132 # Transaction distribution 561system.cpu.toL2Bus.trans_dist::ReadExReq 1539 # Transaction distribution 562system.cpu.toL2Bus.trans_dist::ReadExResp 1539 # Transaction distribution 563system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13245 # Packet count per connected master and slave (bytes) 564system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4286 # Packet count per connected master and slave (bytes) 565system.cpu.toL2Bus.pkt_count::total 17531 # Packet count per connected master and slave (bytes) 566system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 419584 # Cumulative packet size per connected master and slave (bytes) 567system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129024 # Cumulative packet size per connected master and slave (bytes) 568system.cpu.toL2Bus.tot_pkt_size::total 548608 # Cumulative packet size per connected master and slave (bytes) 569system.cpu.toL2Bus.data_through_bus 548608 # Total data (bytes) 570system.cpu.toL2Bus.snoop_data_through_bus 8512 # Total snoop data (bytes) 571system.cpu.toL2Bus.reqLayer0.occupancy 4433000 # Layer occupancy (ticks) | 560system.cpu.toL2Bus.trans_dist::UpgradeReq 226 # Transaction distribution 561system.cpu.toL2Bus.trans_dist::UpgradeResp 226 # Transaction distribution 562system.cpu.toL2Bus.trans_dist::ReadExReq 1544 # Transaction distribution 563system.cpu.toL2Bus.trans_dist::ReadExResp 1544 # Transaction distribution 564system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14075 # Packet count per connected master and slave (bytes) 565system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4490 # Packet count per connected master and slave (bytes) 566system.cpu.toL2Bus.pkt_count::total 18565 # Packet count per connected master and slave (bytes) 567system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 443136 # Cumulative packet size per connected master and slave (bytes) 568system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129600 # Cumulative packet size per connected master and slave (bytes) 569system.cpu.toL2Bus.tot_pkt_size::total 572736 # Cumulative packet size per connected master and slave (bytes) 570system.cpu.toL2Bus.data_through_bus 572736 # Total data (bytes) 571system.cpu.toL2Bus.snoop_data_through_bus 14464 # Total snoop data (bytes) 572system.cpu.toL2Bus.reqLayer0.occupancy 4714500 # Layer occupancy (ticks) |
| 572system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 573system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 573system.cpu.toL2Bus.respLayer0.occupancy 10626750 # Layer occupancy (ticks) | 574system.cpu.toL2Bus.respLayer0.occupancy 11320000 # Layer occupancy (ticks) |
| 574system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 575system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 575system.cpu.toL2Bus.respLayer1.occupancy 3450631 # Layer occupancy (ticks) | 576system.cpu.toL2Bus.respLayer1.occupancy 3508475 # Layer occupancy (ticks) |
| 576system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 577system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 577system.cpu.icache.tags.replacements 4592 # number of replacements 578system.cpu.icache.tags.tagsinuse 1628.049417 # Cycle average of tags in use 579system.cpu.icache.tags.total_refs 22359876 # Total number of references to valid blocks. 580system.cpu.icache.tags.sampled_refs 6557 # Sample count of references to valid blocks. 581system.cpu.icache.tags.avg_refs 3410.077169 # Average number of references to valid blocks. | 578system.cpu.icache.tags.replacements 4955 # number of replacements 579system.cpu.icache.tags.tagsinuse 1627.815791 # Cycle average of tags in use 580system.cpu.icache.tags.total_refs 23126816 # Total number of references to valid blocks. 581system.cpu.icache.tags.sampled_refs 6924 # Sample count of references to valid blocks. 582system.cpu.icache.tags.avg_refs 3340.094743 # Average number of references to valid blocks. |
| 582system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 583system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 583system.cpu.icache.tags.occ_blocks::cpu.inst 1628.049417 # Average occupied blocks per requestor 584system.cpu.icache.tags.occ_percent::cpu.inst 0.794946 # Average percentage of cache occupancy 585system.cpu.icache.tags.occ_percent::total 0.794946 # Average percentage of cache occupancy 586system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id 587system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id 588system.cpu.icache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id 589system.cpu.icache.tags.age_task_id_blocks_1024::2 773 # Occupied blocks per task id 590system.cpu.icache.tags.age_task_id_blocks_1024::3 124 # Occupied blocks per task id 591system.cpu.icache.tags.age_task_id_blocks_1024::4 810 # Occupied blocks per task id 592system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id 593system.cpu.icache.tags.tag_accesses 44744077 # Number of tag accesses 594system.cpu.icache.tags.data_accesses 44744077 # Number of data accesses 595system.cpu.icache.ReadReq_hits::cpu.inst 22359876 # number of ReadReq hits 596system.cpu.icache.ReadReq_hits::total 22359876 # number of ReadReq hits 597system.cpu.icache.demand_hits::cpu.inst 22359876 # number of demand (read+write) hits 598system.cpu.icache.demand_hits::total 22359876 # number of demand (read+write) hits 599system.cpu.icache.overall_hits::cpu.inst 22359876 # number of overall hits 600system.cpu.icache.overall_hits::total 22359876 # number of overall hits 601system.cpu.icache.ReadReq_misses::cpu.inst 8818 # number of ReadReq misses 602system.cpu.icache.ReadReq_misses::total 8818 # number of ReadReq misses 603system.cpu.icache.demand_misses::cpu.inst 8818 # number of demand (read+write) misses 604system.cpu.icache.demand_misses::total 8818 # number of demand (read+write) misses 605system.cpu.icache.overall_misses::cpu.inst 8818 # number of overall misses 606system.cpu.icache.overall_misses::total 8818 # number of overall misses 607system.cpu.icache.ReadReq_miss_latency::cpu.inst 365022750 # number of ReadReq miss cycles 608system.cpu.icache.ReadReq_miss_latency::total 365022750 # number of ReadReq miss cycles 609system.cpu.icache.demand_miss_latency::cpu.inst 365022750 # number of demand (read+write) miss cycles 610system.cpu.icache.demand_miss_latency::total 365022750 # number of demand (read+write) miss cycles 611system.cpu.icache.overall_miss_latency::cpu.inst 365022750 # number of overall miss cycles 612system.cpu.icache.overall_miss_latency::total 365022750 # number of overall miss cycles 613system.cpu.icache.ReadReq_accesses::cpu.inst 22368694 # number of ReadReq accesses(hits+misses) 614system.cpu.icache.ReadReq_accesses::total 22368694 # number of ReadReq accesses(hits+misses) 615system.cpu.icache.demand_accesses::cpu.inst 22368694 # number of demand (read+write) accesses 616system.cpu.icache.demand_accesses::total 22368694 # number of demand (read+write) accesses 617system.cpu.icache.overall_accesses::cpu.inst 22368694 # number of overall (read+write) accesses 618system.cpu.icache.overall_accesses::total 22368694 # number of overall (read+write) accesses 619system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000394 # miss rate for ReadReq accesses 620system.cpu.icache.ReadReq_miss_rate::total 0.000394 # miss rate for ReadReq accesses 621system.cpu.icache.demand_miss_rate::cpu.inst 0.000394 # miss rate for demand accesses 622system.cpu.icache.demand_miss_rate::total 0.000394 # miss rate for demand accesses 623system.cpu.icache.overall_miss_rate::cpu.inst 0.000394 # miss rate for overall accesses 624system.cpu.icache.overall_miss_rate::total 0.000394 # miss rate for overall accesses 625system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41395.185983 # average ReadReq miss latency 626system.cpu.icache.ReadReq_avg_miss_latency::total 41395.185983 # average ReadReq miss latency 627system.cpu.icache.demand_avg_miss_latency::cpu.inst 41395.185983 # average overall miss latency 628system.cpu.icache.demand_avg_miss_latency::total 41395.185983 # average overall miss latency 629system.cpu.icache.overall_avg_miss_latency::cpu.inst 41395.185983 # average overall miss latency 630system.cpu.icache.overall_avg_miss_latency::total 41395.185983 # average overall miss latency 631system.cpu.icache.blocked_cycles::no_mshrs 701 # number of cycles access was blocked | 584system.cpu.icache.tags.occ_blocks::cpu.inst 1627.815791 # Average occupied blocks per requestor 585system.cpu.icache.tags.occ_percent::cpu.inst 0.794832 # Average percentage of cache occupancy 586system.cpu.icache.tags.occ_percent::total 0.794832 # Average percentage of cache occupancy 587system.cpu.icache.tags.occ_task_id_blocks::1024 1969 # Occupied blocks per task id 588system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id 589system.cpu.icache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id 590system.cpu.icache.tags.age_task_id_blocks_1024::2 748 # Occupied blocks per task id 591system.cpu.icache.tags.age_task_id_blocks_1024::3 136 # Occupied blocks per task id 592system.cpu.icache.tags.age_task_id_blocks_1024::4 793 # Occupied blocks per task id 593system.cpu.icache.tags.occ_task_id_percent::1024 0.961426 # Percentage of cache occupancy per task id 594system.cpu.icache.tags.tag_accesses 46279236 # Number of tag accesses 595system.cpu.icache.tags.data_accesses 46279236 # Number of data accesses 596system.cpu.icache.ReadReq_hits::cpu.inst 23126816 # number of ReadReq hits 597system.cpu.icache.ReadReq_hits::total 23126816 # number of ReadReq hits 598system.cpu.icache.demand_hits::cpu.inst 23126816 # number of demand (read+write) hits 599system.cpu.icache.demand_hits::total 23126816 # number of demand (read+write) hits 600system.cpu.icache.overall_hits::cpu.inst 23126816 # number of overall hits 601system.cpu.icache.overall_hits::total 23126816 # number of overall hits 602system.cpu.icache.ReadReq_misses::cpu.inst 9227 # number of ReadReq misses 603system.cpu.icache.ReadReq_misses::total 9227 # number of ReadReq misses 604system.cpu.icache.demand_misses::cpu.inst 9227 # number of demand (read+write) misses 605system.cpu.icache.demand_misses::total 9227 # number of demand (read+write) misses 606system.cpu.icache.overall_misses::cpu.inst 9227 # number of overall misses 607system.cpu.icache.overall_misses::total 9227 # number of overall misses 608system.cpu.icache.ReadReq_miss_latency::cpu.inst 376330999 # number of ReadReq miss cycles 609system.cpu.icache.ReadReq_miss_latency::total 376330999 # number of ReadReq miss cycles 610system.cpu.icache.demand_miss_latency::cpu.inst 376330999 # number of demand (read+write) miss cycles 611system.cpu.icache.demand_miss_latency::total 376330999 # number of demand (read+write) miss cycles 612system.cpu.icache.overall_miss_latency::cpu.inst 376330999 # number of overall miss cycles 613system.cpu.icache.overall_miss_latency::total 376330999 # number of overall miss cycles 614system.cpu.icache.ReadReq_accesses::cpu.inst 23136043 # number of ReadReq accesses(hits+misses) 615system.cpu.icache.ReadReq_accesses::total 23136043 # number of ReadReq accesses(hits+misses) 616system.cpu.icache.demand_accesses::cpu.inst 23136043 # number of demand (read+write) accesses 617system.cpu.icache.demand_accesses::total 23136043 # number of demand (read+write) accesses 618system.cpu.icache.overall_accesses::cpu.inst 23136043 # number of overall (read+write) accesses 619system.cpu.icache.overall_accesses::total 23136043 # number of overall (read+write) accesses 620system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000399 # miss rate for ReadReq accesses 621system.cpu.icache.ReadReq_miss_rate::total 0.000399 # miss rate for ReadReq accesses 622system.cpu.icache.demand_miss_rate::cpu.inst 0.000399 # miss rate for demand accesses 623system.cpu.icache.demand_miss_rate::total 0.000399 # miss rate for demand accesses 624system.cpu.icache.overall_miss_rate::cpu.inst 0.000399 # miss rate for overall accesses 625system.cpu.icache.overall_miss_rate::total 0.000399 # miss rate for overall accesses 626system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40785.845779 # average ReadReq miss latency 627system.cpu.icache.ReadReq_avg_miss_latency::total 40785.845779 # average ReadReq miss latency 628system.cpu.icache.demand_avg_miss_latency::cpu.inst 40785.845779 # average overall miss latency 629system.cpu.icache.demand_avg_miss_latency::total 40785.845779 # average overall miss latency 630system.cpu.icache.overall_avg_miss_latency::cpu.inst 40785.845779 # average overall miss latency 631system.cpu.icache.overall_avg_miss_latency::total 40785.845779 # average overall miss latency 632system.cpu.icache.blocked_cycles::no_mshrs 1569 # number of cycles access was blocked |
| 632system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 633system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 633system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked | 634system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked |
| 634system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 635system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 635system.cpu.icache.avg_blocked_cycles::no_mshrs 46.733333 # average number of cycles each access was blocked | 636system.cpu.icache.avg_blocked_cycles::no_mshrs 98.062500 # average number of cycles each access was blocked |
| 636system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 637system.cpu.icache.fast_writes 0 # number of fast writes performed 638system.cpu.icache.cache_copies 0 # number of cache copies performed | 637system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 638system.cpu.icache.fast_writes 0 # number of fast writes performed 639system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 639system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2129 # number of ReadReq MSHR hits 640system.cpu.icache.ReadReq_mshr_hits::total 2129 # number of ReadReq MSHR hits 641system.cpu.icache.demand_mshr_hits::cpu.inst 2129 # number of demand (read+write) MSHR hits 642system.cpu.icache.demand_mshr_hits::total 2129 # number of demand (read+write) MSHR hits 643system.cpu.icache.overall_mshr_hits::cpu.inst 2129 # number of overall MSHR hits 644system.cpu.icache.overall_mshr_hits::total 2129 # number of overall MSHR hits 645system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6689 # number of ReadReq MSHR misses 646system.cpu.icache.ReadReq_mshr_misses::total 6689 # number of ReadReq MSHR misses 647system.cpu.icache.demand_mshr_misses::cpu.inst 6689 # number of demand (read+write) MSHR misses 648system.cpu.icache.demand_mshr_misses::total 6689 # number of demand (read+write) MSHR misses 649system.cpu.icache.overall_mshr_misses::cpu.inst 6689 # number of overall MSHR misses 650system.cpu.icache.overall_mshr_misses::total 6689 # number of overall MSHR misses 651system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 269490250 # number of ReadReq MSHR miss cycles 652system.cpu.icache.ReadReq_mshr_miss_latency::total 269490250 # number of ReadReq MSHR miss cycles 653system.cpu.icache.demand_mshr_miss_latency::cpu.inst 269490250 # number of demand (read+write) MSHR miss cycles 654system.cpu.icache.demand_mshr_miss_latency::total 269490250 # number of demand (read+write) MSHR miss cycles 655system.cpu.icache.overall_mshr_miss_latency::cpu.inst 269490250 # number of overall MSHR miss cycles 656system.cpu.icache.overall_mshr_miss_latency::total 269490250 # number of overall MSHR miss cycles 657system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for ReadReq accesses 658system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000299 # mshr miss rate for ReadReq accesses 659system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for demand accesses 660system.cpu.icache.demand_mshr_miss_rate::total 0.000299 # mshr miss rate for demand accesses 661system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for overall accesses 662system.cpu.icache.overall_mshr_miss_rate::total 0.000299 # mshr miss rate for overall accesses 663system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40288.570788 # average ReadReq mshr miss latency 664system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40288.570788 # average ReadReq mshr miss latency 665system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40288.570788 # average overall mshr miss latency 666system.cpu.icache.demand_avg_mshr_miss_latency::total 40288.570788 # average overall mshr miss latency 667system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40288.570788 # average overall mshr miss latency 668system.cpu.icache.overall_avg_mshr_miss_latency::total 40288.570788 # average overall mshr miss latency | 640system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2076 # number of ReadReq MSHR hits 641system.cpu.icache.ReadReq_mshr_hits::total 2076 # number of ReadReq MSHR hits 642system.cpu.icache.demand_mshr_hits::cpu.inst 2076 # number of demand (read+write) MSHR hits 643system.cpu.icache.demand_mshr_hits::total 2076 # number of demand (read+write) MSHR hits 644system.cpu.icache.overall_mshr_hits::cpu.inst 2076 # number of overall MSHR hits 645system.cpu.icache.overall_mshr_hits::total 2076 # number of overall MSHR hits 646system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7151 # number of ReadReq MSHR misses 647system.cpu.icache.ReadReq_mshr_misses::total 7151 # number of ReadReq MSHR misses 648system.cpu.icache.demand_mshr_misses::cpu.inst 7151 # number of demand (read+write) MSHR misses 649system.cpu.icache.demand_mshr_misses::total 7151 # number of demand (read+write) MSHR misses 650system.cpu.icache.overall_mshr_misses::cpu.inst 7151 # number of overall MSHR misses 651system.cpu.icache.overall_mshr_misses::total 7151 # number of overall MSHR misses 652system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 279771249 # number of ReadReq MSHR miss cycles 653system.cpu.icache.ReadReq_mshr_miss_latency::total 279771249 # number of ReadReq MSHR miss cycles 654system.cpu.icache.demand_mshr_miss_latency::cpu.inst 279771249 # number of demand (read+write) MSHR miss cycles 655system.cpu.icache.demand_mshr_miss_latency::total 279771249 # number of demand (read+write) MSHR miss cycles 656system.cpu.icache.overall_mshr_miss_latency::cpu.inst 279771249 # number of overall MSHR miss cycles 657system.cpu.icache.overall_mshr_miss_latency::total 279771249 # number of overall MSHR miss cycles 658system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000309 # mshr miss rate for ReadReq accesses 659system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000309 # mshr miss rate for ReadReq accesses 660system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000309 # mshr miss rate for demand accesses 661system.cpu.icache.demand_mshr_miss_rate::total 0.000309 # mshr miss rate for demand accesses 662system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000309 # mshr miss rate for overall accesses 663system.cpu.icache.overall_mshr_miss_rate::total 0.000309 # mshr miss rate for overall accesses 664system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39123.374213 # average ReadReq mshr miss latency 665system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39123.374213 # average ReadReq mshr miss latency 666system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39123.374213 # average overall mshr miss latency 667system.cpu.icache.demand_avg_mshr_miss_latency::total 39123.374213 # average overall mshr miss latency 668system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39123.374213 # average overall mshr miss latency 669system.cpu.icache.overall_avg_mshr_miss_latency::total 39123.374213 # average overall mshr miss latency |
| 669system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 670system.cpu.l2cache.tags.replacements 0 # number of replacements | 670system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 671system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 671system.cpu.l2cache.tags.tagsinuse 2549.629926 # Cycle average of tags in use 672system.cpu.l2cache.tags.total_refs 3205 # Total number of references to valid blocks. 673system.cpu.l2cache.tags.sampled_refs 3824 # Sample count of references to valid blocks. 674system.cpu.l2cache.tags.avg_refs 0.838128 # Average number of references to valid blocks. | 672system.cpu.l2cache.tags.tagsinuse 2580.073748 # Cycle average of tags in use 673system.cpu.l2cache.tags.total_refs 3536 # Total number of references to valid blocks. 674system.cpu.l2cache.tags.sampled_refs 3865 # Sample count of references to valid blocks. 675system.cpu.l2cache.tags.avg_refs 0.914877 # Average number of references to valid blocks. |
| 675system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 676system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 676system.cpu.l2cache.tags.occ_blocks::writebacks 1.731773 # Average occupied blocks per requestor 677system.cpu.l2cache.tags.occ_blocks::cpu.inst 2236.346523 # Average occupied blocks per requestor 678system.cpu.l2cache.tags.occ_blocks::cpu.data 311.551630 # Average occupied blocks per requestor 679system.cpu.l2cache.tags.occ_percent::writebacks 0.000053 # Average percentage of cache occupancy 680system.cpu.l2cache.tags.occ_percent::cpu.inst 0.068248 # Average percentage of cache occupancy 681system.cpu.l2cache.tags.occ_percent::cpu.data 0.009508 # Average percentage of cache occupancy 682system.cpu.l2cache.tags.occ_percent::total 0.077809 # Average percentage of cache occupancy 683system.cpu.l2cache.tags.occ_task_id_blocks::1024 3824 # Occupied blocks per task id 684system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 685system.cpu.l2cache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id 686system.cpu.l2cache.tags.age_task_id_blocks_1024::2 895 # Occupied blocks per task id 687system.cpu.l2cache.tags.age_task_id_blocks_1024::3 142 # Occupied blocks per task id 688system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2568 # Occupied blocks per task id 689system.cpu.l2cache.tags.occ_task_id_percent::1024 0.116699 # Percentage of cache occupancy per task id 690system.cpu.l2cache.tags.tag_accesses 75020 # Number of tag accesses 691system.cpu.l2cache.tags.data_accesses 75020 # Number of data accesses 692system.cpu.l2cache.ReadReq_hits::cpu.inst 3162 # number of ReadReq hits 693system.cpu.l2cache.ReadReq_hits::cpu.data 38 # number of ReadReq hits 694system.cpu.l2cache.ReadReq_hits::total 3200 # number of ReadReq hits | 677system.cpu.l2cache.tags.occ_blocks::writebacks 1.848072 # Average occupied blocks per requestor 678system.cpu.l2cache.tags.occ_blocks::cpu.inst 2267.439437 # Average occupied blocks per requestor 679system.cpu.l2cache.tags.occ_blocks::cpu.data 310.786239 # Average occupied blocks per requestor 680system.cpu.l2cache.tags.occ_percent::writebacks 0.000056 # Average percentage of cache occupancy 681system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069197 # Average percentage of cache occupancy 682system.cpu.l2cache.tags.occ_percent::cpu.data 0.009484 # Average percentage of cache occupancy 683system.cpu.l2cache.tags.occ_percent::total 0.078738 # Average percentage of cache occupancy 684system.cpu.l2cache.tags.occ_task_id_blocks::1024 3865 # Occupied blocks per task id 685system.cpu.l2cache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id 686system.cpu.l2cache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id 687system.cpu.l2cache.tags.age_task_id_blocks_1024::2 868 # Occupied blocks per task id 688system.cpu.l2cache.tags.age_task_id_blocks_1024::3 150 # Occupied blocks per task id 689system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2602 # Occupied blocks per task id 690system.cpu.l2cache.tags.occ_task_id_percent::1024 0.117950 # Percentage of cache occupancy per task id 691system.cpu.l2cache.tags.tag_accesses 78826 # Number of tag accesses 692system.cpu.l2cache.tags.data_accesses 78826 # Number of data accesses 693system.cpu.l2cache.ReadReq_hits::cpu.inst 3491 # number of ReadReq hits 694system.cpu.l2cache.ReadReq_hits::cpu.data 40 # number of ReadReq hits 695system.cpu.l2cache.ReadReq_hits::total 3531 # number of ReadReq hits |
| 695system.cpu.l2cache.Writeback_hits::writebacks 13 # number of Writeback hits 696system.cpu.l2cache.Writeback_hits::total 13 # number of Writeback hits 697system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 698system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits | 696system.cpu.l2cache.Writeback_hits::writebacks 13 # number of Writeback hits 697system.cpu.l2cache.Writeback_hits::total 13 # number of Writeback hits 698system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 699system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits |
| 699system.cpu.l2cache.ReadExReq_hits::cpu.data 6 # number of ReadExReq hits 700system.cpu.l2cache.ReadExReq_hits::total 6 # number of ReadExReq hits 701system.cpu.l2cache.demand_hits::cpu.inst 3162 # number of demand (read+write) hits 702system.cpu.l2cache.demand_hits::cpu.data 44 # number of demand (read+write) hits 703system.cpu.l2cache.demand_hits::total 3206 # number of demand (read+write) hits 704system.cpu.l2cache.overall_hits::cpu.inst 3162 # number of overall hits 705system.cpu.l2cache.overall_hits::cpu.data 44 # number of overall hits 706system.cpu.l2cache.overall_hits::total 3206 # number of overall hits 707system.cpu.l2cache.ReadReq_misses::cpu.inst 3394 # number of ReadReq misses | 700system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # number of ReadExReq hits 701system.cpu.l2cache.ReadExReq_hits::total 7 # number of ReadExReq hits 702system.cpu.l2cache.demand_hits::cpu.inst 3491 # number of demand (read+write) hits 703system.cpu.l2cache.demand_hits::cpu.data 47 # number of demand (read+write) hits 704system.cpu.l2cache.demand_hits::total 3538 # number of demand (read+write) hits 705system.cpu.l2cache.overall_hits::cpu.inst 3491 # number of overall hits 706system.cpu.l2cache.overall_hits::cpu.data 47 # number of overall hits 707system.cpu.l2cache.overall_hits::total 3538 # number of overall hits 708system.cpu.l2cache.ReadReq_misses::cpu.inst 3434 # number of ReadReq misses |
| 708system.cpu.l2cache.ReadReq_misses::cpu.data 429 # number of ReadReq misses | 709system.cpu.l2cache.ReadReq_misses::cpu.data 429 # number of ReadReq misses |
| 709system.cpu.l2cache.ReadReq_misses::total 3823 # number of ReadReq misses 710system.cpu.l2cache.UpgradeReq_misses::cpu.data 131 # number of UpgradeReq misses 711system.cpu.l2cache.UpgradeReq_misses::total 131 # number of UpgradeReq misses 712system.cpu.l2cache.ReadExReq_misses::cpu.data 1533 # number of ReadExReq misses 713system.cpu.l2cache.ReadExReq_misses::total 1533 # number of ReadExReq misses 714system.cpu.l2cache.demand_misses::cpu.inst 3394 # number of demand (read+write) misses 715system.cpu.l2cache.demand_misses::cpu.data 1962 # number of demand (read+write) misses 716system.cpu.l2cache.demand_misses::total 5356 # number of demand (read+write) misses 717system.cpu.l2cache.overall_misses::cpu.inst 3394 # number of overall misses 718system.cpu.l2cache.overall_misses::cpu.data 1962 # number of overall misses 719system.cpu.l2cache.overall_misses::total 5356 # number of overall misses 720system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 231042500 # number of ReadReq miss cycles 721system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32071000 # number of ReadReq miss cycles 722system.cpu.l2cache.ReadReq_miss_latency::total 263113500 # number of ReadReq miss cycles 723system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 103820500 # number of ReadExReq miss cycles 724system.cpu.l2cache.ReadExReq_miss_latency::total 103820500 # number of ReadExReq miss cycles 725system.cpu.l2cache.demand_miss_latency::cpu.inst 231042500 # number of demand (read+write) miss cycles 726system.cpu.l2cache.demand_miss_latency::cpu.data 135891500 # number of demand (read+write) miss cycles 727system.cpu.l2cache.demand_miss_latency::total 366934000 # number of demand (read+write) miss cycles 728system.cpu.l2cache.overall_miss_latency::cpu.inst 231042500 # number of overall miss cycles 729system.cpu.l2cache.overall_miss_latency::cpu.data 135891500 # number of overall miss cycles 730system.cpu.l2cache.overall_miss_latency::total 366934000 # number of overall miss cycles 731system.cpu.l2cache.ReadReq_accesses::cpu.inst 6556 # number of ReadReq accesses(hits+misses) 732system.cpu.l2cache.ReadReq_accesses::cpu.data 467 # number of ReadReq accesses(hits+misses) 733system.cpu.l2cache.ReadReq_accesses::total 7023 # number of ReadReq accesses(hits+misses) | 710system.cpu.l2cache.ReadReq_misses::total 3863 # number of ReadReq misses 711system.cpu.l2cache.UpgradeReq_misses::cpu.data 225 # number of UpgradeReq misses 712system.cpu.l2cache.UpgradeReq_misses::total 225 # number of UpgradeReq misses 713system.cpu.l2cache.ReadExReq_misses::cpu.data 1537 # number of ReadExReq misses 714system.cpu.l2cache.ReadExReq_misses::total 1537 # number of ReadExReq misses 715system.cpu.l2cache.demand_misses::cpu.inst 3434 # number of demand (read+write) misses 716system.cpu.l2cache.demand_misses::cpu.data 1966 # number of demand (read+write) misses 717system.cpu.l2cache.demand_misses::total 5400 # number of demand (read+write) misses 718system.cpu.l2cache.overall_misses::cpu.inst 3434 # number of overall misses 719system.cpu.l2cache.overall_misses::cpu.data 1966 # number of overall misses 720system.cpu.l2cache.overall_misses::total 5400 # number of overall misses 721system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 237479500 # number of ReadReq miss cycles 722system.cpu.l2cache.ReadReq_miss_latency::cpu.data 33236000 # number of ReadReq miss cycles 723system.cpu.l2cache.ReadReq_miss_latency::total 270715500 # number of ReadReq miss cycles 724system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104554500 # number of ReadExReq miss cycles 725system.cpu.l2cache.ReadExReq_miss_latency::total 104554500 # number of ReadExReq miss cycles 726system.cpu.l2cache.demand_miss_latency::cpu.inst 237479500 # number of demand (read+write) miss cycles 727system.cpu.l2cache.demand_miss_latency::cpu.data 137790500 # number of demand (read+write) miss cycles 728system.cpu.l2cache.demand_miss_latency::total 375270000 # number of demand (read+write) miss cycles 729system.cpu.l2cache.overall_miss_latency::cpu.inst 237479500 # number of overall miss cycles 730system.cpu.l2cache.overall_miss_latency::cpu.data 137790500 # number of overall miss cycles 731system.cpu.l2cache.overall_miss_latency::total 375270000 # number of overall miss cycles 732system.cpu.l2cache.ReadReq_accesses::cpu.inst 6925 # number of ReadReq accesses(hits+misses) 733system.cpu.l2cache.ReadReq_accesses::cpu.data 469 # number of ReadReq accesses(hits+misses) 734system.cpu.l2cache.ReadReq_accesses::total 7394 # number of ReadReq accesses(hits+misses) |
| 734system.cpu.l2cache.Writeback_accesses::writebacks 13 # number of Writeback accesses(hits+misses) 735system.cpu.l2cache.Writeback_accesses::total 13 # number of Writeback accesses(hits+misses) | 735system.cpu.l2cache.Writeback_accesses::writebacks 13 # number of Writeback accesses(hits+misses) 736system.cpu.l2cache.Writeback_accesses::total 13 # number of Writeback accesses(hits+misses) |
| 736system.cpu.l2cache.UpgradeReq_accesses::cpu.data 132 # number of UpgradeReq accesses(hits+misses) 737system.cpu.l2cache.UpgradeReq_accesses::total 132 # number of UpgradeReq accesses(hits+misses) 738system.cpu.l2cache.ReadExReq_accesses::cpu.data 1539 # number of ReadExReq accesses(hits+misses) 739system.cpu.l2cache.ReadExReq_accesses::total 1539 # number of ReadExReq accesses(hits+misses) 740system.cpu.l2cache.demand_accesses::cpu.inst 6556 # number of demand (read+write) accesses 741system.cpu.l2cache.demand_accesses::cpu.data 2006 # number of demand (read+write) accesses 742system.cpu.l2cache.demand_accesses::total 8562 # number of demand (read+write) accesses 743system.cpu.l2cache.overall_accesses::cpu.inst 6556 # number of overall (read+write) accesses 744system.cpu.l2cache.overall_accesses::cpu.data 2006 # number of overall (read+write) accesses 745system.cpu.l2cache.overall_accesses::total 8562 # number of overall (read+write) accesses 746system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.517694 # miss rate for ReadReq accesses 747system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.918630 # miss rate for ReadReq accesses 748system.cpu.l2cache.ReadReq_miss_rate::total 0.544354 # miss rate for ReadReq accesses 749system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.992424 # miss rate for UpgradeReq accesses 750system.cpu.l2cache.UpgradeReq_miss_rate::total 0.992424 # miss rate for UpgradeReq accesses 751system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996101 # miss rate for ReadExReq accesses 752system.cpu.l2cache.ReadExReq_miss_rate::total 0.996101 # miss rate for ReadExReq accesses 753system.cpu.l2cache.demand_miss_rate::cpu.inst 0.517694 # miss rate for demand accesses 754system.cpu.l2cache.demand_miss_rate::cpu.data 0.978066 # miss rate for demand accesses 755system.cpu.l2cache.demand_miss_rate::total 0.625555 # miss rate for demand accesses 756system.cpu.l2cache.overall_miss_rate::cpu.inst 0.517694 # miss rate for overall accesses 757system.cpu.l2cache.overall_miss_rate::cpu.data 0.978066 # miss rate for overall accesses 758system.cpu.l2cache.overall_miss_rate::total 0.625555 # miss rate for overall accesses 759system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68073.806718 # average ReadReq miss latency 760system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74757.575758 # average ReadReq miss latency 761system.cpu.l2cache.ReadReq_avg_miss_latency::total 68823.829453 # average ReadReq miss latency 762system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67723.744292 # average ReadExReq miss latency 763system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67723.744292 # average ReadExReq miss latency 764system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68073.806718 # average overall miss latency 765system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69261.722732 # average overall miss latency 766system.cpu.l2cache.demand_avg_miss_latency::total 68508.961912 # average overall miss latency 767system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68073.806718 # average overall miss latency 768system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69261.722732 # average overall miss latency 769system.cpu.l2cache.overall_avg_miss_latency::total 68508.961912 # average overall miss latency | 737system.cpu.l2cache.UpgradeReq_accesses::cpu.data 226 # number of UpgradeReq accesses(hits+misses) 738system.cpu.l2cache.UpgradeReq_accesses::total 226 # number of UpgradeReq accesses(hits+misses) 739system.cpu.l2cache.ReadExReq_accesses::cpu.data 1544 # number of ReadExReq accesses(hits+misses) 740system.cpu.l2cache.ReadExReq_accesses::total 1544 # number of ReadExReq accesses(hits+misses) 741system.cpu.l2cache.demand_accesses::cpu.inst 6925 # number of demand (read+write) accesses 742system.cpu.l2cache.demand_accesses::cpu.data 2013 # number of demand (read+write) accesses 743system.cpu.l2cache.demand_accesses::total 8938 # number of demand (read+write) accesses 744system.cpu.l2cache.overall_accesses::cpu.inst 6925 # number of overall (read+write) accesses 745system.cpu.l2cache.overall_accesses::cpu.data 2013 # number of overall (read+write) accesses 746system.cpu.l2cache.overall_accesses::total 8938 # number of overall (read+write) accesses 747system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.495884 # miss rate for ReadReq accesses 748system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.914712 # miss rate for ReadReq accesses 749system.cpu.l2cache.ReadReq_miss_rate::total 0.522451 # miss rate for ReadReq accesses 750system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.995575 # miss rate for UpgradeReq accesses 751system.cpu.l2cache.UpgradeReq_miss_rate::total 0.995575 # miss rate for UpgradeReq accesses 752system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995466 # miss rate for ReadExReq accesses 753system.cpu.l2cache.ReadExReq_miss_rate::total 0.995466 # miss rate for ReadExReq accesses 754system.cpu.l2cache.demand_miss_rate::cpu.inst 0.495884 # miss rate for demand accesses 755system.cpu.l2cache.demand_miss_rate::cpu.data 0.976652 # miss rate for demand accesses 756system.cpu.l2cache.demand_miss_rate::total 0.604162 # miss rate for demand accesses 757system.cpu.l2cache.overall_miss_rate::cpu.inst 0.495884 # miss rate for overall accesses 758system.cpu.l2cache.overall_miss_rate::cpu.data 0.976652 # miss rate for overall accesses 759system.cpu.l2cache.overall_miss_rate::total 0.604162 # miss rate for overall accesses 760system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69155.358183 # average ReadReq miss latency 761system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77473.193473 # average ReadReq miss latency 762system.cpu.l2cache.ReadReq_avg_miss_latency::total 70079.083614 # average ReadReq miss latency 763system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68025.048796 # average ReadExReq miss latency 764system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68025.048796 # average ReadExReq miss latency 765system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69155.358183 # average overall miss latency 766system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70086.724313 # average overall miss latency 767system.cpu.l2cache.demand_avg_miss_latency::total 69494.444444 # average overall miss latency 768system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69155.358183 # average overall miss latency 769system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70086.724313 # average overall miss latency 770system.cpu.l2cache.overall_avg_miss_latency::total 69494.444444 # average overall miss latency |
| 770system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 771system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 772system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 773system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 774system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 775system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 776system.cpu.l2cache.fast_writes 0 # number of fast writes performed 777system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 771system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 772system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 773system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 774system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 775system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 776system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 777system.cpu.l2cache.fast_writes 0 # number of fast writes performed 778system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 778system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3394 # number of ReadReq MSHR misses | 779system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3434 # number of ReadReq MSHR misses |
| 779system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 429 # number of ReadReq MSHR misses | 780system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 429 # number of ReadReq MSHR misses |
| 780system.cpu.l2cache.ReadReq_mshr_misses::total 3823 # number of ReadReq MSHR misses 781system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 131 # number of UpgradeReq MSHR misses 782system.cpu.l2cache.UpgradeReq_mshr_misses::total 131 # number of UpgradeReq MSHR misses 783system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1533 # number of ReadExReq MSHR misses 784system.cpu.l2cache.ReadExReq_mshr_misses::total 1533 # number of ReadExReq MSHR misses 785system.cpu.l2cache.demand_mshr_misses::cpu.inst 3394 # number of demand (read+write) MSHR misses 786system.cpu.l2cache.demand_mshr_misses::cpu.data 1962 # number of demand (read+write) MSHR misses 787system.cpu.l2cache.demand_mshr_misses::total 5356 # number of demand (read+write) MSHR misses 788system.cpu.l2cache.overall_mshr_misses::cpu.inst 3394 # number of overall MSHR misses 789system.cpu.l2cache.overall_mshr_misses::cpu.data 1962 # number of overall MSHR misses 790system.cpu.l2cache.overall_mshr_misses::total 5356 # number of overall MSHR misses 791system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 188477000 # number of ReadReq MSHR miss cycles 792system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26778500 # number of ReadReq MSHR miss cycles 793system.cpu.l2cache.ReadReq_mshr_miss_latency::total 215255500 # number of ReadReq MSHR miss cycles 794system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1310131 # number of UpgradeReq MSHR miss cycles 795system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1310131 # number of UpgradeReq MSHR miss cycles 796system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 84218500 # number of ReadExReq MSHR miss cycles 797system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 84218500 # number of ReadExReq MSHR miss cycles 798system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 188477000 # number of demand (read+write) MSHR miss cycles 799system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 110997000 # number of demand (read+write) MSHR miss cycles 800system.cpu.l2cache.demand_mshr_miss_latency::total 299474000 # number of demand (read+write) MSHR miss cycles 801system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 188477000 # number of overall MSHR miss cycles 802system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 110997000 # number of overall MSHR miss cycles 803system.cpu.l2cache.overall_mshr_miss_latency::total 299474000 # number of overall MSHR miss cycles 804system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.517694 # mshr miss rate for ReadReq accesses 805system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.918630 # mshr miss rate for ReadReq accesses 806system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.544354 # mshr miss rate for ReadReq accesses 807system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.992424 # mshr miss rate for UpgradeReq accesses 808system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992424 # mshr miss rate for UpgradeReq accesses 809system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996101 # mshr miss rate for ReadExReq accesses 810system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996101 # mshr miss rate for ReadExReq accesses 811system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.517694 # mshr miss rate for demand accesses 812system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.978066 # mshr miss rate for demand accesses 813system.cpu.l2cache.demand_mshr_miss_rate::total 0.625555 # mshr miss rate for demand accesses 814system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.517694 # mshr miss rate for overall accesses 815system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.978066 # mshr miss rate for overall accesses 816system.cpu.l2cache.overall_mshr_miss_rate::total 0.625555 # mshr miss rate for overall accesses 817system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55532.410136 # average ReadReq mshr miss latency 818system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62420.745921 # average ReadReq mshr miss latency 819system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56305.388438 # average ReadReq mshr miss latency | 781system.cpu.l2cache.ReadReq_mshr_misses::total 3863 # number of ReadReq MSHR misses 782system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 225 # number of UpgradeReq MSHR misses 783system.cpu.l2cache.UpgradeReq_mshr_misses::total 225 # number of UpgradeReq MSHR misses 784system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1537 # number of ReadExReq MSHR misses 785system.cpu.l2cache.ReadExReq_mshr_misses::total 1537 # number of ReadExReq MSHR misses 786system.cpu.l2cache.demand_mshr_misses::cpu.inst 3434 # number of demand (read+write) MSHR misses 787system.cpu.l2cache.demand_mshr_misses::cpu.data 1966 # number of demand (read+write) MSHR misses 788system.cpu.l2cache.demand_mshr_misses::total 5400 # number of demand (read+write) MSHR misses 789system.cpu.l2cache.overall_mshr_misses::cpu.inst 3434 # number of overall MSHR misses 790system.cpu.l2cache.overall_mshr_misses::cpu.data 1966 # number of overall MSHR misses 791system.cpu.l2cache.overall_mshr_misses::total 5400 # number of overall MSHR misses 792system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 194452000 # number of ReadReq MSHR miss cycles 793system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27908500 # number of ReadReq MSHR miss cycles 794system.cpu.l2cache.ReadReq_mshr_miss_latency::total 222360500 # number of ReadReq MSHR miss cycles 795system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2250225 # number of UpgradeReq MSHR miss cycles 796system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2250225 # number of UpgradeReq MSHR miss cycles 797system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 85239500 # number of ReadExReq MSHR miss cycles 798system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 85239500 # number of ReadExReq MSHR miss cycles 799system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 194452000 # number of demand (read+write) MSHR miss cycles 800system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 113148000 # number of demand (read+write) MSHR miss cycles 801system.cpu.l2cache.demand_mshr_miss_latency::total 307600000 # number of demand (read+write) MSHR miss cycles 802system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 194452000 # number of overall MSHR miss cycles 803system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 113148000 # number of overall MSHR miss cycles 804system.cpu.l2cache.overall_mshr_miss_latency::total 307600000 # number of overall MSHR miss cycles 805system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.495884 # mshr miss rate for ReadReq accesses 806system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.914712 # mshr miss rate for ReadReq accesses 807system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.522451 # mshr miss rate for ReadReq accesses 808system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.995575 # mshr miss rate for UpgradeReq accesses 809system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.995575 # mshr miss rate for UpgradeReq accesses 810system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995466 # mshr miss rate for ReadExReq accesses 811system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995466 # mshr miss rate for ReadExReq accesses 812system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.495884 # mshr miss rate for demand accesses 813system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.976652 # mshr miss rate for demand accesses 814system.cpu.l2cache.demand_mshr_miss_rate::total 0.604162 # mshr miss rate for demand accesses 815system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.495884 # mshr miss rate for overall accesses 816system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.976652 # mshr miss rate for overall accesses 817system.cpu.l2cache.overall_mshr_miss_rate::total 0.604162 # mshr miss rate for overall accesses 818system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56625.509610 # average ReadReq mshr miss latency 819system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65054.778555 # average ReadReq mshr miss latency 820system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57561.610148 # average ReadReq mshr miss latency |
| 820system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 821system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency | 821system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 822system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency |
| 822system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54937.051533 # average ReadExReq mshr miss latency 823system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54937.051533 # average ReadExReq mshr miss latency 824system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55532.410136 # average overall mshr miss latency 825system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56573.394495 # average overall mshr miss latency 826system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55913.741598 # average overall mshr miss latency 827system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55532.410136 # average overall mshr miss latency 828system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56573.394495 # average overall mshr miss latency 829system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55913.741598 # average overall mshr miss latency | 823system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55458.360442 # average ReadExReq mshr miss latency 824system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55458.360442 # average ReadExReq mshr miss latency 825system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56625.509610 # average overall mshr miss latency 826system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57552.390641 # average overall mshr miss latency 827system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56962.962963 # average overall mshr miss latency 828system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56625.509610 # average overall mshr miss latency 829system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57552.390641 # average overall mshr miss latency 830system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56962.962963 # average overall mshr miss latency |
| 830system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 831system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 831system.cpu.dcache.tags.replacements 59 # number of replacements 832system.cpu.dcache.tags.tagsinuse 1435.036669 # Cycle average of tags in use 833system.cpu.dcache.tags.total_refs 66148000 # Total number of references to valid blocks. 834system.cpu.dcache.tags.sampled_refs 2003 # Sample count of references to valid blocks. 835system.cpu.dcache.tags.avg_refs 33024.463305 # Average number of references to valid blocks. | 832system.cpu.dcache.tags.replacements 57 # number of replacements 833system.cpu.dcache.tags.tagsinuse 1441.863444 # Cycle average of tags in use 834system.cpu.dcache.tags.total_refs 66606870 # Total number of references to valid blocks. 835system.cpu.dcache.tags.sampled_refs 2012 # Sample count of references to valid blocks. 836system.cpu.dcache.tags.avg_refs 33104.806163 # Average number of references to valid blocks. |
| 836system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 837system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 837system.cpu.dcache.tags.occ_blocks::cpu.data 1435.036669 # Average occupied blocks per requestor 838system.cpu.dcache.tags.occ_percent::cpu.data 0.350351 # Average percentage of cache occupancy 839system.cpu.dcache.tags.occ_percent::total 0.350351 # Average percentage of cache occupancy 840system.cpu.dcache.tags.occ_task_id_blocks::1024 1944 # Occupied blocks per task id 841system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 842system.cpu.dcache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id 843system.cpu.dcache.tags.age_task_id_blocks_1024::2 71 # Occupied blocks per task id 844system.cpu.dcache.tags.age_task_id_blocks_1024::3 430 # Occupied blocks per task id 845system.cpu.dcache.tags.age_task_id_blocks_1024::4 1390 # Occupied blocks per task id 846system.cpu.dcache.tags.occ_task_id_percent::1024 0.474609 # Percentage of cache occupancy per task id 847system.cpu.dcache.tags.tag_accesses 132302857 # Number of tag accesses 848system.cpu.dcache.tags.data_accesses 132302857 # Number of data accesses 849system.cpu.dcache.ReadReq_hits::cpu.data 45633758 # number of ReadReq hits 850system.cpu.dcache.ReadReq_hits::total 45633758 # number of ReadReq hits 851system.cpu.dcache.WriteReq_hits::cpu.data 20514059 # number of WriteReq hits 852system.cpu.dcache.WriteReq_hits::total 20514059 # number of WriteReq hits 853system.cpu.dcache.demand_hits::cpu.data 66147817 # number of demand (read+write) hits 854system.cpu.dcache.demand_hits::total 66147817 # number of demand (read+write) hits 855system.cpu.dcache.overall_hits::cpu.data 66147817 # number of overall hits 856system.cpu.dcache.overall_hits::total 66147817 # number of overall hits 857system.cpu.dcache.ReadReq_misses::cpu.data 938 # number of ReadReq misses 858system.cpu.dcache.ReadReq_misses::total 938 # number of ReadReq misses 859system.cpu.dcache.WriteReq_misses::cpu.data 1672 # number of WriteReq misses 860system.cpu.dcache.WriteReq_misses::total 1672 # number of WriteReq misses 861system.cpu.dcache.demand_misses::cpu.data 2610 # number of demand (read+write) misses 862system.cpu.dcache.demand_misses::total 2610 # number of demand (read+write) misses 863system.cpu.dcache.overall_misses::cpu.data 2610 # number of overall misses 864system.cpu.dcache.overall_misses::total 2610 # number of overall misses 865system.cpu.dcache.ReadReq_miss_latency::cpu.data 59941301 # number of ReadReq miss cycles 866system.cpu.dcache.ReadReq_miss_latency::total 59941301 # number of ReadReq miss cycles 867system.cpu.dcache.WriteReq_miss_latency::cpu.data 112492631 # number of WriteReq miss cycles 868system.cpu.dcache.WriteReq_miss_latency::total 112492631 # number of WriteReq miss cycles 869system.cpu.dcache.demand_miss_latency::cpu.data 172433932 # number of demand (read+write) miss cycles 870system.cpu.dcache.demand_miss_latency::total 172433932 # number of demand (read+write) miss cycles 871system.cpu.dcache.overall_miss_latency::cpu.data 172433932 # number of overall miss cycles 872system.cpu.dcache.overall_miss_latency::total 172433932 # number of overall miss cycles 873system.cpu.dcache.ReadReq_accesses::cpu.data 45634696 # number of ReadReq accesses(hits+misses) 874system.cpu.dcache.ReadReq_accesses::total 45634696 # number of ReadReq accesses(hits+misses) | 838system.cpu.dcache.tags.occ_blocks::cpu.data 1441.863444 # Average occupied blocks per requestor 839system.cpu.dcache.tags.occ_percent::cpu.data 0.352017 # Average percentage of cache occupancy 840system.cpu.dcache.tags.occ_percent::total 0.352017 # Average percentage of cache occupancy 841system.cpu.dcache.tags.occ_task_id_blocks::1024 1955 # Occupied blocks per task id 842system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id 843system.cpu.dcache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id 844system.cpu.dcache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id 845system.cpu.dcache.tags.age_task_id_blocks_1024::3 432 # Occupied blocks per task id 846system.cpu.dcache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id 847system.cpu.dcache.tags.occ_task_id_percent::1024 0.477295 # Percentage of cache occupancy per task id 848system.cpu.dcache.tags.tag_accesses 133220616 # Number of tag accesses 849system.cpu.dcache.tags.data_accesses 133220616 # Number of data accesses 850system.cpu.dcache.ReadReq_hits::cpu.data 46092554 # number of ReadReq hits 851system.cpu.dcache.ReadReq_hits::total 46092554 # number of ReadReq hits 852system.cpu.dcache.WriteReq_hits::cpu.data 20513960 # number of WriteReq hits 853system.cpu.dcache.WriteReq_hits::total 20513960 # number of WriteReq hits 854system.cpu.dcache.demand_hits::cpu.data 66606514 # number of demand (read+write) hits 855system.cpu.dcache.demand_hits::total 66606514 # number of demand (read+write) hits 856system.cpu.dcache.overall_hits::cpu.data 66606514 # number of overall hits 857system.cpu.dcache.overall_hits::total 66606514 # number of overall hits 858system.cpu.dcache.ReadReq_misses::cpu.data 1017 # number of ReadReq misses 859system.cpu.dcache.ReadReq_misses::total 1017 # number of ReadReq misses 860system.cpu.dcache.WriteReq_misses::cpu.data 1771 # number of WriteReq misses 861system.cpu.dcache.WriteReq_misses::total 1771 # number of WriteReq misses 862system.cpu.dcache.demand_misses::cpu.data 2788 # number of demand (read+write) misses 863system.cpu.dcache.demand_misses::total 2788 # number of demand (read+write) misses 864system.cpu.dcache.overall_misses::cpu.data 2788 # number of overall misses 865system.cpu.dcache.overall_misses::total 2788 # number of overall misses 866system.cpu.dcache.ReadReq_miss_latency::cpu.data 61229380 # number of ReadReq miss cycles 867system.cpu.dcache.ReadReq_miss_latency::total 61229380 # number of ReadReq miss cycles 868system.cpu.dcache.WriteReq_miss_latency::cpu.data 115680725 # number of WriteReq miss cycles 869system.cpu.dcache.WriteReq_miss_latency::total 115680725 # number of WriteReq miss cycles 870system.cpu.dcache.demand_miss_latency::cpu.data 176910105 # number of demand (read+write) miss cycles 871system.cpu.dcache.demand_miss_latency::total 176910105 # number of demand (read+write) miss cycles 872system.cpu.dcache.overall_miss_latency::cpu.data 176910105 # number of overall miss cycles 873system.cpu.dcache.overall_miss_latency::total 176910105 # number of overall miss cycles 874system.cpu.dcache.ReadReq_accesses::cpu.data 46093571 # number of ReadReq accesses(hits+misses) 875system.cpu.dcache.ReadReq_accesses::total 46093571 # number of ReadReq accesses(hits+misses) |
| 875system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) 876system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) | 876system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) 877system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) |
| 877system.cpu.dcache.demand_accesses::cpu.data 66150427 # number of demand (read+write) accesses 878system.cpu.dcache.demand_accesses::total 66150427 # number of demand (read+write) accesses 879system.cpu.dcache.overall_accesses::cpu.data 66150427 # number of overall (read+write) accesses 880system.cpu.dcache.overall_accesses::total 66150427 # number of overall (read+write) accesses 881system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses 882system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses 883system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses 884system.cpu.dcache.WriteReq_miss_rate::total 0.000081 # miss rate for WriteReq accesses 885system.cpu.dcache.demand_miss_rate::cpu.data 0.000039 # miss rate for demand accesses 886system.cpu.dcache.demand_miss_rate::total 0.000039 # miss rate for demand accesses 887system.cpu.dcache.overall_miss_rate::cpu.data 0.000039 # miss rate for overall accesses 888system.cpu.dcache.overall_miss_rate::total 0.000039 # miss rate for overall accesses 889system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63903.305970 # average ReadReq miss latency 890system.cpu.dcache.ReadReq_avg_miss_latency::total 63903.305970 # average ReadReq miss latency 891system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67280.281699 # average WriteReq miss latency 892system.cpu.dcache.WriteReq_avg_miss_latency::total 67280.281699 # average WriteReq miss latency 893system.cpu.dcache.demand_avg_miss_latency::cpu.data 66066.640613 # average overall miss latency 894system.cpu.dcache.demand_avg_miss_latency::total 66066.640613 # average overall miss latency 895system.cpu.dcache.overall_avg_miss_latency::cpu.data 66066.640613 # average overall miss latency 896system.cpu.dcache.overall_avg_miss_latency::total 66066.640613 # average overall miss latency 897system.cpu.dcache.blocked_cycles::no_mshrs 322 # number of cycles access was blocked | 878system.cpu.dcache.demand_accesses::cpu.data 66609302 # number of demand (read+write) accesses 879system.cpu.dcache.demand_accesses::total 66609302 # number of demand (read+write) accesses 880system.cpu.dcache.overall_accesses::cpu.data 66609302 # number of overall (read+write) accesses 881system.cpu.dcache.overall_accesses::total 66609302 # number of overall (read+write) accesses 882system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses 883system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses 884system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000086 # miss rate for WriteReq accesses 885system.cpu.dcache.WriteReq_miss_rate::total 0.000086 # miss rate for WriteReq accesses 886system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 # miss rate for demand accesses 887system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses 888system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses 889system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses 890system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60205.880039 # average ReadReq miss latency 891system.cpu.dcache.ReadReq_avg_miss_latency::total 60205.880039 # average ReadReq miss latency 892system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65319.438171 # average WriteReq miss latency 893system.cpu.dcache.WriteReq_avg_miss_latency::total 65319.438171 # average WriteReq miss latency 894system.cpu.dcache.demand_avg_miss_latency::cpu.data 63454.126614 # average overall miss latency 895system.cpu.dcache.demand_avg_miss_latency::total 63454.126614 # average overall miss latency 896system.cpu.dcache.overall_avg_miss_latency::cpu.data 63454.126614 # average overall miss latency 897system.cpu.dcache.overall_avg_miss_latency::total 63454.126614 # average overall miss latency 898system.cpu.dcache.blocked_cycles::no_mshrs 94 # number of cycles access was blocked |
| 898system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 899system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 899system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked | 900system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked |
| 900system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 901system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 901system.cpu.dcache.avg_blocked_cycles::no_mshrs 80.500000 # average number of cycles each access was blocked | 902system.cpu.dcache.avg_blocked_cycles::no_mshrs 47 # average number of cycles each access was blocked |
| 902system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 903system.cpu.dcache.fast_writes 0 # number of fast writes performed 904system.cpu.dcache.cache_copies 0 # number of cache copies performed 905system.cpu.dcache.writebacks::writebacks 13 # number of writebacks 906system.cpu.dcache.writebacks::total 13 # number of writebacks | 903system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 904system.cpu.dcache.fast_writes 0 # number of fast writes performed 905system.cpu.dcache.cache_copies 0 # number of cache copies performed 906system.cpu.dcache.writebacks::writebacks 13 # number of writebacks 907system.cpu.dcache.writebacks::total 13 # number of writebacks |
| 907system.cpu.dcache.ReadReq_mshr_hits::cpu.data 470 # number of ReadReq MSHR hits 908system.cpu.dcache.ReadReq_mshr_hits::total 470 # number of ReadReq MSHR hits | 908system.cpu.dcache.ReadReq_mshr_hits::cpu.data 547 # number of ReadReq MSHR hits 909system.cpu.dcache.ReadReq_mshr_hits::total 547 # number of ReadReq MSHR hits |
| 909system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits 910system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits | 910system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits 911system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits |
| 911system.cpu.dcache.demand_mshr_hits::cpu.data 472 # number of demand (read+write) MSHR hits 912system.cpu.dcache.demand_mshr_hits::total 472 # number of demand (read+write) MSHR hits 913system.cpu.dcache.overall_mshr_hits::cpu.data 472 # number of overall MSHR hits 914system.cpu.dcache.overall_mshr_hits::total 472 # number of overall MSHR hits 915system.cpu.dcache.ReadReq_mshr_misses::cpu.data 468 # number of ReadReq MSHR misses 916system.cpu.dcache.ReadReq_mshr_misses::total 468 # number of ReadReq MSHR misses 917system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1670 # number of WriteReq MSHR misses 918system.cpu.dcache.WriteReq_mshr_misses::total 1670 # number of WriteReq MSHR misses 919system.cpu.dcache.demand_mshr_misses::cpu.data 2138 # number of demand (read+write) MSHR misses 920system.cpu.dcache.demand_mshr_misses::total 2138 # number of demand (read+write) MSHR misses 921system.cpu.dcache.overall_mshr_misses::cpu.data 2138 # number of overall MSHR misses 922system.cpu.dcache.overall_mshr_misses::total 2138 # number of overall MSHR misses 923system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32985750 # number of ReadReq MSHR miss cycles 924system.cpu.dcache.ReadReq_mshr_miss_latency::total 32985750 # number of ReadReq MSHR miss cycles 925system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 108417619 # number of WriteReq MSHR miss cycles 926system.cpu.dcache.WriteReq_mshr_miss_latency::total 108417619 # number of WriteReq MSHR miss cycles 927system.cpu.dcache.demand_mshr_miss_latency::cpu.data 141403369 # number of demand (read+write) MSHR miss cycles 928system.cpu.dcache.demand_mshr_miss_latency::total 141403369 # number of demand (read+write) MSHR miss cycles 929system.cpu.dcache.overall_mshr_miss_latency::cpu.data 141403369 # number of overall MSHR miss cycles 930system.cpu.dcache.overall_mshr_miss_latency::total 141403369 # number of overall MSHR miss cycles | 912system.cpu.dcache.demand_mshr_hits::cpu.data 549 # number of demand (read+write) MSHR hits 913system.cpu.dcache.demand_mshr_hits::total 549 # number of demand (read+write) MSHR hits 914system.cpu.dcache.overall_mshr_hits::cpu.data 549 # number of overall MSHR hits 915system.cpu.dcache.overall_mshr_hits::total 549 # number of overall MSHR hits 916system.cpu.dcache.ReadReq_mshr_misses::cpu.data 470 # number of ReadReq MSHR misses 917system.cpu.dcache.ReadReq_mshr_misses::total 470 # number of ReadReq MSHR misses 918system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1769 # number of WriteReq MSHR misses 919system.cpu.dcache.WriteReq_mshr_misses::total 1769 # number of WriteReq MSHR misses 920system.cpu.dcache.demand_mshr_misses::cpu.data 2239 # number of demand (read+write) MSHR misses 921system.cpu.dcache.demand_mshr_misses::total 2239 # number of demand (read+write) MSHR misses 922system.cpu.dcache.overall_mshr_misses::cpu.data 2239 # number of overall MSHR misses 923system.cpu.dcache.overall_mshr_misses::total 2239 # number of overall MSHR misses 924system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34113000 # number of ReadReq MSHR miss cycles 925system.cpu.dcache.ReadReq_mshr_miss_latency::total 34113000 # number of ReadReq MSHR miss cycles 926system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 111361525 # number of WriteReq MSHR miss cycles 927system.cpu.dcache.WriteReq_mshr_miss_latency::total 111361525 # number of WriteReq MSHR miss cycles 928system.cpu.dcache.demand_mshr_miss_latency::cpu.data 145474525 # number of demand (read+write) MSHR miss cycles 929system.cpu.dcache.demand_mshr_miss_latency::total 145474525 # number of demand (read+write) MSHR miss cycles 930system.cpu.dcache.overall_mshr_miss_latency::cpu.data 145474525 # number of overall MSHR miss cycles 931system.cpu.dcache.overall_mshr_miss_latency::total 145474525 # number of overall MSHR miss cycles |
| 931system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses 932system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses | 932system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses 933system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses |
| 933system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000081 # mshr miss rate for WriteReq accesses 934system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000081 # mshr miss rate for WriteReq accesses 935system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses 936system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses 937system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses 938system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses 939system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70482.371795 # average ReadReq mshr miss latency 940system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70482.371795 # average ReadReq mshr miss latency 941system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64920.729940 # average WriteReq mshr miss latency 942system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64920.729940 # average WriteReq mshr miss latency 943system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66138.152011 # average overall mshr miss latency 944system.cpu.dcache.demand_avg_mshr_miss_latency::total 66138.152011 # average overall mshr miss latency 945system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66138.152011 # average overall mshr miss latency 946system.cpu.dcache.overall_avg_mshr_miss_latency::total 66138.152011 # average overall mshr miss latency | 934system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000086 # mshr miss rate for WriteReq accesses 935system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000086 # mshr miss rate for WriteReq accesses 936system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for demand accesses 937system.cpu.dcache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses 938system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for overall accesses 939system.cpu.dcache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses 940system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72580.851064 # average ReadReq mshr miss latency 941system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72580.851064 # average ReadReq mshr miss latency 942system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62951.681741 # average WriteReq mshr miss latency 943system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62951.681741 # average WriteReq mshr miss latency 944system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64972.990174 # average overall mshr miss latency 945system.cpu.dcache.demand_avg_mshr_miss_latency::total 64972.990174 # average overall mshr miss latency 946system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64972.990174 # average overall mshr miss latency 947system.cpu.dcache.overall_avg_mshr_miss_latency::total 64972.990174 # average overall mshr miss latency |
| 947system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 948 949---------- End Simulation Statistics ---------- | 948system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 949 950---------- End Simulation Statistics ---------- |