1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.087752 # Number of seconds simulated 4sim_ticks 87751730000 # Number of ticks simulated 5final_tick 87751730000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 66952 # Simulator instruction rate (inst/s) 8host_op_rate 112217 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 44484510 # Simulator tick rate (ticks/s) 10host_mem_usage 236376 # Number of bytes of host memory used 11host_seconds 1972.64 # Real time elapsed on the host |
12sim_insts 132071227 # Number of instructions simulated 13sim_ops 221363017 # Number of ops (including micro ops) simulated |
14system.physmem.bytes_read::cpu.inst 219584 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 125440 # Number of bytes read from this memory 16system.physmem.bytes_read::total 345024 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 219584 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 219584 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 3431 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 1960 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 5391 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 2502332 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 1429487 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 3931820 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 2502332 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 2502332 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 2502332 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 1429487 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 3931820 # Total bandwidth to/from this memory (bytes/s) |
30system.cpu.workload.num_syscalls 400 # Number of system calls 31system.cpu.numCycles 175503461 # number of cpu cycles simulated 32system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 33system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 34system.cpu.BPredUnit.lookups 20929970 # Number of BP lookups 35system.cpu.BPredUnit.condPredicted 20929970 # Number of conditional branches predicted 36system.cpu.BPredUnit.condIncorrect 2208761 # Number of conditional branches incorrect 37system.cpu.BPredUnit.BTBLookups 15515509 # Number of BTB lookups --- 287 unchanged lines hidden (view full) --- 325system.cpu.icache.overall_miss_latency::total 187306000 # number of overall miss cycles 326system.cpu.icache.ReadReq_accesses::cpu.inst 25822554 # number of ReadReq accesses(hits+misses) 327system.cpu.icache.ReadReq_accesses::total 25822554 # number of ReadReq accesses(hits+misses) 328system.cpu.icache.demand_accesses::cpu.inst 25822554 # number of demand (read+write) accesses 329system.cpu.icache.demand_accesses::total 25822554 # number of demand (read+write) accesses 330system.cpu.icache.overall_accesses::cpu.inst 25822554 # number of overall (read+write) accesses 331system.cpu.icache.overall_accesses::total 25822554 # number of overall (read+write) accesses 332system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000352 # miss rate for ReadReq accesses |
333system.cpu.icache.ReadReq_miss_rate::total 0.000352 # miss rate for ReadReq accesses |
334system.cpu.icache.demand_miss_rate::cpu.inst 0.000352 # miss rate for demand accesses |
335system.cpu.icache.demand_miss_rate::total 0.000352 # miss rate for demand accesses |
336system.cpu.icache.overall_miss_rate::cpu.inst 0.000352 # miss rate for overall accesses |
337system.cpu.icache.overall_miss_rate::total 0.000352 # miss rate for overall accesses |
338system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20598.922248 # average ReadReq miss latency |
339system.cpu.icache.ReadReq_avg_miss_latency::total 20598.922248 # average ReadReq miss latency |
340system.cpu.icache.demand_avg_miss_latency::cpu.inst 20598.922248 # average overall miss latency |
341system.cpu.icache.demand_avg_miss_latency::total 20598.922248 # average overall miss latency |
342system.cpu.icache.overall_avg_miss_latency::cpu.inst 20598.922248 # average overall miss latency |
343system.cpu.icache.overall_avg_miss_latency::total 20598.922248 # average overall miss latency |
344system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 345system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 346system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 347system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 348system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 349system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 350system.cpu.icache.fast_writes 0 # number of fast writes performed 351system.cpu.icache.cache_copies 0 # number of cache copies performed --- 11 unchanged lines hidden (view full) --- 363system.cpu.icache.overall_mshr_misses::total 7726 # number of overall MSHR misses 364system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130634500 # number of ReadReq MSHR miss cycles 365system.cpu.icache.ReadReq_mshr_miss_latency::total 130634500 # number of ReadReq MSHR miss cycles 366system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130634500 # number of demand (read+write) MSHR miss cycles 367system.cpu.icache.demand_mshr_miss_latency::total 130634500 # number of demand (read+write) MSHR miss cycles 368system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130634500 # number of overall MSHR miss cycles 369system.cpu.icache.overall_mshr_miss_latency::total 130634500 # number of overall MSHR miss cycles 370system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for ReadReq accesses |
371system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000299 # mshr miss rate for ReadReq accesses |
372system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for demand accesses |
373system.cpu.icache.demand_mshr_miss_rate::total 0.000299 # mshr miss rate for demand accesses |
374system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for overall accesses |
375system.cpu.icache.overall_mshr_miss_rate::total 0.000299 # mshr miss rate for overall accesses |
376system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16908.426094 # average ReadReq mshr miss latency |
377system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16908.426094 # average ReadReq mshr miss latency |
378system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16908.426094 # average overall mshr miss latency |
379system.cpu.icache.demand_avg_mshr_miss_latency::total 16908.426094 # average overall mshr miss latency |
380system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16908.426094 # average overall mshr miss latency |
381system.cpu.icache.overall_avg_mshr_miss_latency::total 16908.426094 # average overall mshr miss latency |
382system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 383system.cpu.dcache.replacements 56 # number of replacements 384system.cpu.dcache.tagsinuse 1426.584624 # Cycle average of tags in use 385system.cpu.dcache.total_refs 68642098 # Total number of references to valid blocks. 386system.cpu.dcache.sampled_refs 1997 # Sample count of references to valid blocks. 387system.cpu.dcache.avg_refs 34372.607912 # Average number of references to valid blocks. 388system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 389system.cpu.dcache.occ_blocks::cpu.data 1426.584624 # Average occupied blocks per requestor --- 27 unchanged lines hidden (view full) --- 417system.cpu.dcache.ReadReq_accesses::total 48128652 # number of ReadReq accesses(hits+misses) 418system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) 419system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses) 420system.cpu.dcache.demand_accesses::cpu.data 68644382 # number of demand (read+write) accesses 421system.cpu.dcache.demand_accesses::total 68644382 # number of demand (read+write) accesses 422system.cpu.dcache.overall_accesses::cpu.data 68644382 # number of overall (read+write) accesses 423system.cpu.dcache.overall_accesses::total 68644382 # number of overall (read+write) accesses 424system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000016 # miss rate for ReadReq accesses |
425system.cpu.dcache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses |
426system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses |
427system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses |
428system.cpu.dcache.demand_miss_rate::cpu.data 0.000036 # miss rate for demand accesses |
429system.cpu.dcache.demand_miss_rate::total 0.000036 # miss rate for demand accesses |
430system.cpu.dcache.overall_miss_rate::cpu.data 0.000036 # miss rate for overall accesses |
431system.cpu.dcache.overall_miss_rate::total 0.000036 # miss rate for overall accesses |
432system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32154.792746 # average ReadReq miss latency |
433system.cpu.dcache.ReadReq_avg_miss_latency::total 32154.792746 # average ReadReq miss latency |
434system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37945.804196 # average WriteReq miss latency |
435system.cpu.dcache.WriteReq_avg_miss_latency::total 37945.804196 # average WriteReq miss latency |
436system.cpu.dcache.demand_avg_miss_latency::cpu.data 36148.914791 # average overall miss latency |
437system.cpu.dcache.demand_avg_miss_latency::total 36148.914791 # average overall miss latency |
438system.cpu.dcache.overall_avg_miss_latency::cpu.data 36148.914791 # average overall miss latency |
439system.cpu.dcache.overall_avg_miss_latency::total 36148.914791 # average overall miss latency |
440system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 441system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 442system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 443system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 444system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 445system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 446system.cpu.dcache.fast_writes 0 # number of fast writes performed 447system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 19 unchanged lines hidden (view full) --- 467system.cpu.dcache.ReadReq_mshr_miss_latency::total 14546500 # number of ReadReq MSHR miss cycles 468system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59868000 # number of WriteReq MSHR miss cycles 469system.cpu.dcache.WriteReq_mshr_miss_latency::total 59868000 # number of WriteReq MSHR miss cycles 470system.cpu.dcache.demand_mshr_miss_latency::cpu.data 74414500 # number of demand (read+write) MSHR miss cycles 471system.cpu.dcache.demand_mshr_miss_latency::total 74414500 # number of demand (read+write) MSHR miss cycles 472system.cpu.dcache.overall_mshr_miss_latency::cpu.data 74414500 # number of overall MSHR miss cycles 473system.cpu.dcache.overall_mshr_miss_latency::total 74414500 # number of overall MSHR miss cycles 474system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses |
475system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses |
476system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000083 # mshr miss rate for WriteReq accesses |
477system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000083 # mshr miss rate for WriteReq accesses |
478system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for demand accesses |
479system.cpu.dcache.demand_mshr_miss_rate::total 0.000031 # mshr miss rate for demand accesses |
480system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for overall accesses |
481system.cpu.dcache.overall_mshr_miss_rate::total 0.000031 # mshr miss rate for overall accesses |
482system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32985.260771 # average ReadReq mshr miss latency |
483system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32985.260771 # average ReadReq mshr miss latency |
484system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34949.211909 # average WriteReq mshr miss latency |
485system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34949.211909 # average WriteReq mshr miss latency |
486system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34547.121634 # average overall mshr miss latency |
487system.cpu.dcache.demand_avg_mshr_miss_latency::total 34547.121634 # average overall mshr miss latency |
488system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34547.121634 # average overall mshr miss latency |
489system.cpu.dcache.overall_avg_mshr_miss_latency::total 34547.121634 # average overall mshr miss latency |
490system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 491system.cpu.l2cache.replacements 0 # number of replacements 492system.cpu.l2cache.tagsinuse 2579.336511 # Cycle average of tags in use 493system.cpu.l2cache.total_refs 4173 # Total number of references to valid blocks. 494system.cpu.l2cache.sampled_refs 3841 # Sample count of references to valid blocks. 495system.cpu.l2cache.avg_refs 1.086436 # Average number of references to valid blocks. 496system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 497system.cpu.l2cache.occ_blocks::writebacks 1.713269 # Average occupied blocks per requestor --- 52 unchanged lines hidden (view full) --- 550system.cpu.l2cache.demand_accesses::cpu.inst 7571 # number of demand (read+write) accesses 551system.cpu.l2cache.demand_accesses::cpu.data 1999 # number of demand (read+write) accesses 552system.cpu.l2cache.demand_accesses::total 9570 # number of demand (read+write) accesses 553system.cpu.l2cache.overall_accesses::cpu.inst 7571 # number of overall (read+write) accesses 554system.cpu.l2cache.overall_accesses::cpu.data 1999 # number of overall (read+write) accesses 555system.cpu.l2cache.overall_accesses::total 9570 # number of overall (read+write) accesses 556system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.453177 # miss rate for ReadReq accesses 557system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.929545 # miss rate for ReadReq accesses |
558system.cpu.l2cache.ReadReq_miss_rate::total 0.479341 # miss rate for ReadReq accesses |
559system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses |
560system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses |
561system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994869 # miss rate for ReadExReq accesses |
562system.cpu.l2cache.ReadExReq_miss_rate::total 0.994869 # miss rate for ReadExReq accesses |
563system.cpu.l2cache.demand_miss_rate::cpu.inst 0.453177 # miss rate for demand accesses 564system.cpu.l2cache.demand_miss_rate::cpu.data 0.980490 # miss rate for demand accesses |
565system.cpu.l2cache.demand_miss_rate::total 0.563323 # miss rate for demand accesses |
566system.cpu.l2cache.overall_miss_rate::cpu.inst 0.453177 # miss rate for overall accesses 567system.cpu.l2cache.overall_miss_rate::cpu.data 0.980490 # miss rate for overall accesses |
568system.cpu.l2cache.overall_miss_rate::total 0.563323 # miss rate for overall accesses |
569system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34251.967356 # average ReadReq miss latency 570system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34172.371638 # average ReadReq miss latency |
571system.cpu.l2cache.ReadReq_avg_miss_latency::total 34243.489583 # average ReadReq miss latency |
572system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34168.923275 # average ReadExReq miss latency |
573system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34168.923275 # average ReadExReq miss latency |
574system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34251.967356 # average overall miss latency 575system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34169.642857 # average overall miss latency |
576system.cpu.l2cache.demand_avg_miss_latency::total 34222.036728 # average overall miss latency |
577system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34251.967356 # average overall miss latency 578system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34169.642857 # average overall miss latency |
579system.cpu.l2cache.overall_avg_miss_latency::total 34222.036728 # average overall miss latency |
580system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 581system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 582system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 583system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 584system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 585system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 586system.cpu.l2cache.fast_writes 0 # number of fast writes performed 587system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 20 unchanged lines hidden (view full) --- 608system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106440500 # number of demand (read+write) MSHR miss cycles 609system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 60787000 # number of demand (read+write) MSHR miss cycles 610system.cpu.l2cache.demand_mshr_miss_latency::total 167227500 # number of demand (read+write) MSHR miss cycles 611system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106440500 # number of overall MSHR miss cycles 612system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 60787000 # number of overall MSHR miss cycles 613system.cpu.l2cache.overall_mshr_miss_latency::total 167227500 # number of overall MSHR miss cycles 614system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for ReadReq accesses 615system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.929545 # mshr miss rate for ReadReq accesses |
616system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.479341 # mshr miss rate for ReadReq accesses |
617system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses |
618system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses |
619system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994869 # mshr miss rate for ReadExReq accesses |
620system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994869 # mshr miss rate for ReadExReq accesses |
621system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for demand accesses 622system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980490 # mshr miss rate for demand accesses |
623system.cpu.l2cache.demand_mshr_miss_rate::total 0.563323 # mshr miss rate for demand accesses |
624system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for overall accesses 625system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980490 # mshr miss rate for overall accesses |
626system.cpu.l2cache.overall_mshr_miss_rate::total 0.563323 # mshr miss rate for overall accesses |
627system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31023.171087 # average ReadReq mshr miss latency 628system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30993.887531 # average ReadReq mshr miss latency |
629system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31020.052083 # average ReadReq mshr miss latency |
630system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency |
631system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency |
632system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31019.019987 # average ReadExReq mshr miss latency |
633system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31019.019987 # average ReadExReq mshr miss latency |
634system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31023.171087 # average overall mshr miss latency 635system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31013.775510 # average overall mshr miss latency |
636system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31019.755147 # average overall mshr miss latency |
637system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31023.171087 # average overall mshr miss latency 638system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31013.775510 # average overall mshr miss latency |
639system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31019.755147 # average overall mshr miss latency |
640system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 641 642---------- End Simulation Statistics ---------- |