7,11c7,11
< host_inst_rate 66822 # Simulator instruction rate (inst/s)
< host_op_rate 111999 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 73091533 # Simulator tick rate (ticks/s)
< host_mem_usage 308580 # Number of bytes of host memory used
< host_seconds 1976.47 # Real time elapsed on the host
---
> host_inst_rate 55445 # Simulator instruction rate (inst/s)
> host_op_rate 92931 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 60647702 # Simulator tick rate (ticks/s)
> host_mem_usage 328672 # Number of bytes of host memory used
> host_seconds 2382.01 # Real time elapsed on the host
210,211c210,211
< system.physmem.totQLat 28805000 # Total ticks spent queuing
< system.physmem.totMemAccLat 137868750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 28783000 # Total ticks spent queuing
> system.physmem.totMemAccLat 137846750 # Total ticks spent from burst creation until serviced by the DRAM
214c214
< system.physmem.avgQLat 5380.09 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 5375.98 # Average queueing delay per DRAM burst
217c217
< system.physmem.avgMemAccLat 25750.61 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 25746.50 # Average memory access latency per DRAM burst
250c250
< system.membus.reqLayer0.occupancy 6948500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 6950000 # Layer occupancy (ticks)
254,255c254,255
< system.cpu.branchPred.lookups 18648234 # Number of BP lookups
< system.cpu.branchPred.condPredicted 18648234 # Number of conditional branches predicted
---
> system.cpu.branchPred.lookups 18648233 # Number of BP lookups
> system.cpu.branchPred.condPredicted 18648233 # Number of conditional branches predicted
267,269c267,269
< system.cpu.fetch.icacheStallCycles 23458037 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 206724223 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 18648234 # Number of branches that fetch encountered
---
> system.cpu.fetch.icacheStallCycles 23458043 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 206724218 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 18648233 # Number of branches that fetch encountered
271,272c271,272
< system.cpu.fetch.Cycles 54209099 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 15518775 # Number of cycles fetch has spent squashing
---
> system.cpu.fetch.Cycles 54209097 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 15518774 # Number of cycles fetch has spent squashing
277,279c277,279
< system.cpu.fetch.CacheLines 22353213 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 224062 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 269612466 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 22353211 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 224061 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 269612469 # Number of instructions fetched each cycle (Total)
283c283
< system.cpu.fetch.rateDist::0 216842558 80.43% 80.43% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 216842563 80.43% 80.43% # Number of instructions fetched each cycle (Total)
285c285
< system.cpu.fetch.rateDist::2 2312056 0.86% 82.34% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::2 2312055 0.86% 82.34% # Number of instructions fetched each cycle (Total)
291c291
< system.cpu.fetch.rateDist::8 31977576 11.86% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::8 31977575 11.86% 100.00% # Number of instructions fetched each cycle (Total)
295c295
< system.cpu.fetch.rateDist::total 269612466 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 269612469 # Number of instructions fetched each cycle (Total)
298,300c298,300
< system.cpu.decode.IdleCycles 36899349 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 167130008 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 41545231 # Number of cycles decode is running
---
> system.cpu.decode.IdleCycles 36899359 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 167130004 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 41545229 # Number of cycles decode is running
302,306c302,306
< system.cpu.decode.SquashCycles 13773251 # Number of cycles decode is squashing
< system.cpu.decode.DecodedInsts 336001478 # Number of instructions handled by decode
< system.cpu.rename.SquashCycles 13773251 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 44972476 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 116686700 # Number of cycles rename is blocking
---
> system.cpu.decode.SquashCycles 13773250 # Number of cycles decode is squashing
> system.cpu.decode.DecodedInsts 336001462 # Number of instructions handled by decode
> system.cpu.rename.SquashCycles 13773250 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 44972487 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 116686698 # Number of cycles rename is blocking
308,310c308,310
< system.cpu.rename.RunCycles 42701692 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 51445802 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 329633797 # Number of instructions processed by rename
---
> system.cpu.rename.RunCycles 42701689 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 51445800 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 329633775 # Number of instructions processed by rename
313,316c313,316
< system.cpu.rename.LSQFullEvents 22730551 # Number of times rename has blocked due to LSQ full
< system.cpu.rename.RenamedOperands 382342114 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 917586762 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 605878307 # Number of integer rename lookups
---
> system.cpu.rename.LSQFullEvents 22730549 # Number of times rename has blocked due to LSQ full
> system.cpu.rename.RenamedOperands 382342090 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 917586713 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 605878272 # Number of integer rename lookups
319c319
< system.cpu.rename.UndoneMaps 122912664 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 122912640 # Number of HB maps that are undone due to squashing
322,323c322,323
< system.cpu.rename.skidInsts 105140053 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 84507278 # Number of loads inserted to the mem dependence unit.
---
> system.cpu.rename.skidInsts 105140052 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 84507276 # Number of loads inserted to the mem dependence unit.
327c327
< system.cpu.iq.iqInstsAdded 322730912 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 322730905 # Number of instructions added to the IQ (excludes non-spec)
329c329
< system.cpu.iq.iqInstsIssued 260501997 # Number of instructions issued
---
> system.cpu.iq.iqInstsIssued 260501994 # Number of instructions issued
331,332c331,332
< system.cpu.iq.iqSquashedInstsExamined 100987198 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 210203666 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedInstsExamined 100987191 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 210203655 # Number of squashed operands that are examined and possibly removed from graph
334c334
< system.cpu.iq.issued_per_cycle::samples 269612466 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 269612469 # Number of insts issued each cycle
338,344c338,344
< system.cpu.iq.issued_per_cycle::0 143429906 53.20% 53.20% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 55567349 20.61% 73.81% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 34108146 12.65% 86.46% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 19044984 7.06% 93.52% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 10887633 4.04% 97.56% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 4152281 1.54% 99.10% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 1816698 0.67% 99.78% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 143429912 53.20% 53.20% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 55567346 20.61% 73.81% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 34108148 12.65% 86.46% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 19044980 7.06% 93.52% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 10887634 4.04% 97.56% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 4152283 1.54% 99.10% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 1816697 0.67% 99.78% # Number of insts issued each cycle
350c350
< system.cpu.iq.issued_per_cycle::total 269612466 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 269612469 # Number of insts issued each cycle
386c386
< system.cpu.iq.FU_type_0::IntAlu 162055945 62.21% 62.67% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 162055944 62.21% 62.67% # Type of FU issued
415c415
< system.cpu.iq.FU_type_0::MemRead 65414515 25.11% 91.34% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 65414513 25.11% 91.34% # Type of FU issued
419,420c419,420
< system.cpu.iq.FU_type_0::total 260501997 # Type of FU issued
< system.cpu.iq.rate 0.900700 # Inst issue rate
---
> system.cpu.iq.FU_type_0::total 260501994 # Type of FU issued
> system.cpu.iq.rate 0.900699 # Inst issue rate
423,425c423,425
< system.cpu.iq.int_inst_queue_reads 788557581 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 420384882 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 255147074 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.int_inst_queue_reads 788557578 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 420384868 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 255147075 # Number of integer instruction queue wakeup accesses
429c429
< system.cpu.iq.int_alu_accesses 259544029 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 259544026 # Number of integer alu accesses
431c431
< system.cpu.iew.lsq.thread0.forwLoads 18903383 # Number of loads that had data forwarded from stores
---
> system.cpu.iew.lsq.thread0.forwLoads 18903382 # Number of loads that had data forwarded from stores
433,434c433,434
< system.cpu.iew.lsq.thread0.squashedLoads 27857691 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 25993 # Number of memory responses ignored because the instruction is squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 27857689 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 25992 # Number of memory responses ignored because the instruction is squashed
442,443c442,443
< system.cpu.iew.iewSquashCycles 13773251 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 85040641 # Number of cycles IEW is blocking
---
> system.cpu.iew.iewSquashCycles 13773250 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 85040639 # Number of cycles IEW is blocking
445c445
< system.cpu.iew.iewDispatchedInsts 322734981 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewDispatchedInsts 322734974 # Number of instructions dispatched to IQ
447c447
< system.cpu.iew.iewDispLoadInsts 84507278 # Number of dispatched load instructions
---
> system.cpu.iew.iewDispLoadInsts 84507276 # Number of dispatched load instructions
454,455c454,455
< system.cpu.iew.predictedNotTakenIncorrect 901241 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 1540639 # Number of branch mispredicts detected at execute
---
> system.cpu.iew.predictedNotTakenIncorrect 901242 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 1540640 # Number of branch mispredicts detected at execute
458c458
< system.cpu.iew.iewExecSquashedInsts 1769566 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecSquashedInsts 1769563 # Number of squashed instructions skipped in execute
462c462
< system.cpu.iew.exec_branches 14265860 # Number of branches executed
---
> system.cpu.iew.exec_branches 14265859 # Number of branches executed
465,466c465,466
< system.cpu.iew.wb_sent 258096694 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 257496638 # cumulative count of insts written-back
---
> system.cpu.iew.wb_sent 258096693 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 257496639 # cumulative count of insts written-back
468c468
< system.cpu.iew.wb_consumers 369130532 # num instructions consuming a value
---
> system.cpu.iew.wb_consumers 369130530 # num instructions consuming a value
473c473
< system.cpu.commit.commitSquashedInsts 101448847 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 101448840 # The number of squashed insts skipped by commit
476c476
< system.cpu.commit.committed_per_cycle::samples 255839215 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 255839219 # Number of insts commited each cycle
480c480
< system.cpu.commit.committed_per_cycle::0 156486613 61.17% 61.17% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 156486617 61.17% 61.17% # Number of insts commited each cycle
483,488c483,488
< system.cpu.commit.committed_per_cycle::3 12054069 4.71% 93.73% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 4176262 1.63% 95.37% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 2944385 1.15% 96.52% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 904563 0.35% 96.87% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 1049057 0.41% 97.28% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 6958755 2.72% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::3 12054068 4.71% 93.73% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 4176261 1.63% 95.37% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 2944387 1.15% 96.52% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 904564 0.35% 96.87% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 1049058 0.41% 97.28% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 6958753 2.72% 100.00% # Number of insts commited each cycle
492c492
< system.cpu.commit.committed_per_cycle::total 255839215 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 255839219 # Number of insts commited each cycle
503c503
< system.cpu.commit.bw_lim_events 6958755 # number cycles where commit BW limit reached
---
> system.cpu.commit.bw_lim_events 6958753 # number cycles where commit BW limit reached
505,506c505,506
< system.cpu.rob.rob_reads 571692691 # The number of ROB reads
< system.cpu.rob.rob_writes 659422929 # The number of ROB writes
---
> system.cpu.rob.rob_reads 571692690 # The number of ROB reads
> system.cpu.rob.rob_writes 659422914 # The number of ROB writes
508c508
< system.cpu.idleCycles 19609407 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 19609404 # Total number of cycles that the CPU has spent unscheduled due to idling
516c516
< system.cpu.int_regfile_reads 451224157 # number of integer regfile reads
---
> system.cpu.int_regfile_reads 451224153 # number of integer regfile reads
520,522c520,522
< system.cpu.cc_regfile_reads 102809518 # number of cc regfile reads
< system.cpu.cc_regfile_writes 59799385 # number of cc regfile writes
< system.cpu.misc_regfile_reads 133324418 # number of misc regfile reads
---
> system.cpu.cc_regfile_reads 102809513 # number of cc regfile reads
> system.cpu.cc_regfile_writes 59799383 # number of cc regfile writes
> system.cpu.misc_regfile_reads 133324417 # number of misc regfile reads
548c548
< system.cpu.icache.tags.total_refs 22344301 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.total_refs 22344300 # Total number of references to valid blocks.
550c550
< system.cpu.icache.tags.avg_refs 3375.272054 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 3375.271903 # Average number of references to valid blocks.
555,578c555,578
< system.cpu.icache.ReadReq_hits::cpu.inst 22344301 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 22344301 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 22344301 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 22344301 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 22344301 # number of overall hits
< system.cpu.icache.overall_hits::total 22344301 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 8911 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 8911 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 8911 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 8911 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 8911 # number of overall misses
< system.cpu.icache.overall_misses::total 8911 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 368225749 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 368225749 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 368225749 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 368225749 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 368225749 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 368225749 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 22353212 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 22353212 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 22353212 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 22353212 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 22353212 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 22353212 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_hits::cpu.inst 22344300 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 22344300 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 22344300 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 22344300 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 22344300 # number of overall hits
> system.cpu.icache.overall_hits::total 22344300 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 8910 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 8910 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 8910 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 8910 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 8910 # number of overall misses
> system.cpu.icache.overall_misses::total 8910 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 368144999 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 368144999 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 368144999 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 368144999 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 368144999 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 368144999 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 22353210 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 22353210 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 22353210 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 22353210 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 22353210 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 22353210 # number of overall (read+write) accesses
585,590c585,590
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41322.606778 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 41322.606778 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 41322.606778 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 41322.606778 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 41322.606778 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 41322.606778 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41318.181706 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 41318.181706 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 41318.181706 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 41318.181706 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 41318.181706 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 41318.181706 # average overall miss latency
599,604c599,604
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2127 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 2127 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 2127 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 2127 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 2127 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 2127 # number of overall MSHR hits
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2126 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 2126 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 2126 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 2126 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 2126 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 2126 # number of overall MSHR hits
611,616c611,616
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 271661249 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 271661249 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 271661249 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 271661249 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 271661249 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 271661249 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 271638749 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 271638749 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 271638749 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 271638749 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 271638749 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 271638749 # number of overall MSHR miss cycles
623,628c623,628
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40044.405808 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40044.405808 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40044.405808 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 40044.405808 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40044.405808 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 40044.405808 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40041.089180 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40041.089180 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40041.089180 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 40041.089180 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40041.089180 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 40041.089180 # average overall mshr miss latency
631c631
< system.cpu.l2cache.tags.tagsinuse 2543.926921 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 2543.926920 # Cycle average of tags in use
637c637
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 2230.334816 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 2230.334814 # Average occupied blocks per requestor
669c669
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 232439500 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 232417000 # number of ReadReq miss cycles
671c671
< system.cpu.l2cache.ReadReq_miss_latency::total 265195000 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::total 265172500 # number of ReadReq miss cycles
674c674
< system.cpu.l2cache.demand_miss_latency::cpu.inst 232439500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 232417000 # number of demand (read+write) miss cycles
676,677c676,677
< system.cpu.l2cache.demand_miss_latency::total 369629000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 232439500 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::total 369606500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 232417000 # number of overall miss cycles
679c679
< system.cpu.l2cache.overall_miss_latency::total 369629000 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::total 369606500 # number of overall miss cycles
708c708
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68505.599764 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68498.968464 # average ReadReq miss latency
710c710
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 69368.297149 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 69362.411719 # average ReadReq miss latency
713c713
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68505.599764 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68498.968464 # average overall miss latency
715,716c715,716
< system.cpu.l2cache.demand_avg_miss_latency::total 69025.023343 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68505.599764 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::total 69020.821662 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68498.968464 # average overall miss latency
718c718
< system.cpu.l2cache.overall_avg_miss_latency::total 69025.023343 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::total 69020.821662 # average overall miss latency
740c740
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 189922000 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 189899500 # number of ReadReq MSHR miss cycles
742c742
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 217348500 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 217326000 # number of ReadReq MSHR miss cycles
747c747
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 189922000 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 189899500 # number of demand (read+write) MSHR miss cycles
749,750c749,750
< system.cpu.l2cache.demand_mshr_miss_latency::total 302222500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 189922000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::total 302200000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 189899500 # number of overall MSHR miss cycles
752c752
< system.cpu.l2cache.overall_mshr_miss_latency::total 302222500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::total 302200000 # number of overall MSHR miss cycles
766c766
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55974.653699 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55968.022399 # average ReadReq mshr miss latency
768c768
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56852.864243 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56846.978812 # average ReadReq mshr miss latency
773c773
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55974.653699 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55968.022399 # average overall mshr miss latency
775,776c775,776
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56437.441643 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55974.653699 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56433.239963 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55968.022399 # average overall mshr miss latency
778c778
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56437.441643 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56433.239963 # average overall mshr miss latency
782c782
< system.cpu.dcache.tags.total_refs 66102355 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 66102356 # Total number of references to valid blocks.
784c784
< system.cpu.dcache.tags.avg_refs 32985.207086 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 32985.207585 # Average number of references to valid blocks.
789,790c789,790
< system.cpu.dcache.ReadReq_hits::cpu.data 45588096 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 45588096 # number of ReadReq hits
---
> system.cpu.dcache.ReadReq_hits::cpu.data 45588097 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 45588097 # number of ReadReq hits
793,796c793,796
< system.cpu.dcache.demand_hits::cpu.data 66102125 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 66102125 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 66102125 # number of overall hits
< system.cpu.dcache.overall_hits::total 66102125 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 66102126 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 66102126 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 66102126 # number of overall hits
> system.cpu.dcache.overall_hits::total 66102126 # number of overall hits
813,814c813,814
< system.cpu.dcache.ReadReq_accesses::cpu.data 45589031 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 45589031 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_accesses::cpu.data 45589032 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 45589032 # number of ReadReq accesses(hits+misses)
817,820c817,820
< system.cpu.dcache.demand_accesses::cpu.data 66104762 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 66104762 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 66104762 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 66104762 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 66104763 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 66104763 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 66104763 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 66104763 # number of overall (read+write) accesses
< host_inst_rate 66822 # Simulator instruction rate (inst/s)
< host_op_rate 111999 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 73091533 # Simulator tick rate (ticks/s)
< host_mem_usage 308580 # Number of bytes of host memory used
< host_seconds 1976.47 # Real time elapsed on the host
---
> host_inst_rate 55445 # Simulator instruction rate (inst/s)
> host_op_rate 92931 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 60647702 # Simulator tick rate (ticks/s)
> host_mem_usage 328672 # Number of bytes of host memory used
> host_seconds 2382.01 # Real time elapsed on the host
210,211c210,211
< system.physmem.totQLat 28805000 # Total ticks spent queuing
< system.physmem.totMemAccLat 137868750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 28783000 # Total ticks spent queuing
> system.physmem.totMemAccLat 137846750 # Total ticks spent from burst creation until serviced by the DRAM
214c214
< system.physmem.avgQLat 5380.09 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 5375.98 # Average queueing delay per DRAM burst
217c217
< system.physmem.avgMemAccLat 25750.61 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 25746.50 # Average memory access latency per DRAM burst
250c250
< system.membus.reqLayer0.occupancy 6948500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 6950000 # Layer occupancy (ticks)
254,255c254,255
< system.cpu.branchPred.lookups 18648234 # Number of BP lookups
< system.cpu.branchPred.condPredicted 18648234 # Number of conditional branches predicted
---
> system.cpu.branchPred.lookups 18648233 # Number of BP lookups
> system.cpu.branchPred.condPredicted 18648233 # Number of conditional branches predicted
267,269c267,269
< system.cpu.fetch.icacheStallCycles 23458037 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 206724223 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 18648234 # Number of branches that fetch encountered
---
> system.cpu.fetch.icacheStallCycles 23458043 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 206724218 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 18648233 # Number of branches that fetch encountered
271,272c271,272
< system.cpu.fetch.Cycles 54209099 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 15518775 # Number of cycles fetch has spent squashing
---
> system.cpu.fetch.Cycles 54209097 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 15518774 # Number of cycles fetch has spent squashing
277,279c277,279
< system.cpu.fetch.CacheLines 22353213 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 224062 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 269612466 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 22353211 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 224061 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 269612469 # Number of instructions fetched each cycle (Total)
283c283
< system.cpu.fetch.rateDist::0 216842558 80.43% 80.43% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 216842563 80.43% 80.43% # Number of instructions fetched each cycle (Total)
285c285
< system.cpu.fetch.rateDist::2 2312056 0.86% 82.34% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::2 2312055 0.86% 82.34% # Number of instructions fetched each cycle (Total)
291c291
< system.cpu.fetch.rateDist::8 31977576 11.86% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::8 31977575 11.86% 100.00% # Number of instructions fetched each cycle (Total)
295c295
< system.cpu.fetch.rateDist::total 269612466 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 269612469 # Number of instructions fetched each cycle (Total)
298,300c298,300
< system.cpu.decode.IdleCycles 36899349 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 167130008 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 41545231 # Number of cycles decode is running
---
> system.cpu.decode.IdleCycles 36899359 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 167130004 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 41545229 # Number of cycles decode is running
302,306c302,306
< system.cpu.decode.SquashCycles 13773251 # Number of cycles decode is squashing
< system.cpu.decode.DecodedInsts 336001478 # Number of instructions handled by decode
< system.cpu.rename.SquashCycles 13773251 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 44972476 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 116686700 # Number of cycles rename is blocking
---
> system.cpu.decode.SquashCycles 13773250 # Number of cycles decode is squashing
> system.cpu.decode.DecodedInsts 336001462 # Number of instructions handled by decode
> system.cpu.rename.SquashCycles 13773250 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 44972487 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 116686698 # Number of cycles rename is blocking
308,310c308,310
< system.cpu.rename.RunCycles 42701692 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 51445802 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 329633797 # Number of instructions processed by rename
---
> system.cpu.rename.RunCycles 42701689 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 51445800 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 329633775 # Number of instructions processed by rename
313,316c313,316
< system.cpu.rename.LSQFullEvents 22730551 # Number of times rename has blocked due to LSQ full
< system.cpu.rename.RenamedOperands 382342114 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 917586762 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 605878307 # Number of integer rename lookups
---
> system.cpu.rename.LSQFullEvents 22730549 # Number of times rename has blocked due to LSQ full
> system.cpu.rename.RenamedOperands 382342090 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 917586713 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 605878272 # Number of integer rename lookups
319c319
< system.cpu.rename.UndoneMaps 122912664 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 122912640 # Number of HB maps that are undone due to squashing
322,323c322,323
< system.cpu.rename.skidInsts 105140053 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 84507278 # Number of loads inserted to the mem dependence unit.
---
> system.cpu.rename.skidInsts 105140052 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 84507276 # Number of loads inserted to the mem dependence unit.
327c327
< system.cpu.iq.iqInstsAdded 322730912 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 322730905 # Number of instructions added to the IQ (excludes non-spec)
329c329
< system.cpu.iq.iqInstsIssued 260501997 # Number of instructions issued
---
> system.cpu.iq.iqInstsIssued 260501994 # Number of instructions issued
331,332c331,332
< system.cpu.iq.iqSquashedInstsExamined 100987198 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 210203666 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedInstsExamined 100987191 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 210203655 # Number of squashed operands that are examined and possibly removed from graph
334c334
< system.cpu.iq.issued_per_cycle::samples 269612466 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 269612469 # Number of insts issued each cycle
338,344c338,344
< system.cpu.iq.issued_per_cycle::0 143429906 53.20% 53.20% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 55567349 20.61% 73.81% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 34108146 12.65% 86.46% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 19044984 7.06% 93.52% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 10887633 4.04% 97.56% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 4152281 1.54% 99.10% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 1816698 0.67% 99.78% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 143429912 53.20% 53.20% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 55567346 20.61% 73.81% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 34108148 12.65% 86.46% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 19044980 7.06% 93.52% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 10887634 4.04% 97.56% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 4152283 1.54% 99.10% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 1816697 0.67% 99.78% # Number of insts issued each cycle
350c350
< system.cpu.iq.issued_per_cycle::total 269612466 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 269612469 # Number of insts issued each cycle
386c386
< system.cpu.iq.FU_type_0::IntAlu 162055945 62.21% 62.67% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 162055944 62.21% 62.67% # Type of FU issued
415c415
< system.cpu.iq.FU_type_0::MemRead 65414515 25.11% 91.34% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 65414513 25.11% 91.34% # Type of FU issued
419,420c419,420
< system.cpu.iq.FU_type_0::total 260501997 # Type of FU issued
< system.cpu.iq.rate 0.900700 # Inst issue rate
---
> system.cpu.iq.FU_type_0::total 260501994 # Type of FU issued
> system.cpu.iq.rate 0.900699 # Inst issue rate
423,425c423,425
< system.cpu.iq.int_inst_queue_reads 788557581 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 420384882 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 255147074 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.int_inst_queue_reads 788557578 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 420384868 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 255147075 # Number of integer instruction queue wakeup accesses
429c429
< system.cpu.iq.int_alu_accesses 259544029 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 259544026 # Number of integer alu accesses
431c431
< system.cpu.iew.lsq.thread0.forwLoads 18903383 # Number of loads that had data forwarded from stores
---
> system.cpu.iew.lsq.thread0.forwLoads 18903382 # Number of loads that had data forwarded from stores
433,434c433,434
< system.cpu.iew.lsq.thread0.squashedLoads 27857691 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 25993 # Number of memory responses ignored because the instruction is squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 27857689 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 25992 # Number of memory responses ignored because the instruction is squashed
442,443c442,443
< system.cpu.iew.iewSquashCycles 13773251 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 85040641 # Number of cycles IEW is blocking
---
> system.cpu.iew.iewSquashCycles 13773250 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 85040639 # Number of cycles IEW is blocking
445c445
< system.cpu.iew.iewDispatchedInsts 322734981 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewDispatchedInsts 322734974 # Number of instructions dispatched to IQ
447c447
< system.cpu.iew.iewDispLoadInsts 84507278 # Number of dispatched load instructions
---
> system.cpu.iew.iewDispLoadInsts 84507276 # Number of dispatched load instructions
454,455c454,455
< system.cpu.iew.predictedNotTakenIncorrect 901241 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 1540639 # Number of branch mispredicts detected at execute
---
> system.cpu.iew.predictedNotTakenIncorrect 901242 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 1540640 # Number of branch mispredicts detected at execute
458c458
< system.cpu.iew.iewExecSquashedInsts 1769566 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecSquashedInsts 1769563 # Number of squashed instructions skipped in execute
462c462
< system.cpu.iew.exec_branches 14265860 # Number of branches executed
---
> system.cpu.iew.exec_branches 14265859 # Number of branches executed
465,466c465,466
< system.cpu.iew.wb_sent 258096694 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 257496638 # cumulative count of insts written-back
---
> system.cpu.iew.wb_sent 258096693 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 257496639 # cumulative count of insts written-back
468c468
< system.cpu.iew.wb_consumers 369130532 # num instructions consuming a value
---
> system.cpu.iew.wb_consumers 369130530 # num instructions consuming a value
473c473
< system.cpu.commit.commitSquashedInsts 101448847 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 101448840 # The number of squashed insts skipped by commit
476c476
< system.cpu.commit.committed_per_cycle::samples 255839215 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 255839219 # Number of insts commited each cycle
480c480
< system.cpu.commit.committed_per_cycle::0 156486613 61.17% 61.17% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 156486617 61.17% 61.17% # Number of insts commited each cycle
483,488c483,488
< system.cpu.commit.committed_per_cycle::3 12054069 4.71% 93.73% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 4176262 1.63% 95.37% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 2944385 1.15% 96.52% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 904563 0.35% 96.87% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 1049057 0.41% 97.28% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 6958755 2.72% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::3 12054068 4.71% 93.73% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 4176261 1.63% 95.37% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 2944387 1.15% 96.52% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 904564 0.35% 96.87% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 1049058 0.41% 97.28% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 6958753 2.72% 100.00% # Number of insts commited each cycle
492c492
< system.cpu.commit.committed_per_cycle::total 255839215 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 255839219 # Number of insts commited each cycle
503c503
< system.cpu.commit.bw_lim_events 6958755 # number cycles where commit BW limit reached
---
> system.cpu.commit.bw_lim_events 6958753 # number cycles where commit BW limit reached
505,506c505,506
< system.cpu.rob.rob_reads 571692691 # The number of ROB reads
< system.cpu.rob.rob_writes 659422929 # The number of ROB writes
---
> system.cpu.rob.rob_reads 571692690 # The number of ROB reads
> system.cpu.rob.rob_writes 659422914 # The number of ROB writes
508c508
< system.cpu.idleCycles 19609407 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 19609404 # Total number of cycles that the CPU has spent unscheduled due to idling
516c516
< system.cpu.int_regfile_reads 451224157 # number of integer regfile reads
---
> system.cpu.int_regfile_reads 451224153 # number of integer regfile reads
520,522c520,522
< system.cpu.cc_regfile_reads 102809518 # number of cc regfile reads
< system.cpu.cc_regfile_writes 59799385 # number of cc regfile writes
< system.cpu.misc_regfile_reads 133324418 # number of misc regfile reads
---
> system.cpu.cc_regfile_reads 102809513 # number of cc regfile reads
> system.cpu.cc_regfile_writes 59799383 # number of cc regfile writes
> system.cpu.misc_regfile_reads 133324417 # number of misc regfile reads
548c548
< system.cpu.icache.tags.total_refs 22344301 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.total_refs 22344300 # Total number of references to valid blocks.
550c550
< system.cpu.icache.tags.avg_refs 3375.272054 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 3375.271903 # Average number of references to valid blocks.
555,578c555,578
< system.cpu.icache.ReadReq_hits::cpu.inst 22344301 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 22344301 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 22344301 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 22344301 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 22344301 # number of overall hits
< system.cpu.icache.overall_hits::total 22344301 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 8911 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 8911 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 8911 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 8911 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 8911 # number of overall misses
< system.cpu.icache.overall_misses::total 8911 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 368225749 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 368225749 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 368225749 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 368225749 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 368225749 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 368225749 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 22353212 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 22353212 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 22353212 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 22353212 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 22353212 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 22353212 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_hits::cpu.inst 22344300 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 22344300 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 22344300 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 22344300 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 22344300 # number of overall hits
> system.cpu.icache.overall_hits::total 22344300 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 8910 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 8910 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 8910 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 8910 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 8910 # number of overall misses
> system.cpu.icache.overall_misses::total 8910 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 368144999 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 368144999 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 368144999 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 368144999 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 368144999 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 368144999 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 22353210 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 22353210 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 22353210 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 22353210 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 22353210 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 22353210 # number of overall (read+write) accesses
585,590c585,590
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41322.606778 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 41322.606778 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 41322.606778 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 41322.606778 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 41322.606778 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 41322.606778 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41318.181706 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 41318.181706 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 41318.181706 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 41318.181706 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 41318.181706 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 41318.181706 # average overall miss latency
599,604c599,604
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2127 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 2127 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 2127 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 2127 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 2127 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 2127 # number of overall MSHR hits
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2126 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 2126 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 2126 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 2126 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 2126 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 2126 # number of overall MSHR hits
611,616c611,616
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 271661249 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 271661249 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 271661249 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 271661249 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 271661249 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 271661249 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 271638749 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 271638749 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 271638749 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 271638749 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 271638749 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 271638749 # number of overall MSHR miss cycles
623,628c623,628
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40044.405808 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40044.405808 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40044.405808 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 40044.405808 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40044.405808 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 40044.405808 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40041.089180 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40041.089180 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40041.089180 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 40041.089180 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40041.089180 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 40041.089180 # average overall mshr miss latency
631c631
< system.cpu.l2cache.tags.tagsinuse 2543.926921 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 2543.926920 # Cycle average of tags in use
637c637
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 2230.334816 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 2230.334814 # Average occupied blocks per requestor
669c669
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 232439500 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 232417000 # number of ReadReq miss cycles
671c671
< system.cpu.l2cache.ReadReq_miss_latency::total 265195000 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::total 265172500 # number of ReadReq miss cycles
674c674
< system.cpu.l2cache.demand_miss_latency::cpu.inst 232439500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 232417000 # number of demand (read+write) miss cycles
676,677c676,677
< system.cpu.l2cache.demand_miss_latency::total 369629000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 232439500 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::total 369606500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 232417000 # number of overall miss cycles
679c679
< system.cpu.l2cache.overall_miss_latency::total 369629000 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::total 369606500 # number of overall miss cycles
708c708
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68505.599764 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68498.968464 # average ReadReq miss latency
710c710
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 69368.297149 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 69362.411719 # average ReadReq miss latency
713c713
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68505.599764 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68498.968464 # average overall miss latency
715,716c715,716
< system.cpu.l2cache.demand_avg_miss_latency::total 69025.023343 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68505.599764 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::total 69020.821662 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68498.968464 # average overall miss latency
718c718
< system.cpu.l2cache.overall_avg_miss_latency::total 69025.023343 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::total 69020.821662 # average overall miss latency
740c740
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 189922000 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 189899500 # number of ReadReq MSHR miss cycles
742c742
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 217348500 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 217326000 # number of ReadReq MSHR miss cycles
747c747
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 189922000 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 189899500 # number of demand (read+write) MSHR miss cycles
749,750c749,750
< system.cpu.l2cache.demand_mshr_miss_latency::total 302222500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 189922000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::total 302200000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 189899500 # number of overall MSHR miss cycles
752c752
< system.cpu.l2cache.overall_mshr_miss_latency::total 302222500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::total 302200000 # number of overall MSHR miss cycles
766c766
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55974.653699 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55968.022399 # average ReadReq mshr miss latency
768c768
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56852.864243 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56846.978812 # average ReadReq mshr miss latency
773c773
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55974.653699 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55968.022399 # average overall mshr miss latency
775,776c775,776
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56437.441643 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55974.653699 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56433.239963 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55968.022399 # average overall mshr miss latency
778c778
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56437.441643 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56433.239963 # average overall mshr miss latency
782c782
< system.cpu.dcache.tags.total_refs 66102355 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 66102356 # Total number of references to valid blocks.
784c784
< system.cpu.dcache.tags.avg_refs 32985.207086 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 32985.207585 # Average number of references to valid blocks.
789,790c789,790
< system.cpu.dcache.ReadReq_hits::cpu.data 45588096 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 45588096 # number of ReadReq hits
---
> system.cpu.dcache.ReadReq_hits::cpu.data 45588097 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 45588097 # number of ReadReq hits
793,796c793,796
< system.cpu.dcache.demand_hits::cpu.data 66102125 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 66102125 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 66102125 # number of overall hits
< system.cpu.dcache.overall_hits::total 66102125 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 66102126 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 66102126 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 66102126 # number of overall hits
> system.cpu.dcache.overall_hits::total 66102126 # number of overall hits
813,814c813,814
< system.cpu.dcache.ReadReq_accesses::cpu.data 45589031 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 45589031 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_accesses::cpu.data 45589032 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 45589032 # number of ReadReq accesses(hits+misses)
817,820c817,820
< system.cpu.dcache.demand_accesses::cpu.data 66104762 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 66104762 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 66104762 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 66104762 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 66104763 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 66104763 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 66104763 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 66104763 # number of overall (read+write) accesses