7,11c7,11
< host_inst_rate 53269 # Simulator instruction rate (inst/s)
< host_op_rate 89284 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 58216660 # Simulator tick rate (ticks/s)
< host_mem_usage 281036 # Number of bytes of host memory used
< host_seconds 2479.31 # Real time elapsed on the host
---
> host_inst_rate 71990 # Simulator instruction rate (inst/s)
> host_op_rate 120663 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 78676444 # Simulator tick rate (ticks/s)
> host_mem_usage 280564 # Number of bytes of host memory used
> host_seconds 1834.57 # Real time elapsed on the host
218,219c218,219
< system.physmem.totQLat 12663500 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 119173500 # Sum of mem lat for all requests
---
> system.physmem.totQLat 12694000 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 119204000 # Sum of mem lat for all requests
222c222
< system.physmem.avgQLat 2361.27 # Average queueing delay per request
---
> system.physmem.avgQLat 2366.96 # Average queueing delay per request
225c225
< system.physmem.avgMemAccLat 22221.42 # Average memory access latency
---
> system.physmem.avgMemAccLat 22227.11 # Average memory access latency
254c254
< system.membus.reqLayer0.occupancy 6992500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 6990500 # Layer occupancy (ticks)
256c256
< system.membus.respLayer1.occupancy 50918345 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 50919845 # Layer occupancy (ticks)
258,259c258,259
< system.cpu.branchPred.lookups 18643049 # Number of BP lookups
< system.cpu.branchPred.condPredicted 18643049 # Number of conditional branches predicted
---
> system.cpu.branchPred.lookups 18643050 # Number of BP lookups
> system.cpu.branchPred.condPredicted 18643050 # Number of conditional branches predicted
261,262c261,262
< system.cpu.branchPred.BTBLookups 11410311 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 10785937 # Number of BTB hits
---
> system.cpu.branchPred.BTBLookups 11410312 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 10785938 # Number of BTB hits
264c264
< system.cpu.branchPred.BTBHitPct 94.527984 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 94.527985 # BTB Hit Percentage
268c268
< system.cpu.numCycles 288958648 # number of cpu cycles simulated
---
> system.cpu.numCycles 288958646 # number of cpu cycles simulated
272,277c272,277
< system.cpu.fetch.Insts 206693383 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 18643049 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 12105441 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 54202283 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 15520862 # Number of cycles fetch has spent squashing
< system.cpu.fetch.BlockedCycles 177854698 # Number of cycles fetch has spent blocked
---
> system.cpu.fetch.Insts 206693394 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 18643050 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 12105442 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 54202287 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 15520872 # Number of cycles fetch has spent squashing
> system.cpu.fetch.BlockedCycles 177854529 # Number of cycles fetch has spent blocked
281,285c281,285
< system.cpu.fetch.CacheLines 22344440 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 223501 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 269290807 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.269558 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.757533 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 22344441 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 223502 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 269290652 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.269559 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.757534 # Number of instructions fetched each cycle (Total)
287c287
< system.cpu.fetch.rateDist::0 216527174 80.41% 80.41% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 216527015 80.41% 80.41% # Number of instructions fetched each cycle (Total)
290c290
< system.cpu.fetch.rateDist::3 2635919 0.98% 83.30% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::3 2635920 0.98% 83.30% # Number of instructions fetched each cycle (Total)
295c295
< system.cpu.fetch.rateDist::8 31978830 11.88% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::8 31978833 11.88% 100.00% # Number of instructions fetched each cycle (Total)
299c299
< system.cpu.fetch.rateDist::total 269290807 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 269290652 # Number of instructions fetched each cycle (Total)
302,310c302,310
< system.cpu.decode.IdleCycles 36876726 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 166835214 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 41579224 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 10227847 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 13771796 # Number of cycles decode is squashing
< system.cpu.decode.DecodedInsts 335978319 # Number of instructions handled by decode
< system.cpu.rename.SquashCycles 13771796 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 44930870 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 116571073 # Number of cycles rename is blocking
---
> system.cpu.decode.IdleCycles 36876732 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 166835033 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 41579230 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 10227851 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 13771806 # Number of cycles decode is squashing
> system.cpu.decode.DecodedInsts 335978387 # Number of instructions handled by decode
> system.cpu.rename.SquashCycles 13771806 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 44930878 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 116570981 # Number of cycles rename is blocking
313,322c313,321
< system.cpu.rename.UnblockCycles 51278615 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 329616563 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 10879 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 26000887 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LSQFullEvents 22678374 # Number of times rename has blocked due to LSQ full
< system.cpu.rename.FullRegisterEvents 233 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 382329747 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 917574423 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 909394709 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 8179714 # Number of floating rename lookups
---
> system.cpu.rename.UnblockCycles 51278534 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 329616672 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 10920 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 26000838 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LSQFullEvents 22678371 # Number of times rename has blocked due to LSQ full
> system.cpu.rename.RenamedOperands 382329896 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 917574751 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 605864950 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 4114395 # Number of floating rename lookups
324c323
< system.cpu.rename.UndoneMaps 122900297 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 122900446 # Number of HB maps that are undone due to squashing
327,328c326,327
< system.cpu.rename.skidInsts 104883276 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 84491863 # Number of loads inserted to the mem dependence unit.
---
> system.cpu.rename.skidInsts 104883314 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 84491871 # Number of loads inserted to the mem dependence unit.
330c329
< system.cpu.memDep0.conflictingLoads 58238424 # Number of conflicting loads.
---
> system.cpu.memDep0.conflictingLoads 58238426 # Number of conflicting loads.
332c331
< system.cpu.iq.iqInstsAdded 322680217 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 322680314 # Number of instructions added to the IQ (excludes non-spec)
334,337c333,336
< system.cpu.iq.iqInstsIssued 260554825 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 118516 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 100936987 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 209936629 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqInstsIssued 260554870 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 118520 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 100937084 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 209936848 # Number of squashed operands that are examined and possibly removed from graph
339,341c338,340
< system.cpu.iq.issued_per_cycle::samples 269290807 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.967559 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.344978 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 269290652 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.967560 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.344979 # Number of insts issued each cycle
343,350c342,349
< system.cpu.iq.issued_per_cycle::0 143216984 53.18% 53.18% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 55392011 20.57% 73.75% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 34136175 12.68% 86.43% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 19056796 7.08% 93.51% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 10890988 4.04% 97.55% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 4174840 1.55% 99.10% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 1812715 0.67% 99.77% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 476750 0.18% 99.95% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 143216818 53.18% 53.18% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 55391998 20.57% 73.75% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 34136198 12.68% 86.43% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 19056794 7.08% 93.51% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 10890991 4.04% 97.55% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 4174838 1.55% 99.10% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 1812713 0.67% 99.77% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 476754 0.18% 99.95% # Number of insts issued each cycle
355c354
< system.cpu.iq.issued_per_cycle::total 269290807 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 269290652 # Number of insts issued each cycle
357c356
< system.cpu.iq.fu_full::IntAlu 129590 4.77% 4.77% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 129591 4.77% 4.77% # attempts to use FU when none available
391,392c390,391
< system.cpu.iq.FU_type_0::IntAlu 162062843 62.20% 62.66% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 788599 0.30% 62.97% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 162062878 62.20% 62.66% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 788601 0.30% 62.97% # Type of FU issued
420c419
< system.cpu.iq.FU_type_0::MemRead 65458478 25.12% 91.34% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 65458486 25.12% 91.34% # Type of FU issued
424c423
< system.cpu.iq.FU_type_0::total 260554825 # Type of FU issued
---
> system.cpu.iq.FU_type_0::total 260554870 # Type of FU issued
426c425
< system.cpu.iq.fu_busy_cnt 2717985 # FU busy when requested
---
> system.cpu.iq.fu_busy_cnt 2717986 # FU busy when requested
428,430c427,429
< system.cpu.iq.int_inst_queue_reads 788349726 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 420314001 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 255192171 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.int_inst_queue_reads 788349666 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 420314195 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 255192215 # Number of integer instruction queue wakeup accesses
434c433
< system.cpu.iq.int_alu_accesses 259602149 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 259602195 # Number of integer alu accesses
436c435
< system.cpu.iew.lsq.thread0.forwLoads 18922789 # Number of loads that had data forwarded from stores
---
> system.cpu.iew.lsq.thread0.forwLoads 18922795 # Number of loads that had data forwarded from stores
438c437
< system.cpu.iew.lsq.thread0.squashedLoads 27842276 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 27842284 # Number of loads squashed
447,450c446,449
< system.cpu.iew.iewSquashCycles 13771796 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 85093935 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 5458597 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 322684485 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 13771806 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 85094278 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 5458618 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 322684582 # Number of instructions dispatched to IQ
452c451
< system.cpu.iew.iewDispLoadInsts 84491863 # Number of dispatched load instructions
---
> system.cpu.iew.iewDispLoadInsts 84491871 # Number of dispatched load instructions
455c454
< system.cpu.iew.iewIQFullEvents 2689496 # Number of times the IQ has become full, causing a stall
---
> system.cpu.iew.iewIQFullEvents 2689502 # Number of times the IQ has become full, causing a stall
461,463c460,462
< system.cpu.iew.iewExecutedInsts 258780587 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 64687693 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 1774238 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecutedInsts 258780631 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 64687698 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 1774239 # Number of squashed instructions skipped in execute
466c465
< system.cpu.iew.exec_refs 87035311 # number of memory reference insts executed
---
> system.cpu.iew.exec_refs 87035316 # number of memory reference insts executed
470,473c469,472
< system.cpu.iew.wb_sent 258140928 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 257541852 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 206006710 # num instructions producing a value
< system.cpu.iew.wb_consumers 369206768 # num instructions consuming a value
---
> system.cpu.iew.wb_sent 258140972 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 257541896 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 206006775 # num instructions producing a value
> system.cpu.iew.wb_consumers 369206880 # num instructions consuming a value
478c477
< system.cpu.commit.commitSquashedInsts 101393272 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 101393363 # The number of squashed insts skipped by commit
481,483c480,482
< system.cpu.commit.committed_per_cycle::samples 255519011 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.866328 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.656610 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 255518846 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.866329 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.656611 # Number of insts commited each cycle
485c484
< system.cpu.commit.committed_per_cycle::0 156315570 61.18% 61.18% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 156315405 61.18% 61.18% # Number of insts commited each cycle
488,489c487,488
< system.cpu.commit.committed_per_cycle::3 12048530 4.72% 93.71% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 4172669 1.63% 95.34% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::3 12048531 4.72% 93.71% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 4172668 1.63% 95.34% # Number of insts commited each cycle
492,493c491,492
< system.cpu.commit.committed_per_cycle::7 1048603 0.41% 97.27% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 6974170 2.73% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::7 1048602 0.41% 97.27% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 6974171 2.73% 100.00% # Number of insts commited each cycle
497c496
< system.cpu.commit.committed_per_cycle::total 255519011 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 255518846 # Number of insts commited each cycle
506c505
< system.cpu.commit.int_insts 220339553 # Number of committed integer instructions.
---
> system.cpu.commit.int_insts 219019985 # Number of committed integer instructions.
508c507
< system.cpu.commit.bw_lim_events 6974170 # number cycles where commit BW limit reached
---
> system.cpu.commit.bw_lim_events 6974171 # number cycles where commit BW limit reached
510,513c509,512
< system.cpu.rob.rob_reads 571301497 # The number of ROB reads
< system.cpu.rob.rob_writes 659310607 # The number of ROB writes
< system.cpu.timesIdled 5931768 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 19667841 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 571301422 # The number of ROB reads
> system.cpu.rob.rob_writes 659310799 # The number of ROB writes
> system.cpu.timesIdled 5931788 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 19667994 # Total number of cycles that the CPU has spent unscheduled due to idling
521,522c520,521
< system.cpu.int_regfile_reads 554180321 # number of integer regfile reads
< system.cpu.int_regfile_writes 293821719 # number of integer regfile writes
---
> system.cpu.int_regfile_reads 451358394 # number of integer regfile reads
> system.cpu.int_regfile_writes 233998694 # number of integer regfile writes
525c524,526
< system.cpu.misc_regfile_reads 133360565 # number of misc regfile reads
---
> system.cpu.cc_regfile_reads 102822009 # number of cc regfile reads
> system.cpu.cc_regfile_writes 59823089 # number of cc regfile writes
> system.cpu.misc_regfile_reads 133360573 # number of misc regfile reads
550,551c551,552
< system.cpu.icache.tags.tagsinuse 1626.526470 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 22335617 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 1626.526476 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 22335618 # Total number of references to valid blocks.
553c554
< system.cpu.icache.tags.avg_refs 3378.042498 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 3378.042650 # Average number of references to valid blocks.
555c556
< system.cpu.icache.tags.occ_blocks::cpu.inst 1626.526470 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1626.526476 # Average occupied blocks per requestor
558,563c559,564
< system.cpu.icache.ReadReq_hits::cpu.inst 22335617 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 22335617 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 22335617 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 22335617 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 22335617 # number of overall hits
< system.cpu.icache.overall_hits::total 22335617 # number of overall hits
---
> system.cpu.icache.ReadReq_hits::cpu.inst 22335618 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 22335618 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 22335618 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 22335618 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 22335618 # number of overall hits
> system.cpu.icache.overall_hits::total 22335618 # number of overall hits
570,581c571,582
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 351986000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 351986000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 351986000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 351986000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 351986000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 351986000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 22344440 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 22344440 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 22344440 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 22344440 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 22344440 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 22344440 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 352032500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 352032500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 352032500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 352032500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 352032500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 352032500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 22344441 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 22344441 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 22344441 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 22344441 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 22344441 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 22344441 # number of overall (read+write) accesses
588,593c589,594
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39894.140315 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 39894.140315 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 39894.140315 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 39894.140315 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 39894.140315 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 39894.140315 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39899.410631 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 39899.410631 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 39899.410631 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 39899.410631 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 39899.410631 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 39899.410631 # average overall miss latency
614,619c615,620
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 262790750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 262790750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 262790750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 262790750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 262790750 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 262790750 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 262819250 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 262819250 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 262819250 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 262819250 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 262819250 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 262819250 # number of overall MSHR miss cycles
626,631c627,632
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38822.684296 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38822.684296 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38822.684296 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 38822.684296 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38822.684296 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 38822.684296 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38826.894667 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38826.894667 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38826.894667 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 38826.894667 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38826.894667 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 38826.894667 # average overall mshr miss latency
634c635
< system.cpu.l2cache.tags.tagsinuse 2554.250999 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 2554.251018 # Cycle average of tags in use
640,641c641,642
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 2240.158867 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 312.330146 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 2240.158882 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 312.330149 # Average occupied blocks per requestor
674,676c675,677
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 223798500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 31028500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 254827000 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 223827000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 31029500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 254856500 # number of ReadReq miss cycles
679,684c680,685
< system.cpu.l2cache.demand_miss_latency::cpu.inst 223798500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 127712000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 351510500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 223798500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 127712000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 351510500 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 223827000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 127713000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 351540000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 223827000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 127713000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 351540000 # number of overall miss cycles
713,715c714,716
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65687.848547 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72496.495327 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 66447.718383 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65696.213678 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72498.831776 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 66455.410691 # average ReadReq miss latency
718,723c719,724
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65687.848547 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65259.070005 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 65531.413125 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65687.848547 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65259.070005 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 65531.413125 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65696.213678 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65259.580991 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 65536.912752 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65696.213678 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65259.580991 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 65536.912752 # average overall miss latency
745,747c746,748
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 180903000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25684500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 206587500 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 180933000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25685000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 206618000 # number of ReadReq MSHR miss cycles
752,757c753,758
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 180903000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 102760000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 283663000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 180903000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 102760000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 283663000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 180933000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 102760500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 283693500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 180933000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 102760500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 283693500 # number of overall MSHR miss cycles
771,773c772,774
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53097.446434 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60010.514019 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53868.970013 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53106.251834 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60011.682243 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53876.923077 # average ReadReq mshr miss latency
778,783c779,784
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53097.446434 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52508.942259 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52882.736764 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53097.446434 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52508.942259 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52882.736764 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53106.251834 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52509.197752 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52888.422819 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53106.251834 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52509.197752 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52888.422819 # average overall mshr miss latency
786,787c787,788
< system.cpu.dcache.tags.tagsinuse 1431.071362 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 66125332 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 1431.071380 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 66125331 # Total number of references to valid blocks.
789c790
< system.cpu.dcache.tags.avg_refs 33112.334502 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 33112.334001 # Average number of references to valid blocks.
791c792
< system.cpu.dcache.tags.occ_blocks::cpu.data 1431.071362 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 1431.071380 # Average occupied blocks per requestor
794,795c795,796
< system.cpu.dcache.ReadReq_hits::cpu.data 45611086 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 45611086 # number of ReadReq hits
---
> system.cpu.dcache.ReadReq_hits::cpu.data 45611085 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 45611085 # number of ReadReq hits
798,801c799,802
< system.cpu.dcache.demand_hits::cpu.data 66125124 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 66125124 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 66125124 # number of overall hits
< system.cpu.dcache.overall_hits::total 66125124 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 66125123 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 66125123 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 66125123 # number of overall hits
> system.cpu.dcache.overall_hits::total 66125123 # number of overall hits
810,819c811,820
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 55173302 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 55173302 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 106078655 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 106078655 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 161251957 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 161251957 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 161251957 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 161251957 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 45612001 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 45612001 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 55175302 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 55175302 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 106081155 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 106081155 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 161256457 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 161256457 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 161256457 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 161256457 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 45612000 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 45612000 # number of ReadReq accesses(hits+misses)
822,825c823,826
< system.cpu.dcache.demand_accesses::cpu.data 66127732 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 66127732 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 66127732 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 66127732 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 66127731 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 66127731 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 66127731 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 66127731 # number of overall (read+write) accesses
834,841c835,842
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60298.690710 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 60298.690710 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62657.209096 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 62657.209096 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 61829.738113 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 61829.738113 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 61829.738113 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 61829.738113 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60300.876503 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 60300.876503 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62658.685765 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 62658.685765 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 61831.463574 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 61831.463574 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 61831.463574 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 61831.463574 # average overall miss latency
868,875c869,876
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31923750 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 31923750 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101848595 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 101848595 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 133772345 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 133772345 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 133772345 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 133772345 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31924750 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 31924750 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101851095 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 101851095 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 133775845 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 133775845 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 133775845 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 133775845 # number of overall MSHR miss cycles
884,891c885,892
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68653.225806 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68653.225806 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60229.801892 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60229.801892 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62046.542208 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 62046.542208 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62046.542208 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 62046.542208 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68655.376344 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68655.376344 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60231.280308 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60231.280308 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62048.165584 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 62048.165584 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62048.165584 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 62048.165584 # average overall mshr miss latency
< host_inst_rate 53269 # Simulator instruction rate (inst/s)
< host_op_rate 89284 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 58216660 # Simulator tick rate (ticks/s)
< host_mem_usage 281036 # Number of bytes of host memory used
< host_seconds 2479.31 # Real time elapsed on the host
---
> host_inst_rate 71990 # Simulator instruction rate (inst/s)
> host_op_rate 120663 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 78676444 # Simulator tick rate (ticks/s)
> host_mem_usage 280564 # Number of bytes of host memory used
> host_seconds 1834.57 # Real time elapsed on the host
218,219c218,219
< system.physmem.totQLat 12663500 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 119173500 # Sum of mem lat for all requests
---
> system.physmem.totQLat 12694000 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 119204000 # Sum of mem lat for all requests
222c222
< system.physmem.avgQLat 2361.27 # Average queueing delay per request
---
> system.physmem.avgQLat 2366.96 # Average queueing delay per request
225c225
< system.physmem.avgMemAccLat 22221.42 # Average memory access latency
---
> system.physmem.avgMemAccLat 22227.11 # Average memory access latency
254c254
< system.membus.reqLayer0.occupancy 6992500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 6990500 # Layer occupancy (ticks)
256c256
< system.membus.respLayer1.occupancy 50918345 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 50919845 # Layer occupancy (ticks)
258,259c258,259
< system.cpu.branchPred.lookups 18643049 # Number of BP lookups
< system.cpu.branchPred.condPredicted 18643049 # Number of conditional branches predicted
---
> system.cpu.branchPred.lookups 18643050 # Number of BP lookups
> system.cpu.branchPred.condPredicted 18643050 # Number of conditional branches predicted
261,262c261,262
< system.cpu.branchPred.BTBLookups 11410311 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 10785937 # Number of BTB hits
---
> system.cpu.branchPred.BTBLookups 11410312 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 10785938 # Number of BTB hits
264c264
< system.cpu.branchPred.BTBHitPct 94.527984 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 94.527985 # BTB Hit Percentage
268c268
< system.cpu.numCycles 288958648 # number of cpu cycles simulated
---
> system.cpu.numCycles 288958646 # number of cpu cycles simulated
272,277c272,277
< system.cpu.fetch.Insts 206693383 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 18643049 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 12105441 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 54202283 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 15520862 # Number of cycles fetch has spent squashing
< system.cpu.fetch.BlockedCycles 177854698 # Number of cycles fetch has spent blocked
---
> system.cpu.fetch.Insts 206693394 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 18643050 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 12105442 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 54202287 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 15520872 # Number of cycles fetch has spent squashing
> system.cpu.fetch.BlockedCycles 177854529 # Number of cycles fetch has spent blocked
281,285c281,285
< system.cpu.fetch.CacheLines 22344440 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 223501 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 269290807 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.269558 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.757533 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 22344441 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 223502 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 269290652 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.269559 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.757534 # Number of instructions fetched each cycle (Total)
287c287
< system.cpu.fetch.rateDist::0 216527174 80.41% 80.41% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 216527015 80.41% 80.41% # Number of instructions fetched each cycle (Total)
290c290
< system.cpu.fetch.rateDist::3 2635919 0.98% 83.30% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::3 2635920 0.98% 83.30% # Number of instructions fetched each cycle (Total)
295c295
< system.cpu.fetch.rateDist::8 31978830 11.88% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::8 31978833 11.88% 100.00% # Number of instructions fetched each cycle (Total)
299c299
< system.cpu.fetch.rateDist::total 269290807 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 269290652 # Number of instructions fetched each cycle (Total)
302,310c302,310
< system.cpu.decode.IdleCycles 36876726 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 166835214 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 41579224 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 10227847 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 13771796 # Number of cycles decode is squashing
< system.cpu.decode.DecodedInsts 335978319 # Number of instructions handled by decode
< system.cpu.rename.SquashCycles 13771796 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 44930870 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 116571073 # Number of cycles rename is blocking
---
> system.cpu.decode.IdleCycles 36876732 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 166835033 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 41579230 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 10227851 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 13771806 # Number of cycles decode is squashing
> system.cpu.decode.DecodedInsts 335978387 # Number of instructions handled by decode
> system.cpu.rename.SquashCycles 13771806 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 44930878 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 116570981 # Number of cycles rename is blocking
313,322c313,321
< system.cpu.rename.UnblockCycles 51278615 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 329616563 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 10879 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 26000887 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LSQFullEvents 22678374 # Number of times rename has blocked due to LSQ full
< system.cpu.rename.FullRegisterEvents 233 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 382329747 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 917574423 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 909394709 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 8179714 # Number of floating rename lookups
---
> system.cpu.rename.UnblockCycles 51278534 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 329616672 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 10920 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 26000838 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LSQFullEvents 22678371 # Number of times rename has blocked due to LSQ full
> system.cpu.rename.RenamedOperands 382329896 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 917574751 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 605864950 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 4114395 # Number of floating rename lookups
324c323
< system.cpu.rename.UndoneMaps 122900297 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 122900446 # Number of HB maps that are undone due to squashing
327,328c326,327
< system.cpu.rename.skidInsts 104883276 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 84491863 # Number of loads inserted to the mem dependence unit.
---
> system.cpu.rename.skidInsts 104883314 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 84491871 # Number of loads inserted to the mem dependence unit.
330c329
< system.cpu.memDep0.conflictingLoads 58238424 # Number of conflicting loads.
---
> system.cpu.memDep0.conflictingLoads 58238426 # Number of conflicting loads.
332c331
< system.cpu.iq.iqInstsAdded 322680217 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 322680314 # Number of instructions added to the IQ (excludes non-spec)
334,337c333,336
< system.cpu.iq.iqInstsIssued 260554825 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 118516 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 100936987 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 209936629 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqInstsIssued 260554870 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 118520 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 100937084 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 209936848 # Number of squashed operands that are examined and possibly removed from graph
339,341c338,340
< system.cpu.iq.issued_per_cycle::samples 269290807 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.967559 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.344978 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 269290652 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.967560 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.344979 # Number of insts issued each cycle
343,350c342,349
< system.cpu.iq.issued_per_cycle::0 143216984 53.18% 53.18% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 55392011 20.57% 73.75% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 34136175 12.68% 86.43% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 19056796 7.08% 93.51% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 10890988 4.04% 97.55% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 4174840 1.55% 99.10% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 1812715 0.67% 99.77% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 476750 0.18% 99.95% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 143216818 53.18% 53.18% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 55391998 20.57% 73.75% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 34136198 12.68% 86.43% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 19056794 7.08% 93.51% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 10890991 4.04% 97.55% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 4174838 1.55% 99.10% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 1812713 0.67% 99.77% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 476754 0.18% 99.95% # Number of insts issued each cycle
355c354
< system.cpu.iq.issued_per_cycle::total 269290807 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 269290652 # Number of insts issued each cycle
357c356
< system.cpu.iq.fu_full::IntAlu 129590 4.77% 4.77% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 129591 4.77% 4.77% # attempts to use FU when none available
391,392c390,391
< system.cpu.iq.FU_type_0::IntAlu 162062843 62.20% 62.66% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 788599 0.30% 62.97% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 162062878 62.20% 62.66% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 788601 0.30% 62.97% # Type of FU issued
420c419
< system.cpu.iq.FU_type_0::MemRead 65458478 25.12% 91.34% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 65458486 25.12% 91.34% # Type of FU issued
424c423
< system.cpu.iq.FU_type_0::total 260554825 # Type of FU issued
---
> system.cpu.iq.FU_type_0::total 260554870 # Type of FU issued
426c425
< system.cpu.iq.fu_busy_cnt 2717985 # FU busy when requested
---
> system.cpu.iq.fu_busy_cnt 2717986 # FU busy when requested
428,430c427,429
< system.cpu.iq.int_inst_queue_reads 788349726 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 420314001 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 255192171 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.int_inst_queue_reads 788349666 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 420314195 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 255192215 # Number of integer instruction queue wakeup accesses
434c433
< system.cpu.iq.int_alu_accesses 259602149 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 259602195 # Number of integer alu accesses
436c435
< system.cpu.iew.lsq.thread0.forwLoads 18922789 # Number of loads that had data forwarded from stores
---
> system.cpu.iew.lsq.thread0.forwLoads 18922795 # Number of loads that had data forwarded from stores
438c437
< system.cpu.iew.lsq.thread0.squashedLoads 27842276 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 27842284 # Number of loads squashed
447,450c446,449
< system.cpu.iew.iewSquashCycles 13771796 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 85093935 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 5458597 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 322684485 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 13771806 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 85094278 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 5458618 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 322684582 # Number of instructions dispatched to IQ
452c451
< system.cpu.iew.iewDispLoadInsts 84491863 # Number of dispatched load instructions
---
> system.cpu.iew.iewDispLoadInsts 84491871 # Number of dispatched load instructions
455c454
< system.cpu.iew.iewIQFullEvents 2689496 # Number of times the IQ has become full, causing a stall
---
> system.cpu.iew.iewIQFullEvents 2689502 # Number of times the IQ has become full, causing a stall
461,463c460,462
< system.cpu.iew.iewExecutedInsts 258780587 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 64687693 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 1774238 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecutedInsts 258780631 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 64687698 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 1774239 # Number of squashed instructions skipped in execute
466c465
< system.cpu.iew.exec_refs 87035311 # number of memory reference insts executed
---
> system.cpu.iew.exec_refs 87035316 # number of memory reference insts executed
470,473c469,472
< system.cpu.iew.wb_sent 258140928 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 257541852 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 206006710 # num instructions producing a value
< system.cpu.iew.wb_consumers 369206768 # num instructions consuming a value
---
> system.cpu.iew.wb_sent 258140972 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 257541896 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 206006775 # num instructions producing a value
> system.cpu.iew.wb_consumers 369206880 # num instructions consuming a value
478c477
< system.cpu.commit.commitSquashedInsts 101393272 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 101393363 # The number of squashed insts skipped by commit
481,483c480,482
< system.cpu.commit.committed_per_cycle::samples 255519011 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.866328 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.656610 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 255518846 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.866329 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.656611 # Number of insts commited each cycle
485c484
< system.cpu.commit.committed_per_cycle::0 156315570 61.18% 61.18% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 156315405 61.18% 61.18% # Number of insts commited each cycle
488,489c487,488
< system.cpu.commit.committed_per_cycle::3 12048530 4.72% 93.71% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 4172669 1.63% 95.34% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::3 12048531 4.72% 93.71% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 4172668 1.63% 95.34% # Number of insts commited each cycle
492,493c491,492
< system.cpu.commit.committed_per_cycle::7 1048603 0.41% 97.27% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 6974170 2.73% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::7 1048602 0.41% 97.27% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 6974171 2.73% 100.00% # Number of insts commited each cycle
497c496
< system.cpu.commit.committed_per_cycle::total 255519011 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 255518846 # Number of insts commited each cycle
506c505
< system.cpu.commit.int_insts 220339553 # Number of committed integer instructions.
---
> system.cpu.commit.int_insts 219019985 # Number of committed integer instructions.
508c507
< system.cpu.commit.bw_lim_events 6974170 # number cycles where commit BW limit reached
---
> system.cpu.commit.bw_lim_events 6974171 # number cycles where commit BW limit reached
510,513c509,512
< system.cpu.rob.rob_reads 571301497 # The number of ROB reads
< system.cpu.rob.rob_writes 659310607 # The number of ROB writes
< system.cpu.timesIdled 5931768 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 19667841 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 571301422 # The number of ROB reads
> system.cpu.rob.rob_writes 659310799 # The number of ROB writes
> system.cpu.timesIdled 5931788 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 19667994 # Total number of cycles that the CPU has spent unscheduled due to idling
521,522c520,521
< system.cpu.int_regfile_reads 554180321 # number of integer regfile reads
< system.cpu.int_regfile_writes 293821719 # number of integer regfile writes
---
> system.cpu.int_regfile_reads 451358394 # number of integer regfile reads
> system.cpu.int_regfile_writes 233998694 # number of integer regfile writes
525c524,526
< system.cpu.misc_regfile_reads 133360565 # number of misc regfile reads
---
> system.cpu.cc_regfile_reads 102822009 # number of cc regfile reads
> system.cpu.cc_regfile_writes 59823089 # number of cc regfile writes
> system.cpu.misc_regfile_reads 133360573 # number of misc regfile reads
550,551c551,552
< system.cpu.icache.tags.tagsinuse 1626.526470 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 22335617 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 1626.526476 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 22335618 # Total number of references to valid blocks.
553c554
< system.cpu.icache.tags.avg_refs 3378.042498 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 3378.042650 # Average number of references to valid blocks.
555c556
< system.cpu.icache.tags.occ_blocks::cpu.inst 1626.526470 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1626.526476 # Average occupied blocks per requestor
558,563c559,564
< system.cpu.icache.ReadReq_hits::cpu.inst 22335617 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 22335617 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 22335617 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 22335617 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 22335617 # number of overall hits
< system.cpu.icache.overall_hits::total 22335617 # number of overall hits
---
> system.cpu.icache.ReadReq_hits::cpu.inst 22335618 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 22335618 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 22335618 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 22335618 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 22335618 # number of overall hits
> system.cpu.icache.overall_hits::total 22335618 # number of overall hits
570,581c571,582
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 351986000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 351986000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 351986000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 351986000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 351986000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 351986000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 22344440 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 22344440 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 22344440 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 22344440 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 22344440 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 22344440 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 352032500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 352032500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 352032500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 352032500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 352032500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 352032500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 22344441 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 22344441 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 22344441 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 22344441 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 22344441 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 22344441 # number of overall (read+write) accesses
588,593c589,594
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39894.140315 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 39894.140315 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 39894.140315 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 39894.140315 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 39894.140315 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 39894.140315 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39899.410631 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 39899.410631 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 39899.410631 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 39899.410631 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 39899.410631 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 39899.410631 # average overall miss latency
614,619c615,620
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 262790750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 262790750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 262790750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 262790750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 262790750 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 262790750 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 262819250 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 262819250 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 262819250 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 262819250 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 262819250 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 262819250 # number of overall MSHR miss cycles
626,631c627,632
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38822.684296 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38822.684296 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38822.684296 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 38822.684296 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38822.684296 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 38822.684296 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38826.894667 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38826.894667 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38826.894667 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 38826.894667 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38826.894667 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 38826.894667 # average overall mshr miss latency
634c635
< system.cpu.l2cache.tags.tagsinuse 2554.250999 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 2554.251018 # Cycle average of tags in use
640,641c641,642
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 2240.158867 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 312.330146 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 2240.158882 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 312.330149 # Average occupied blocks per requestor
674,676c675,677
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 223798500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 31028500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 254827000 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 223827000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 31029500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 254856500 # number of ReadReq miss cycles
679,684c680,685
< system.cpu.l2cache.demand_miss_latency::cpu.inst 223798500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 127712000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 351510500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 223798500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 127712000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 351510500 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 223827000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 127713000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 351540000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 223827000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 127713000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 351540000 # number of overall miss cycles
713,715c714,716
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65687.848547 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72496.495327 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 66447.718383 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65696.213678 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72498.831776 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 66455.410691 # average ReadReq miss latency
718,723c719,724
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65687.848547 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65259.070005 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 65531.413125 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65687.848547 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65259.070005 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 65531.413125 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65696.213678 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65259.580991 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 65536.912752 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65696.213678 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65259.580991 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 65536.912752 # average overall miss latency
745,747c746,748
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 180903000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25684500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 206587500 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 180933000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25685000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 206618000 # number of ReadReq MSHR miss cycles
752,757c753,758
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 180903000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 102760000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 283663000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 180903000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 102760000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 283663000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 180933000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 102760500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 283693500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 180933000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 102760500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 283693500 # number of overall MSHR miss cycles
771,773c772,774
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53097.446434 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60010.514019 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53868.970013 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53106.251834 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60011.682243 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53876.923077 # average ReadReq mshr miss latency
778,783c779,784
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53097.446434 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52508.942259 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52882.736764 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53097.446434 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52508.942259 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52882.736764 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53106.251834 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52509.197752 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52888.422819 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53106.251834 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52509.197752 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52888.422819 # average overall mshr miss latency
786,787c787,788
< system.cpu.dcache.tags.tagsinuse 1431.071362 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 66125332 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 1431.071380 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 66125331 # Total number of references to valid blocks.
789c790
< system.cpu.dcache.tags.avg_refs 33112.334502 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 33112.334001 # Average number of references to valid blocks.
791c792
< system.cpu.dcache.tags.occ_blocks::cpu.data 1431.071362 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 1431.071380 # Average occupied blocks per requestor
794,795c795,796
< system.cpu.dcache.ReadReq_hits::cpu.data 45611086 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 45611086 # number of ReadReq hits
---
> system.cpu.dcache.ReadReq_hits::cpu.data 45611085 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 45611085 # number of ReadReq hits
798,801c799,802
< system.cpu.dcache.demand_hits::cpu.data 66125124 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 66125124 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 66125124 # number of overall hits
< system.cpu.dcache.overall_hits::total 66125124 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 66125123 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 66125123 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 66125123 # number of overall hits
> system.cpu.dcache.overall_hits::total 66125123 # number of overall hits
810,819c811,820
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 55173302 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 55173302 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 106078655 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 106078655 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 161251957 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 161251957 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 161251957 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 161251957 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 45612001 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 45612001 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 55175302 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 55175302 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 106081155 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 106081155 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 161256457 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 161256457 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 161256457 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 161256457 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 45612000 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 45612000 # number of ReadReq accesses(hits+misses)
822,825c823,826
< system.cpu.dcache.demand_accesses::cpu.data 66127732 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 66127732 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 66127732 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 66127732 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 66127731 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 66127731 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 66127731 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 66127731 # number of overall (read+write) accesses
834,841c835,842
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60298.690710 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 60298.690710 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62657.209096 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 62657.209096 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 61829.738113 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 61829.738113 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 61829.738113 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 61829.738113 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60300.876503 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 60300.876503 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62658.685765 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 62658.685765 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 61831.463574 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 61831.463574 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 61831.463574 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 61831.463574 # average overall miss latency
868,875c869,876
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31923750 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 31923750 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101848595 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 101848595 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 133772345 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 133772345 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 133772345 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 133772345 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31924750 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 31924750 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101851095 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 101851095 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 133775845 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 133775845 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 133775845 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 133775845 # number of overall MSHR miss cycles
884,891c885,892
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68653.225806 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68653.225806 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60229.801892 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60229.801892 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62046.542208 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 62046.542208 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62046.542208 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 62046.542208 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68655.376344 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68655.376344 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60231.280308 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60231.280308 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62048.165584 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 62048.165584 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62048.165584 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 62048.165584 # average overall mshr miss latency