7,11c7,11
< host_inst_rate 58118 # Simulator instruction rate (inst/s)
< host_op_rate 97410 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 36369167 # Simulator tick rate (ticks/s)
< host_mem_usage 286740 # Number of bytes of host memory used
< host_seconds 2272.48 # Real time elapsed on the host
---
> host_inst_rate 31465 # Simulator instruction rate (inst/s)
> host_op_rate 52738 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 19690094 # Simulator tick rate (ticks/s)
> host_mem_usage 268216 # Number of bytes of host memory used
> host_seconds 4197.45 # Real time elapsed on the host
73c73
< system.physmem.totGap 82648108000 # Total gap between requests
---
> system.physmem.totGap 82648109000 # Total gap between requests
167,168c167,168
< system.physmem.totQLat 16873322 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 122447322 # Sum of mem lat for all requests
---
> system.physmem.totQLat 16873822 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 122447822 # Sum of mem lat for all requests
171c171
< system.physmem.avgQLat 3155.07 # Average queueing delay per request
---
> system.physmem.avgQLat 3155.16 # Average queueing delay per request
174c174
< system.physmem.avgMemAccLat 22895.91 # Average memory access latency
---
> system.physmem.avgMemAccLat 22896.00 # Average memory access latency
187c187
< system.physmem.avgGap 15454021.69 # Average gap between requests
---
> system.physmem.avgGap 15454021.88 # Average gap between requests
200c200
< system.cpu.fetch.icacheStallCycles 25830999 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 25831000 # Number of cycles fetch is stalled on an Icache miss
207c207
< system.cpu.fetch.MiscStallCycles 241 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
---
> system.cpu.fetch.MiscStallCycles 240 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
210,211c210,211
< system.cpu.fetch.CacheLines 24446052 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 431778 # Number of outstanding Icache misses that were squashed
---
> system.cpu.fetch.CacheLines 24446053 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 431779 # Number of outstanding Icache misses that were squashed
457c457
< system.cpu.icache.tagsinuse 1624.168421 # Cycle average of tags in use
---
> system.cpu.icache.tagsinuse 1624.168426 # Cycle average of tags in use
462c462
< system.cpu.icache.occ_blocks::cpu.inst 1624.168421 # Average occupied blocks per requestor
---
> system.cpu.icache.occ_blocks::cpu.inst 1624.168426 # Average occupied blocks per requestor
471,488c471,488
< system.cpu.icache.ReadReq_misses::cpu.inst 8951 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 8951 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 8951 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 8951 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 8951 # number of overall misses
< system.cpu.icache.overall_misses::total 8951 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 259393998 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 259393998 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 259393998 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 259393998 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 259393998 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 259393998 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 24446052 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 24446052 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 24446052 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 24446052 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 24446052 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 24446052 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_misses::cpu.inst 8952 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 8952 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 8952 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 8952 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 8952 # number of overall misses
> system.cpu.icache.overall_misses::total 8952 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 259465998 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 259465998 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 259465998 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 259465998 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 259465998 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 259465998 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 24446053 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 24446053 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 24446053 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 24446053 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 24446053 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 24446053 # number of overall (read+write) accesses
495,500c495,500
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28979.331695 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 28979.331695 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 28979.331695 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 28979.331695 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 28979.331695 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 28979.331695 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28984.137399 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 28984.137399 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 28984.137399 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 28984.137399 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 28984.137399 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 28984.137399 # average overall miss latency
509,514c509,514
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2096 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 2096 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 2096 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 2096 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 2096 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 2096 # number of overall MSHR hits
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2097 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 2097 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 2097 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 2097 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 2097 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 2097 # number of overall MSHR hits
521,526c521,526
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 198301998 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 198301998 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 198301998 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 198301998 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 198301998 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 198301998 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 198302998 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 198302998 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 198302998 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 198302998 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 198302998 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 198302998 # number of overall MSHR miss cycles
533,538c533,538
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28928.081400 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28928.081400 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28928.081400 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 28928.081400 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28928.081400 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 28928.081400 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28928.227279 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28928.227279 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28928.227279 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 28928.227279 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28928.227279 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 28928.227279 # average overall mshr miss latency
540,647d539
< system.cpu.dcache.replacements 55 # number of replacements
< system.cpu.dcache.tagsinuse 1411.367255 # Cycle average of tags in use
< system.cpu.dcache.total_refs 67560996 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 1981 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 34104.490661 # Average number of references to valid blocks.
< system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.occ_blocks::cpu.data 1411.367255 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.344572 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.344572 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits::cpu.data 47046789 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 47046789 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 20514009 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 20514009 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 67560798 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 67560798 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 67560798 # number of overall hits
< system.cpu.dcache.overall_hits::total 67560798 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 791 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 791 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 1722 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 1722 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 2513 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 2513 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 2513 # number of overall misses
< system.cpu.dcache.overall_misses::total 2513 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 37144500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 37144500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 76853000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 76853000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 113997500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 113997500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 113997500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 113997500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 47047580 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 47047580 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 67563311 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 67563311 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 67563311 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 67563311 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46958.912769 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 46958.912769 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44630.081301 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 44630.081301 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 45363.111819 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 45363.111819 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 45363.111819 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 45363.111819 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 86 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 43 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.writebacks::writebacks 14 # number of writebacks
< system.cpu.dcache.writebacks::total 14 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 374 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 374 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 376 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 376 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 376 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 376 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 417 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1720 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 1720 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 2137 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 2137 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 2137 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 2137 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22474500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 22474500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73299500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 73299500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 95774000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 95774000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 95774000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 95774000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000084 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53895.683453 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53895.683453 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42615.988372 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42615.988372 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44817.033224 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 44817.033224 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44817.033224 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 44817.033224 # average overall mshr miss latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
649c541
< system.cpu.l2cache.tagsinuse 2509.913634 # Cycle average of tags in use
---
> system.cpu.l2cache.tagsinuse 2509.913640 # Cycle average of tags in use
655,656c547,548
< system.cpu.l2cache.occ_blocks::cpu.inst 2234.774408 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 274.236525 # Average occupied blocks per requestor
---
> system.cpu.l2cache.occ_blocks::cpu.inst 2234.774413 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 274.236526 # Average occupied blocks per requestor
687,689c579,581
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 158303000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21677500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 179980500 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 158304000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21677000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 179981000 # number of ReadReq miss cycles
692,697c584,589
< system.cpu.l2cache.demand_miss_latency::cpu.inst 158303000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 89911500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 248214500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 158303000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 89911500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 248214500 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 158304000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 89911000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 248215000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 158304000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 89911000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 248215000 # number of overall miss cycles
726,728c618,620
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 46532.333921 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56159.326425 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 47513.331573 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 46532.627866 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56158.031088 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 47513.463569 # average ReadReq miss latency
731,736c623,628
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 46532.333921 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46203.237410 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 46412.584144 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 46532.333921 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46203.237410 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 46412.584144 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 46532.627866 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46202.980473 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 46412.677636 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 46532.627866 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46202.980473 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 46412.677636 # average overall miss latency
758,759c650,651
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115394483 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16844598 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115394983 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16844098 # number of ReadReq MSHR miss cycles
765,766c657,658
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115394483 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 65277091 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115394983 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 65276591 # number of demand (read+write) MSHR miss cycles
768,769c660,661
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115394483 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 65277091 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115394983 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 65276591 # number of overall MSHR miss cycles
784,785c676,677
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33919.601117 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43638.854922 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33919.748089 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43637.559585 # average ReadReq mshr miss latency
791,792c683,684
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33919.601117 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33544.239979 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33919.748089 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33543.983042 # average overall mshr miss latency
794,795c686,687
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33919.601117 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33544.239979 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33919.748089 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33543.983042 # average overall mshr miss latency
797a690,797
> system.cpu.dcache.replacements 55 # number of replacements
> system.cpu.dcache.tagsinuse 1411.367257 # Cycle average of tags in use
> system.cpu.dcache.total_refs 67560996 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 1981 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 34104.490661 # Average number of references to valid blocks.
> system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.occ_blocks::cpu.data 1411.367257 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.344572 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.344572 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 47046789 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 47046789 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 20514009 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 20514009 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 67560798 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 67560798 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 67560798 # number of overall hits
> system.cpu.dcache.overall_hits::total 67560798 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 791 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 791 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 1722 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 1722 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 2513 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 2513 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 2513 # number of overall misses
> system.cpu.dcache.overall_misses::total 2513 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 37144000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 37144000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 76853000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 76853000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 113997000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 113997000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 113997000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 113997000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 47047580 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 47047580 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 67563311 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 67563311 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 67563311 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 67563311 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46958.280657 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 46958.280657 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44630.081301 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 44630.081301 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 45362.912853 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 45362.912853 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 45362.912853 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 45362.912853 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 86 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 43 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.writebacks::writebacks 14 # number of writebacks
> system.cpu.dcache.writebacks::total 14 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 374 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 374 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 376 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 376 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 376 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 376 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 417 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1720 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 1720 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 2137 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 2137 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 2137 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 2137 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22474000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 22474000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73299500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 73299500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 95773500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 95773500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 95773500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 95773500 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000084 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53894.484412 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53894.484412 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42615.988372 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42615.988372 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44816.799251 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 44816.799251 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44816.799251 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 44816.799251 # average overall mshr miss latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
< host_inst_rate 58118 # Simulator instruction rate (inst/s)
< host_op_rate 97410 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 36369167 # Simulator tick rate (ticks/s)
< host_mem_usage 286740 # Number of bytes of host memory used
< host_seconds 2272.48 # Real time elapsed on the host
---
> host_inst_rate 31465 # Simulator instruction rate (inst/s)
> host_op_rate 52738 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 19690094 # Simulator tick rate (ticks/s)
> host_mem_usage 268216 # Number of bytes of host memory used
> host_seconds 4197.45 # Real time elapsed on the host
73c73
< system.physmem.totGap 82648108000 # Total gap between requests
---
> system.physmem.totGap 82648109000 # Total gap between requests
167,168c167,168
< system.physmem.totQLat 16873322 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 122447322 # Sum of mem lat for all requests
---
> system.physmem.totQLat 16873822 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 122447822 # Sum of mem lat for all requests
171c171
< system.physmem.avgQLat 3155.07 # Average queueing delay per request
---
> system.physmem.avgQLat 3155.16 # Average queueing delay per request
174c174
< system.physmem.avgMemAccLat 22895.91 # Average memory access latency
---
> system.physmem.avgMemAccLat 22896.00 # Average memory access latency
187c187
< system.physmem.avgGap 15454021.69 # Average gap between requests
---
> system.physmem.avgGap 15454021.88 # Average gap between requests
200c200
< system.cpu.fetch.icacheStallCycles 25830999 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 25831000 # Number of cycles fetch is stalled on an Icache miss
207c207
< system.cpu.fetch.MiscStallCycles 241 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
---
> system.cpu.fetch.MiscStallCycles 240 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
210,211c210,211
< system.cpu.fetch.CacheLines 24446052 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 431778 # Number of outstanding Icache misses that were squashed
---
> system.cpu.fetch.CacheLines 24446053 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 431779 # Number of outstanding Icache misses that were squashed
457c457
< system.cpu.icache.tagsinuse 1624.168421 # Cycle average of tags in use
---
> system.cpu.icache.tagsinuse 1624.168426 # Cycle average of tags in use
462c462
< system.cpu.icache.occ_blocks::cpu.inst 1624.168421 # Average occupied blocks per requestor
---
> system.cpu.icache.occ_blocks::cpu.inst 1624.168426 # Average occupied blocks per requestor
471,488c471,488
< system.cpu.icache.ReadReq_misses::cpu.inst 8951 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 8951 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 8951 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 8951 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 8951 # number of overall misses
< system.cpu.icache.overall_misses::total 8951 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 259393998 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 259393998 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 259393998 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 259393998 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 259393998 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 259393998 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 24446052 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 24446052 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 24446052 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 24446052 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 24446052 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 24446052 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_misses::cpu.inst 8952 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 8952 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 8952 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 8952 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 8952 # number of overall misses
> system.cpu.icache.overall_misses::total 8952 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 259465998 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 259465998 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 259465998 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 259465998 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 259465998 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 259465998 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 24446053 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 24446053 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 24446053 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 24446053 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 24446053 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 24446053 # number of overall (read+write) accesses
495,500c495,500
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28979.331695 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 28979.331695 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 28979.331695 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 28979.331695 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 28979.331695 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 28979.331695 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28984.137399 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 28984.137399 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 28984.137399 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 28984.137399 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 28984.137399 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 28984.137399 # average overall miss latency
509,514c509,514
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2096 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 2096 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 2096 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 2096 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 2096 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 2096 # number of overall MSHR hits
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2097 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 2097 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 2097 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 2097 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 2097 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 2097 # number of overall MSHR hits
521,526c521,526
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 198301998 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 198301998 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 198301998 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 198301998 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 198301998 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 198301998 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 198302998 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 198302998 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 198302998 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 198302998 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 198302998 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 198302998 # number of overall MSHR miss cycles
533,538c533,538
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28928.081400 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28928.081400 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28928.081400 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 28928.081400 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28928.081400 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 28928.081400 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28928.227279 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28928.227279 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28928.227279 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 28928.227279 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28928.227279 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 28928.227279 # average overall mshr miss latency
540,647d539
< system.cpu.dcache.replacements 55 # number of replacements
< system.cpu.dcache.tagsinuse 1411.367255 # Cycle average of tags in use
< system.cpu.dcache.total_refs 67560996 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 1981 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 34104.490661 # Average number of references to valid blocks.
< system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.occ_blocks::cpu.data 1411.367255 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.344572 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.344572 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits::cpu.data 47046789 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 47046789 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 20514009 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 20514009 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 67560798 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 67560798 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 67560798 # number of overall hits
< system.cpu.dcache.overall_hits::total 67560798 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 791 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 791 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 1722 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 1722 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 2513 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 2513 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 2513 # number of overall misses
< system.cpu.dcache.overall_misses::total 2513 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 37144500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 37144500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 76853000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 76853000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 113997500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 113997500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 113997500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 113997500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 47047580 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 47047580 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 67563311 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 67563311 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 67563311 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 67563311 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46958.912769 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 46958.912769 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44630.081301 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 44630.081301 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 45363.111819 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 45363.111819 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 45363.111819 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 45363.111819 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 86 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 43 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.writebacks::writebacks 14 # number of writebacks
< system.cpu.dcache.writebacks::total 14 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 374 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 374 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 376 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 376 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 376 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 376 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 417 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1720 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 1720 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 2137 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 2137 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 2137 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 2137 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22474500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 22474500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73299500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 73299500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 95774000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 95774000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 95774000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 95774000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000084 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53895.683453 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53895.683453 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42615.988372 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42615.988372 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44817.033224 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 44817.033224 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44817.033224 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 44817.033224 # average overall mshr miss latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
649c541
< system.cpu.l2cache.tagsinuse 2509.913634 # Cycle average of tags in use
---
> system.cpu.l2cache.tagsinuse 2509.913640 # Cycle average of tags in use
655,656c547,548
< system.cpu.l2cache.occ_blocks::cpu.inst 2234.774408 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 274.236525 # Average occupied blocks per requestor
---
> system.cpu.l2cache.occ_blocks::cpu.inst 2234.774413 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 274.236526 # Average occupied blocks per requestor
687,689c579,581
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 158303000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21677500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 179980500 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 158304000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21677000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 179981000 # number of ReadReq miss cycles
692,697c584,589
< system.cpu.l2cache.demand_miss_latency::cpu.inst 158303000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 89911500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 248214500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 158303000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 89911500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 248214500 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 158304000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 89911000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 248215000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 158304000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 89911000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 248215000 # number of overall miss cycles
726,728c618,620
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 46532.333921 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56159.326425 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 47513.331573 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 46532.627866 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56158.031088 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 47513.463569 # average ReadReq miss latency
731,736c623,628
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 46532.333921 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46203.237410 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 46412.584144 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 46532.333921 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46203.237410 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 46412.584144 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 46532.627866 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46202.980473 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 46412.677636 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 46532.627866 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46202.980473 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 46412.677636 # average overall miss latency
758,759c650,651
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115394483 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16844598 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115394983 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16844098 # number of ReadReq MSHR miss cycles
765,766c657,658
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115394483 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 65277091 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115394983 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 65276591 # number of demand (read+write) MSHR miss cycles
768,769c660,661
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115394483 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 65277091 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115394983 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 65276591 # number of overall MSHR miss cycles
784,785c676,677
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33919.601117 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43638.854922 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33919.748089 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43637.559585 # average ReadReq mshr miss latency
791,792c683,684
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33919.601117 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33544.239979 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33919.748089 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33543.983042 # average overall mshr miss latency
794,795c686,687
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33919.601117 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33544.239979 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33919.748089 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33543.983042 # average overall mshr miss latency
797a690,797
> system.cpu.dcache.replacements 55 # number of replacements
> system.cpu.dcache.tagsinuse 1411.367257 # Cycle average of tags in use
> system.cpu.dcache.total_refs 67560996 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 1981 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 34104.490661 # Average number of references to valid blocks.
> system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.occ_blocks::cpu.data 1411.367257 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.344572 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.344572 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 47046789 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 47046789 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 20514009 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 20514009 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 67560798 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 67560798 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 67560798 # number of overall hits
> system.cpu.dcache.overall_hits::total 67560798 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 791 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 791 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 1722 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 1722 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 2513 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 2513 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 2513 # number of overall misses
> system.cpu.dcache.overall_misses::total 2513 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 37144000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 37144000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 76853000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 76853000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 113997000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 113997000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 113997000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 113997000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 47047580 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 47047580 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 67563311 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 67563311 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 67563311 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 67563311 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46958.280657 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 46958.280657 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44630.081301 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 44630.081301 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 45362.912853 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 45362.912853 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 45362.912853 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 45362.912853 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 86 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 43 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.writebacks::writebacks 14 # number of writebacks
> system.cpu.dcache.writebacks::total 14 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 374 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 374 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 376 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 376 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 376 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 376 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 417 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1720 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 1720 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 2137 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 2137 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 2137 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 2137 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22474000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 22474000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73299500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 73299500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 95773500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 95773500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 95773500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 95773500 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000084 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53894.484412 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53894.484412 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42615.988372 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42615.988372 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44816.799251 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 44816.799251 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44816.799251 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 44816.799251 # average overall mshr miss latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate