7,11c7,11
< host_inst_rate 56809 # Simulator instruction rate (inst/s)
< host_op_rate 95217 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 37745520 # Simulator tick rate (ticks/s)
< host_mem_usage 259224 # Number of bytes of host memory used
< host_seconds 2324.83 # Real time elapsed on the host
---
> host_inst_rate 66952 # Simulator instruction rate (inst/s)
> host_op_rate 112217 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 44484510 # Simulator tick rate (ticks/s)
> host_mem_usage 236376 # Number of bytes of host memory used
> host_seconds 1972.64 # Real time elapsed on the host
14,22c14,29
< system.physmem.bytes_read 345024 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 219584 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 0 # Number of bytes written to this memory
< system.physmem.num_reads 5391 # Number of read requests responded to by this memory
< system.physmem.num_writes 0 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 3931820 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 2502332 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total 3931820 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 219584 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 125440 # Number of bytes read from this memory
> system.physmem.bytes_read::total 345024 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 219584 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 219584 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 3431 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 1960 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 5391 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 2502332 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 1429487 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 3931820 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 2502332 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 2502332 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 2502332 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 1429487 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 3931820 # Total bandwidth to/from this memory (bytes/s)
325a333
> system.cpu.icache.ReadReq_miss_rate::total 0.000352 # miss rate for ReadReq accesses
326a335
> system.cpu.icache.demand_miss_rate::total 0.000352 # miss rate for demand accesses
327a337
> system.cpu.icache.overall_miss_rate::total 0.000352 # miss rate for overall accesses
328a339
> system.cpu.icache.ReadReq_avg_miss_latency::total 20598.922248 # average ReadReq miss latency
329a341
> system.cpu.icache.demand_avg_miss_latency::total 20598.922248 # average overall miss latency
330a343
> system.cpu.icache.overall_avg_miss_latency::total 20598.922248 # average overall miss latency
357a371
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000299 # mshr miss rate for ReadReq accesses
358a373
> system.cpu.icache.demand_mshr_miss_rate::total 0.000299 # mshr miss rate for demand accesses
359a375
> system.cpu.icache.overall_mshr_miss_rate::total 0.000299 # mshr miss rate for overall accesses
360a377
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16908.426094 # average ReadReq mshr miss latency
361a379
> system.cpu.icache.demand_avg_mshr_miss_latency::total 16908.426094 # average overall mshr miss latency
362a381
> system.cpu.icache.overall_avg_mshr_miss_latency::total 16908.426094 # average overall mshr miss latency
405a425
> system.cpu.dcache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses
406a427
> system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses
407a429
> system.cpu.dcache.demand_miss_rate::total 0.000036 # miss rate for demand accesses
408a431
> system.cpu.dcache.overall_miss_rate::total 0.000036 # miss rate for overall accesses
409a433
> system.cpu.dcache.ReadReq_avg_miss_latency::total 32154.792746 # average ReadReq miss latency
410a435
> system.cpu.dcache.WriteReq_avg_miss_latency::total 37945.804196 # average WriteReq miss latency
411a437
> system.cpu.dcache.demand_avg_miss_latency::total 36148.914791 # average overall miss latency
412a439
> system.cpu.dcache.overall_avg_miss_latency::total 36148.914791 # average overall miss latency
447a475
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
448a477
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000083 # mshr miss rate for WriteReq accesses
449a479
> system.cpu.dcache.demand_mshr_miss_rate::total 0.000031 # mshr miss rate for demand accesses
450a481
> system.cpu.dcache.overall_mshr_miss_rate::total 0.000031 # mshr miss rate for overall accesses
451a483
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32985.260771 # average ReadReq mshr miss latency
452a485
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34949.211909 # average WriteReq mshr miss latency
453a487
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 34547.121634 # average overall mshr miss latency
454a489
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 34547.121634 # average overall mshr miss latency
522a558
> system.cpu.l2cache.ReadReq_miss_rate::total 0.479341 # miss rate for ReadReq accesses
523a560
> system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
524a562
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.994869 # miss rate for ReadExReq accesses
526a565
> system.cpu.l2cache.demand_miss_rate::total 0.563323 # miss rate for demand accesses
528a568
> system.cpu.l2cache.overall_miss_rate::total 0.563323 # miss rate for overall accesses
530a571
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 34243.489583 # average ReadReq miss latency
531a573
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34168.923275 # average ReadExReq miss latency
533a576
> system.cpu.l2cache.demand_avg_miss_latency::total 34222.036728 # average overall miss latency
535a579
> system.cpu.l2cache.overall_avg_miss_latency::total 34222.036728 # average overall miss latency
571a616
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.479341 # mshr miss rate for ReadReq accesses
572a618
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
573a620
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994869 # mshr miss rate for ReadExReq accesses
575a623
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.563323 # mshr miss rate for demand accesses
577a626
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.563323 # mshr miss rate for overall accesses
579a629
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31020.052083 # average ReadReq mshr miss latency
580a631
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency
581a633
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31019.019987 # average ReadExReq mshr miss latency
583a636
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31019.755147 # average overall mshr miss latency
585a639
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31019.755147 # average overall mshr miss latency
< host_inst_rate 56809 # Simulator instruction rate (inst/s)
< host_op_rate 95217 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 37745520 # Simulator tick rate (ticks/s)
< host_mem_usage 259224 # Number of bytes of host memory used
< host_seconds 2324.83 # Real time elapsed on the host
---
> host_inst_rate 66952 # Simulator instruction rate (inst/s)
> host_op_rate 112217 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 44484510 # Simulator tick rate (ticks/s)
> host_mem_usage 236376 # Number of bytes of host memory used
> host_seconds 1972.64 # Real time elapsed on the host
14,22c14,29
< system.physmem.bytes_read 345024 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 219584 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 0 # Number of bytes written to this memory
< system.physmem.num_reads 5391 # Number of read requests responded to by this memory
< system.physmem.num_writes 0 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 3931820 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 2502332 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total 3931820 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 219584 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 125440 # Number of bytes read from this memory
> system.physmem.bytes_read::total 345024 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 219584 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 219584 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 3431 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 1960 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 5391 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 2502332 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 1429487 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 3931820 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 2502332 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 2502332 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 2502332 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 1429487 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 3931820 # Total bandwidth to/from this memory (bytes/s)
325a333
> system.cpu.icache.ReadReq_miss_rate::total 0.000352 # miss rate for ReadReq accesses
326a335
> system.cpu.icache.demand_miss_rate::total 0.000352 # miss rate for demand accesses
327a337
> system.cpu.icache.overall_miss_rate::total 0.000352 # miss rate for overall accesses
328a339
> system.cpu.icache.ReadReq_avg_miss_latency::total 20598.922248 # average ReadReq miss latency
329a341
> system.cpu.icache.demand_avg_miss_latency::total 20598.922248 # average overall miss latency
330a343
> system.cpu.icache.overall_avg_miss_latency::total 20598.922248 # average overall miss latency
357a371
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000299 # mshr miss rate for ReadReq accesses
358a373
> system.cpu.icache.demand_mshr_miss_rate::total 0.000299 # mshr miss rate for demand accesses
359a375
> system.cpu.icache.overall_mshr_miss_rate::total 0.000299 # mshr miss rate for overall accesses
360a377
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16908.426094 # average ReadReq mshr miss latency
361a379
> system.cpu.icache.demand_avg_mshr_miss_latency::total 16908.426094 # average overall mshr miss latency
362a381
> system.cpu.icache.overall_avg_mshr_miss_latency::total 16908.426094 # average overall mshr miss latency
405a425
> system.cpu.dcache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses
406a427
> system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses
407a429
> system.cpu.dcache.demand_miss_rate::total 0.000036 # miss rate for demand accesses
408a431
> system.cpu.dcache.overall_miss_rate::total 0.000036 # miss rate for overall accesses
409a433
> system.cpu.dcache.ReadReq_avg_miss_latency::total 32154.792746 # average ReadReq miss latency
410a435
> system.cpu.dcache.WriteReq_avg_miss_latency::total 37945.804196 # average WriteReq miss latency
411a437
> system.cpu.dcache.demand_avg_miss_latency::total 36148.914791 # average overall miss latency
412a439
> system.cpu.dcache.overall_avg_miss_latency::total 36148.914791 # average overall miss latency
447a475
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
448a477
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000083 # mshr miss rate for WriteReq accesses
449a479
> system.cpu.dcache.demand_mshr_miss_rate::total 0.000031 # mshr miss rate for demand accesses
450a481
> system.cpu.dcache.overall_mshr_miss_rate::total 0.000031 # mshr miss rate for overall accesses
451a483
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32985.260771 # average ReadReq mshr miss latency
452a485
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34949.211909 # average WriteReq mshr miss latency
453a487
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 34547.121634 # average overall mshr miss latency
454a489
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 34547.121634 # average overall mshr miss latency
522a558
> system.cpu.l2cache.ReadReq_miss_rate::total 0.479341 # miss rate for ReadReq accesses
523a560
> system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
524a562
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.994869 # miss rate for ReadExReq accesses
526a565
> system.cpu.l2cache.demand_miss_rate::total 0.563323 # miss rate for demand accesses
528a568
> system.cpu.l2cache.overall_miss_rate::total 0.563323 # miss rate for overall accesses
530a571
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 34243.489583 # average ReadReq miss latency
531a573
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34168.923275 # average ReadExReq miss latency
533a576
> system.cpu.l2cache.demand_avg_miss_latency::total 34222.036728 # average overall miss latency
535a579
> system.cpu.l2cache.overall_avg_miss_latency::total 34222.036728 # average overall miss latency
571a616
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.479341 # mshr miss rate for ReadReq accesses
572a618
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
573a620
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994869 # mshr miss rate for ReadExReq accesses
575a623
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.563323 # mshr miss rate for demand accesses
577a626
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.563323 # mshr miss rate for overall accesses
579a629
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31020.052083 # average ReadReq mshr miss latency
580a631
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency
581a633
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31019.019987 # average ReadExReq mshr miss latency
583a636
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31019.755147 # average overall mshr miss latency
585a639
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31019.755147 # average overall mshr miss latency