3,5c3,5
< sim_seconds 0.079147 # Number of seconds simulated
< sim_ticks 79147317000 # Number of ticks simulated
< final_tick 79147317000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.079190 # Number of seconds simulated
> sim_ticks 79190347500 # Number of ticks simulated
> final_tick 79190347500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 70947 # Simulator instruction rate (inst/s)
< host_op_rate 118914 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 42517019 # Simulator tick rate (ticks/s)
< host_mem_usage 343896 # Number of bytes of host memory used
< host_seconds 1861.54 # Real time elapsed on the host
---
> host_inst_rate 91850 # Simulator instruction rate (inst/s)
> host_op_rate 153949 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 55073733 # Simulator tick rate (ticks/s)
> host_mem_usage 350132 # Number of bytes of host memory used
> host_seconds 1437.90 # Real time elapsed on the host
16,32c16,32
< system.physmem.bytes_read::cpu.inst 221376 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 124928 # Number of bytes read from this memory
< system.physmem.bytes_read::total 346304 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 221376 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 221376 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 3459 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 1952 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 5411 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 2797012 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 1578424 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 4375436 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 2797012 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 2797012 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 2797012 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 1578424 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 4375436 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 5413 # Number of read requests accepted
---
> system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 125120 # Number of bytes read from this memory
> system.physmem.bytes_read::total 345920 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 220800 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 220800 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 3450 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 1955 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 5405 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 2788219 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 1579991 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 4368209 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 2788219 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 2788219 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 2788219 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 1579991 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 4368209 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 5405 # Number of read requests accepted
34c34
< system.physmem.readBursts 5413 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 5405 # Number of DRAM read bursts, including those serviced by the write queue
36c36
< system.physmem.bytesReadDRAM 346304 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 345920 # Total number of bytes read from DRAM
39c39
< system.physmem.bytesReadSys 346432 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 345920 # Total read bytes from the system interface side
43c43
< system.physmem.neitherReadNorWriteReqs 303 # Number of requests that are neither read nor write
---
> system.physmem.neitherReadNorWriteReqs 296 # Number of requests that are neither read nor write
45c45
< system.physmem.perBankRdBursts::1 344 # Per bank write bursts
---
> system.physmem.perBankRdBursts::1 345 # Per bank write bursts
47,52c47,52
< system.physmem.perBankRdBursts::3 354 # Per bank write bursts
< system.physmem.perBankRdBursts::4 343 # Per bank write bursts
< system.physmem.perBankRdBursts::5 326 # Per bank write bursts
< system.physmem.perBankRdBursts::6 401 # Per bank write bursts
< system.physmem.perBankRdBursts::7 385 # Per bank write bursts
< system.physmem.perBankRdBursts::8 338 # Per bank write bursts
---
> system.physmem.perBankRdBursts::3 350 # Per bank write bursts
> system.physmem.perBankRdBursts::4 340 # Per bank write bursts
> system.physmem.perBankRdBursts::5 325 # Per bank write bursts
> system.physmem.perBankRdBursts::6 403 # Per bank write bursts
> system.physmem.perBankRdBursts::7 384 # Per bank write bursts
> system.physmem.perBankRdBursts::8 342 # Per bank write bursts
54,59c54,59
< system.physmem.perBankRdBursts::10 237 # Per bank write bursts
< system.physmem.perBankRdBursts::11 285 # Per bank write bursts
< system.physmem.perBankRdBursts::12 221 # Per bank write bursts
< system.physmem.perBankRdBursts::13 466 # Per bank write bursts
< system.physmem.perBankRdBursts::14 386 # Per bank write bursts
< system.physmem.perBankRdBursts::15 284 # Per bank write bursts
---
> system.physmem.perBankRdBursts::10 239 # Per bank write bursts
> system.physmem.perBankRdBursts::11 284 # Per bank write bursts
> system.physmem.perBankRdBursts::12 217 # Per bank write bursts
> system.physmem.perBankRdBursts::13 467 # Per bank write bursts
> system.physmem.perBankRdBursts::14 385 # Per bank write bursts
> system.physmem.perBankRdBursts::15 283 # Per bank write bursts
78c78
< system.physmem.totGap 79147284500 # Total gap between requests
---
> system.physmem.totGap 79190259000 # Total gap between requests
85c85
< system.physmem.readPktSize::6 5413 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 5405 # Read request sizes (log2)
93,97c93,97
< system.physmem.rdQLenPdf::0 4288 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 911 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 178 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 4301 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 898 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 174 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 28 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
189,209c189,209
< system.physmem.bytesPerActivate::samples 1109 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 312.266907 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 183.102740 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 326.449427 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 425 38.32% 38.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 245 22.09% 60.41% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 103 9.29% 69.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 58 5.23% 74.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 62 5.59% 80.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 52 4.69% 85.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 24 2.16% 87.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 18 1.62% 89.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 122 11.00% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1109 # Bytes accessed per row activation
< system.physmem.totQLat 39588000 # Total ticks spent queuing
< system.physmem.totMemAccLat 141044250 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 27055000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 7313.50 # Average queueing delay per DRAM burst
< system.physmem.avgBusLat 4998.15 # Average bus latency per DRAM burst
< system.physmem.avgMemAccLat 26056.58 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 4.38 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.bytesPerActivate::samples 1097 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 314.107566 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 184.474477 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 326.278271 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 419 38.20% 38.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 241 21.97% 60.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 97 8.84% 69.01% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 63 5.74% 74.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 63 5.74% 80.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 54 4.92% 85.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 22 2.01% 87.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 17 1.55% 88.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 121 11.03% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1097 # Bytes accessed per row activation
> system.physmem.totQLat 39419500 # Total ticks spent queuing
> system.physmem.totMemAccLat 140763250 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 27025000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 7293.15 # Average queueing delay per DRAM burst
> system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
> system.physmem.avgMemAccLat 26043.15 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 4.37 # Average DRAM read bandwidth in MiByte/s
211c211
< system.physmem.avgRdBWSys 4.38 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 4.37 # Average system read bandwidth in MiByte/s
217c217
< system.physmem.avgRdQLen 1.32 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing
219c219
< system.physmem.readRowHits 4302 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 4299 # Number of row buffer hits during reads
221c221
< system.physmem.readRowHitRate 79.48 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 79.54 # Row buffer hit rate for reads
223,227c223,227
< system.physmem.avgGap 14621704.14 # Average gap between requests
< system.physmem.pageHitRate 79.48 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 4951800 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 2701875 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 22721400 # Energy for read commands per rank (pJ)
---
> system.physmem.avgGap 14651296.76 # Average gap between requests
> system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 4883760 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 2664750 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 22565400 # Energy for read commands per rank (pJ)
229,235c229,235
< system.physmem_0.refreshEnergy 5169512400 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 2476092825 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 45316483500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 52992463800 # Total energy per rank (pJ)
< system.physmem_0.averagePower 669.540663 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 75384383500 # Time in different power states
< system.physmem_0.memoryStateTime::REF 2642640000 # Time in different power states
---
> system.physmem_0.refreshEnergy 5172055200 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 2473079805 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 45342485250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 53017734165 # Total energy per rank (pJ)
> system.physmem_0.averagePower 669.530615 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 75427842500 # Time in different power states
> system.physmem_0.memoryStateTime::REF 2644200000 # Time in different power states
237c237
< system.physmem_0.memoryStateTime::ACT 1120221500 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 1114667500 # Time in different power states
239,241c239,241
< system.physmem_1.actEnergy 3432240 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 1872750 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 19484400 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 3402000 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 1856250 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 19305000 # Energy for read commands per rank (pJ)
243,249c243,249
< system.physmem_1.refreshEnergy 5169512400 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 2281510215 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 45487170000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 52962982005 # Total energy per rank (pJ)
< system.physmem_1.averagePower 669.168172 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 75669637750 # Time in different power states
< system.physmem_1.memoryStateTime::REF 2642640000 # Time in different power states
---
> system.physmem_1.refreshEnergy 5172055200 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 2272318965 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 45518583000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 52987520415 # Total energy per rank (pJ)
> system.physmem_1.averagePower 669.149179 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 75723788000 # Time in different power states
> system.physmem_1.memoryStateTime::REF 2644200000 # Time in different power states
251c251
< system.physmem_1.memoryStateTime::ACT 834967250 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 820354000 # Time in different power states
253,257c253,257
< system.cpu.branchPred.lookups 20588400 # Number of BP lookups
< system.cpu.branchPred.condPredicted 20588400 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 1327971 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 12696525 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 12013993 # Number of BTB hits
---
> system.cpu.branchPred.lookups 20589195 # Number of BP lookups
> system.cpu.branchPred.condPredicted 20589195 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 1327817 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 12690862 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 12013274 # Number of BTB hits
259,261c259,261
< system.cpu.branchPred.BTBHitPct 94.624261 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 1440282 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 16776 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 94.660820 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 1440361 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 16897 # Number of incorrect RAS predictions.
265c265
< system.cpu.numCycles 158294635 # number of cpu cycles simulated
---
> system.cpu.numCycles 158380696 # number of cpu cycles simulated
268,276c268,276
< system.cpu.fetch.icacheStallCycles 25247816 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 227405263 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 20588400 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 13454275 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 131222766 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 3194613 # Number of cycles fetch has spent squashing
< system.cpu.fetch.TlbCycles 4 # Number of cycles fetch has spent waiting for tlb
< system.cpu.fetch.MiscStallCycles 1919 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 20727 # Number of stall cycles due to pending traps
---
> system.cpu.fetch.icacheStallCycles 25245702 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 227408017 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 20589195 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 13453635 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 131309354 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 3192879 # Number of cycles fetch has spent squashing
> system.cpu.fetch.TlbCycles 16 # Number of cycles fetch has spent waiting for tlb
> system.cpu.fetch.MiscStallCycles 1952 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 21042 # Number of stall cycles due to pending traps
279,283c279,283
< system.cpu.fetch.CacheLines 24255799 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 267811 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 158090598 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 2.379045 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 3.324681 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 24254364 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 267325 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 158174565 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 2.377629 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 3.324169 # Number of instructions fetched each cycle (Total)
285,293c285,293
< system.cpu.fetch.rateDist::0 95773120 60.58% 60.58% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 4766421 3.01% 63.60% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 3796193 2.40% 66.00% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 4366321 2.76% 68.76% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 4228924 2.68% 71.43% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 4813507 3.04% 74.48% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 4702194 2.97% 77.45% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 3700875 2.34% 79.79% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 31943043 20.21% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 95855369 60.60% 60.60% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 4772394 3.02% 63.62% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 3794325 2.40% 66.02% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 4370382 2.76% 68.78% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 4226374 2.67% 71.45% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 4818979 3.05% 74.50% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 4692035 2.97% 77.46% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 3702011 2.34% 79.81% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 31942696 20.19% 100.00% # Number of instructions fetched each cycle (Total)
297,320c297,320
< system.cpu.fetch.rateDist::total 158090598 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.130064 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.436595 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 15405711 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 96196393 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 23270128 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 21621060 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 1597306 # Number of cycles decode is squashing
< system.cpu.decode.DecodedInsts 336557336 # Number of instructions handled by decode
< system.cpu.rename.SquashCycles 1597306 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 23296942 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 31816084 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 30705 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 35988234 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 65361327 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 328199746 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 1272 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 57739687 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 7687780 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 164697 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 380395487 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 909798638 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 600491080 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 4191135 # Number of floating rename lookups
---
> system.cpu.fetch.rateDist::total 158174565 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.129998 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.435832 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 15399565 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 96291119 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 23261573 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 21625869 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 1596439 # Number of cycles decode is squashing
> system.cpu.decode.DecodedInsts 336537122 # Number of instructions handled by decode
> system.cpu.rename.SquashCycles 1596439 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 23302832 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 31798352 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 30486 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 35975056 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 65471400 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 328175182 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 1530 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 57810134 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 7763747 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 166308 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 380366291 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 909731361 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 600445935 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 4186121 # Number of floating rename lookups
322,339c322,339
< system.cpu.rename.UndoneMaps 120966037 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 1948 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 1925 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 121028118 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 82726275 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 29782185 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 59498195 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 20364114 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 317775977 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 4062 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 259339716 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 70716 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 96416655 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 197093622 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 2817 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 158090598 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 1.640450 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.524161 # Number of insts issued each cycle
---
> system.cpu.rename.UndoneMaps 120936841 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 1921 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 1898 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 121141633 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 82738842 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 29779777 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 59550134 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 20391789 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 317761802 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 4069 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 259358612 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 72184 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 96402487 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 196983368 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 2824 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 158174565 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 1.639699 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.523293 # Number of insts issued each cycle
341,349c341,349
< system.cpu.iq.issued_per_cycle::0 40031018 25.32% 25.32% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 47550925 30.08% 55.40% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 33058238 20.91% 76.31% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 17999758 11.39% 87.70% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 10966409 6.94% 94.63% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 4755401 3.01% 97.64% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 2459487 1.56% 99.20% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 881418 0.56% 99.75% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 387944 0.25% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 40029224 25.31% 25.31% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 47620381 30.11% 55.41% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 33114320 20.94% 76.35% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 17999452 11.38% 87.73% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 10926984 6.91% 94.64% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 4757371 3.01% 97.64% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 2459469 1.55% 99.20% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 879282 0.56% 99.75% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 388082 0.25% 100.00% # Number of insts issued each cycle
353c353
< system.cpu.iq.issued_per_cycle::total 158090598 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 158174565 # Number of insts issued each cycle
355,385c355,385
< system.cpu.iq.fu_full::IntAlu 232409 7.35% 7.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 7.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 7.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 7.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 7.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 7.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 2543467 80.43% 87.78% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 386453 12.22% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 231613 7.32% 7.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 7.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 7.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 7.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 7.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 7.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 2544922 80.40% 87.72% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 388680 12.28% 100.00% # attempts to use FU when none available
388,419c388,419
< system.cpu.iq.FU_type_0::No_OpClass 1213129 0.47% 0.47% # Type of FU issued
< system.cpu.iq.FU_type_0::IntAlu 161789317 62.39% 62.85% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 789379 0.30% 63.16% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 7038032 2.71% 65.87% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 1187047 0.46% 66.33% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.33% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.33% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.33% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.33% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.33% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 64866508 25.01% 91.34% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 22456304 8.66% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::No_OpClass 1213055 0.47% 0.47% # Type of FU issued
> system.cpu.iq.FU_type_0::IntAlu 161788642 62.38% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 789415 0.30% 63.15% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 7038152 2.71% 65.87% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 1187589 0.46% 66.32% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.32% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.32% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.32% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.32% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.32% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 64884960 25.02% 91.34% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 22456799 8.66% 100.00% # Type of FU issued
422,434c422,434
< system.cpu.iq.FU_type_0::total 259339716 # Type of FU issued
< system.cpu.iq.rate 1.638335 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 3162329 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.012194 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 675146049 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 410783686 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 253609186 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 4857026 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 3709843 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 2340813 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 258843472 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 2445444 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 18733712 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 259358612 # Type of FU issued
> system.cpu.iq.rate 1.637565 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 3165215 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.012204 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 675270057 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 410763185 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 253622616 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 4859131 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 3700913 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 2341090 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 258863930 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 2446842 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 18717155 # Number of loads that had data forwarded from stores
436,439c436,439
< system.cpu.iew.lsq.thread0.squashedLoads 26076688 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 12661 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 303068 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 9266468 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 26089255 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 12841 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 302099 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 9264060 # Number of stores squashed
442,443c442,443
< system.cpu.iew.lsq.thread0.rescheduledLoads 50753 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 50731 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 43 # Number of times an access to memory failed due to the cache being blocked
445,461c445,461
< system.cpu.iew.iewSquashCycles 1597306 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 12475143 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 492608 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 317780039 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 92128 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 82726275 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 29782185 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 1904 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 385254 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 64210 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 303068 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 551876 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 825683 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 1377559 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 257278299 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 64049933 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 2061417 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 1596439 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 12482349 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 492760 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 317765871 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 91851 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 82738842 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 29779777 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 1874 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 386744 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 63788 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 302099 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 551455 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 825732 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 1377187 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 257295592 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 64068122 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 2063020 # Number of squashed instructions skipped in execute
464,471c464,471
< system.cpu.iew.exec_refs 86328991 # number of memory reference insts executed
< system.cpu.iew.exec_branches 14325599 # Number of branches executed
< system.cpu.iew.exec_stores 22279058 # Number of stores executed
< system.cpu.iew.exec_rate 1.625313 # Inst execution rate
< system.cpu.iew.wb_sent 256636877 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 255949999 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 204329368 # num instructions producing a value
< system.cpu.iew.wb_consumers 369642243 # num instructions consuming a value
---
> system.cpu.iew.exec_refs 86346654 # number of memory reference insts executed
> system.cpu.iew.exec_branches 14327856 # Number of branches executed
> system.cpu.iew.exec_stores 22278532 # Number of stores executed
> system.cpu.iew.exec_rate 1.624539 # Inst execution rate
> system.cpu.iew.wb_sent 256649039 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 255963706 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 204348842 # num instructions producing a value
> system.cpu.iew.wb_consumers 369627181 # num instructions consuming a value
473,474c473,474
< system.cpu.iew.wb_rate 1.616922 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.552776 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 1.616129 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.552851 # average fanout of values written-back
476c476
< system.cpu.commit.commitSquashedInsts 96424533 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 96410316 # The number of squashed insts skipped by commit
478,481c478,481
< system.cpu.commit.branchMispredicts 1329745 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 144946815 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.527204 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.957309 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 1329636 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 145035845 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.526267 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.955883 # Number of insts commited each cycle
483,491c483,491
< system.cpu.commit.committed_per_cycle::0 45502245 31.39% 31.39% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 57364882 39.58% 70.97% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 14168547 9.77% 80.74% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 11990061 8.27% 89.02% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 4061557 2.80% 91.82% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 2847156 1.96% 93.78% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 903972 0.62% 94.41% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 1081775 0.75% 95.15% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 7026620 4.85% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 45546155 31.40% 31.40% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 57399506 39.58% 70.98% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 14176238 9.77% 80.75% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 11993202 8.27% 89.02% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 4061532 2.80% 91.82% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 2861406 1.97% 93.80% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 912773 0.63% 94.43% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 1078264 0.74% 95.17% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 7006769 4.83% 100.00% # Number of insts commited each cycle
495c495
< system.cpu.commit.committed_per_cycle::total 144946815 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 145035845 # Number of insts commited each cycle
541,545c541,545
< system.cpu.commit.bw_lim_events 7026620 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 455708112 # The number of ROB reads
< system.cpu.rob.rob_writes 648756933 # The number of ROB writes
< system.cpu.timesIdled 2654 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 204037 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.commit.bw_lim_events 7006769 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 455802776 # The number of ROB reads
> system.cpu.rob.rob_writes 648723400 # The number of ROB writes
> system.cpu.timesIdled 2658 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 206131 # Total number of cycles that the CPU has spent unscheduled due to idling
548,558c548,558
< system.cpu.cpi 1.198555 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 1.198555 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.834338 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.834338 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 448462774 # number of integer regfile reads
< system.cpu.int_regfile_writes 232558570 # number of integer regfile writes
< system.cpu.fp_regfile_reads 3214394 # number of floating regfile reads
< system.cpu.fp_regfile_writes 1998880 # number of floating regfile writes
< system.cpu.cc_regfile_reads 102524460 # number of cc regfile reads
< system.cpu.cc_regfile_writes 59518831 # number of cc regfile writes
< system.cpu.misc_regfile_reads 132416718 # number of misc regfile reads
---
> system.cpu.cpi 1.199207 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 1.199207 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.833884 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.833884 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 448507967 # number of integer regfile reads
> system.cpu.int_regfile_writes 232568909 # number of integer regfile writes
> system.cpu.fp_regfile_reads 3215393 # number of floating regfile reads
> system.cpu.fp_regfile_writes 1999198 # number of floating regfile writes
> system.cpu.cc_regfile_reads 102530516 # number of cc regfile reads
> system.cpu.cc_regfile_writes 59523273 # number of cc regfile writes
> system.cpu.misc_regfile_reads 132435302 # number of misc regfile reads
560,564c560,564
< system.cpu.dcache.tags.replacements 53 # number of replacements
< system.cpu.dcache.tags.tagsinuse 1431.895248 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 65702088 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1996 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 32916.877756 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.replacements 52 # number of replacements
> system.cpu.dcache.tags.tagsinuse 1432.092422 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 65736813 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 2001 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 32851.980510 # Average number of references to valid blocks.
566,570c566,570
< system.cpu.dcache.tags.occ_blocks::cpu.data 1431.895248 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.349584 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.349584 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_task_id_blocks::1024 1943 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 1432.092422 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.349632 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.349632 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_task_id_blocks::1024 1949 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id
572c572
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 500 # Occupied blocks per task id
574,603c574,603
< system.cpu.dcache.tags.age_task_id_blocks_1024::4 1395 # Occupied blocks per task id
< system.cpu.dcache.tags.occ_task_id_percent::1024 0.474365 # Percentage of cache occupancy per task id
< system.cpu.dcache.tags.tag_accesses 131411014 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 131411014 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 45187780 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 45187780 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 20513887 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 20513887 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 65701667 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 65701667 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 65701667 # number of overall hits
< system.cpu.dcache.overall_hits::total 65701667 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 998 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 998 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 1844 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 1844 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 2842 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 2842 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 2842 # number of overall misses
< system.cpu.dcache.overall_misses::total 2842 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 65947500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 65947500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 129226000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 129226000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 195173500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 195173500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 195173500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 195173500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 45188778 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 45188778 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::4 1397 # Occupied blocks per task id
> system.cpu.dcache.tags.occ_task_id_percent::1024 0.475830 # Percentage of cache occupancy per task id
> system.cpu.dcache.tags.tag_accesses 131480483 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 131480483 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 45222500 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 45222500 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 20513893 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 20513893 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 65736393 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 65736393 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 65736393 # number of overall hits
> system.cpu.dcache.overall_hits::total 65736393 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1010 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1010 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 1838 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 1838 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 2848 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 2848 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 2848 # number of overall misses
> system.cpu.dcache.overall_misses::total 2848 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 65396000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 65396000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 129164500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 129164500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 194560500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 194560500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 194560500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 194560500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 45223510 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 45223510 # number of ReadReq accesses(hits+misses)
606,609c606,609
< system.cpu.dcache.demand_accesses::cpu.data 65704509 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 65704509 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 65704509 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 65704509 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 65739241 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 65739241 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 65739241 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 65739241 # number of overall (read+write) accesses
618,626c618,626
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66079.659319 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 66079.659319 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70079.175705 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 70079.175705 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 68674.700915 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 68674.700915 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 68674.700915 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 68674.700915 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 656 # number of cycles access was blocked
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64748.514851 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 64748.514851 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70274.483134 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 70274.483134 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 68314.782303 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 68314.782303 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 68314.782303 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 68314.782303 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 697 # number of cycles access was blocked
628c628
< system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked
630c630
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 93.714286 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 87.125000 # average number of cycles each access was blocked
634,637c634,637
< system.cpu.dcache.writebacks::writebacks 12 # number of writebacks
< system.cpu.dcache.writebacks::total 12 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 541 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 541 # number of ReadReq MSHR hits
---
> system.cpu.dcache.writebacks::writebacks 10 # number of writebacks
> system.cpu.dcache.writebacks::total 10 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 549 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 549 # number of ReadReq MSHR hits
640,659c640,659
< system.cpu.dcache.demand_mshr_hits::cpu.data 543 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 543 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 543 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 543 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 457 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 457 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1842 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 1842 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 2299 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 2299 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 2299 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 2299 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36552500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 36552500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127238000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 127238000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163790500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 163790500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 163790500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 163790500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 551 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 551 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 551 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 551 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 461 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 461 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1836 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 1836 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 2297 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 2297 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 2297 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 2297 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36137000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 36137000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127182500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 127182500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163319500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 163319500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 163319500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 163319500 # number of overall MSHR miss cycles
662,663c662,663
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000090 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000090 # mshr miss rate for WriteReq accesses
---
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses
668,675c668,675
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79983.588621 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79983.588621 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69076.004343 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69076.004343 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71244.236625 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 71244.236625 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71244.236625 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 71244.236625 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78388.286334 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78388.286334 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69271.514161 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69271.514161 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71101.218981 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 71101.218981 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71101.218981 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 71101.218981 # average overall mshr miss latency
677,681c677,681
< system.cpu.icache.tags.replacements 5044 # number of replacements
< system.cpu.icache.tags.tagsinuse 1638.951309 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 24246301 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 7022 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 3452.905298 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 4970 # number of replacements
> system.cpu.icache.tags.tagsinuse 1639.175035 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 24244955 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 6947 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 3489.989204 # Average number of references to valid blocks.
683,731c683,731
< system.cpu.icache.tags.occ_blocks::cpu.inst 1638.951309 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.800269 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.800269 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 874 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::4 790 # Occupied blocks per task id
< system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 48518920 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 48518920 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 24246303 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 24246303 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 24246303 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 24246303 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 24246303 # number of overall hits
< system.cpu.icache.overall_hits::total 24246303 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 9495 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 9495 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 9495 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 9495 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 9495 # number of overall misses
< system.cpu.icache.overall_misses::total 9495 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 408233999 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 408233999 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 408233999 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 408233999 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 408233999 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 408233999 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 24255798 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 24255798 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 24255798 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 24255798 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 24255798 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 24255798 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000391 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.000391 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.000391 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.000391 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.000391 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.000391 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42994.628647 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 42994.628647 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 42994.628647 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 42994.628647 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 42994.628647 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 42994.628647 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 791 # number of cycles access was blocked
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1639.175035 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.800378 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.800378 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_task_id_blocks::1024 1977 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 870 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::4 793 # Occupied blocks per task id
> system.cpu.icache.tags.occ_task_id_percent::1024 0.965332 # Percentage of cache occupancy per task id
> system.cpu.icache.tags.tag_accesses 48515969 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 48515969 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 24244955 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 24244955 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 24244955 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 24244955 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 24244955 # number of overall hits
> system.cpu.icache.overall_hits::total 24244955 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 9408 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 9408 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 9408 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 9408 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 9408 # number of overall misses
> system.cpu.icache.overall_misses::total 9408 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 407324999 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 407324999 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 407324999 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 407324999 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 407324999 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 407324999 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 24254363 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 24254363 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 24254363 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 24254363 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 24254363 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 24254363 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000388 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.000388 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.000388 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.000388 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.000388 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.000388 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43295.599384 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 43295.599384 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 43295.599384 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 43295.599384 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 43295.599384 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 43295.599384 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 788 # number of cycles access was blocked
733c733
< system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked
735c735
< system.cpu.icache.avg_blocked_cycles::no_mshrs 60.846154 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 65.666667 # average number of cycles each access was blocked
739,768c739,768
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2168 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 2168 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 2168 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 2168 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 2168 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 2168 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7327 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 7327 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 7327 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 7327 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 7327 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 7327 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 310311499 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 310311499 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 310311499 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 310311499 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 310311499 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 310311499 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000302 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000302 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000302 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.000302 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000302 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.000302 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42351.780947 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42351.780947 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42351.780947 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 42351.780947 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42351.780947 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 42351.780947 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2164 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 2164 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 2164 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 2164 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 2164 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 2164 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7244 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 7244 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 7244 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 7244 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 7244 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 7244 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 309481499 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 309481499 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 309481499 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 309481499 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 309481499 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 309481499 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000299 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.000299 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.000299 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42722.459829 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42722.459829 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42722.459829 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 42722.459829 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42722.459829 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 42722.459829 # average overall mshr miss latency
771,774c771,774
< system.cpu.l2cache.tags.tagsinuse 2588.297524 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 8549 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 3882 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 2.202215 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 2588.929088 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 8413 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 3873 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 2.172218 # Average number of references to valid blocks.
776,807c776,807
< system.cpu.l2cache.tags.occ_blocks::writebacks 0.823385 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 2282.748954 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 304.725185 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.000025 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069664 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.009299 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.078989 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 3882 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 994 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 40 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2615 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118469 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 119661 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 119661 # Number of data accesses
< system.cpu.l2cache.Writeback_hits::writebacks 12 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 12 # number of Writeback hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 5 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 5 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3560 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 3560 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 39 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 39 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 3560 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 44 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 3604 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 3560 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 44 # number of overall hits
< system.cpu.l2cache.overall_hits::total 3604 # number of overall hits
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 303 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 303 # number of UpgradeReq misses
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 1.256976 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 2282.894376 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 304.777736 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.000038 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069668 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.009301 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.079008 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 3873 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 989 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 39 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2616 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118195 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 118429 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 118429 # Number of data accesses
> system.cpu.l2cache.Writeback_hits::writebacks 10 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 10 # number of Writeback hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 6 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 6 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3494 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 3494 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 40 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 40 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 3494 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 46 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 3540 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 3494 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 46 # number of overall hits
> system.cpu.l2cache.overall_hits::total 3540 # number of overall hits
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 296 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 296 # number of UpgradeReq misses
810,847c810,847
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3462 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 3462 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 418 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 418 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 3462 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 1952 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 5414 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 3462 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 1952 # number of overall misses
< system.cpu.l2cache.overall_misses::total 5414 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 115109000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 115109000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 261483000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 261483000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35445000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 35445000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 261483000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 150554000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 412037000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 261483000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 150554000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 412037000 # number of overall miss cycles
< system.cpu.l2cache.Writeback_accesses::writebacks 12 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 12 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 303 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 303 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 1539 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 1539 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 7022 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 7022 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 457 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 457 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 7022 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1996 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 9018 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 7022 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1996 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 9018 # number of overall (read+write) accesses
---
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3451 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 3451 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 421 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 421 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 3451 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 1955 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 5406 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 3451 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 1955 # number of overall misses
> system.cpu.l2cache.overall_misses::total 5406 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 114989000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 114989000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 261344500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 261344500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 34980500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 34980500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 261344500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 149969500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 411314000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 261344500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 149969500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 411314000 # number of overall miss cycles
> system.cpu.l2cache.Writeback_accesses::writebacks 10 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 10 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 296 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 296 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 1540 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 1540 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6945 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 6945 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 461 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 461 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 6945 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 2001 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 8946 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 6945 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 2001 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 8946 # number of overall (read+write) accesses
850,873c850,873
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996751 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.996751 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.493022 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.493022 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.914661 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.914661 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.493022 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.977956 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.600355 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.493022 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.977956 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.600355 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75038.461538 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75038.461538 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75529.462738 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75529.462738 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84796.650718 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84796.650718 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75529.462738 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77128.073770 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 76105.836720 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75529.462738 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77128.073770 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 76105.836720 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996104 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.996104 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.496904 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.496904 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.913232 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.913232 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.496904 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.977011 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.604292 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.496904 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.977011 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.604292 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74960.234681 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74960.234681 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75730.078238 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75730.078238 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83089.073634 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83089.073634 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75730.078238 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76710.741688 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 76084.720681 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75730.078238 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76710.741688 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 76084.720681 # average overall miss latency
882,883c882,883
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 303 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 303 # number of UpgradeReq MSHR misses
---
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 296 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 296 # number of UpgradeReq MSHR misses
886,909c886,909
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3462 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3462 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 418 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 418 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 3462 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 1952 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 5414 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 3462 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 1952 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 5414 # number of overall MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6283500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6283500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 99769000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 99769000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 226893000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 226893000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31265000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31265000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 226893000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131034000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 357927000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 226893000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131034000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 357927000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3451 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3451 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 421 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 421 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 3451 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 1955 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 5406 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 3451 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 1955 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 5406 # number of overall MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6416500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6416500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 99649000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 99649000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 226844500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 226844500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30770500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30770500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 226844500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 130419500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 357264000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 226844500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 130419500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 357264000 # number of overall MSHR miss cycles
912,937c912,937
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996751 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996751 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.493022 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.493022 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.914661 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.914661 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.493022 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.977956 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.600355 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.493022 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.977956 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.600355 # mshr miss rate for overall accesses
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20737.623762 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20737.623762 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65038.461538 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65038.461538 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65538.128250 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65538.128250 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74796.650718 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74796.650718 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65538.128250 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67128.073770 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66111.377909 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65538.128250 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67128.073770 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66111.377909 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996104 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996104 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.496904 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.496904 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.913232 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.913232 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.496904 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.977011 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.604292 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496904 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.977011 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.604292 # mshr miss rate for overall accesses
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21677.364865 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21677.364865 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64960.234681 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64960.234681 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65732.975949 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65732.975949 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73089.073634 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73089.073634 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65732.975949 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66710.741688 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66086.570477 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65732.975949 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66710.741688 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66086.570477 # average overall mshr miss latency
939,957c939,963
< system.cpu.toL2Bus.trans_dist::ReadResp 7781 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 12 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 4947 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 303 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 303 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 1539 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 1539 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 7327 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 457 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19253 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4650 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 23903 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 449216 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128512 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 577728 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 305 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 14723 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_filter.tot_requests 14563 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 5344 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 433 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.trans_dist::ReadResp 7704 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 10 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 4875 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 296 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 296 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 1540 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 1540 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 7244 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 461 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19022 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4645 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 23667 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 444416 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128704 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 573120 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 299 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 14563 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.061251 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.239799 # Request fanout histogram
959,960c965,966
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 14723 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 13671 93.87% 93.87% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 892 6.13% 100.00% # Request fanout histogram
963c969
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
965,966c971,972
< system.cpu.toL2Bus.snoop_fanout::total 14723 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 7373500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 14563 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 7291500 # Layer occupancy (ticks)
968c974
< system.cpu.toL2Bus.respLayer0.occupancy 10986000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 10864500 # Layer occupancy (ticks)
970c976
< system.cpu.toL2Bus.respLayer1.occupancy 3145500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 3149999 # Layer occupancy (ticks)
972,974c978,980
< system.membus.trans_dist::ReadResp 3877 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 303 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 303 # Transaction distribution
---
> system.membus.trans_dist::ReadResp 3871 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 296 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 296 # Transaction distribution
977,983c983,989
< system.membus.trans_dist::ReadSharedReq 3879 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11430 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11430 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 11430 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 346304 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 346304 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 346304 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadSharedReq 3871 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11402 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11402 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 11402 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 345920 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 345920 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 345920 # Cumulative packet size per connected master and slave (bytes)
985c991
< system.membus.snoop_fanout::samples 5716 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 5701 # Request fanout histogram
989c995
< system.membus.snoop_fanout::0 5716 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 5701 100.00% 100.00% # Request fanout histogram
994,995c1000,1001
< system.membus.snoop_fanout::total 5716 # Request fanout histogram
< system.membus.reqLayer0.occupancy 7099000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 5701 # Request fanout histogram
> system.membus.reqLayer0.occupancy 6922500 # Layer occupancy (ticks)
997c1003
< system.membus.respLayer1.occupancy 29276697 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 29231454 # Layer occupancy (ticks)