3sim_seconds 0.102721 # Number of seconds simulated 4sim_ticks 102721386000 # Number of ticks simulated 5final_tick 102721386000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 115023 # Simulator instruction rate (inst/s) 8host_op_rate 192789 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 89461870 # Simulator tick rate (ticks/s) 10host_mem_usage 308536 # Number of bytes of host memory used 11host_seconds 1148.21 # Real time elapsed on the host 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221363384 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 235072 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 130944 # Number of bytes read from this memory 19system.physmem.bytes_read::total 366016 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 235072 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 235072 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 3673 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 2046 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 5719 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 2288443 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 1274749 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 3563192 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 2288443 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 2288443 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 2288443 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 1274749 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 3563192 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 5719 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 5719 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 366016 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 366016 # Total read bytes from the system interface side 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 45system.physmem.perBankRdBursts::0 315 # Per bank write bursts 46system.physmem.perBankRdBursts::1 393 # Per bank write bursts 47system.physmem.perBankRdBursts::2 481 # Per bank write bursts 48system.physmem.perBankRdBursts::3 362 # Per bank write bursts 49system.physmem.perBankRdBursts::4 367 # Per bank write bursts 50system.physmem.perBankRdBursts::5 335 # Per bank write bursts 51system.physmem.perBankRdBursts::6 442 # Per bank write bursts 52system.physmem.perBankRdBursts::7 357 # Per bank write bursts 53system.physmem.perBankRdBursts::8 405 # Per bank write bursts 54system.physmem.perBankRdBursts::9 298 # Per bank write bursts 55system.physmem.perBankRdBursts::10 258 # Per bank write bursts 56system.physmem.perBankRdBursts::11 270 # Per bank write bursts 57system.physmem.perBankRdBursts::12 235 # Per bank write bursts 58system.physmem.perBankRdBursts::13 489 # Per bank write bursts 59system.physmem.perBankRdBursts::14 424 # Per bank write bursts 60system.physmem.perBankRdBursts::15 288 # Per bank write bursts 61system.physmem.perBankWrBursts::0 0 # Per bank write bursts 62system.physmem.perBankWrBursts::1 0 # Per bank write bursts 63system.physmem.perBankWrBursts::2 0 # Per bank write bursts 64system.physmem.perBankWrBursts::3 0 # Per bank write bursts 65system.physmem.perBankWrBursts::4 0 # Per bank write bursts 66system.physmem.perBankWrBursts::5 0 # Per bank write bursts 67system.physmem.perBankWrBursts::6 0 # Per bank write bursts 68system.physmem.perBankWrBursts::7 0 # Per bank write bursts 69system.physmem.perBankWrBursts::8 0 # Per bank write bursts 70system.physmem.perBankWrBursts::9 0 # Per bank write bursts 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 79system.physmem.totGap 102721127000 # Total gap between requests 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 5719 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) 94system.physmem.rdQLenPdf::0 4464 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::1 987 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 224 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 126system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.physmem.bytesPerActivate::samples 1259 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 289.245433 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 165.404896 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 321.969258 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 547 43.45% 43.45% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 270 21.45% 64.89% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 107 8.50% 73.39% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 51 4.05% 77.44% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 47 3.73% 81.18% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 64 5.08% 86.26% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 24 1.91% 88.17% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 25 1.99% 90.15% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 124 9.85% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 1259 # Bytes accessed per row activation 204system.physmem.totQLat 198070500 # Total ticks spent queuing 205system.physmem.totMemAccLat 305301750 # Total ticks spent from burst creation until serviced by the DRAM 206system.physmem.totBusLat 28595000 # Total ticks spent in databus transfers 207system.physmem.avgQLat 34633.76 # Average queueing delay per DRAM burst 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 209system.physmem.avgMemAccLat 53383.76 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 3.56 # Average DRAM read bandwidth in MiByte/s 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 212system.physmem.avgRdBWSys 3.56 # Average system read bandwidth in MiByte/s 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 0.03 # Data bus utilization in percentage 216system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 220system.physmem.readRowHits 4452 # Number of row buffer hits during reads 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes 222system.physmem.readRowHitRate 77.85 # Row buffer hit rate for reads 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 224system.physmem.avgGap 17961379.09 # Average gap between requests 225system.physmem.pageHitRate 77.85 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 5319300 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 2808300 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 21791280 # Energy for read commands per rank (pJ) 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 308549280.000000 # Energy for refresh commands per rank (pJ) 231system.physmem_0.actBackEnergy 94282560 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 17303520 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 739487790 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 445716000 # Energy for precharge power-down per rank (pJ) 235system.physmem_0.selfRefreshEnergy 23991769245 # Energy for self refresh per rank (pJ) 236system.physmem_0.totalEnergy 25627073595 # Total energy per rank (pJ) 237system.physmem_0.averagePower 249.481384 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 102469123000 # Total Idle time Per DRAM Rank 239system.physmem_0.memoryStateTime::IDLE 33581500 # Time in different power states 240system.physmem_0.memoryStateTime::REF 131264000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 99687058000 # Time in different power states 242system.physmem_0.memoryStateTime::PRE_PDN 1160707250 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 87094500 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 1621680750 # Time in different power states 245system.physmem_1.actEnergy 3727080 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 1969605 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 19042380 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 233563200.000000 # Energy for refresh commands per rank (pJ) 250system.physmem_1.actBackEnergy 75326640 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 12588960 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 599034660 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 319716000 # Energy for precharge power-down per rank (pJ) 254system.physmem_1.selfRefreshEnergy 24137455500 # Energy for self refresh per rank (pJ) 255system.physmem_1.totalEnergy 25402424025 # Total energy per rank (pJ) 256system.physmem_1.averagePower 247.294404 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 102523153750 # Total Idle time Per DRAM Rank 258system.physmem_1.memoryStateTime::IDLE 23880000 # Time in different power states 259system.physmem_1.memoryStateTime::REF 99310000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 100377149750 # Time in different power states 261system.physmem_1.memoryStateTime::PRE_PDN 832585250 # Time in different power states 262system.physmem_1.memoryStateTime::ACT 74819500 # Time in different power states 263system.physmem_1.memoryStateTime::ACT_PDN 1313641500 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 40475108 # Number of BP lookups 266system.cpu.branchPred.condPredicted 40475108 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 6616133 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 34806541 # Number of BTB lookups 269system.cpu.branchPred.BTBHits 0 # Number of BTB hits 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 271system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 272system.cpu.branchPred.usedRAS 3130768 # Number of times the RAS was used to get a target. 273system.cpu.branchPred.RASInCorrect 590894 # Number of incorrect RAS predictions. 274system.cpu.branchPred.indirectLookups 34806541 # Number of indirect predictor lookups. 275system.cpu.branchPred.indirectHits 9997740 # Number of indirect target hits. 276system.cpu.branchPred.indirectMisses 24808801 # Number of indirect misses. 277system.cpu.branchPredindirectMispredicted 4890379 # Number of mispredicted indirect branches. 278system.cpu_clk_domain.clock 500 # Clock period in ticks 279system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states 280system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 281system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states 282system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states 283system.cpu.workload.numSyscalls 400 # Number of system calls 284system.cpu.pwrStateResidencyTicks::ON 102721386000 # Cumulative time (in ticks) in various power states 285system.cpu.numCycles 205442773 # number of cpu cycles simulated 286system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 287system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 288system.cpu.fetch.icacheStallCycles 45893468 # Number of cycles fetch is stalled on an Icache miss 289system.cpu.fetch.Insts 415890095 # Number of instructions fetch has processed 290system.cpu.fetch.Branches 40475108 # Number of branches that fetch encountered 291system.cpu.fetch.predictedBranches 13128508 # Number of branches that fetch has predicted taken 292system.cpu.fetch.Cycles 151898710 # Number of cycles fetch has run and was not squashing or blocked 293system.cpu.fetch.SquashCycles 14677491 # Number of cycles fetch has spent squashing 294system.cpu.fetch.TlbCycles 200 # Number of cycles fetch has spent waiting for tlb 295system.cpu.fetch.MiscStallCycles 5835 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 296system.cpu.fetch.PendingTrapStallCycles 64355 # Number of stall cycles due to pending traps 297system.cpu.fetch.PendingQuiesceStallCycles 603 # Number of stall cycles due to pending quiesce instructions 298system.cpu.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR 299system.cpu.fetch.CacheLines 40893606 # Number of cache lines fetched 300system.cpu.fetch.IcacheSquashes 1496111 # Number of outstanding Icache misses that were squashed 301system.cpu.fetch.ItlbSquashes 12 # Number of outstanding ITLB misses that were squashed 302system.cpu.fetch.rateDist::samples 205202132 # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::mean 3.402306 # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::stdev 3.658033 # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::0 98918732 48.21% 48.21% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::1 5142243 2.51% 50.71% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::2 5340112 2.60% 53.31% # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::3 5342271 2.60% 55.92% # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::4 5947890 2.90% 58.82% # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::5 5817544 2.84% 61.65% # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::6 5684313 2.77% 64.42% # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::7 4746268 2.31% 66.73% # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::8 68262759 33.27% 100.00% # Number of instructions fetched each cycle (Total) 315system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 316system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 318system.cpu.fetch.rateDist::total 205202132 # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.branchRate 0.197014 # Number of branch fetches per cycle 320system.cpu.fetch.rate 2.024360 # Number of inst fetches per cycle 321system.cpu.decode.IdleCycles 31935878 # Number of cycles decode is idle 322system.cpu.decode.BlockedCycles 86571693 # Number of cycles decode is blocked 323system.cpu.decode.RunCycles 61623233 # Number of cycles decode is running 324system.cpu.decode.UnblockCycles 17732583 # Number of cycles decode is unblocking 325system.cpu.decode.SquashCycles 7338745 # Number of cycles decode is squashing 326system.cpu.decode.DecodedInsts 585424017 # Number of instructions handled by decode 327system.cpu.rename.SquashCycles 7338745 # Number of cycles rename is squashing 328system.cpu.rename.IdleCycles 41662208 # Number of cycles rename is idle 329system.cpu.rename.BlockCycles 46227710 # Number of cycles rename is blocking 330system.cpu.rename.serializeStallCycles 28975 # count of cycles rename stalled for serializing inst 331system.cpu.rename.RunCycles 68218759 # Number of cycles rename is running 332system.cpu.rename.UnblockCycles 41725735 # Number of cycles rename is unblocking 333system.cpu.rename.RenamedInsts 547333455 # Number of instructions processed by rename 334system.cpu.rename.ROBFullEvents 1808 # Number of times rename has blocked due to ROB full 335system.cpu.rename.IQFullEvents 36710047 # Number of times rename has blocked due to IQ full 336system.cpu.rename.LQFullEvents 4936211 # Number of times rename has blocked due to LQ full 337system.cpu.rename.SQFullEvents 172798 # Number of times rename has blocked due to SQ full 338system.cpu.rename.RenamedOperands 624155686 # Number of destination operands rename has renamed 339system.cpu.rename.RenameLookups 1473918398 # Number of register rename lookups that rename has made 340system.cpu.rename.int_rename_lookups 966803184 # Number of integer rename lookups 341system.cpu.rename.fp_rename_lookups 14714209 # Number of floating rename lookups 342system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed 343system.cpu.rename.UndoneMaps 364726236 # Number of HB maps that are undone due to squashing 344system.cpu.rename.serializingInsts 2257 # count of serializing insts renamed 345system.cpu.rename.tempSerializingInsts 2274 # count of temporary serializing insts renamed 346system.cpu.rename.skidInsts 89803577 # count of insts added to the skid buffer 347system.cpu.memDep0.insertedLoads 127813025 # Number of loads inserted to the mem dependence unit. 348system.cpu.memDep0.insertedStores 45569326 # Number of stores inserted to the mem dependence unit. 349system.cpu.memDep0.conflictingLoads 76700063 # Number of conflicting loads. 350system.cpu.memDep0.conflictingStores 25076085 # Number of conflicting stores. 351system.cpu.iq.iqInstsAdded 486700618 # Number of instructions added to the IQ (excludes non-spec) 352system.cpu.iq.iqNonSpecInstsAdded 63617 # Number of non-speculative instructions added to the IQ 353system.cpu.iq.iqInstsIssued 336591199 # Number of instructions issued 354system.cpu.iq.iqSquashedInstsIssued 1075816 # Number of squashed instructions issued 355system.cpu.iq.iqSquashedInstsExamined 265400851 # Number of squashed instructions iterated over during squash; mainly for profiling 356system.cpu.iq.iqSquashedOperandsExamined 520101355 # Number of squashed operands that are examined and possibly removed from graph 357system.cpu.iq.iqSquashedNonSpecRemoved 62372 # Number of squashed non-spec instructions that were removed 358system.cpu.iq.issued_per_cycle::samples 205202132 # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::mean 1.640291 # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::stdev 1.801229 # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::0 72558879 35.36% 35.36% # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::1 46563371 22.69% 58.05% # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::2 32833591 16.00% 74.05% # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::3 20829399 10.15% 84.20% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::4 14957397 7.29% 91.49% # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::5 8327086 4.06% 95.55% # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::6 5158088 2.51% 98.06% # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::7 2335665 1.14% 99.20% # Number of insts issued each cycle 370system.cpu.iq.issued_per_cycle::8 1638656 0.80% 100.00% # Number of insts issued each cycle 371system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 374system.cpu.iq.issued_per_cycle::total 205202132 # Number of insts issued each cycle 375system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 376system.cpu.iq.fu_full::IntAlu 746075 18.99% 18.99% # attempts to use FU when none available 377system.cpu.iq.fu_full::IntMult 0 0.00% 18.99% # attempts to use FU when none available 378system.cpu.iq.fu_full::IntDiv 0 0.00% 18.99% # attempts to use FU when none available 379system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.99% # attempts to use FU when none available 380system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.99% # attempts to use FU when none available 381system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.99% # attempts to use FU when none available 382system.cpu.iq.fu_full::FloatMult 0 0.00% 18.99% # attempts to use FU when none available 383system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 18.99% # attempts to use FU when none available 384system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.99% # attempts to use FU when none available 385system.cpu.iq.fu_full::FloatMisc 0 0.00% 18.99% # attempts to use FU when none available 386system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.99% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.99% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.99% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.99% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.99% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.99% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.99% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdMult 0 0.00% 18.99% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.99% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdShift 0 0.00% 18.99% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.99% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.99% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.99% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.99% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.99% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.99% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.99% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.99% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.99% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.99% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.99% # attempts to use FU when none available 407system.cpu.iq.fu_full::MemRead 2709270 68.98% 87.97% # attempts to use FU when none available 408system.cpu.iq.fu_full::MemWrite 425878 10.84% 98.81% # attempts to use FU when none available 409system.cpu.iq.fu_full::FloatMemRead 43262 1.10% 99.91% # attempts to use FU when none available 410system.cpu.iq.fu_full::FloatMemWrite 3383 0.09% 100.00% # attempts to use FU when none available 411system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 412system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 413system.cpu.iq.FU_type_0::No_OpClass 1212158 0.36% 0.36% # Type of FU issued 414system.cpu.iq.FU_type_0::IntAlu 215249611 63.95% 64.31% # Type of FU issued 415system.cpu.iq.FU_type_0::IntMult 800532 0.24% 64.55% # Type of FU issued 416system.cpu.iq.FU_type_0::IntDiv 7048368 2.09% 66.64% # Type of FU issued 417system.cpu.iq.FU_type_0::FloatAdd 1789279 0.53% 67.17% # Type of FU issued 418system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.17% # Type of FU issued 419system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.17% # Type of FU issued 420system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.17% # Type of FU issued 421system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.17% # Type of FU issued 422system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.17% # Type of FU issued 423system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.17% # Type of FU issued 424system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.17% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.17% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.17% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.17% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.17% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.17% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.17% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.17% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.17% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.17% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.17% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.17% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.17% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.17% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.17% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.17% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.17% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.17% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.17% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.17% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.17% # Type of FU issued 445system.cpu.iq.FU_type_0::MemRead 82235879 24.43% 91.61% # Type of FU issued 446system.cpu.iq.FU_type_0::MemWrite 26412297 7.85% 99.45% # Type of FU issued 447system.cpu.iq.FU_type_0::FloatMemRead 1712250 0.51% 99.96% # Type of FU issued 448system.cpu.iq.FU_type_0::FloatMemWrite 130825 0.04% 100.00% # Type of FU issued 449system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 450system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 451system.cpu.iq.FU_type_0::total 336591199 # Type of FU issued 452system.cpu.iq.rate 1.638370 # Inst issue rate 453system.cpu.iq.fu_busy_cnt 3927868 # FU busy when requested 454system.cpu.iq.fu_busy_rate 0.011670 # FU busy rate (busy events/executed inst) 455system.cpu.iq.int_inst_queue_reads 875283157 # Number of integer instruction queue reads 456system.cpu.iq.int_inst_queue_writes 737961913 # Number of integer instruction queue writes 457system.cpu.iq.int_inst_queue_wakeup_accesses 314539873 # Number of integer instruction queue wakeup accesses 458system.cpu.iq.fp_inst_queue_reads 8105057 # Number of floating instruction queue reads 459system.cpu.iq.fp_inst_queue_writes 15024545 # Number of floating instruction queue writes 460system.cpu.iq.fp_inst_queue_wakeup_accesses 3526208 # Number of floating instruction queue wakeup accesses 461system.cpu.iq.int_alu_accesses 335233754 # Number of integer alu accesses 462system.cpu.iq.fp_alu_accesses 4073155 # Number of floating point alu accesses 463system.cpu.iew.lsq.thread0.forwLoads 18221671 # Number of loads that had data forwarded from stores 464system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 465system.cpu.iew.lsq.thread0.squashedLoads 71163438 # Number of loads squashed 466system.cpu.iew.lsq.thread0.ignoredResponses 53029 # Number of memory responses ignored because the instruction is squashed 467system.cpu.iew.lsq.thread0.memOrderViolation 858947 # Number of memory ordering violations 468system.cpu.iew.lsq.thread0.squashedStores 25053609 # Number of stores squashed 469system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 470system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 471system.cpu.iew.lsq.thread0.rescheduledLoads 50433 # Number of loads that were rescheduled 472system.cpu.iew.lsq.thread0.cacheBlocked 53 # Number of times an access to memory failed due to the cache being blocked 473system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 474system.cpu.iew.iewSquashCycles 7338745 # Number of cycles IEW is squashing 475system.cpu.iew.iewBlockCycles 35257397 # Number of cycles IEW is blocking 476system.cpu.iew.iewUnblockCycles 584477 # Number of cycles IEW is unblocking 477system.cpu.iew.iewDispatchedInsts 486764235 # Number of instructions dispatched to IQ 478system.cpu.iew.iewDispSquashedInsts 1231542 # Number of squashed instructions skipped by dispatch 479system.cpu.iew.iewDispLoadInsts 127813025 # Number of dispatched load instructions 480system.cpu.iew.iewDispStoreInsts 45569326 # Number of dispatched store instructions 481system.cpu.iew.iewDispNonSpecInsts 23100 # Number of dispatched non-speculative instructions 482system.cpu.iew.iewIQFullEvents 542722 # Number of times the IQ has become full, causing a stall 483system.cpu.iew.iewLSQFullEvents 38323 # Number of times the LSQ has become full, causing a stall 484system.cpu.iew.memOrderViolationEvents 858947 # Number of memory order violations 485system.cpu.iew.predictedTakenIncorrect 1297189 # Number of branches that were predicted taken incorrectly 486system.cpu.iew.predictedNotTakenIncorrect 6715157 # Number of branches that were predicted not taken incorrectly 487system.cpu.iew.branchMispredicts 8012346 # Number of branch mispredicts detected at execute 488system.cpu.iew.iewExecutedInsts 324846022 # Number of executed instructions 489system.cpu.iew.iewExecLoadInsts 80370790 # Number of load instructions executed 490system.cpu.iew.iewExecSquashedInsts 11745177 # Number of squashed instructions skipped in execute 491system.cpu.iew.exec_swp 0 # number of swp insts executed 492system.cpu.iew.exec_nop 0 # number of nop insts executed 493system.cpu.iew.exec_refs 105939673 # number of memory reference insts executed 494system.cpu.iew.exec_branches 18800592 # Number of branches executed 495system.cpu.iew.exec_stores 25568883 # Number of stores executed 496system.cpu.iew.exec_rate 1.581200 # Inst execution rate 497system.cpu.iew.wb_sent 321037948 # cumulative count of insts sent to commit 498system.cpu.iew.wb_count 318066081 # cumulative count of insts written-back 499system.cpu.iew.wb_producers 255309822 # num instructions producing a value 500system.cpu.iew.wb_consumers 434053597 # num instructions consuming a value 501system.cpu.iew.wb_rate 1.548198 # insts written-back per cycle 502system.cpu.iew.wb_fanout 0.588199 # average fanout of values written-back 503system.cpu.commit.commitSquashedInsts 265431223 # The number of squashed insts skipped by commit 504system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards 505system.cpu.commit.branchMispredicts 6620631 # The number of times a branch was mispredicted 506system.cpu.commit.committed_per_cycle::samples 163283495 # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::mean 1.355700 # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::stdev 1.936592 # Number of insts commited each cycle 509system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::0 66681947 40.84% 40.84% # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::1 54877402 33.61% 74.45% # Number of insts commited each cycle 512system.cpu.commit.committed_per_cycle::2 13218916 8.10% 82.54% # Number of insts commited each cycle 513system.cpu.commit.committed_per_cycle::3 10716769 6.56% 89.11% # Number of insts commited each cycle 514system.cpu.commit.committed_per_cycle::4 5408933 3.31% 92.42% # Number of insts commited each cycle 515system.cpu.commit.committed_per_cycle::5 3143149 1.92% 94.34% # Number of insts commited each cycle 516system.cpu.commit.committed_per_cycle::6 1097453 0.67% 95.02% # Number of insts commited each cycle 517system.cpu.commit.committed_per_cycle::7 1149760 0.70% 95.72% # Number of insts commited each cycle 518system.cpu.commit.committed_per_cycle::8 6989166 4.28% 100.00% # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::total 163283495 # Number of insts commited each cycle 523system.cpu.commit.committedInsts 132071192 # Number of instructions committed 524system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed 525system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 526system.cpu.commit.refs 77165304 # Number of memory references committed 527system.cpu.commit.loads 56649587 # Number of loads committed 528system.cpu.commit.membars 0 # Number of memory barriers committed 529system.cpu.commit.branches 12326938 # Number of branches committed 530system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. 531system.cpu.commit.int_insts 219019985 # Number of committed integer instructions. 532system.cpu.commit.function_calls 797818 # Number of function calls committed. 533system.cpu.commit.op_class_0::No_OpClass 1176721 0.53% 0.53% # Class of committed instruction 534system.cpu.commit.op_class_0::IntAlu 134111832 60.58% 61.12% # Class of committed instruction 535system.cpu.commit.op_class_0::IntMult 772953 0.35% 61.47% # Class of committed instruction 536system.cpu.commit.op_class_0::IntDiv 7031501 3.18% 64.64% # Class of committed instruction 537system.cpu.commit.op_class_0::FloatAdd 1105073 0.50% 65.14% # Class of committed instruction 538system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.14% # Class of committed instruction 539system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.14% # Class of committed instruction 540system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.14% # Class of committed instruction 541system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 65.14% # Class of committed instruction 542system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.14% # Class of committed instruction 543system.cpu.commit.op_class_0::FloatMisc 0 0.00% 65.14% # Class of committed instruction 544system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.14% # Class of committed instruction 545system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.14% # Class of committed instruction 546system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.14% # Class of committed instruction 547system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.14% # Class of committed instruction 548system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.14% # Class of committed instruction 549system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.14% # Class of committed instruction 550system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.14% # Class of committed instruction 551system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.14% # Class of committed instruction 552system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.14% # Class of committed instruction 553system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.14% # Class of committed instruction 554system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.14% # Class of committed instruction 555system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.14% # Class of committed instruction 556system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.14% # Class of committed instruction 557system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.14% # Class of committed instruction 558system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.14% # Class of committed instruction 559system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.14% # Class of committed instruction 560system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.14% # Class of committed instruction 561system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.14% # Class of committed instruction 562system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction 563system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction 564system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction 565system.cpu.commit.op_class_0::MemRead 55945136 25.27% 90.41% # Class of committed instruction 566system.cpu.commit.op_class_0::MemWrite 20410230 9.22% 99.63% # Class of committed instruction 567system.cpu.commit.op_class_0::FloatMemRead 704451 0.32% 99.95% # Class of committed instruction 568system.cpu.commit.op_class_0::FloatMemWrite 105487 0.05% 100.00% # Class of committed instruction 569system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 570system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 571system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction 572system.cpu.commit.bw_lim_events 6989166 # number cycles where commit BW limit reached 573system.cpu.rob.rob_reads 643088936 # The number of ROB reads 574system.cpu.rob.rob_writes 1015902477 # The number of ROB writes 575system.cpu.timesIdled 2803 # Number of times that the entire CPU went into an idle state and unscheduled itself 576system.cpu.idleCycles 240641 # Total number of cycles that the CPU has spent unscheduled due to idling 577system.cpu.committedInsts 132071192 # Number of Instructions Simulated 578system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated 579system.cpu.cpi 1.555546 # CPI: Cycles Per Instruction 580system.cpu.cpi_total 1.555546 # CPI: Total CPI of All Threads 581system.cpu.ipc 0.642861 # IPC: Instructions Per Cycle 582system.cpu.ipc_total 0.642861 # IPC: Total IPC of All Threads 583system.cpu.int_regfile_reads 522853571 # number of integer regfile reads 584system.cpu.int_regfile_writes 287693953 # number of integer regfile writes 585system.cpu.fp_regfile_reads 4488277 # number of floating regfile reads 586system.cpu.fp_regfile_writes 3288210 # number of floating regfile writes 587system.cpu.cc_regfile_reads 106934935 # number of cc regfile reads 588system.cpu.cc_regfile_writes 65654592 # number of cc regfile writes 589system.cpu.misc_regfile_reads 175824659 # number of misc regfile reads 590system.cpu.misc_regfile_writes 1689 # number of misc regfile writes 591system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states 592system.cpu.dcache.tags.replacements 101 # number of replacements 593system.cpu.dcache.tags.tagsinuse 1519.152295 # Cycle average of tags in use 594system.cpu.dcache.tags.total_refs 82373071 # Total number of references to valid blocks. 595system.cpu.dcache.tags.sampled_refs 2121 # Sample count of references to valid blocks. 596system.cpu.dcache.tags.avg_refs 38836.902876 # Average number of references to valid blocks. 597system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 598system.cpu.dcache.tags.occ_blocks::cpu.data 1519.152295 # Average occupied blocks per requestor 599system.cpu.dcache.tags.occ_percent::cpu.data 0.370887 # Average percentage of cache occupancy 600system.cpu.dcache.tags.occ_percent::total 0.370887 # Average percentage of cache occupancy 601system.cpu.dcache.tags.occ_task_id_blocks::1024 2020 # Occupied blocks per task id 602system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id 603system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id 604system.cpu.dcache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id 605system.cpu.dcache.tags.age_task_id_blocks_1024::3 426 # Occupied blocks per task id 606system.cpu.dcache.tags.age_task_id_blocks_1024::4 1452 # Occupied blocks per task id 607system.cpu.dcache.tags.occ_task_id_percent::1024 0.493164 # Percentage of cache occupancy per task id 608system.cpu.dcache.tags.tag_accesses 164753603 # Number of tag accesses 609system.cpu.dcache.tags.data_accesses 164753603 # Number of data accesses 610system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states 611system.cpu.dcache.ReadReq_hits::cpu.data 61858750 # number of ReadReq hits 612system.cpu.dcache.ReadReq_hits::total 61858750 # number of ReadReq hits 613system.cpu.dcache.WriteReq_hits::cpu.data 20513717 # number of WriteReq hits 614system.cpu.dcache.WriteReq_hits::total 20513717 # number of WriteReq hits 615system.cpu.dcache.demand_hits::cpu.data 82372467 # number of demand (read+write) hits 616system.cpu.dcache.demand_hits::total 82372467 # number of demand (read+write) hits 617system.cpu.dcache.overall_hits::cpu.data 82372467 # number of overall hits 618system.cpu.dcache.overall_hits::total 82372467 # number of overall hits 619system.cpu.dcache.ReadReq_misses::cpu.data 1260 # number of ReadReq misses 620system.cpu.dcache.ReadReq_misses::total 1260 # number of ReadReq misses 621system.cpu.dcache.WriteReq_misses::cpu.data 2014 # number of WriteReq misses 622system.cpu.dcache.WriteReq_misses::total 2014 # number of WriteReq misses 623system.cpu.dcache.demand_misses::cpu.data 3274 # number of demand (read+write) misses 624system.cpu.dcache.demand_misses::total 3274 # number of demand (read+write) misses 625system.cpu.dcache.overall_misses::cpu.data 3274 # number of overall misses 626system.cpu.dcache.overall_misses::total 3274 # number of overall misses 627system.cpu.dcache.ReadReq_miss_latency::cpu.data 128800000 # number of ReadReq miss cycles 628system.cpu.dcache.ReadReq_miss_latency::total 128800000 # number of ReadReq miss cycles 629system.cpu.dcache.WriteReq_miss_latency::cpu.data 138047000 # number of WriteReq miss cycles 630system.cpu.dcache.WriteReq_miss_latency::total 138047000 # number of WriteReq miss cycles 631system.cpu.dcache.demand_miss_latency::cpu.data 266847000 # number of demand (read+write) miss cycles 632system.cpu.dcache.demand_miss_latency::total 266847000 # number of demand (read+write) miss cycles 633system.cpu.dcache.overall_miss_latency::cpu.data 266847000 # number of overall miss cycles 634system.cpu.dcache.overall_miss_latency::total 266847000 # number of overall miss cycles 635system.cpu.dcache.ReadReq_accesses::cpu.data 61860010 # number of ReadReq accesses(hits+misses) 636system.cpu.dcache.ReadReq_accesses::total 61860010 # number of ReadReq accesses(hits+misses) 637system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) 638system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) 639system.cpu.dcache.demand_accesses::cpu.data 82375741 # number of demand (read+write) accesses 640system.cpu.dcache.demand_accesses::total 82375741 # number of demand (read+write) accesses 641system.cpu.dcache.overall_accesses::cpu.data 82375741 # number of overall (read+write) accesses 642system.cpu.dcache.overall_accesses::total 82375741 # number of overall (read+write) accesses 643system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses 644system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses 645system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000098 # miss rate for WriteReq accesses 646system.cpu.dcache.WriteReq_miss_rate::total 0.000098 # miss rate for WriteReq accesses 647system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses 648system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses 649system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses 650system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses 651system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 102222.222222 # average ReadReq miss latency 652system.cpu.dcache.ReadReq_avg_miss_latency::total 102222.222222 # average ReadReq miss latency 653system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68543.694141 # average WriteReq miss latency 654system.cpu.dcache.WriteReq_avg_miss_latency::total 68543.694141 # average WriteReq miss latency 655system.cpu.dcache.demand_avg_miss_latency::cpu.data 81504.886988 # average overall miss latency 656system.cpu.dcache.demand_avg_miss_latency::total 81504.886988 # average overall miss latency 657system.cpu.dcache.overall_avg_miss_latency::cpu.data 81504.886988 # average overall miss latency 658system.cpu.dcache.overall_avg_miss_latency::total 81504.886988 # average overall miss latency 659system.cpu.dcache.blocked_cycles::no_mshrs 635 # number of cycles access was blocked 660system.cpu.dcache.blocked_cycles::no_targets 58 # number of cycles access was blocked 661system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked 662system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked 663system.cpu.dcache.avg_blocked_cycles::no_mshrs 127 # average number of cycles each access was blocked 664system.cpu.dcache.avg_blocked_cycles::no_targets 58 # average number of cycles each access was blocked 665system.cpu.dcache.writebacks::writebacks 22 # number of writebacks 666system.cpu.dcache.writebacks::total 22 # number of writebacks 667system.cpu.dcache.ReadReq_mshr_hits::cpu.data 652 # number of ReadReq MSHR hits 668system.cpu.dcache.ReadReq_mshr_hits::total 652 # number of ReadReq MSHR hits 669system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11 # number of WriteReq MSHR hits 670system.cpu.dcache.WriteReq_mshr_hits::total 11 # number of WriteReq MSHR hits 671system.cpu.dcache.demand_mshr_hits::cpu.data 663 # number of demand (read+write) MSHR hits 672system.cpu.dcache.demand_mshr_hits::total 663 # number of demand (read+write) MSHR hits 673system.cpu.dcache.overall_mshr_hits::cpu.data 663 # number of overall MSHR hits 674system.cpu.dcache.overall_mshr_hits::total 663 # number of overall MSHR hits 675system.cpu.dcache.ReadReq_mshr_misses::cpu.data 608 # number of ReadReq MSHR misses 676system.cpu.dcache.ReadReq_mshr_misses::total 608 # number of ReadReq MSHR misses 677system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2003 # number of WriteReq MSHR misses 678system.cpu.dcache.WriteReq_mshr_misses::total 2003 # number of WriteReq MSHR misses 679system.cpu.dcache.demand_mshr_misses::cpu.data 2611 # number of demand (read+write) MSHR misses 680system.cpu.dcache.demand_mshr_misses::total 2611 # number of demand (read+write) MSHR misses 681system.cpu.dcache.overall_mshr_misses::cpu.data 2611 # number of overall MSHR misses 682system.cpu.dcache.overall_mshr_misses::total 2611 # number of overall MSHR misses 683system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 79597500 # number of ReadReq MSHR miss cycles 684system.cpu.dcache.ReadReq_mshr_miss_latency::total 79597500 # number of ReadReq MSHR miss cycles 685system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 135457500 # number of WriteReq MSHR miss cycles 686system.cpu.dcache.WriteReq_mshr_miss_latency::total 135457500 # number of WriteReq MSHR miss cycles 687system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215055000 # number of demand (read+write) MSHR miss cycles 688system.cpu.dcache.demand_mshr_miss_latency::total 215055000 # number of demand (read+write) MSHR miss cycles 689system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215055000 # number of overall MSHR miss cycles 690system.cpu.dcache.overall_mshr_miss_latency::total 215055000 # number of overall MSHR miss cycles 691system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses 692system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses 693system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000098 # mshr miss rate for WriteReq accesses 694system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000098 # mshr miss rate for WriteReq accesses 695system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses 696system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses 697system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses 698system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses 699system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 130916.940789 # average ReadReq mshr miss latency 700system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 130916.940789 # average ReadReq mshr miss latency 701system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67627.309036 # average WriteReq mshr miss latency 702system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67627.309036 # average WriteReq mshr miss latency 703system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82364.994255 # average overall mshr miss latency 704system.cpu.dcache.demand_avg_mshr_miss_latency::total 82364.994255 # average overall mshr miss latency 705system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82364.994255 # average overall mshr miss latency 706system.cpu.dcache.overall_avg_mshr_miss_latency::total 82364.994255 # average overall mshr miss latency 707system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states 708system.cpu.icache.tags.replacements 6438 # number of replacements 709system.cpu.icache.tags.tagsinuse 1691.823634 # Cycle average of tags in use 710system.cpu.icache.tags.total_refs 40880551 # Total number of references to valid blocks. 711system.cpu.icache.tags.sampled_refs 8435 # Sample count of references to valid blocks. 712system.cpu.icache.tags.avg_refs 4846.538352 # Average number of references to valid blocks. 713system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 714system.cpu.icache.tags.occ_blocks::cpu.inst 1691.823634 # Average occupied blocks per requestor 715system.cpu.icache.tags.occ_percent::cpu.inst 0.826086 # Average percentage of cache occupancy 716system.cpu.icache.tags.occ_percent::total 0.826086 # Average percentage of cache occupancy 717system.cpu.icache.tags.occ_task_id_blocks::1024 1997 # Occupied blocks per task id 718system.cpu.icache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id 719system.cpu.icache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id 720system.cpu.icache.tags.age_task_id_blocks_1024::2 850 # Occupied blocks per task id 721system.cpu.icache.tags.age_task_id_blocks_1024::3 153 # Occupied blocks per task id 722system.cpu.icache.tags.age_task_id_blocks_1024::4 731 # Occupied blocks per task id 723system.cpu.icache.tags.occ_task_id_percent::1024 0.975098 # Percentage of cache occupancy per task id 724system.cpu.icache.tags.tag_accesses 81796128 # Number of tag accesses 725system.cpu.icache.tags.data_accesses 81796128 # Number of data accesses 726system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states 727system.cpu.icache.ReadReq_hits::cpu.inst 40880552 # number of ReadReq hits 728system.cpu.icache.ReadReq_hits::total 40880552 # number of ReadReq hits 729system.cpu.icache.demand_hits::cpu.inst 40880552 # number of demand (read+write) hits 730system.cpu.icache.demand_hits::total 40880552 # number of demand (read+write) hits 731system.cpu.icache.overall_hits::cpu.inst 40880552 # number of overall hits 732system.cpu.icache.overall_hits::total 40880552 # number of overall hits 733system.cpu.icache.ReadReq_misses::cpu.inst 13050 # number of ReadReq misses 734system.cpu.icache.ReadReq_misses::total 13050 # number of ReadReq misses 735system.cpu.icache.demand_misses::cpu.inst 13050 # number of demand (read+write) misses 736system.cpu.icache.demand_misses::total 13050 # number of demand (read+write) misses 737system.cpu.icache.overall_misses::cpu.inst 13050 # number of overall misses 738system.cpu.icache.overall_misses::total 13050 # number of overall misses 739system.cpu.icache.ReadReq_miss_latency::cpu.inst 646702000 # number of ReadReq miss cycles 740system.cpu.icache.ReadReq_miss_latency::total 646702000 # number of ReadReq miss cycles 741system.cpu.icache.demand_miss_latency::cpu.inst 646702000 # number of demand (read+write) miss cycles 742system.cpu.icache.demand_miss_latency::total 646702000 # number of demand (read+write) miss cycles 743system.cpu.icache.overall_miss_latency::cpu.inst 646702000 # number of overall miss cycles 744system.cpu.icache.overall_miss_latency::total 646702000 # number of overall miss cycles 745system.cpu.icache.ReadReq_accesses::cpu.inst 40893602 # number of ReadReq accesses(hits+misses) 746system.cpu.icache.ReadReq_accesses::total 40893602 # number of ReadReq accesses(hits+misses) 747system.cpu.icache.demand_accesses::cpu.inst 40893602 # number of demand (read+write) accesses 748system.cpu.icache.demand_accesses::total 40893602 # number of demand (read+write) accesses 749system.cpu.icache.overall_accesses::cpu.inst 40893602 # number of overall (read+write) accesses 750system.cpu.icache.overall_accesses::total 40893602 # number of overall (read+write) accesses 751system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000319 # miss rate for ReadReq accesses 752system.cpu.icache.ReadReq_miss_rate::total 0.000319 # miss rate for ReadReq accesses 753system.cpu.icache.demand_miss_rate::cpu.inst 0.000319 # miss rate for demand accesses 754system.cpu.icache.demand_miss_rate::total 0.000319 # miss rate for demand accesses 755system.cpu.icache.overall_miss_rate::cpu.inst 0.000319 # miss rate for overall accesses 756system.cpu.icache.overall_miss_rate::total 0.000319 # miss rate for overall accesses 757system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49555.708812 # average ReadReq miss latency 758system.cpu.icache.ReadReq_avg_miss_latency::total 49555.708812 # average ReadReq miss latency 759system.cpu.icache.demand_avg_miss_latency::cpu.inst 49555.708812 # average overall miss latency 760system.cpu.icache.demand_avg_miss_latency::total 49555.708812 # average overall miss latency 761system.cpu.icache.overall_avg_miss_latency::cpu.inst 49555.708812 # average overall miss latency 762system.cpu.icache.overall_avg_miss_latency::total 49555.708812 # average overall miss latency 763system.cpu.icache.blocked_cycles::no_mshrs 2923 # number of cycles access was blocked 764system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 765system.cpu.icache.blocked::no_mshrs 38 # number of cycles access was blocked 766system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 767system.cpu.icache.avg_blocked_cycles::no_mshrs 76.921053 # average number of cycles each access was blocked 768system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 769system.cpu.icache.writebacks::writebacks 6438 # number of writebacks 770system.cpu.icache.writebacks::total 6438 # number of writebacks 771system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4125 # number of ReadReq MSHR hits 772system.cpu.icache.ReadReq_mshr_hits::total 4125 # number of ReadReq MSHR hits 773system.cpu.icache.demand_mshr_hits::cpu.inst 4125 # number of demand (read+write) MSHR hits 774system.cpu.icache.demand_mshr_hits::total 4125 # number of demand (read+write) MSHR hits 775system.cpu.icache.overall_mshr_hits::cpu.inst 4125 # number of overall MSHR hits 776system.cpu.icache.overall_mshr_hits::total 4125 # number of overall MSHR hits 777system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8925 # number of ReadReq MSHR misses 778system.cpu.icache.ReadReq_mshr_misses::total 8925 # number of ReadReq MSHR misses 779system.cpu.icache.demand_mshr_misses::cpu.inst 8925 # number of demand (read+write) MSHR misses 780system.cpu.icache.demand_mshr_misses::total 8925 # number of demand (read+write) MSHR misses 781system.cpu.icache.overall_mshr_misses::cpu.inst 8925 # number of overall MSHR misses 782system.cpu.icache.overall_mshr_misses::total 8925 # number of overall MSHR misses 783system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 457055500 # number of ReadReq MSHR miss cycles 784system.cpu.icache.ReadReq_mshr_miss_latency::total 457055500 # number of ReadReq MSHR miss cycles 785system.cpu.icache.demand_mshr_miss_latency::cpu.inst 457055500 # number of demand (read+write) MSHR miss cycles 786system.cpu.icache.demand_mshr_miss_latency::total 457055500 # number of demand (read+write) MSHR miss cycles 787system.cpu.icache.overall_mshr_miss_latency::cpu.inst 457055500 # number of overall MSHR miss cycles 788system.cpu.icache.overall_mshr_miss_latency::total 457055500 # number of overall MSHR miss cycles 789system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for ReadReq accesses 790system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000218 # mshr miss rate for ReadReq accesses 791system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for demand accesses 792system.cpu.icache.demand_mshr_miss_rate::total 0.000218 # mshr miss rate for demand accesses 793system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for overall accesses 794system.cpu.icache.overall_mshr_miss_rate::total 0.000218 # mshr miss rate for overall accesses 795system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51210.700280 # average ReadReq mshr miss latency 796system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51210.700280 # average ReadReq mshr miss latency 797system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51210.700280 # average overall mshr miss latency 798system.cpu.icache.demand_avg_mshr_miss_latency::total 51210.700280 # average overall mshr miss latency 799system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51210.700280 # average overall mshr miss latency 800system.cpu.icache.overall_avg_mshr_miss_latency::total 51210.700280 # average overall mshr miss latency 801system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states 802system.cpu.l2cache.tags.replacements 0 # number of replacements 803system.cpu.l2cache.tags.tagsinuse 3920.889398 # Cycle average of tags in use 804system.cpu.l2cache.tags.total_refs 11824 # Total number of references to valid blocks. 805system.cpu.l2cache.tags.sampled_refs 5719 # Sample count of references to valid blocks. 806system.cpu.l2cache.tags.avg_refs 2.067494 # Average number of references to valid blocks. 807system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 808system.cpu.l2cache.tags.occ_blocks::cpu.inst 2430.261173 # Average occupied blocks per requestor 809system.cpu.l2cache.tags.occ_blocks::cpu.data 1490.628224 # Average occupied blocks per requestor 810system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074166 # Average percentage of cache occupancy 811system.cpu.l2cache.tags.occ_percent::cpu.data 0.045490 # Average percentage of cache occupancy 812system.cpu.l2cache.tags.occ_percent::total 0.119656 # Average percentage of cache occupancy 813system.cpu.l2cache.tags.occ_task_id_blocks::1024 5719 # Occupied blocks per task id 814system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 815system.cpu.l2cache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id 816system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1010 # Occupied blocks per task id 817system.cpu.l2cache.tags.age_task_id_blocks_1024::3 536 # Occupied blocks per task id 818system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3957 # Occupied blocks per task id 819system.cpu.l2cache.tags.occ_task_id_percent::1024 0.174530 # Percentage of cache occupancy per task id 820system.cpu.l2cache.tags.tag_accesses 146063 # Number of tag accesses 821system.cpu.l2cache.tags.data_accesses 146063 # Number of data accesses 822system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states 823system.cpu.l2cache.WritebackDirty_hits::writebacks 22 # number of WritebackDirty hits 824system.cpu.l2cache.WritebackDirty_hits::total 22 # number of WritebackDirty hits 825system.cpu.l2cache.WritebackClean_hits::writebacks 6400 # number of WritebackClean hits 826system.cpu.l2cache.WritebackClean_hits::total 6400 # number of WritebackClean hits 827system.cpu.l2cache.UpgradeReq_hits::cpu.data 490 # number of UpgradeReq hits 828system.cpu.l2cache.UpgradeReq_hits::total 490 # number of UpgradeReq hits 829system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits 830system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits 831system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4761 # number of ReadCleanReq hits 832system.cpu.l2cache.ReadCleanReq_hits::total 4761 # number of ReadCleanReq hits 833system.cpu.l2cache.ReadSharedReq_hits::cpu.data 67 # number of ReadSharedReq hits 834system.cpu.l2cache.ReadSharedReq_hits::total 67 # number of ReadSharedReq hits 835system.cpu.l2cache.demand_hits::cpu.inst 4761 # number of demand (read+write) hits 836system.cpu.l2cache.demand_hits::cpu.data 75 # number of demand (read+write) hits 837system.cpu.l2cache.demand_hits::total 4836 # number of demand (read+write) hits 838system.cpu.l2cache.overall_hits::cpu.inst 4761 # number of overall hits 839system.cpu.l2cache.overall_hits::cpu.data 75 # number of overall hits 840system.cpu.l2cache.overall_hits::total 4836 # number of overall hits 841system.cpu.l2cache.ReadExReq_misses::cpu.data 1507 # number of ReadExReq misses 842system.cpu.l2cache.ReadExReq_misses::total 1507 # number of ReadExReq misses 843system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3673 # number of ReadCleanReq misses 844system.cpu.l2cache.ReadCleanReq_misses::total 3673 # number of ReadCleanReq misses 845system.cpu.l2cache.ReadSharedReq_misses::cpu.data 539 # number of ReadSharedReq misses 846system.cpu.l2cache.ReadSharedReq_misses::total 539 # number of ReadSharedReq misses 847system.cpu.l2cache.demand_misses::cpu.inst 3673 # number of demand (read+write) misses 848system.cpu.l2cache.demand_misses::cpu.data 2046 # number of demand (read+write) misses 849system.cpu.l2cache.demand_misses::total 5719 # number of demand (read+write) misses 850system.cpu.l2cache.overall_misses::cpu.inst 3673 # number of overall misses 851system.cpu.l2cache.overall_misses::cpu.data 2046 # number of overall misses 852system.cpu.l2cache.overall_misses::total 5719 # number of overall misses 853system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 126886000 # number of ReadExReq miss cycles 854system.cpu.l2cache.ReadExReq_miss_latency::total 126886000 # number of ReadExReq miss cycles 855system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 392741000 # number of ReadCleanReq miss cycles 856system.cpu.l2cache.ReadCleanReq_miss_latency::total 392741000 # number of ReadCleanReq miss cycles 857system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 77762500 # number of ReadSharedReq miss cycles 858system.cpu.l2cache.ReadSharedReq_miss_latency::total 77762500 # number of ReadSharedReq miss cycles 859system.cpu.l2cache.demand_miss_latency::cpu.inst 392741000 # number of demand (read+write) miss cycles 860system.cpu.l2cache.demand_miss_latency::cpu.data 204648500 # number of demand (read+write) miss cycles 861system.cpu.l2cache.demand_miss_latency::total 597389500 # number of demand (read+write) miss cycles 862system.cpu.l2cache.overall_miss_latency::cpu.inst 392741000 # number of overall miss cycles 863system.cpu.l2cache.overall_miss_latency::cpu.data 204648500 # number of overall miss cycles 864system.cpu.l2cache.overall_miss_latency::total 597389500 # number of overall miss cycles 865system.cpu.l2cache.WritebackDirty_accesses::writebacks 22 # number of WritebackDirty accesses(hits+misses) 866system.cpu.l2cache.WritebackDirty_accesses::total 22 # number of WritebackDirty accesses(hits+misses) 867system.cpu.l2cache.WritebackClean_accesses::writebacks 6400 # number of WritebackClean accesses(hits+misses) 868system.cpu.l2cache.WritebackClean_accesses::total 6400 # number of WritebackClean accesses(hits+misses) 869system.cpu.l2cache.UpgradeReq_accesses::cpu.data 490 # number of UpgradeReq accesses(hits+misses) 870system.cpu.l2cache.UpgradeReq_accesses::total 490 # number of UpgradeReq accesses(hits+misses) 871system.cpu.l2cache.ReadExReq_accesses::cpu.data 1515 # number of ReadExReq accesses(hits+misses) 872system.cpu.l2cache.ReadExReq_accesses::total 1515 # number of ReadExReq accesses(hits+misses) 873system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8434 # number of ReadCleanReq accesses(hits+misses) 874system.cpu.l2cache.ReadCleanReq_accesses::total 8434 # number of ReadCleanReq accesses(hits+misses) 875system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 606 # number of ReadSharedReq accesses(hits+misses) 876system.cpu.l2cache.ReadSharedReq_accesses::total 606 # number of ReadSharedReq accesses(hits+misses) 877system.cpu.l2cache.demand_accesses::cpu.inst 8434 # number of demand (read+write) accesses 878system.cpu.l2cache.demand_accesses::cpu.data 2121 # number of demand (read+write) accesses 879system.cpu.l2cache.demand_accesses::total 10555 # number of demand (read+write) accesses 880system.cpu.l2cache.overall_accesses::cpu.inst 8434 # number of overall (read+write) accesses 881system.cpu.l2cache.overall_accesses::cpu.data 2121 # number of overall (read+write) accesses 882system.cpu.l2cache.overall_accesses::total 10555 # number of overall (read+write) accesses 883system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994719 # miss rate for ReadExReq accesses 884system.cpu.l2cache.ReadExReq_miss_rate::total 0.994719 # miss rate for ReadExReq accesses 885system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.435499 # miss rate for ReadCleanReq accesses 886system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.435499 # miss rate for ReadCleanReq accesses 887system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.889439 # miss rate for ReadSharedReq accesses 888system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.889439 # miss rate for ReadSharedReq accesses 889system.cpu.l2cache.demand_miss_rate::cpu.inst 0.435499 # miss rate for demand accesses 890system.cpu.l2cache.demand_miss_rate::cpu.data 0.964639 # miss rate for demand accesses 891system.cpu.l2cache.demand_miss_rate::total 0.541829 # miss rate for demand accesses 892system.cpu.l2cache.overall_miss_rate::cpu.inst 0.435499 # miss rate for overall accesses 893system.cpu.l2cache.overall_miss_rate::cpu.data 0.964639 # miss rate for overall accesses 894system.cpu.l2cache.overall_miss_rate::total 0.541829 # miss rate for overall accesses 895system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84197.743862 # average ReadExReq miss latency 896system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84197.743862 # average ReadExReq miss latency 897system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 106926.490607 # average ReadCleanReq miss latency 898system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 106926.490607 # average ReadCleanReq miss latency 899system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 144271.799629 # average ReadSharedReq miss latency 900system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 144271.799629 # average ReadSharedReq miss latency 901system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 106926.490607 # average overall miss latency 902system.cpu.l2cache.demand_avg_miss_latency::cpu.data 100023.704790 # average overall miss latency 903system.cpu.l2cache.demand_avg_miss_latency::total 104456.985487 # average overall miss latency 904system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 106926.490607 # average overall miss latency 905system.cpu.l2cache.overall_avg_miss_latency::cpu.data 100023.704790 # average overall miss latency 906system.cpu.l2cache.overall_avg_miss_latency::total 104456.985487 # average overall miss latency 907system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 908system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 909system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 910system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 911system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 912system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 913system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1507 # number of ReadExReq MSHR misses 914system.cpu.l2cache.ReadExReq_mshr_misses::total 1507 # number of ReadExReq MSHR misses 915system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3673 # number of ReadCleanReq MSHR misses 916system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3673 # number of ReadCleanReq MSHR misses 917system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 539 # number of ReadSharedReq MSHR misses 918system.cpu.l2cache.ReadSharedReq_mshr_misses::total 539 # number of ReadSharedReq MSHR misses 919system.cpu.l2cache.demand_mshr_misses::cpu.inst 3673 # number of demand (read+write) MSHR misses 920system.cpu.l2cache.demand_mshr_misses::cpu.data 2046 # number of demand (read+write) MSHR misses 921system.cpu.l2cache.demand_mshr_misses::total 5719 # number of demand (read+write) MSHR misses 922system.cpu.l2cache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses 923system.cpu.l2cache.overall_mshr_misses::cpu.data 2046 # number of overall MSHR misses 924system.cpu.l2cache.overall_mshr_misses::total 5719 # number of overall MSHR misses 925system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111816000 # number of ReadExReq MSHR miss cycles 926system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111816000 # number of ReadExReq MSHR miss cycles 927system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 356011000 # number of ReadCleanReq MSHR miss cycles 928system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 356011000 # number of ReadCleanReq MSHR miss cycles 929system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 72372500 # number of ReadSharedReq MSHR miss cycles 930system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 72372500 # number of ReadSharedReq MSHR miss cycles 931system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 356011000 # number of demand (read+write) MSHR miss cycles 932system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 184188500 # number of demand (read+write) MSHR miss cycles 933system.cpu.l2cache.demand_mshr_miss_latency::total 540199500 # number of demand (read+write) MSHR miss cycles 934system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 356011000 # number of overall MSHR miss cycles 935system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 184188500 # number of overall MSHR miss cycles 936system.cpu.l2cache.overall_mshr_miss_latency::total 540199500 # number of overall MSHR miss cycles 937system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994719 # mshr miss rate for ReadExReq accesses 938system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994719 # mshr miss rate for ReadExReq accesses 939system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.435499 # mshr miss rate for ReadCleanReq accesses 940system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.435499 # mshr miss rate for ReadCleanReq accesses 941system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.889439 # mshr miss rate for ReadSharedReq accesses 942system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.889439 # mshr miss rate for ReadSharedReq accesses 943system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.435499 # mshr miss rate for demand accesses 944system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964639 # mshr miss rate for demand accesses 945system.cpu.l2cache.demand_mshr_miss_rate::total 0.541829 # mshr miss rate for demand accesses 946system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.435499 # mshr miss rate for overall accesses 947system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964639 # mshr miss rate for overall accesses 948system.cpu.l2cache.overall_mshr_miss_rate::total 0.541829 # mshr miss rate for overall accesses 949system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74197.743862 # average ReadExReq mshr miss latency 950system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74197.743862 # average ReadExReq mshr miss latency 951system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 96926.490607 # average ReadCleanReq mshr miss latency 952system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 96926.490607 # average ReadCleanReq mshr miss latency 953system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 134271.799629 # average ReadSharedReq mshr miss latency 954system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 134271.799629 # average ReadSharedReq mshr miss latency 955system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 96926.490607 # average overall mshr miss latency 956system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 90023.704790 # average overall mshr miss latency 957system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94456.985487 # average overall mshr miss latency 958system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 96926.490607 # average overall mshr miss latency 959system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 90023.704790 # average overall mshr miss latency 960system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94456.985487 # average overall mshr miss latency 961system.cpu.toL2Bus.snoop_filter.tot_requests 18075 # Total number of requests made to the snoop filter. 962system.cpu.toL2Bus.snoop_filter.hit_single_requests 6619 # Number of requests hitting in the snoop filter with a single holder of the requested data. 963system.cpu.toL2Bus.snoop_filter.hit_multi_requests 979 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 964system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 965system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 966system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 967system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states 968system.cpu.toL2Bus.trans_dist::ReadResp 9530 # Transaction distribution 969system.cpu.toL2Bus.trans_dist::WritebackDirty 22 # Transaction distribution 970system.cpu.toL2Bus.trans_dist::WritebackClean 6438 # Transaction distribution 971system.cpu.toL2Bus.trans_dist::CleanEvict 79 # Transaction distribution 972system.cpu.toL2Bus.trans_dist::UpgradeReq 490 # Transaction distribution 973system.cpu.toL2Bus.trans_dist::UpgradeResp 490 # Transaction distribution 974system.cpu.toL2Bus.trans_dist::ReadExReq 1515 # Transaction distribution 975system.cpu.toL2Bus.trans_dist::ReadExResp 1515 # Transaction distribution 976system.cpu.toL2Bus.trans_dist::ReadCleanReq 8925 # Transaction distribution 977system.cpu.toL2Bus.trans_dist::ReadSharedReq 606 # Transaction distribution 978system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23796 # Packet count per connected master and slave (bytes) 979system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5323 # Packet count per connected master and slave (bytes) 980system.cpu.toL2Bus.pkt_count::total 29119 # Packet count per connected master and slave (bytes) 981system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 951744 # Cumulative packet size per connected master and slave (bytes) 982system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 137152 # Cumulative packet size per connected master and slave (bytes) 983system.cpu.toL2Bus.pkt_size::total 1088896 # Cumulative packet size per connected master and slave (bytes) 984system.cpu.toL2Bus.snoops 491 # Total snoops (count) 985system.cpu.toL2Bus.snoopTraffic 31424 # Total snoop traffic (bytes) 986system.cpu.toL2Bus.snoop_fanout::samples 11536 # Request fanout histogram 987system.cpu.toL2Bus.snoop_fanout::mean 0.091713 # Request fanout histogram 988system.cpu.toL2Bus.snoop_fanout::stdev 0.288633 # Request fanout histogram 989system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 990system.cpu.toL2Bus.snoop_fanout::0 10478 90.83% 90.83% # Request fanout histogram 991system.cpu.toL2Bus.snoop_fanout::1 1058 9.17% 100.00% # Request fanout histogram 992system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 993system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 994system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 995system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 996system.cpu.toL2Bus.snoop_fanout::total 11536 # Request fanout histogram 997system.cpu.toL2Bus.reqLayer0.occupancy 15497500 # Layer occupancy (ticks) 998system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 999system.cpu.toL2Bus.respLayer0.occupancy 13386000 # Layer occupancy (ticks) 1000system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1001system.cpu.toL2Bus.respLayer1.occupancy 3426999 # Layer occupancy (ticks) 1002system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1003system.membus.snoop_filter.tot_requests 5719 # Total number of requests made to the snoop filter. 1004system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1005system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1006system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1007system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1008system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1009system.membus.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states 1010system.membus.trans_dist::ReadResp 4212 # Transaction distribution 1011system.membus.trans_dist::ReadExReq 1507 # Transaction distribution 1012system.membus.trans_dist::ReadExResp 1507 # Transaction distribution 1013system.membus.trans_dist::ReadSharedReq 4212 # Transaction distribution 1014system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11438 # Packet count per connected master and slave (bytes) 1015system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11438 # Packet count per connected master and slave (bytes) 1016system.membus.pkt_count::total 11438 # Packet count per connected master and slave (bytes) 1017system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 366016 # Cumulative packet size per connected master and slave (bytes) 1018system.membus.pkt_size_system.cpu.l2cache.mem_side::total 366016 # Cumulative packet size per connected master and slave (bytes) 1019system.membus.pkt_size::total 366016 # Cumulative packet size per connected master and slave (bytes) 1020system.membus.snoops 0 # Total snoops (count) 1021system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 1022system.membus.snoop_fanout::samples 5719 # Request fanout histogram 1023system.membus.snoop_fanout::mean 0 # Request fanout histogram 1024system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1025system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1026system.membus.snoop_fanout::0 5719 100.00% 100.00% # Request fanout histogram 1027system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1028system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1029system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1030system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1031system.membus.snoop_fanout::total 5719 # Request fanout histogram 1032system.membus.reqLayer0.occupancy 6957500 # Layer occupancy (ticks) 1033system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1034system.membus.respLayer1.occupancy 30309750 # Layer occupancy (ticks) 1035system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
| 3sim_seconds 0.102720 4sim_ticks 102720088500 5final_tick 102720088500 6sim_freq 1000000000000 7host_inst_rate 110078 8host_op_rate 184500 9host_tick_rate 85614304 10host_mem_usage 318036 11host_seconds 1199.80 12sim_insts 132071192 13sim_ops 221363384 14system.voltage_domain.voltage 1 15system.clk_domain.clock 1000 16system.physmem.pwrStateResidencyTicks::UNDEFINED 102720088500 17system.physmem.bytes_read::cpu.inst 235072 18system.physmem.bytes_read::cpu.data 130880 19system.physmem.bytes_read::total 365952 20system.physmem.bytes_inst_read::cpu.inst 235072 21system.physmem.bytes_inst_read::total 235072 22system.physmem.num_reads::cpu.inst 3673 23system.physmem.num_reads::cpu.data 2045 24system.physmem.num_reads::total 5718 25system.physmem.bw_read::cpu.inst 2288472 26system.physmem.bw_read::cpu.data 1274142 27system.physmem.bw_read::total 3562614 28system.physmem.bw_inst_read::cpu.inst 2288472 29system.physmem.bw_inst_read::total 2288472 30system.physmem.bw_total::cpu.inst 2288472 31system.physmem.bw_total::cpu.data 1274142 32system.physmem.bw_total::total 3562614 33system.physmem.readReqs 5718 34system.physmem.writeReqs 0 35system.physmem.readBursts 5718 36system.physmem.writeBursts 0 37system.physmem.bytesReadDRAM 365952 38system.physmem.bytesReadWrQ 0 39system.physmem.bytesWritten 0 40system.physmem.bytesReadSys 365952 41system.physmem.bytesWrittenSys 0 42system.physmem.servicedByWrQ 0 43system.physmem.mergedWrBursts 0 44system.physmem.neitherReadNorWriteReqs 0 45system.physmem.perBankRdBursts::0 308 46system.physmem.perBankRdBursts::1 393 47system.physmem.perBankRdBursts::2 481 48system.physmem.perBankRdBursts::3 362 49system.physmem.perBankRdBursts::4 367 50system.physmem.perBankRdBursts::5 342 51system.physmem.perBankRdBursts::6 448 52system.physmem.perBankRdBursts::7 369 53system.physmem.perBankRdBursts::8 368 54system.physmem.perBankRdBursts::9 301 55system.physmem.perBankRdBursts::10 254 56system.physmem.perBankRdBursts::11 270 57system.physmem.perBankRdBursts::12 266 58system.physmem.perBankRdBursts::13 486 59system.physmem.perBankRdBursts::14 412 60system.physmem.perBankRdBursts::15 291 61system.physmem.perBankWrBursts::0 0 62system.physmem.perBankWrBursts::1 0 63system.physmem.perBankWrBursts::2 0 64system.physmem.perBankWrBursts::3 0 65system.physmem.perBankWrBursts::4 0 66system.physmem.perBankWrBursts::5 0 67system.physmem.perBankWrBursts::6 0 68system.physmem.perBankWrBursts::7 0 69system.physmem.perBankWrBursts::8 0 70system.physmem.perBankWrBursts::9 0 71system.physmem.perBankWrBursts::10 0 72system.physmem.perBankWrBursts::11 0 73system.physmem.perBankWrBursts::12 0 74system.physmem.perBankWrBursts::13 0 75system.physmem.perBankWrBursts::14 0 76system.physmem.perBankWrBursts::15 0 77system.physmem.numRdRetry 0 78system.physmem.numWrRetry 0 79system.physmem.totGap 102719826000 80system.physmem.readPktSize::0 0 81system.physmem.readPktSize::1 0 82system.physmem.readPktSize::2 0 83system.physmem.readPktSize::3 0 84system.physmem.readPktSize::4 0 85system.physmem.readPktSize::5 0 86system.physmem.readPktSize::6 5718 87system.physmem.writePktSize::0 0 88system.physmem.writePktSize::1 0 89system.physmem.writePktSize::2 0 90system.physmem.writePktSize::3 0 91system.physmem.writePktSize::4 0 92system.physmem.writePktSize::5 0 93system.physmem.writePktSize::6 0 94system.physmem.rdQLenPdf::0 4465 95system.physmem.rdQLenPdf::1 986 96system.physmem.rdQLenPdf::2 224 97system.physmem.rdQLenPdf::3 32 98system.physmem.rdQLenPdf::4 9 99system.physmem.rdQLenPdf::5 2 100system.physmem.rdQLenPdf::6 0 101system.physmem.rdQLenPdf::7 0 102system.physmem.rdQLenPdf::8 0 103system.physmem.rdQLenPdf::9 0 104system.physmem.rdQLenPdf::10 0 105system.physmem.rdQLenPdf::11 0 106system.physmem.rdQLenPdf::12 0 107system.physmem.rdQLenPdf::13 0 108system.physmem.rdQLenPdf::14 0 109system.physmem.rdQLenPdf::15 0 110system.physmem.rdQLenPdf::16 0 111system.physmem.rdQLenPdf::17 0 112system.physmem.rdQLenPdf::18 0 113system.physmem.rdQLenPdf::19 0 114system.physmem.rdQLenPdf::20 0 115system.physmem.rdQLenPdf::21 0 116system.physmem.rdQLenPdf::22 0 117system.physmem.rdQLenPdf::23 0 118system.physmem.rdQLenPdf::24 0 119system.physmem.rdQLenPdf::25 0 120system.physmem.rdQLenPdf::26 0 121system.physmem.rdQLenPdf::27 0 122system.physmem.rdQLenPdf::28 0 123system.physmem.rdQLenPdf::29 0 124system.physmem.rdQLenPdf::30 0 125system.physmem.rdQLenPdf::31 0 126system.physmem.wrQLenPdf::0 0 127system.physmem.wrQLenPdf::1 0 128system.physmem.wrQLenPdf::2 0 129system.physmem.wrQLenPdf::3 0 130system.physmem.wrQLenPdf::4 0 131system.physmem.wrQLenPdf::5 0 132system.physmem.wrQLenPdf::6 0 133system.physmem.wrQLenPdf::7 0 134system.physmem.wrQLenPdf::8 0 135system.physmem.wrQLenPdf::9 0 136system.physmem.wrQLenPdf::10 0 137system.physmem.wrQLenPdf::11 0 138system.physmem.wrQLenPdf::12 0 139system.physmem.wrQLenPdf::13 0 140system.physmem.wrQLenPdf::14 0 141system.physmem.wrQLenPdf::15 0 142system.physmem.wrQLenPdf::16 0 143system.physmem.wrQLenPdf::17 0 144system.physmem.wrQLenPdf::18 0 145system.physmem.wrQLenPdf::19 0 146system.physmem.wrQLenPdf::20 0 147system.physmem.wrQLenPdf::21 0 148system.physmem.wrQLenPdf::22 0 149system.physmem.wrQLenPdf::23 0 150system.physmem.wrQLenPdf::24 0 151system.physmem.wrQLenPdf::25 0 152system.physmem.wrQLenPdf::26 0 153system.physmem.wrQLenPdf::27 0 154system.physmem.wrQLenPdf::28 0 155system.physmem.wrQLenPdf::29 0 156system.physmem.wrQLenPdf::30 0 157system.physmem.wrQLenPdf::31 0 158system.physmem.wrQLenPdf::32 0 159system.physmem.wrQLenPdf::33 0 160system.physmem.wrQLenPdf::34 0 161system.physmem.wrQLenPdf::35 0 162system.physmem.wrQLenPdf::36 0 163system.physmem.wrQLenPdf::37 0 164system.physmem.wrQLenPdf::38 0 165system.physmem.wrQLenPdf::39 0 166system.physmem.wrQLenPdf::40 0 167system.physmem.wrQLenPdf::41 0 168system.physmem.wrQLenPdf::42 0 169system.physmem.wrQLenPdf::43 0 170system.physmem.wrQLenPdf::44 0 171system.physmem.wrQLenPdf::45 0 172system.physmem.wrQLenPdf::46 0 173system.physmem.wrQLenPdf::47 0 174system.physmem.wrQLenPdf::48 0 175system.physmem.wrQLenPdf::49 0 176system.physmem.wrQLenPdf::50 0 177system.physmem.wrQLenPdf::51 0 178system.physmem.wrQLenPdf::52 0 179system.physmem.wrQLenPdf::53 0 180system.physmem.wrQLenPdf::54 0 181system.physmem.wrQLenPdf::55 0 182system.physmem.wrQLenPdf::56 0 183system.physmem.wrQLenPdf::57 0 184system.physmem.wrQLenPdf::58 0 185system.physmem.wrQLenPdf::59 0 186system.physmem.wrQLenPdf::60 0 187system.physmem.wrQLenPdf::61 0 188system.physmem.wrQLenPdf::62 0 189system.physmem.wrQLenPdf::63 0 190system.physmem.bytesPerActivate::samples 1260 191system.physmem.bytesPerActivate::mean 288.914286 192system.physmem.bytesPerActivate::gmean 165.287070 193system.physmem.bytesPerActivate::stdev 321.712301 194system.physmem.bytesPerActivate::0-127 547 43.41% 43.41% 195system.physmem.bytesPerActivate::128-255 272 21.59% 65.00% 196system.physmem.bytesPerActivate::256-383 106 8.41% 73.41% 197system.physmem.bytesPerActivate::384-511 51 4.05% 77.46% 198system.physmem.bytesPerActivate::512-639 47 3.73% 81.19% 199system.physmem.bytesPerActivate::640-767 65 5.16% 86.35% 200system.physmem.bytesPerActivate::768-895 23 1.83% 88.17% 201system.physmem.bytesPerActivate::896-1023 25 1.98% 90.16% 202system.physmem.bytesPerActivate::1024-1151 124 9.84% 100.00% 203system.physmem.bytesPerActivate::total 1260 204system.physmem.totQLat 196407250 205system.physmem.totMemAccLat 303619750 206system.physmem.totBusLat 28590000 207system.physmem.avgQLat 34348.94 208system.physmem.avgBusLat 5000.00 209system.physmem.avgMemAccLat 53098.94 210system.physmem.avgRdBW 3.56 211system.physmem.avgWrBW 0.00 212system.physmem.avgRdBWSys 3.56 213system.physmem.avgWrBWSys 0.00 214system.physmem.peakBW 12800.00 215system.physmem.busUtil 0.03 216system.physmem.busUtilRead 0.03 217system.physmem.busUtilWrite 0.00 218system.physmem.avgRdQLen 1.05 219system.physmem.avgWrQLen 0.00 220system.physmem.readRowHits 4449 221system.physmem.writeRowHits 0 222system.physmem.readRowHitRate 77.81 223system.physmem.writeRowHitRate nan 224system.physmem.avgGap 17964292.76 225system.physmem.pageHitRate 77.81 226system.physmem_0.actEnergy 5397840 227system.physmem_0.preEnergy 2846250 228system.physmem_0.readEnergy 21919800 229system.physmem_0.writeEnergy 0 230system.physmem_0.refreshEnergy 308549280.000000 231system.physmem_0.actBackEnergy 94558440 232system.physmem_0.preBackEnergy 17132160 233system.physmem_0.actPowerDownEnergy 742713990 234system.physmem_0.prePowerDownEnergy 449076000 235system.physmem_0.selfRefreshEnergy 23986517265 236system.physmem_0.totalEnergy 25628757345 237system.physmem_0.averagePower 249.500927 238system.physmem_0.totalIdleTime 102467665750 239system.physmem_0.memoryStateTime::IDLE 33083500 240system.physmem_0.memoryStateTime::REF 131252000 241system.physmem_0.memoryStateTime::SREF 99669779750 242system.physmem_0.memoryStateTime::PRE_PDN 1169466500 243system.physmem_0.memoryStateTime::ACT 87760750 244system.physmem_0.memoryStateTime::ACT_PDN 1628746000 245system.physmem_1.actEnergy 3662820 246system.physmem_1.preEnergy 1935450 247system.physmem_1.readEnergy 18906720 248system.physmem_1.writeEnergy 0 249system.physmem_1.refreshEnergy 232333920.000000 250system.physmem_1.actBackEnergy 74817060 251system.physmem_1.preBackEnergy 12559200 252system.physmem_1.actPowerDownEnergy 593057070 253system.physmem_1.prePowerDownEnergy 320340000 254system.physmem_1.selfRefreshEnergy 24140187000 255system.physmem_1.totalEnergy 25397799240 256system.physmem_1.averagePower 247.252505 257system.physmem_1.totalIdleTime 102523033750 258system.physmem_1.memoryStateTime::IDLE 23868000 259system.physmem_1.memoryStateTime::REF 98790000 260system.physmem_1.memoryStateTime::SREF 100388528750 261system.physmem_1.memoryStateTime::PRE_PDN 834205000 262system.physmem_1.memoryStateTime::ACT 74170500 263system.physmem_1.memoryStateTime::ACT_PDN 1300526250 264system.pwrStateResidencyTicks::UNDEFINED 102720088500 265system.cpu.branchPred.lookups 40475084 266system.cpu.branchPred.condPredicted 40475084 267system.cpu.branchPred.condIncorrect 6616129 268system.cpu.branchPred.BTBLookups 34806523 269system.cpu.branchPred.BTBHits 0 270system.cpu.branchPred.BTBCorrect 0 271system.cpu.branchPred.BTBHitPct 0.000000 272system.cpu.branchPred.usedRAS 3130762 273system.cpu.branchPred.RASInCorrect 590891 274system.cpu.branchPred.indirectLookups 34806523 275system.cpu.branchPred.indirectHits 9997741 276system.cpu.branchPred.indirectMisses 24808782 277system.cpu.branchPredindirectMispredicted 4890378 278system.cpu_clk_domain.clock 500 279system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 102720088500 280system.cpu.apic_clk_domain.clock 8000 281system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 102720088500 282system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 102720088500 283system.cpu.workload.numSyscalls 400 284system.cpu.pwrStateResidencyTicks::ON 102720088500 285system.cpu.numCycles 205440178 286system.cpu.numWorkItemsStarted 0 287system.cpu.numWorkItemsCompleted 0 288system.cpu.fetch.icacheStallCycles 45893457 289system.cpu.fetch.Insts 415890076 290system.cpu.fetch.Branches 40475084 291system.cpu.fetch.predictedBranches 13128503 292system.cpu.fetch.Cycles 151898082 293system.cpu.fetch.SquashCycles 14677483 294system.cpu.fetch.TlbCycles 200 295system.cpu.fetch.MiscStallCycles 5835 296system.cpu.fetch.PendingTrapStallCycles 64355 297system.cpu.fetch.PendingQuiesceStallCycles 603 298system.cpu.fetch.IcacheWaitRetryStallCycles 216 299system.cpu.fetch.CacheLines 40893606 300system.cpu.fetch.IcacheSquashes 1496125 301system.cpu.fetch.ItlbSquashes 12 302system.cpu.fetch.rateDist::samples 205201489 303system.cpu.fetch.rateDist::mean 3.402316 304system.cpu.fetch.rateDist::stdev 3.658034 305system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% 306system.cpu.fetch.rateDist::0 98918093 48.21% 48.21% 307system.cpu.fetch.rateDist::1 5142251 2.51% 50.71% 308system.cpu.fetch.rateDist::2 5340115 2.60% 53.31% 309system.cpu.fetch.rateDist::3 5342270 2.60% 55.92% 310system.cpu.fetch.rateDist::4 5947887 2.90% 58.82% 311system.cpu.fetch.rateDist::5 5817548 2.84% 61.65% 312system.cpu.fetch.rateDist::6 5684311 2.77% 64.42% 313system.cpu.fetch.rateDist::7 4746260 2.31% 66.73% 314system.cpu.fetch.rateDist::8 68262754 33.27% 100.00% 315system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% 316system.cpu.fetch.rateDist::min_value 0 317system.cpu.fetch.rateDist::max_value 8 318system.cpu.fetch.rateDist::total 205201489 319system.cpu.fetch.branchRate 0.197016 320system.cpu.fetch.rate 2.024385 321system.cpu.decode.IdleCycles 31935868 322system.cpu.decode.BlockedCycles 86571071 323system.cpu.decode.RunCycles 61623221 324system.cpu.decode.UnblockCycles 17732588 325system.cpu.decode.SquashCycles 7338741 326system.cpu.decode.DecodedInsts 585423984 327system.cpu.rename.SquashCycles 7338741 328system.cpu.rename.IdleCycles 41662198 329system.cpu.rename.BlockCycles 46227032 330system.cpu.rename.serializeStallCycles 28975 331system.cpu.rename.RunCycles 68218755 332system.cpu.rename.UnblockCycles 41725788 333system.cpu.rename.RenamedInsts 547333443 334system.cpu.rename.ROBFullEvents 1805 335system.cpu.rename.IQFullEvents 36710058 336system.cpu.rename.LQFullEvents 4936211 337system.cpu.rename.SQFullEvents 172839 338system.cpu.rename.RenamedOperands 624155655 339system.cpu.rename.RenameLookups 1473918429 340system.cpu.rename.int_rename_lookups 966803164 341system.cpu.rename.fp_rename_lookups 14714209 342system.cpu.rename.CommittedMaps 259429450 343system.cpu.rename.UndoneMaps 364726205 344system.cpu.rename.serializingInsts 2257 345system.cpu.rename.tempSerializingInsts 2274 346system.cpu.rename.skidInsts 89803547 347system.cpu.memDep0.insertedLoads 127813041 348system.cpu.memDep0.insertedStores 45569331 349system.cpu.memDep0.conflictingLoads 76700066 350system.cpu.memDep0.conflictingStores 25076087 351system.cpu.iq.iqInstsAdded 486700641 352system.cpu.iq.iqNonSpecInstsAdded 63617 353system.cpu.iq.iqInstsIssued 336591190 354system.cpu.iq.iqSquashedInstsIssued 1075815 355system.cpu.iq.iqSquashedInstsExamined 265400874 356system.cpu.iq.iqSquashedOperandsExamined 520101528 357system.cpu.iq.iqSquashedNonSpecRemoved 62372 358system.cpu.iq.issued_per_cycle::samples 205201489 359system.cpu.iq.issued_per_cycle::mean 1.640296 360system.cpu.iq.issued_per_cycle::stdev 1.801230 361system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% 362system.cpu.iq.issued_per_cycle::0 72558251 35.36% 35.36% 363system.cpu.iq.issued_per_cycle::1 46563358 22.69% 58.05% 364system.cpu.iq.issued_per_cycle::2 32833586 16.00% 74.05% 365system.cpu.iq.issued_per_cycle::3 20829408 10.15% 84.20% 366system.cpu.iq.issued_per_cycle::4 14957393 7.29% 91.49% 367system.cpu.iq.issued_per_cycle::5 8327082 4.06% 95.55% 368system.cpu.iq.issued_per_cycle::6 5158084 2.51% 98.06% 369system.cpu.iq.issued_per_cycle::7 2335666 1.14% 99.20% 370system.cpu.iq.issued_per_cycle::8 1638661 0.80% 100.00% 371system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% 372system.cpu.iq.issued_per_cycle::min_value 0 373system.cpu.iq.issued_per_cycle::max_value 8 374system.cpu.iq.issued_per_cycle::total 205201489 375system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% 376system.cpu.iq.fu_full::IntAlu 746083 18.99% 18.99% 377system.cpu.iq.fu_full::IntMult 0 0.00% 18.99% 378system.cpu.iq.fu_full::IntDiv 0 0.00% 18.99% 379system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.99% 380system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.99% 381system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.99% 382system.cpu.iq.fu_full::FloatMult 0 0.00% 18.99% 383system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 18.99% 384system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.99% 385system.cpu.iq.fu_full::FloatMisc 0 0.00% 18.99% 386system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.99% 387system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.99% 388system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.99% 389system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.99% 390system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.99% 391system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.99% 392system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.99% 393system.cpu.iq.fu_full::SimdMult 0 0.00% 18.99% 394system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.99% 395system.cpu.iq.fu_full::SimdShift 0 0.00% 18.99% 396system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.99% 397system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.99% 398system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.99% 399system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.99% 400system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.99% 401system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.99% 402system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.99% 403system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.99% 404system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.99% 405system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.99% 406system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.99% 407system.cpu.iq.fu_full::MemRead 2709271 68.98% 87.97% 408system.cpu.iq.fu_full::MemWrite 425877 10.84% 98.81% 409system.cpu.iq.fu_full::FloatMemRead 43262 1.10% 99.91% 410system.cpu.iq.fu_full::FloatMemWrite 3383 0.09% 100.00% 411system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% 412system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% 413system.cpu.iq.FU_type_0::No_OpClass 1212158 0.36% 0.36% 414system.cpu.iq.FU_type_0::IntAlu 215249595 63.95% 64.31% 415system.cpu.iq.FU_type_0::IntMult 800532 0.24% 64.55% 416system.cpu.iq.FU_type_0::IntDiv 7048368 2.09% 66.64% 417system.cpu.iq.FU_type_0::FloatAdd 1789279 0.53% 67.17% 418system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.17% 419system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.17% 420system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.17% 421system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.17% 422system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.17% 423system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.17% 424system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.17% 425system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.17% 426system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.17% 427system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.17% 428system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.17% 429system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.17% 430system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.17% 431system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.17% 432system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.17% 433system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.17% 434system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.17% 435system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.17% 436system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.17% 437system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.17% 438system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.17% 439system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.17% 440system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.17% 441system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.17% 442system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.17% 443system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.17% 444system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.17% 445system.cpu.iq.FU_type_0::MemRead 82235884 24.43% 91.61% 446system.cpu.iq.FU_type_0::MemWrite 26412299 7.85% 99.45% 447system.cpu.iq.FU_type_0::FloatMemRead 1712250 0.51% 99.96% 448system.cpu.iq.FU_type_0::FloatMemWrite 130825 0.04% 100.00% 449system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% 450system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% 451system.cpu.iq.FU_type_0::total 336591190 452system.cpu.iq.rate 1.638390 453system.cpu.iq.fu_busy_cnt 3927876 454system.cpu.iq.fu_busy_rate 0.011670 455system.cpu.iq.int_inst_queue_reads 875282503 456system.cpu.iq.int_inst_queue_writes 737961959 457system.cpu.iq.int_inst_queue_wakeup_accesses 314539840 458system.cpu.iq.fp_inst_queue_reads 8105057 459system.cpu.iq.fp_inst_queue_writes 15024545 460system.cpu.iq.fp_inst_queue_wakeup_accesses 3526208 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