Cross Reference: /gem5/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt

Deleted Added

sdiff udiff text old ( 10726:8a20e2a1562d ) new ( 10736:4433fb00fa7d )

full compact

stats.txt (10726:8a20e2a1562d)	stats.txt (10736:4433fb00fa7d)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.148669 # Number of seconds simulated 4sim_ticks 148668850500 # Number of ticks simulated 5final_tick 148668850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 82634 # Simulator instruction rate (inst/s) 8host_op_rate 138502 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 93018548 # Simulator tick rate (ticks/s) 10host_mem_usage 346916 # Number of bytes of host memory used 11host_seconds 1598.27 # Real time elapsed on the host 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221363384 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 225344 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 125504 # Number of bytes read from this memory 18system.physmem.bytes_read::total 350848 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 225344 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 225344 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 3521 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1961 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 5482 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1515745 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 844185 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 2359929 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1515745 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1515745 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1515745 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 844185 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 2359929 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 5482 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 5482 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 350848 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 350848 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 345 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 294 # Per bank write bursts 45system.physmem.perBankRdBursts::1 364 # Per bank write bursts 46system.physmem.perBankRdBursts::2 457 # Per bank write bursts 47system.physmem.perBankRdBursts::3 371 # Per bank write bursts 48system.physmem.perBankRdBursts::4 339 # Per bank write bursts 49system.physmem.perBankRdBursts::5 333 # Per bank write bursts 50system.physmem.perBankRdBursts::6 398 # Per bank write bursts 51system.physmem.perBankRdBursts::7 383 # Per bank write bursts 52system.physmem.perBankRdBursts::8 344 # Per bank write bursts 53system.physmem.perBankRdBursts::9 280 # Per bank write bursts 54system.physmem.perBankRdBursts::10 239 # Per bank write bursts 55system.physmem.perBankRdBursts::11 268 # Per bank write bursts 56system.physmem.perBankRdBursts::12 225 # Per bank write bursts 57system.physmem.perBankRdBursts::13 502 # Per bank write bursts 58system.physmem.perBankRdBursts::14 395 # Per bank write bursts 59system.physmem.perBankRdBursts::15 290 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 148668756000 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 5482 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 4368 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 913 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 173 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 24 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 1140 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 306.470175 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 178.641766 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 326.557853 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 448 39.30% 39.30% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 255 22.37% 61.67% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 105 9.21% 70.88% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 70 6.14% 77.02% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 38 3.33% 80.35% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 59 5.18% 85.53% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 19 1.67% 87.19% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 18 1.58% 88.77% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 128 11.23% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 1140 # Bytes accessed per row activation 203system.physmem.totQLat 40930250 # Total ticks spent queuing 204system.physmem.totMemAccLat 143717750 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 27410000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 7466.30 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 26216.30 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 2.36 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 2.36 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.02 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 4334 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 79.06 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 27119437.43 # Average gap between requests 224system.physmem.pageHitRate 79.06 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 5027400 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 2743125 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 22776000 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 9709936080 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 4021675470 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 85670093250 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 99432251325 # Total energy per rank (pJ) 233system.physmem_0.averagePower 668.842708 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 142518159000 # Time in different power states 235system.physmem_0.memoryStateTime::REF 4964180000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 237system.physmem_0.memoryStateTime::ACT 1181750000 # Time in different power states 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.physmem_1.actEnergy 3568320 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 1947000 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 19648200 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 9709936080 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 3821631120 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 85845562500 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 99402293220 # Total energy per rank (pJ) 247system.physmem_1.averagePower 668.641253 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 142814554750 # Time in different power states 249system.physmem_1.memoryStateTime::REF 4964180000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 888260750 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.cpu.branchPred.lookups 22385702 # Number of BP lookups 254system.cpu.branchPred.condPredicted 22385702 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 1554139 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 14132286 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 13246709 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 93.733661 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 1526841 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 22095 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 264system.cpu.workload.num_syscalls 400 # Number of system calls 265system.cpu.numCycles 297337717 # number of cpu cycles simulated 266system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 267system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 268system.cpu.fetch.icacheStallCycles 27888104 # Number of cycles fetch is stalled on an Icache miss 269system.cpu.fetch.Insts 249064218 # Number of instructions fetch has processed 270system.cpu.fetch.Branches 22385702 # Number of branches that fetch encountered 271system.cpu.fetch.predictedBranches 14773550 # Number of branches that fetch has predicted taken 272system.cpu.fetch.Cycles 267343346 # Number of cycles fetch has run and was not squashing or blocked 273system.cpu.fetch.SquashCycles 3703385 # Number of cycles fetch has spent squashing 274system.cpu.fetch.TlbCycles 34 # Number of cycles fetch has spent waiting for tlb 275system.cpu.fetch.MiscStallCycles 5713 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 276system.cpu.fetch.PendingTrapStallCycles 48972 # Number of stall cycles due to pending traps 277system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions 278system.cpu.fetch.IcacheWaitRetryStallCycles 83 # Number of stall cycles due to full MSHR 279system.cpu.fetch.CacheLines 26656558 # Number of cache lines fetched 280system.cpu.fetch.IcacheSquashes 259176 # Number of outstanding Icache misses that were squashed 281system.cpu.fetch.rateDist::samples 297137957 # Number of instructions fetched each cycle (Total) 282system.cpu.fetch.rateDist::mean 1.382061 # Number of instructions fetched each cycle (Total) 283system.cpu.fetch.rateDist::stdev 2.790607 # Number of instructions fetched each cycle (Total) 284system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 285system.cpu.fetch.rateDist::0 229077480 77.09% 77.09% # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::1 5080600 1.71% 78.80% # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::2 4128062 1.39% 80.19% # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::3 4791015 1.61% 81.81% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::4 4884919 1.64% 83.45% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::5 5103681 1.72% 85.17% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::6 5337561 1.80% 86.96% # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::7 4007445 1.35% 88.31% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::8 34727194 11.69% 100.00% # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::total 297137957 # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.branchRate 0.075287 # Number of branch fetches per cycle 299system.cpu.fetch.rate 0.837648 # Number of inst fetches per cycle 300system.cpu.decode.IdleCycles 16350382 # Number of cycles decode is idle 301system.cpu.decode.BlockedCycles 230944995 # Number of cycles decode is blocked 302system.cpu.decode.RunCycles 26142980 # Number of cycles decode is running 303system.cpu.decode.UnblockCycles 21847908 # Number of cycles decode is unblocking 304system.cpu.decode.SquashCycles 1851692 # Number of cycles decode is squashing 305system.cpu.decode.DecodedInsts 359376016 # Number of instructions handled by decode 306system.cpu.rename.SquashCycles 1851692 # Number of cycles rename is squashing 307system.cpu.rename.IdleCycles 24144395 # Number of cycles rename is idle 308system.cpu.rename.BlockCycles 162574126 # Number of cycles rename is blocking 309system.cpu.rename.serializeStallCycles 34810 # count of cycles rename stalled for serializing inst 310system.cpu.rename.RunCycles 38280834 # Number of cycles rename is running 311system.cpu.rename.UnblockCycles 70252100 # Number of cycles rename is unblocking 312system.cpu.rename.RenamedInsts 350628030 # Number of instructions processed by rename 313system.cpu.rename.ROBFullEvents 42505 # Number of times rename has blocked due to ROB full 314system.cpu.rename.IQFullEvents 62013521 # Number of times rename has blocked due to IQ full 315system.cpu.rename.LQFullEvents 7956456 # Number of times rename has blocked due to LQ full 316system.cpu.rename.SQFullEvents 170486 # Number of times rename has blocked due to SQ full 317system.cpu.rename.RenamedOperands 405834886 # Number of destination operands rename has renamed 318system.cpu.rename.RenameLookups 972854229 # Number of register rename lookups that rename has made 319system.cpu.rename.int_rename_lookups 642281329 # Number of integer rename lookups 320system.cpu.rename.fp_rename_lookups 4678301 # Number of floating rename lookups 321system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed 322system.cpu.rename.UndoneMaps 146405436 # Number of HB maps that are undone due to squashing 323system.cpu.rename.serializingInsts 2386 # count of serializing insts renamed 324system.cpu.rename.tempSerializingInsts 2313 # count of temporary serializing insts renamed 325system.cpu.rename.skidInsts 128573116 # count of insts added to the skid buffer 326system.cpu.memDep0.insertedLoads 89639956 # Number of loads inserted to the mem dependence unit. 327system.cpu.memDep0.insertedStores 32032649 # Number of stores inserted to the mem dependence unit. 328system.cpu.memDep0.conflictingLoads 63973866 # Number of conflicting loads. 329system.cpu.memDep0.conflictingStores 21576036 # Number of conflicting stores. 330system.cpu.iq.iqInstsAdded 341334735 # Number of instructions added to the IQ (excludes non-spec) 331system.cpu.iq.iqNonSpecInstsAdded 4899 # Number of non-speculative instructions added to the IQ 332system.cpu.iq.iqInstsIssued 266857181 # Number of instructions issued 333system.cpu.iq.iqSquashedInstsIssued 74594 # Number of squashed instructions issued 334system.cpu.iq.iqSquashedInstsExamined 119571219 # Number of squashed instructions iterated over during squash; mainly for profiling 335system.cpu.iq.iqSquashedOperandsExamined 250511173 # Number of squashed operands that are examined and possibly removed from graph 336system.cpu.iq.iqSquashedNonSpecRemoved 3654 # Number of squashed non-spec instructions that were removed 337system.cpu.iq.issued_per_cycle::samples 297137957 # Number of insts issued each cycle 338system.cpu.iq.issued_per_cycle::mean 0.898092 # Number of insts issued each cycle 339system.cpu.iq.issued_per_cycle::stdev 1.364162 # Number of insts issued each cycle 340system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 341system.cpu.iq.issued_per_cycle::0 171399069 57.68% 57.68% # Number of insts issued each cycle 342system.cpu.iq.issued_per_cycle::1 54278133 18.27% 75.95% # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::2 33575860 11.30% 87.25% # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::3 19165859 6.45% 93.70% # Number of insts issued each cycle 345system.cpu.iq.issued_per_cycle::4 10861721 3.66% 97.36% # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::5 4344660 1.46% 98.82% # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::6 2227090 0.75% 99.57% # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::7 887493 0.30% 99.87% # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::8 398072 0.13% 100.00% # Number of insts issued each cycle 350system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 351system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 352system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 353system.cpu.iq.issued_per_cycle::total 297137957 # Number of insts issued each cycle 354system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 355system.cpu.iq.fu_full::IntAlu 235011 7.30% 7.30% # attempts to use FU when none available 356system.cpu.iq.fu_full::IntMult 0 0.00% 7.30% # attempts to use FU when none available 357system.cpu.iq.fu_full::IntDiv 0 0.00% 7.30% # attempts to use FU when none available 358system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.30% # attempts to use FU when none available 359system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.30% # attempts to use FU when none available 360system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.30% # attempts to use FU when none available 361system.cpu.iq.fu_full::FloatMult 0 0.00% 7.30% # attempts to use FU when none available 362system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.30% # attempts to use FU when none available 363system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.30% # attempts to use FU when none available 364system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.30% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.30% # attempts to use FU when none available 366system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.30% # attempts to use FU when none available 367system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.30% # attempts to use FU when none available 368system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.30% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.30% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdMult 0 0.00% 7.30% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.30% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdShift 0 0.00% 7.30% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.30% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.30% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.30% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.30% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.30% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.30% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.30% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.30% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.30% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.30% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.30% # attempts to use FU when none available 384system.cpu.iq.fu_full::MemRead 2578157 80.11% 87.41% # attempts to use FU when none available 385system.cpu.iq.fu_full::MemWrite 405217 12.59% 100.00% # attempts to use FU when none available 386system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 387system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 388system.cpu.iq.FU_type_0::No_OpClass 1211344 0.45% 0.45% # Type of FU issued 389system.cpu.iq.FU_type_0::IntAlu 167292419 62.69% 63.14% # Type of FU issued 390system.cpu.iq.FU_type_0::IntMult 790150 0.30% 63.44% # Type of FU issued 391system.cpu.iq.FU_type_0::IntDiv 7035672 2.64% 66.08% # Type of FU issued 392system.cpu.iq.FU_type_0::FloatAdd 1215098 0.46% 66.53% # Type of FU issued 393system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.53% # Type of FU issued 394system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.53% # Type of FU issued 395system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.53% # Type of FU issued 396system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.53% # Type of FU issued 397system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.53% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.53% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.53% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.53% # Type of FU issued 401system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.53% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.53% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.53% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.53% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.53% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.53% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.53% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.53% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.53% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.53% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.53% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.53% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.53% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.53% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.53% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.53% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.53% # Type of FU issued 418system.cpu.iq.FU_type_0::MemRead 66512451 24.92% 91.46% # Type of FU issued 419system.cpu.iq.FU_type_0::MemWrite 22800047 8.54% 100.00% # Type of FU issued 420system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 421system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 422system.cpu.iq.FU_type_0::total 266857181 # Type of FU issued 423system.cpu.iq.rate 0.897488 # Inst issue rate 424system.cpu.iq.fu_busy_cnt 3218385 # FU busy when requested 425system.cpu.iq.fu_busy_rate 0.012060 # FU busy rate (busy events/executed inst) 426system.cpu.iq.int_inst_queue_reads 829150425 # Number of integer instruction queue reads 427system.cpu.iq.int_inst_queue_writes 456900250 # Number of integer instruction queue writes 428system.cpu.iq.int_inst_queue_wakeup_accesses 260922611 # Number of integer instruction queue wakeup accesses 429system.cpu.iq.fp_inst_queue_reads 4994873 # Number of floating instruction queue reads 430system.cpu.iq.fp_inst_queue_writes 4333463 # Number of floating instruction queue writes 431system.cpu.iq.fp_inst_queue_wakeup_accesses 2397328 # Number of floating instruction queue wakeup accesses 432system.cpu.iq.int_alu_accesses 266351243 # Number of integer alu accesses 433system.cpu.iq.fp_alu_accesses 2512979 # Number of floating point alu accesses 434system.cpu.iew.lsq.thread0.forwLoads 18909810 # Number of loads that had data forwarded from stores 435system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 436system.cpu.iew.lsq.thread0.squashedLoads 32990369 # Number of loads squashed 437system.cpu.iew.lsq.thread0.ignoredResponses 14136 # Number of memory responses ignored because the instruction is squashed 438system.cpu.iew.lsq.thread0.memOrderViolation 328607 # Number of memory ordering violations 439system.cpu.iew.lsq.thread0.squashedStores 11516932 # Number of stores squashed 440system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 441system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 442system.cpu.iew.lsq.thread0.rescheduledLoads 52167 # Number of loads that were rescheduled 443system.cpu.iew.lsq.thread0.cacheBlocked 10 # Number of times an access to memory failed due to the cache being blocked 444system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 445system.cpu.iew.iewSquashCycles 1851692 # Number of cycles IEW is squashing 446system.cpu.iew.iewBlockCycles 126137646 # Number of cycles IEW is blocking 447system.cpu.iew.iewUnblockCycles 5532810 # Number of cycles IEW is unblocking 448system.cpu.iew.iewDispatchedInsts 341339634 # Number of instructions dispatched to IQ 449system.cpu.iew.iewDispSquashedInsts 112602 # Number of squashed instructions skipped by dispatch 450system.cpu.iew.iewDispLoadInsts 89639956 # Number of dispatched load instructions 451system.cpu.iew.iewDispStoreInsts 32032649 # Number of dispatched store instructions 452system.cpu.iew.iewDispNonSpecInsts 2212 # Number of dispatched non-speculative instructions 453system.cpu.iew.iewIQFullEvents 2223479 # Number of times the IQ has become full, causing a stall 454system.cpu.iew.iewLSQFullEvents 382778 # Number of times the LSQ has become full, causing a stall 455system.cpu.iew.memOrderViolationEvents 328607 # Number of memory order violations 456system.cpu.iew.predictedTakenIncorrect 684628 # Number of branches that were predicted taken incorrectly 457system.cpu.iew.predictedNotTakenIncorrect 928175 # Number of branches that were predicted not taken incorrectly 458system.cpu.iew.branchMispredicts 1612803 # Number of branch mispredicts detected at execute 459system.cpu.iew.iewExecutedInsts 264737771 # Number of executed instructions 460system.cpu.iew.iewExecLoadInsts 65643847 # Number of load instructions executed 461system.cpu.iew.iewExecSquashedInsts 2119410 # Number of squashed instructions skipped in execute 462system.cpu.iew.exec_swp 0 # number of swp insts executed 463system.cpu.iew.exec_nop 0 # number of nop insts executed 464system.cpu.iew.exec_refs 88241442 # number of memory reference insts executed 465system.cpu.iew.exec_branches 14589088 # Number of branches executed 466system.cpu.iew.exec_stores 22597595 # Number of stores executed 467system.cpu.iew.exec_rate 0.890361 # Inst execution rate 468system.cpu.iew.wb_sent 264036391 # cumulative count of insts sent to commit 469system.cpu.iew.wb_count 263319939 # cumulative count of insts written-back 470system.cpu.iew.wb_producers 208896510 # num instructions producing a value 471system.cpu.iew.wb_consumers 376872402 # num instructions consuming a value 472system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 473system.cpu.iew.wb_rate 0.885592 # insts written-back per cycle 474system.cpu.iew.wb_fanout 0.554290 # average fanout of values written-back 475system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 476system.cpu.commit.commitSquashedInsts 120026923 # The number of squashed insts skipped by commit 477system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards 478system.cpu.commit.branchMispredicts 1559493 # The number of times a branch was mispredicted 479system.cpu.commit.committed_per_cycle::samples 280830334 # Number of insts commited each cycle 480system.cpu.commit.committed_per_cycle::mean 0.788246 # Number of insts commited each cycle 481system.cpu.commit.committed_per_cycle::stdev 1.594394 # Number of insts commited each cycle 482system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 483system.cpu.commit.committed_per_cycle::0 180946233 64.43% 64.43% # Number of insts commited each cycle 484system.cpu.commit.committed_per_cycle::1 57795535 20.58% 85.01% # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::2 14201408 5.06% 90.07% # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::3 11929876 4.25% 94.32% # Number of insts commited each cycle 487system.cpu.commit.committed_per_cycle::4 4188274 1.49% 95.81% # Number of insts commited each cycle 488system.cpu.commit.committed_per_cycle::5 2885386 1.03% 96.84% # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::6 910038 0.32% 97.16% # Number of insts commited each cycle 490system.cpu.commit.committed_per_cycle::7 1053521 0.38% 97.54% # Number of insts commited each cycle 491system.cpu.commit.committed_per_cycle::8 6920063 2.46% 100.00% # Number of insts commited each cycle 492system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 493system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 494system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 495system.cpu.commit.committed_per_cycle::total 280830334 # Number of insts commited each cycle 496system.cpu.commit.committedInsts 132071192 # Number of instructions committed 497system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed 498system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 499system.cpu.commit.refs 77165304 # Number of memory references committed 500system.cpu.commit.loads 56649587 # Number of loads committed 501system.cpu.commit.membars 0 # Number of memory barriers committed 502system.cpu.commit.branches 12326938 # Number of branches committed 503system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. 504system.cpu.commit.int_insts 219019985 # Number of committed integer instructions. 505system.cpu.commit.function_calls 797818 # Number of function calls committed. 506system.cpu.commit.op_class_0::No_OpClass 1176721 0.53% 0.53% # Class of committed instruction 507system.cpu.commit.op_class_0::IntAlu 134111832 60.58% 61.12% # Class of committed instruction 508system.cpu.commit.op_class_0::IntMult 772953 0.35% 61.47% # Class of committed instruction 509system.cpu.commit.op_class_0::IntDiv 7031501 3.18% 64.64% # Class of committed instruction 510system.cpu.commit.op_class_0::FloatAdd 1105073 0.50% 65.14% # Class of committed instruction 511system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.14% # Class of committed instruction 512system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.14% # Class of committed instruction 513system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.14% # Class of committed instruction 514system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.14% # Class of committed instruction 515system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.14% # Class of committed instruction 516system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.14% # Class of committed instruction 517system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.14% # Class of committed instruction 518system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.14% # Class of committed instruction 519system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.14% # Class of committed instruction 520system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.14% # Class of committed instruction 521system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.14% # Class of committed instruction 522system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.14% # Class of committed instruction 523system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.14% # Class of committed instruction 524system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.14% # Class of committed instruction 525system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.14% # Class of committed instruction 526system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.14% # Class of committed instruction 527system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.14% # Class of committed instruction 528system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.14% # Class of committed instruction 529system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.14% # Class of committed instruction 530system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.14% # Class of committed instruction 531system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.14% # Class of committed instruction 532system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.14% # Class of committed instruction 533system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction 534system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction 535system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction 536system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction 537system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction 538system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 539system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 540system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction 541system.cpu.commit.bw_lim_events 6920063 # number cycles where commit BW limit reached	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.148669 # Number of seconds simulated 4sim_ticks 148668850500 # Number of ticks simulated 5final_tick 148668850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 82634 # Simulator instruction rate (inst/s) 8host_op_rate 138502 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 93018548 # Simulator tick rate (ticks/s) 10host_mem_usage 346916 # Number of bytes of host memory used 11host_seconds 1598.27 # Real time elapsed on the host 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221363384 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 225344 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 125504 # Number of bytes read from this memory 18system.physmem.bytes_read::total 350848 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 225344 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 225344 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 3521 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1961 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 5482 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1515745 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 844185 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 2359929 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1515745 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1515745 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1515745 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 844185 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 2359929 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 5482 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 5482 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 350848 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 350848 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 345 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 294 # Per bank write bursts 45system.physmem.perBankRdBursts::1 364 # Per bank write bursts 46system.physmem.perBankRdBursts::2 457 # Per bank write bursts 47system.physmem.perBankRdBursts::3 371 # Per bank write bursts 48system.physmem.perBankRdBursts::4 339 # Per bank write bursts 49system.physmem.perBankRdBursts::5 333 # Per bank write bursts 50system.physmem.perBankRdBursts::6 398 # Per bank write bursts 51system.physmem.perBankRdBursts::7 383 # Per bank write bursts 52system.physmem.perBankRdBursts::8 344 # Per bank write bursts 53system.physmem.perBankRdBursts::9 280 # Per bank write bursts 54system.physmem.perBankRdBursts::10 239 # Per bank write bursts 55system.physmem.perBankRdBursts::11 268 # Per bank write bursts 56system.physmem.perBankRdBursts::12 225 # Per bank write bursts 57system.physmem.perBankRdBursts::13 502 # Per bank write bursts 58system.physmem.perBankRdBursts::14 395 # Per bank write bursts 59system.physmem.perBankRdBursts::15 290 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 148668756000 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 5482 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 4368 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 913 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 173 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 24 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 1140 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 306.470175 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 178.641766 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 326.557853 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 448 39.30% 39.30% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 255 22.37% 61.67% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 105 9.21% 70.88% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 70 6.14% 77.02% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 38 3.33% 80.35% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 59 5.18% 85.53% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 19 1.67% 87.19% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 18 1.58% 88.77% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 128 11.23% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 1140 # Bytes accessed per row activation 203system.physmem.totQLat 40930250 # Total ticks spent queuing 204system.physmem.totMemAccLat 143717750 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 27410000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 7466.30 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 26216.30 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 2.36 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 2.36 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.02 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 4334 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 79.06 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 27119437.43 # Average gap between requests 224system.physmem.pageHitRate 79.06 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 5027400 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 2743125 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 22776000 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 9709936080 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 4021675470 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 85670093250 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 99432251325 # Total energy per rank (pJ) 233system.physmem_0.averagePower 668.842708 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 142518159000 # Time in different power states 235system.physmem_0.memoryStateTime::REF 4964180000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 237system.physmem_0.memoryStateTime::ACT 1181750000 # Time in different power states 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.physmem_1.actEnergy 3568320 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 1947000 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 19648200 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 9709936080 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 3821631120 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 85845562500 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 99402293220 # Total energy per rank (pJ) 247system.physmem_1.averagePower 668.641253 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 142814554750 # Time in different power states 249system.physmem_1.memoryStateTime::REF 4964180000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 888260750 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.cpu.branchPred.lookups 22385702 # Number of BP lookups 254system.cpu.branchPred.condPredicted 22385702 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 1554139 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 14132286 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 13246709 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 93.733661 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 1526841 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 22095 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 264system.cpu.workload.num_syscalls 400 # Number of system calls 265system.cpu.numCycles 297337717 # number of cpu cycles simulated 266system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 267system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 268system.cpu.fetch.icacheStallCycles 27888104 # Number of cycles fetch is stalled on an Icache miss 269system.cpu.fetch.Insts 249064218 # Number of instructions fetch has processed 270system.cpu.fetch.Branches 22385702 # Number of branches that fetch encountered 271system.cpu.fetch.predictedBranches 14773550 # Number of branches that fetch has predicted taken 272system.cpu.fetch.Cycles 267343346 # Number of cycles fetch has run and was not squashing or blocked 273system.cpu.fetch.SquashCycles 3703385 # Number of cycles fetch has spent squashing 274system.cpu.fetch.TlbCycles 34 # Number of cycles fetch has spent waiting for tlb 275system.cpu.fetch.MiscStallCycles 5713 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 276system.cpu.fetch.PendingTrapStallCycles 48972 # Number of stall cycles due to pending traps 277system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions 278system.cpu.fetch.IcacheWaitRetryStallCycles 83 # Number of stall cycles due to full MSHR 279system.cpu.fetch.CacheLines 26656558 # Number of cache lines fetched 280system.cpu.fetch.IcacheSquashes 259176 # Number of outstanding Icache misses that were squashed 281system.cpu.fetch.rateDist::samples 297137957 # Number of instructions fetched each cycle (Total) 282system.cpu.fetch.rateDist::mean 1.382061 # Number of instructions fetched each cycle (Total) 283system.cpu.fetch.rateDist::stdev 2.790607 # Number of instructions fetched each cycle (Total) 284system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 285system.cpu.fetch.rateDist::0 229077480 77.09% 77.09% # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::1 5080600 1.71% 78.80% # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::2 4128062 1.39% 80.19% # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::3 4791015 1.61% 81.81% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::4 4884919 1.64% 83.45% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::5 5103681 1.72% 85.17% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::6 5337561 1.80% 86.96% # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::7 4007445 1.35% 88.31% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::8 34727194 11.69% 100.00% # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::total 297137957 # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.branchRate 0.075287 # Number of branch fetches per cycle 299system.cpu.fetch.rate 0.837648 # Number of inst fetches per cycle 300system.cpu.decode.IdleCycles 16350382 # Number of cycles decode is idle 301system.cpu.decode.BlockedCycles 230944995 # Number of cycles decode is blocked 302system.cpu.decode.RunCycles 26142980 # Number of cycles decode is running 303system.cpu.decode.UnblockCycles 21847908 # Number of cycles decode is unblocking 304system.cpu.decode.SquashCycles 1851692 # Number of cycles decode is squashing 305system.cpu.decode.DecodedInsts 359376016 # Number of instructions handled by decode 306system.cpu.rename.SquashCycles 1851692 # Number of cycles rename is squashing 307system.cpu.rename.IdleCycles 24144395 # Number of cycles rename is idle 308system.cpu.rename.BlockCycles 162574126 # Number of cycles rename is blocking 309system.cpu.rename.serializeStallCycles 34810 # count of cycles rename stalled for serializing inst 310system.cpu.rename.RunCycles 38280834 # Number of cycles rename is running 311system.cpu.rename.UnblockCycles 70252100 # Number of cycles rename is unblocking 312system.cpu.rename.RenamedInsts 350628030 # Number of instructions processed by rename 313system.cpu.rename.ROBFullEvents 42505 # Number of times rename has blocked due to ROB full 314system.cpu.rename.IQFullEvents 62013521 # Number of times rename has blocked due to IQ full 315system.cpu.rename.LQFullEvents 7956456 # Number of times rename has blocked due to LQ full 316system.cpu.rename.SQFullEvents 170486 # Number of times rename has blocked due to SQ full 317system.cpu.rename.RenamedOperands 405834886 # Number of destination operands rename has renamed 318system.cpu.rename.RenameLookups 972854229 # Number of register rename lookups that rename has made 319system.cpu.rename.int_rename_lookups 642281329 # Number of integer rename lookups 320system.cpu.rename.fp_rename_lookups 4678301 # Number of floating rename lookups 321system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed 322system.cpu.rename.UndoneMaps 146405436 # Number of HB maps that are undone due to squashing 323system.cpu.rename.serializingInsts 2386 # count of serializing insts renamed 324system.cpu.rename.tempSerializingInsts 2313 # count of temporary serializing insts renamed 325system.cpu.rename.skidInsts 128573116 # count of insts added to the skid buffer 326system.cpu.memDep0.insertedLoads 89639956 # Number of loads inserted to the mem dependence unit. 327system.cpu.memDep0.insertedStores 32032649 # Number of stores inserted to the mem dependence unit. 328system.cpu.memDep0.conflictingLoads 63973866 # Number of conflicting loads. 329system.cpu.memDep0.conflictingStores 21576036 # Number of conflicting stores. 330system.cpu.iq.iqInstsAdded 341334735 # Number of instructions added to the IQ (excludes non-spec) 331system.cpu.iq.iqNonSpecInstsAdded 4899 # Number of non-speculative instructions added to the IQ 332system.cpu.iq.iqInstsIssued 266857181 # Number of instructions issued 333system.cpu.iq.iqSquashedInstsIssued 74594 # Number of squashed instructions issued 334system.cpu.iq.iqSquashedInstsExamined 119571219 # Number of squashed instructions iterated over during squash; mainly for profiling 335system.cpu.iq.iqSquashedOperandsExamined 250511173 # Number of squashed operands that are examined and possibly removed from graph 336system.cpu.iq.iqSquashedNonSpecRemoved 3654 # Number of squashed non-spec instructions that were removed 337system.cpu.iq.issued_per_cycle::samples 297137957 # Number of insts issued each cycle 338system.cpu.iq.issued_per_cycle::mean 0.898092 # Number of insts issued each cycle 339system.cpu.iq.issued_per_cycle::stdev 1.364162 # Number of insts issued each cycle 340system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 341system.cpu.iq.issued_per_cycle::0 171399069 57.68% 57.68% # Number of insts issued each cycle 342system.cpu.iq.issued_per_cycle::1 54278133 18.27% 75.95% # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::2 33575860 11.30% 87.25% # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::3 19165859 6.45% 93.70% # Number of insts issued each cycle 345system.cpu.iq.issued_per_cycle::4 10861721 3.66% 97.36% # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::5 4344660 1.46% 98.82% # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::6 2227090 0.75% 99.57% # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::7 887493 0.30% 99.87% # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::8 398072 0.13% 100.00% # Number of insts issued each cycle 350system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 351system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 352system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 353system.cpu.iq.issued_per_cycle::total 297137957 # Number of insts issued each cycle 354system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 355system.cpu.iq.fu_full::IntAlu 235011 7.30% 7.30% # attempts to use FU when none available 356system.cpu.iq.fu_full::IntMult 0 0.00% 7.30% # attempts to use FU when none available 357system.cpu.iq.fu_full::IntDiv 0 0.00% 7.30% # attempts to use FU when none available 358system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.30% # attempts to use FU when none available 359system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.30% # attempts to use FU when none available 360system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.30% # attempts to use FU when none available 361system.cpu.iq.fu_full::FloatMult 0 0.00% 7.30% # attempts to use FU when none available 362system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.30% # attempts to use FU when none available 363system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.30% # attempts to use FU when none available 364system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.30% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.30% # attempts to use FU when none available 366system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.30% # attempts to use FU when none available 367system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.30% # attempts to use FU when none available 368system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.30% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.30% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdMult 0 0.00% 7.30% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.30% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdShift 0 0.00% 7.30% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.30% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.30% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.30% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.30% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.30% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.30% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.30% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.30% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.30% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.30% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.30% # attempts to use FU when none available 384system.cpu.iq.fu_full::MemRead 2578157 80.11% 87.41% # attempts to use FU when none available 385system.cpu.iq.fu_full::MemWrite 405217 12.59% 100.00% # attempts to use FU when none available 386system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 387system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 388system.cpu.iq.FU_type_0::No_OpClass 1211344 0.45% 0.45% # Type of FU issued 389system.cpu.iq.FU_type_0::IntAlu 167292419 62.69% 63.14% # Type of FU issued 390system.cpu.iq.FU_type_0::IntMult 790150 0.30% 63.44% # Type of FU issued 391system.cpu.iq.FU_type_0::IntDiv 7035672 2.64% 66.08% # Type of FU issued 392system.cpu.iq.FU_type_0::FloatAdd 1215098 0.46% 66.53% # Type of FU issued 393system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.53% # Type of FU issued 394system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.53% # Type of FU issued 395system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.53% # Type of FU issued 396system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.53% # Type of FU issued 397system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.53% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.53% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.53% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.53% # Type of FU issued 401system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.53% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.53% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.53% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.53% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.53% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.53% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.53% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.53% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.53% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.53% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.53% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.53% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.53% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.53% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.53% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.53% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.53% # Type of FU issued 418system.cpu.iq.FU_type_0::MemRead 66512451 24.92% 91.46% # Type of FU issued 419system.cpu.iq.FU_type_0::MemWrite 22800047 8.54% 100.00% # Type of FU issued 420system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 421system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 422system.cpu.iq.FU_type_0::total 266857181 # Type of FU issued 423system.cpu.iq.rate 0.897488 # Inst issue rate 424system.cpu.iq.fu_busy_cnt 3218385 # FU busy when requested 425system.cpu.iq.fu_busy_rate 0.012060 # FU busy rate (busy events/executed inst) 426system.cpu.iq.int_inst_queue_reads 829150425 # Number of integer instruction queue reads 427system.cpu.iq.int_inst_queue_writes 456900250 # Number of integer instruction queue writes 428system.cpu.iq.int_inst_queue_wakeup_accesses 260922611 # Number of integer instruction queue wakeup accesses 429system.cpu.iq.fp_inst_queue_reads 4994873 # Number of floating instruction queue reads 430system.cpu.iq.fp_inst_queue_writes 4333463 # Number of floating instruction queue writes 431system.cpu.iq.fp_inst_queue_wakeup_accesses 2397328 # Number of floating instruction queue wakeup accesses 432system.cpu.iq.int_alu_accesses 266351243 # Number of integer alu accesses 433system.cpu.iq.fp_alu_accesses 2512979 # Number of floating point alu accesses 434system.cpu.iew.lsq.thread0.forwLoads 18909810 # Number of loads that had data forwarded from stores 435system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 436system.cpu.iew.lsq.thread0.squashedLoads 32990369 # Number of loads squashed 437system.cpu.iew.lsq.thread0.ignoredResponses 14136 # Number of memory responses ignored because the instruction is squashed 438system.cpu.iew.lsq.thread0.memOrderViolation 328607 # Number of memory ordering violations 439system.cpu.iew.lsq.thread0.squashedStores 11516932 # Number of stores squashed 440system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 441system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 442system.cpu.iew.lsq.thread0.rescheduledLoads 52167 # Number of loads that were rescheduled 443system.cpu.iew.lsq.thread0.cacheBlocked 10 # Number of times an access to memory failed due to the cache being blocked 444system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 445system.cpu.iew.iewSquashCycles 1851692 # Number of cycles IEW is squashing 446system.cpu.iew.iewBlockCycles 126137646 # Number of cycles IEW is blocking 447system.cpu.iew.iewUnblockCycles 5532810 # Number of cycles IEW is unblocking 448system.cpu.iew.iewDispatchedInsts 341339634 # Number of instructions dispatched to IQ 449system.cpu.iew.iewDispSquashedInsts 112602 # Number of squashed instructions skipped by dispatch 450system.cpu.iew.iewDispLoadInsts 89639956 # Number of dispatched load instructions 451system.cpu.iew.iewDispStoreInsts 32032649 # Number of dispatched store instructions 452system.cpu.iew.iewDispNonSpecInsts 2212 # Number of dispatched non-speculative instructions 453system.cpu.iew.iewIQFullEvents 2223479 # Number of times the IQ has become full, causing a stall 454system.cpu.iew.iewLSQFullEvents 382778 # Number of times the LSQ has become full, causing a stall 455system.cpu.iew.memOrderViolationEvents 328607 # Number of memory order violations 456system.cpu.iew.predictedTakenIncorrect 684628 # Number of branches that were predicted taken incorrectly 457system.cpu.iew.predictedNotTakenIncorrect 928175 # Number of branches that were predicted not taken incorrectly 458system.cpu.iew.branchMispredicts 1612803 # Number of branch mispredicts detected at execute 459system.cpu.iew.iewExecutedInsts 264737771 # Number of executed instructions 460system.cpu.iew.iewExecLoadInsts 65643847 # Number of load instructions executed 461system.cpu.iew.iewExecSquashedInsts 2119410 # Number of squashed instructions skipped in execute 462system.cpu.iew.exec_swp 0 # number of swp insts executed 463system.cpu.iew.exec_nop 0 # number of nop insts executed 464system.cpu.iew.exec_refs 88241442 # number of memory reference insts executed 465system.cpu.iew.exec_branches 14589088 # Number of branches executed 466system.cpu.iew.exec_stores 22597595 # Number of stores executed 467system.cpu.iew.exec_rate 0.890361 # Inst execution rate 468system.cpu.iew.wb_sent 264036391 # cumulative count of insts sent to commit 469system.cpu.iew.wb_count 263319939 # cumulative count of insts written-back 470system.cpu.iew.wb_producers 208896510 # num instructions producing a value 471system.cpu.iew.wb_consumers 376872402 # num instructions consuming a value 472system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 473system.cpu.iew.wb_rate 0.885592 # insts written-back per cycle 474system.cpu.iew.wb_fanout 0.554290 # average fanout of values written-back 475system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 476system.cpu.commit.commitSquashedInsts 120026923 # The number of squashed insts skipped by commit 477system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards 478system.cpu.commit.branchMispredicts 1559493 # The number of times a branch was mispredicted 479system.cpu.commit.committed_per_cycle::samples 280830334 # Number of insts commited each cycle 480system.cpu.commit.committed_per_cycle::mean 0.788246 # Number of insts commited each cycle 481system.cpu.commit.committed_per_cycle::stdev 1.594394 # Number of insts commited each cycle 482system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 483system.cpu.commit.committed_per_cycle::0 180946233 64.43% 64.43% # Number of insts commited each cycle 484system.cpu.commit.committed_per_cycle::1 57795535 20.58% 85.01% # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::2 14201408 5.06% 90.07% # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::3 11929876 4.25% 94.32% # Number of insts commited each cycle 487system.cpu.commit.committed_per_cycle::4 4188274 1.49% 95.81% # Number of insts commited each cycle 488system.cpu.commit.committed_per_cycle::5 2885386 1.03% 96.84% # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::6 910038 0.32% 97.16% # Number of insts commited each cycle 490system.cpu.commit.committed_per_cycle::7 1053521 0.38% 97.54% # Number of insts commited each cycle 491system.cpu.commit.committed_per_cycle::8 6920063 2.46% 100.00% # Number of insts commited each cycle 492system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 493system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 494system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 495system.cpu.commit.committed_per_cycle::total 280830334 # Number of insts commited each cycle 496system.cpu.commit.committedInsts 132071192 # Number of instructions committed 497system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed 498system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 499system.cpu.commit.refs 77165304 # Number of memory references committed 500system.cpu.commit.loads 56649587 # Number of loads committed 501system.cpu.commit.membars 0 # Number of memory barriers committed 502system.cpu.commit.branches 12326938 # Number of branches committed 503system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. 504system.cpu.commit.int_insts 219019985 # Number of committed integer instructions. 505system.cpu.commit.function_calls 797818 # Number of function calls committed. 506system.cpu.commit.op_class_0::No_OpClass 1176721 0.53% 0.53% # Class of committed instruction 507system.cpu.commit.op_class_0::IntAlu 134111832 60.58% 61.12% # Class of committed instruction 508system.cpu.commit.op_class_0::IntMult 772953 0.35% 61.47% # Class of committed instruction 509system.cpu.commit.op_class_0::IntDiv 7031501 3.18% 64.64% # Class of committed instruction 510system.cpu.commit.op_class_0::FloatAdd 1105073 0.50% 65.14% # Class of committed instruction 511system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.14% # Class of committed instruction 512system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.14% # Class of committed instruction 513system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.14% # Class of committed instruction 514system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.14% # Class of committed instruction 515system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.14% # Class of committed instruction 516system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.14% # Class of committed instruction 517system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.14% # Class of committed instruction 518system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.14% # Class of committed instruction 519system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.14% # Class of committed instruction 520system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.14% # Class of committed instruction 521system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.14% # Class of committed instruction 522system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.14% # Class of committed instruction 523system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.14% # Class of committed instruction 524system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.14% # Class of committed instruction 525system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.14% # Class of committed instruction 526system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.14% # Class of committed instruction 527system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.14% # Class of committed instruction 528system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.14% # Class of committed instruction 529system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.14% # Class of committed instruction 530system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.14% # Class of committed instruction 531system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.14% # Class of committed instruction 532system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.14% # Class of committed instruction 533system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction 534system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction 535system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction 536system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction 537system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction 538system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 539system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 540system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction 541system.cpu.commit.bw_lim_events 6920063 # number cycles where commit BW limit reached
542system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
543system.cpu.rob.rob_reads 615300578 # The number of ROB reads 544system.cpu.rob.rob_writes 699132843 # The number of ROB writes 545system.cpu.timesIdled 3156 # Number of times that the entire CPU went into an idle state and unscheduled itself 546system.cpu.idleCycles 199760 # Total number of cycles that the CPU has spent unscheduled due to idling 547system.cpu.committedInsts 132071192 # Number of Instructions Simulated 548system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated 549system.cpu.cpi 2.251344 # CPI: Cycles Per Instruction 550system.cpu.cpi_total 2.251344 # CPI: Total CPI of All Threads 551system.cpu.ipc 0.444179 # IPC: Instructions Per Cycle 552system.cpu.ipc_total 0.444179 # IPC: Total IPC of All Threads 553system.cpu.int_regfile_reads 456486870 # number of integer regfile reads 554system.cpu.int_regfile_writes 239256029 # number of integer regfile writes 555system.cpu.fp_regfile_reads 3277423 # number of floating regfile reads 556system.cpu.fp_regfile_writes 2057707 # number of floating regfile writes 557system.cpu.cc_regfile_reads 102994410 # number of cc regfile reads 558system.cpu.cc_regfile_writes 60201710 # number of cc regfile writes 559system.cpu.misc_regfile_reads 136869897 # number of misc regfile reads 560system.cpu.misc_regfile_writes 1689 # number of misc regfile writes 561system.cpu.dcache.tags.replacements 51 # number of replacements 562system.cpu.dcache.tags.tagsinuse 1444.566400 # Cycle average of tags in use 563system.cpu.dcache.tags.total_refs 67084714 # Total number of references to valid blocks. 564system.cpu.dcache.tags.sampled_refs 2000 # Sample count of references to valid blocks. 565system.cpu.dcache.tags.avg_refs 33542.357000 # Average number of references to valid blocks. 566system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 567system.cpu.dcache.tags.occ_blocks::cpu.data 1444.566400 # Average occupied blocks per requestor 568system.cpu.dcache.tags.occ_percent::cpu.data 0.352677 # Average percentage of cache occupancy 569system.cpu.dcache.tags.occ_percent::total 0.352677 # Average percentage of cache occupancy 570system.cpu.dcache.tags.occ_task_id_blocks::1024 1949 # Occupied blocks per task id 571system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id 572system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id 573system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id 574system.cpu.dcache.tags.age_task_id_blocks_1024::3 432 # Occupied blocks per task id 575system.cpu.dcache.tags.age_task_id_blocks_1024::4 1405 # Occupied blocks per task id 576system.cpu.dcache.tags.occ_task_id_percent::1024 0.475830 # Percentage of cache occupancy per task id 577system.cpu.dcache.tags.tag_accesses 134176300 # Number of tag accesses 578system.cpu.dcache.tags.data_accesses 134176300 # Number of data accesses 579system.cpu.dcache.ReadReq_hits::cpu.data 46570369 # number of ReadReq hits 580system.cpu.dcache.ReadReq_hits::total 46570369 # number of ReadReq hits 581system.cpu.dcache.WriteReq_hits::cpu.data 20513845 # number of WriteReq hits 582system.cpu.dcache.WriteReq_hits::total 20513845 # number of WriteReq hits 583system.cpu.dcache.demand_hits::cpu.data 67084214 # number of demand (read+write) hits 584system.cpu.dcache.demand_hits::total 67084214 # number of demand (read+write) hits 585system.cpu.dcache.overall_hits::cpu.data 67084214 # number of overall hits 586system.cpu.dcache.overall_hits::total 67084214 # number of overall hits 587system.cpu.dcache.ReadReq_misses::cpu.data 1050 # number of ReadReq misses 588system.cpu.dcache.ReadReq_misses::total 1050 # number of ReadReq misses 589system.cpu.dcache.WriteReq_misses::cpu.data 1886 # number of WriteReq misses 590system.cpu.dcache.WriteReq_misses::total 1886 # number of WriteReq misses 591system.cpu.dcache.demand_misses::cpu.data 2936 # number of demand (read+write) misses 592system.cpu.dcache.demand_misses::total 2936 # number of demand (read+write) misses 593system.cpu.dcache.overall_misses::cpu.data 2936 # number of overall misses 594system.cpu.dcache.overall_misses::total 2936 # number of overall misses 595system.cpu.dcache.ReadReq_miss_latency::cpu.data 66068903 # number of ReadReq miss cycles 596system.cpu.dcache.ReadReq_miss_latency::total 66068903 # number of ReadReq miss cycles 597system.cpu.dcache.WriteReq_miss_latency::cpu.data 130813345 # number of WriteReq miss cycles 598system.cpu.dcache.WriteReq_miss_latency::total 130813345 # number of WriteReq miss cycles 599system.cpu.dcache.demand_miss_latency::cpu.data 196882248 # number of demand (read+write) miss cycles 600system.cpu.dcache.demand_miss_latency::total 196882248 # number of demand (read+write) miss cycles 601system.cpu.dcache.overall_miss_latency::cpu.data 196882248 # number of overall miss cycles 602system.cpu.dcache.overall_miss_latency::total 196882248 # number of overall miss cycles 603system.cpu.dcache.ReadReq_accesses::cpu.data 46571419 # number of ReadReq accesses(hits+misses) 604system.cpu.dcache.ReadReq_accesses::total 46571419 # number of ReadReq accesses(hits+misses) 605system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) 606system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) 607system.cpu.dcache.demand_accesses::cpu.data 67087150 # number of demand (read+write) accesses 608system.cpu.dcache.demand_accesses::total 67087150 # number of demand (read+write) accesses 609system.cpu.dcache.overall_accesses::cpu.data 67087150 # number of overall (read+write) accesses 610system.cpu.dcache.overall_accesses::total 67087150 # number of overall (read+write) accesses 611system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses 612system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses 613system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000092 # miss rate for WriteReq accesses 614system.cpu.dcache.WriteReq_miss_rate::total 0.000092 # miss rate for WriteReq accesses 615system.cpu.dcache.demand_miss_rate::cpu.data 0.000044 # miss rate for demand accesses 616system.cpu.dcache.demand_miss_rate::total 0.000044 # miss rate for demand accesses 617system.cpu.dcache.overall_miss_rate::cpu.data 0.000044 # miss rate for overall accesses 618system.cpu.dcache.overall_miss_rate::total 0.000044 # miss rate for overall accesses 619system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62922.764762 # average ReadReq miss latency 620system.cpu.dcache.ReadReq_avg_miss_latency::total 62922.764762 # average ReadReq miss latency 621system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69360.204136 # average WriteReq miss latency 622system.cpu.dcache.WriteReq_avg_miss_latency::total 69360.204136 # average WriteReq miss latency 623system.cpu.dcache.demand_avg_miss_latency::cpu.data 67057.986376 # average overall miss latency 624system.cpu.dcache.demand_avg_miss_latency::total 67057.986376 # average overall miss latency 625system.cpu.dcache.overall_avg_miss_latency::cpu.data 67057.986376 # average overall miss latency 626system.cpu.dcache.overall_avg_miss_latency::total 67057.986376 # average overall miss latency 627system.cpu.dcache.blocked_cycles::no_mshrs 241 # number of cycles access was blocked 628system.cpu.dcache.blocked_cycles::no_targets 39 # number of cycles access was blocked 629system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked 630system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked 631system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.200000 # average number of cycles each access was blocked 632system.cpu.dcache.avg_blocked_cycles::no_targets 19.500000 # average number of cycles each access was blocked 633system.cpu.dcache.fast_writes 0 # number of fast writes performed 634system.cpu.dcache.cache_copies 0 # number of cache copies performed 635system.cpu.dcache.writebacks::writebacks 10 # number of writebacks 636system.cpu.dcache.writebacks::total 10 # number of writebacks 637system.cpu.dcache.ReadReq_mshr_hits::cpu.data 588 # number of ReadReq MSHR hits 638system.cpu.dcache.ReadReq_mshr_hits::total 588 # number of ReadReq MSHR hits 639system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits 640system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits 641system.cpu.dcache.demand_mshr_hits::cpu.data 589 # number of demand (read+write) MSHR hits 642system.cpu.dcache.demand_mshr_hits::total 589 # number of demand (read+write) MSHR hits 643system.cpu.dcache.overall_mshr_hits::cpu.data 589 # number of overall MSHR hits 644system.cpu.dcache.overall_mshr_hits::total 589 # number of overall MSHR hits 645system.cpu.dcache.ReadReq_mshr_misses::cpu.data 462 # number of ReadReq MSHR misses 646system.cpu.dcache.ReadReq_mshr_misses::total 462 # number of ReadReq MSHR misses 647system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1885 # number of WriteReq MSHR misses 648system.cpu.dcache.WriteReq_mshr_misses::total 1885 # number of WriteReq MSHR misses 649system.cpu.dcache.demand_mshr_misses::cpu.data 2347 # number of demand (read+write) MSHR misses 650system.cpu.dcache.demand_mshr_misses::total 2347 # number of demand (read+write) MSHR misses 651system.cpu.dcache.overall_mshr_misses::cpu.data 2347 # number of overall MSHR misses 652system.cpu.dcache.overall_mshr_misses::total 2347 # number of overall MSHR misses 653system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36319250 # number of ReadReq MSHR miss cycles 654system.cpu.dcache.ReadReq_mshr_miss_latency::total 36319250 # number of ReadReq MSHR miss cycles 655system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127241905 # number of WriteReq MSHR miss cycles 656system.cpu.dcache.WriteReq_mshr_miss_latency::total 127241905 # number of WriteReq MSHR miss cycles 657system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163561155 # number of demand (read+write) MSHR miss cycles 658system.cpu.dcache.demand_mshr_miss_latency::total 163561155 # number of demand (read+write) MSHR miss cycles 659system.cpu.dcache.overall_mshr_miss_latency::cpu.data 163561155 # number of overall MSHR miss cycles 660system.cpu.dcache.overall_mshr_miss_latency::total 163561155 # number of overall MSHR miss cycles 661system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses 662system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses 663system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000092 # mshr miss rate for WriteReq accesses 664system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000092 # mshr miss rate for WriteReq accesses 665system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for demand accesses 666system.cpu.dcache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses 667system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for overall accesses 668system.cpu.dcache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses 669system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78613.095238 # average ReadReq mshr miss latency 670system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78613.095238 # average ReadReq mshr miss latency 671system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67502.336870 # average WriteReq mshr miss latency 672system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67502.336870 # average WriteReq mshr miss latency 673system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69689.456753 # average overall mshr miss latency 674system.cpu.dcache.demand_avg_mshr_miss_latency::total 69689.456753 # average overall mshr miss latency 675system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69689.456753 # average overall mshr miss latency 676system.cpu.dcache.overall_avg_mshr_miss_latency::total 69689.456753 # average overall mshr miss latency 677system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 678system.cpu.icache.tags.replacements 5861 # number of replacements 679system.cpu.icache.tags.tagsinuse 1662.434995 # Cycle average of tags in use 680system.cpu.icache.tags.total_refs 26645946 # Total number of references to valid blocks. 681system.cpu.icache.tags.sampled_refs 7838 # Sample count of references to valid blocks. 682system.cpu.icache.tags.avg_refs 3399.584843 # Average number of references to valid blocks. 683system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 684system.cpu.icache.tags.occ_blocks::cpu.inst 1662.434995 # Average occupied blocks per requestor 685system.cpu.icache.tags.occ_percent::cpu.inst 0.811736 # Average percentage of cache occupancy 686system.cpu.icache.tags.occ_percent::total 0.811736 # Average percentage of cache occupancy 687system.cpu.icache.tags.occ_task_id_blocks::1024 1977 # Occupied blocks per task id 688system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id 689system.cpu.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id 690system.cpu.icache.tags.age_task_id_blocks_1024::2 756 # Occupied blocks per task id 691system.cpu.icache.tags.age_task_id_blocks_1024::3 135 # Occupied blocks per task id 692system.cpu.icache.tags.age_task_id_blocks_1024::4 777 # Occupied blocks per task id 693system.cpu.icache.tags.occ_task_id_percent::1024 0.965332 # Percentage of cache occupancy per task id 694system.cpu.icache.tags.tag_accesses 53321296 # Number of tag accesses 695system.cpu.icache.tags.data_accesses 53321296 # Number of data accesses 696system.cpu.icache.ReadReq_hits::cpu.inst 26645946 # number of ReadReq hits 697system.cpu.icache.ReadReq_hits::total 26645946 # number of ReadReq hits 698system.cpu.icache.demand_hits::cpu.inst 26645946 # number of demand (read+write) hits 699system.cpu.icache.demand_hits::total 26645946 # number of demand (read+write) hits 700system.cpu.icache.overall_hits::cpu.inst 26645946 # number of overall hits 701system.cpu.icache.overall_hits::total 26645946 # number of overall hits 702system.cpu.icache.ReadReq_misses::cpu.inst 10610 # number of ReadReq misses 703system.cpu.icache.ReadReq_misses::total 10610 # number of ReadReq misses 704system.cpu.icache.demand_misses::cpu.inst 10610 # number of demand (read+write) misses 705system.cpu.icache.demand_misses::total 10610 # number of demand (read+write) misses 706system.cpu.icache.overall_misses::cpu.inst 10610 # number of overall misses 707system.cpu.icache.overall_misses::total 10610 # number of overall misses 708system.cpu.icache.ReadReq_miss_latency::cpu.inst 431026999 # number of ReadReq miss cycles 709system.cpu.icache.ReadReq_miss_latency::total 431026999 # number of ReadReq miss cycles 710system.cpu.icache.demand_miss_latency::cpu.inst 431026999 # number of demand (read+write) miss cycles 711system.cpu.icache.demand_miss_latency::total 431026999 # number of demand (read+write) miss cycles 712system.cpu.icache.overall_miss_latency::cpu.inst 431026999 # number of overall miss cycles 713system.cpu.icache.overall_miss_latency::total 431026999 # number of overall miss cycles 714system.cpu.icache.ReadReq_accesses::cpu.inst 26656556 # number of ReadReq accesses(hits+misses) 715system.cpu.icache.ReadReq_accesses::total 26656556 # number of ReadReq accesses(hits+misses) 716system.cpu.icache.demand_accesses::cpu.inst 26656556 # number of demand (read+write) accesses 717system.cpu.icache.demand_accesses::total 26656556 # number of demand (read+write) accesses 718system.cpu.icache.overall_accesses::cpu.inst 26656556 # number of overall (read+write) accesses 719system.cpu.icache.overall_accesses::total 26656556 # number of overall (read+write) accesses 720system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000398 # miss rate for ReadReq accesses 721system.cpu.icache.ReadReq_miss_rate::total 0.000398 # miss rate for ReadReq accesses 722system.cpu.icache.demand_miss_rate::cpu.inst 0.000398 # miss rate for demand accesses 723system.cpu.icache.demand_miss_rate::total 0.000398 # miss rate for demand accesses 724system.cpu.icache.overall_miss_rate::cpu.inst 0.000398 # miss rate for overall accesses 725system.cpu.icache.overall_miss_rate::total 0.000398 # miss rate for overall accesses 726system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40624.599340 # average ReadReq miss latency 727system.cpu.icache.ReadReq_avg_miss_latency::total 40624.599340 # average ReadReq miss latency 728system.cpu.icache.demand_avg_miss_latency::cpu.inst 40624.599340 # average overall miss latency 729system.cpu.icache.demand_avg_miss_latency::total 40624.599340 # average overall miss latency 730system.cpu.icache.overall_avg_miss_latency::cpu.inst 40624.599340 # average overall miss latency 731system.cpu.icache.overall_avg_miss_latency::total 40624.599340 # average overall miss latency 732system.cpu.icache.blocked_cycles::no_mshrs 1664 # number of cycles access was blocked 733system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 734system.cpu.icache.blocked::no_mshrs 27 # number of cycles access was blocked 735system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 736system.cpu.icache.avg_blocked_cycles::no_mshrs 61.629630 # average number of cycles each access was blocked 737system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 738system.cpu.icache.fast_writes 0 # number of fast writes performed 739system.cpu.icache.cache_copies 0 # number of cache copies performed 740system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2425 # number of ReadReq MSHR hits 741system.cpu.icache.ReadReq_mshr_hits::total 2425 # number of ReadReq MSHR hits 742system.cpu.icache.demand_mshr_hits::cpu.inst 2425 # number of demand (read+write) MSHR hits 743system.cpu.icache.demand_mshr_hits::total 2425 # number of demand (read+write) MSHR hits 744system.cpu.icache.overall_mshr_hits::cpu.inst 2425 # number of overall MSHR hits 745system.cpu.icache.overall_mshr_hits::total 2425 # number of overall MSHR hits 746system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8185 # number of ReadReq MSHR misses 747system.cpu.icache.ReadReq_mshr_misses::total 8185 # number of ReadReq MSHR misses 748system.cpu.icache.demand_mshr_misses::cpu.inst 8185 # number of demand (read+write) MSHR misses 749system.cpu.icache.demand_mshr_misses::total 8185 # number of demand (read+write) MSHR misses 750system.cpu.icache.overall_mshr_misses::cpu.inst 8185 # number of overall MSHR misses 751system.cpu.icache.overall_mshr_misses::total 8185 # number of overall MSHR misses 752system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 323320999 # number of ReadReq MSHR miss cycles 753system.cpu.icache.ReadReq_mshr_miss_latency::total 323320999 # number of ReadReq MSHR miss cycles 754system.cpu.icache.demand_mshr_miss_latency::cpu.inst 323320999 # number of demand (read+write) MSHR miss cycles 755system.cpu.icache.demand_mshr_miss_latency::total 323320999 # number of demand (read+write) MSHR miss cycles 756system.cpu.icache.overall_mshr_miss_latency::cpu.inst 323320999 # number of overall MSHR miss cycles 757system.cpu.icache.overall_mshr_miss_latency::total 323320999 # number of overall MSHR miss cycles 758system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for ReadReq accesses 759system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000307 # mshr miss rate for ReadReq accesses 760system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for demand accesses 761system.cpu.icache.demand_mshr_miss_rate::total 0.000307 # mshr miss rate for demand accesses 762system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for overall accesses 763system.cpu.icache.overall_mshr_miss_rate::total 0.000307 # mshr miss rate for overall accesses 764system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39501.649236 # average ReadReq mshr miss latency 765system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39501.649236 # average ReadReq mshr miss latency 766system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39501.649236 # average overall mshr miss latency 767system.cpu.icache.demand_avg_mshr_miss_latency::total 39501.649236 # average overall mshr miss latency 768system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39501.649236 # average overall mshr miss latency 769system.cpu.icache.overall_avg_mshr_miss_latency::total 39501.649236 # average overall mshr miss latency 770system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 771system.cpu.l2cache.tags.replacements 0 # number of replacements 772system.cpu.l2cache.tags.tagsinuse 2641.798011 # Cycle average of tags in use 773system.cpu.l2cache.tags.total_refs 4354 # Total number of references to valid blocks. 774system.cpu.l2cache.tags.sampled_refs 3951 # Sample count of references to valid blocks. 775system.cpu.l2cache.tags.avg_refs 1.101999 # Average number of references to valid blocks. 776system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 777system.cpu.l2cache.tags.occ_blocks::writebacks 1.181969 # Average occupied blocks per requestor 778system.cpu.l2cache.tags.occ_blocks::cpu.inst 2328.091219 # Average occupied blocks per requestor 779system.cpu.l2cache.tags.occ_blocks::cpu.data 312.524822 # Average occupied blocks per requestor 780system.cpu.l2cache.tags.occ_percent::writebacks 0.000036 # Average percentage of cache occupancy 781system.cpu.l2cache.tags.occ_percent::cpu.inst 0.071048 # Average percentage of cache occupancy 782system.cpu.l2cache.tags.occ_percent::cpu.data 0.009538 # Average percentage of cache occupancy 783system.cpu.l2cache.tags.occ_percent::total 0.080621 # Average percentage of cache occupancy 784system.cpu.l2cache.tags.occ_task_id_blocks::1024 3951 # Occupied blocks per task id 785system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 786system.cpu.l2cache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id 787system.cpu.l2cache.tags.age_task_id_blocks_1024::2 894 # Occupied blocks per task id 788system.cpu.l2cache.tags.age_task_id_blocks_1024::3 157 # Occupied blocks per task id 789system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2664 # Occupied blocks per task id 790system.cpu.l2cache.tags.occ_task_id_percent::1024 0.120575 # Percentage of cache occupancy per task id 791system.cpu.l2cache.tags.tag_accesses 87043 # Number of tag accesses 792system.cpu.l2cache.tags.data_accesses 87043 # Number of data accesses 793system.cpu.l2cache.ReadReq_hits::cpu.inst 4315 # number of ReadReq hits 794system.cpu.l2cache.ReadReq_hits::cpu.data 34 # number of ReadReq hits 795system.cpu.l2cache.ReadReq_hits::total 4349 # number of ReadReq hits 796system.cpu.l2cache.Writeback_hits::writebacks 10 # number of Writeback hits 797system.cpu.l2cache.Writeback_hits::total 10 # number of Writeback hits 798system.cpu.l2cache.UpgradeReq_hits::cpu.data 2 # number of UpgradeReq hits 799system.cpu.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits 800system.cpu.l2cache.ReadExReq_hits::cpu.data 5 # number of ReadExReq hits 801system.cpu.l2cache.ReadExReq_hits::total 5 # number of ReadExReq hits 802system.cpu.l2cache.demand_hits::cpu.inst 4315 # number of demand (read+write) hits 803system.cpu.l2cache.demand_hits::cpu.data 39 # number of demand (read+write) hits 804system.cpu.l2cache.demand_hits::total 4354 # number of demand (read+write) hits 805system.cpu.l2cache.overall_hits::cpu.inst 4315 # number of overall hits 806system.cpu.l2cache.overall_hits::cpu.data 39 # number of overall hits 807system.cpu.l2cache.overall_hits::total 4354 # number of overall hits 808system.cpu.l2cache.ReadReq_misses::cpu.inst 3522 # number of ReadReq misses 809system.cpu.l2cache.ReadReq_misses::cpu.data 428 # number of ReadReq misses 810system.cpu.l2cache.ReadReq_misses::total 3950 # number of ReadReq misses 811system.cpu.l2cache.UpgradeReq_misses::cpu.data 345 # number of UpgradeReq misses 812system.cpu.l2cache.UpgradeReq_misses::total 345 # number of UpgradeReq misses 813system.cpu.l2cache.ReadExReq_misses::cpu.data 1533 # number of ReadExReq misses 814system.cpu.l2cache.ReadExReq_misses::total 1533 # number of ReadExReq misses 815system.cpu.l2cache.demand_misses::cpu.inst 3522 # number of demand (read+write) misses 816system.cpu.l2cache.demand_misses::cpu.data 1961 # number of demand (read+write) misses 817system.cpu.l2cache.demand_misses::total 5483 # number of demand (read+write) misses 818system.cpu.l2cache.overall_misses::cpu.inst 3522 # number of overall misses 819system.cpu.l2cache.overall_misses::cpu.data 1961 # number of overall misses 820system.cpu.l2cache.overall_misses::total 5483 # number of overall misses 821system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 269302250 # number of ReadReq miss cycles 822system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35486250 # number of ReadReq miss cycles 823system.cpu.l2cache.ReadReq_miss_latency::total 304788500 # number of ReadReq miss cycles 824system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 114514250 # number of ReadExReq miss cycles 825system.cpu.l2cache.ReadExReq_miss_latency::total 114514250 # number of ReadExReq miss cycles 826system.cpu.l2cache.demand_miss_latency::cpu.inst 269302250 # number of demand (read+write) miss cycles 827system.cpu.l2cache.demand_miss_latency::cpu.data 150000500 # number of demand (read+write) miss cycles 828system.cpu.l2cache.demand_miss_latency::total 419302750 # number of demand (read+write) miss cycles 829system.cpu.l2cache.overall_miss_latency::cpu.inst 269302250 # number of overall miss cycles 830system.cpu.l2cache.overall_miss_latency::cpu.data 150000500 # number of overall miss cycles 831system.cpu.l2cache.overall_miss_latency::total 419302750 # number of overall miss cycles 832system.cpu.l2cache.ReadReq_accesses::cpu.inst 7837 # number of ReadReq accesses(hits+misses) 833system.cpu.l2cache.ReadReq_accesses::cpu.data 462 # number of ReadReq accesses(hits+misses) 834system.cpu.l2cache.ReadReq_accesses::total 8299 # number of ReadReq accesses(hits+misses) 835system.cpu.l2cache.Writeback_accesses::writebacks 10 # number of Writeback accesses(hits+misses) 836system.cpu.l2cache.Writeback_accesses::total 10 # number of Writeback accesses(hits+misses) 837system.cpu.l2cache.UpgradeReq_accesses::cpu.data 347 # number of UpgradeReq accesses(hits+misses) 838system.cpu.l2cache.UpgradeReq_accesses::total 347 # number of UpgradeReq accesses(hits+misses) 839system.cpu.l2cache.ReadExReq_accesses::cpu.data 1538 # number of ReadExReq accesses(hits+misses) 840system.cpu.l2cache.ReadExReq_accesses::total 1538 # number of ReadExReq accesses(hits+misses) 841system.cpu.l2cache.demand_accesses::cpu.inst 7837 # number of demand (read+write) accesses 842system.cpu.l2cache.demand_accesses::cpu.data 2000 # number of demand (read+write) accesses 843system.cpu.l2cache.demand_accesses::total 9837 # number of demand (read+write) accesses 844system.cpu.l2cache.overall_accesses::cpu.inst 7837 # number of overall (read+write) accesses 845system.cpu.l2cache.overall_accesses::cpu.data 2000 # number of overall (read+write) accesses 846system.cpu.l2cache.overall_accesses::total 9837 # number of overall (read+write) accesses 847system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.449407 # miss rate for ReadReq accesses 848system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.926407 # miss rate for ReadReq accesses 849system.cpu.l2cache.ReadReq_miss_rate::total 0.475961 # miss rate for ReadReq accesses 850system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.994236 # miss rate for UpgradeReq accesses 851system.cpu.l2cache.UpgradeReq_miss_rate::total 0.994236 # miss rate for UpgradeReq accesses 852system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996749 # miss rate for ReadExReq accesses 853system.cpu.l2cache.ReadExReq_miss_rate::total 0.996749 # miss rate for ReadExReq accesses 854system.cpu.l2cache.demand_miss_rate::cpu.inst 0.449407 # miss rate for demand accesses 855system.cpu.l2cache.demand_miss_rate::cpu.data 0.980500 # miss rate for demand accesses 856system.cpu.l2cache.demand_miss_rate::total 0.557385 # miss rate for demand accesses 857system.cpu.l2cache.overall_miss_rate::cpu.inst 0.449407 # miss rate for overall accesses 858system.cpu.l2cache.overall_miss_rate::cpu.data 0.980500 # miss rate for overall accesses 859system.cpu.l2cache.overall_miss_rate::total 0.557385 # miss rate for overall accesses 860system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76462.876207 # average ReadReq miss latency 861system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82911.799065 # average ReadReq miss latency 862system.cpu.l2cache.ReadReq_avg_miss_latency::total 77161.645570 # average ReadReq miss latency 863system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74699.445532 # average ReadExReq miss latency 864system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74699.445532 # average ReadExReq miss latency 865system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76462.876207 # average overall miss latency 866system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76491.840898 # average overall miss latency 867system.cpu.l2cache.demand_avg_miss_latency::total 76473.235455 # average overall miss latency 868system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76462.876207 # average overall miss latency 869system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76491.840898 # average overall miss latency 870system.cpu.l2cache.overall_avg_miss_latency::total 76473.235455 # average overall miss latency 871system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 872system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 873system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 874system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 875system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 876system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 877system.cpu.l2cache.fast_writes 0 # number of fast writes performed 878system.cpu.l2cache.cache_copies 0 # number of cache copies performed 879system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3522 # number of ReadReq MSHR misses 880system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 428 # number of ReadReq MSHR misses 881system.cpu.l2cache.ReadReq_mshr_misses::total 3950 # number of ReadReq MSHR misses 882system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 345 # number of UpgradeReq MSHR misses 883system.cpu.l2cache.UpgradeReq_mshr_misses::total 345 # number of UpgradeReq MSHR misses 884system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1533 # number of ReadExReq MSHR misses 885system.cpu.l2cache.ReadExReq_mshr_misses::total 1533 # number of ReadExReq MSHR misses 886system.cpu.l2cache.demand_mshr_misses::cpu.inst 3522 # number of demand (read+write) MSHR misses 887system.cpu.l2cache.demand_mshr_misses::cpu.data 1961 # number of demand (read+write) MSHR misses 888system.cpu.l2cache.demand_mshr_misses::total 5483 # number of demand (read+write) MSHR misses 889system.cpu.l2cache.overall_mshr_misses::cpu.inst 3522 # number of overall MSHR misses 890system.cpu.l2cache.overall_mshr_misses::cpu.data 1961 # number of overall MSHR misses 891system.cpu.l2cache.overall_mshr_misses::total 5483 # number of overall MSHR misses 892system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 225343750 # number of ReadReq MSHR miss cycles 893system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30127250 # number of ReadReq MSHR miss cycles 894system.cpu.l2cache.ReadReq_mshr_miss_latency::total 255471000 # number of ReadReq MSHR miss cycles 895system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6111844 # number of UpgradeReq MSHR miss cycles 896system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6111844 # number of UpgradeReq MSHR miss cycles 897system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 95336750 # number of ReadExReq MSHR miss cycles 898system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95336750 # number of ReadExReq MSHR miss cycles 899system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 225343750 # number of demand (read+write) MSHR miss cycles 900system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 125464000 # number of demand (read+write) MSHR miss cycles 901system.cpu.l2cache.demand_mshr_miss_latency::total 350807750 # number of demand (read+write) MSHR miss cycles 902system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 225343750 # number of overall MSHR miss cycles 903system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 125464000 # number of overall MSHR miss cycles 904system.cpu.l2cache.overall_mshr_miss_latency::total 350807750 # number of overall MSHR miss cycles 905system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.449407 # mshr miss rate for ReadReq accesses 906system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.926407 # mshr miss rate for ReadReq accesses 907system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.475961 # mshr miss rate for ReadReq accesses 908system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.994236 # mshr miss rate for UpgradeReq accesses 909system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.994236 # mshr miss rate for UpgradeReq accesses 910system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996749 # mshr miss rate for ReadExReq accesses 911system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996749 # mshr miss rate for ReadExReq accesses 912system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.449407 # mshr miss rate for demand accesses 913system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980500 # mshr miss rate for demand accesses 914system.cpu.l2cache.demand_mshr_miss_rate::total 0.557385 # mshr miss rate for demand accesses 915system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.449407 # mshr miss rate for overall accesses 916system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980500 # mshr miss rate for overall accesses 917system.cpu.l2cache.overall_mshr_miss_rate::total 0.557385 # mshr miss rate for overall accesses 918system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63981.757524 # average ReadReq mshr miss latency 919system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70390.771028 # average ReadReq mshr miss latency 920system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64676.202532 # average ReadReq mshr miss latency 921system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17715.489855 # average UpgradeReq mshr miss latency 922system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17715.489855 # average UpgradeReq mshr miss latency 923system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62189.660796 # average ReadExReq mshr miss latency 924system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62189.660796 # average ReadExReq mshr miss latency 925system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63981.757524 # average overall mshr miss latency 926system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63979.602244 # average overall mshr miss latency 927system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63980.986686 # average overall mshr miss latency 928system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63981.757524 # average overall mshr miss latency 929system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63979.602244 # average overall mshr miss latency 930system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63980.986686 # average overall mshr miss latency 931system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 932system.cpu.toL2Bus.trans_dist::ReadReq 8647 # Transaction distribution 933system.cpu.toL2Bus.trans_dist::ReadResp 8646 # Transaction distribution 934system.cpu.toL2Bus.trans_dist::Writeback 10 # Transaction distribution 935system.cpu.toL2Bus.trans_dist::UpgradeReq 347 # Transaction distribution 936system.cpu.toL2Bus.trans_dist::UpgradeResp 347 # Transaction distribution 937system.cpu.toL2Bus.trans_dist::ReadExReq 1538 # Transaction distribution 938system.cpu.toL2Bus.trans_dist::ReadExResp 1538 # Transaction distribution 939system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16021 # Packet count per connected master and slave (bytes) 940system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4704 # Packet count per connected master and slave (bytes) 941system.cpu.toL2Bus.pkt_count::total 20725 # Packet count per connected master and slave (bytes) 942system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 501504 # Cumulative packet size per connected master and slave (bytes) 943system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128640 # Cumulative packet size per connected master and slave (bytes) 944system.cpu.toL2Bus.pkt_size::total 630144 # Cumulative packet size per connected master and slave (bytes) 945system.cpu.toL2Bus.snoops 348 # Total snoops (count) 946system.cpu.toL2Bus.snoop_fanout::samples 10542 # Request fanout histogram 947system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram 948system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 949system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 950system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 951system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 952system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 953system.cpu.toL2Bus.snoop_fanout::3 10542 100.00% 100.00% # Request fanout histogram 954system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 955system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 956system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 957system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 958system.cpu.toL2Bus.snoop_fanout::total 10542 # Request fanout histogram 959system.cpu.toL2Bus.reqLayer0.occupancy 5281499 # Layer occupancy (ticks) 960system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 961system.cpu.toL2Bus.respLayer0.occupancy 12941000 # Layer occupancy (ticks) 962system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 963system.cpu.toL2Bus.respLayer1.occupancy 3566845 # Layer occupancy (ticks) 964system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 965system.membus.trans_dist::ReadReq 3949 # Transaction distribution 966system.membus.trans_dist::ReadResp 3949 # Transaction distribution 967system.membus.trans_dist::UpgradeReq 345 # Transaction distribution 968system.membus.trans_dist::UpgradeResp 345 # Transaction distribution 969system.membus.trans_dist::ReadExReq 1533 # Transaction distribution 970system.membus.trans_dist::ReadExResp 1533 # Transaction distribution 971system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11654 # Packet count per connected master and slave (bytes) 972system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11654 # Packet count per connected master and slave (bytes) 973system.membus.pkt_count::total 11654 # Packet count per connected master and slave (bytes) 974system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 350848 # Cumulative packet size per connected master and slave (bytes) 975system.membus.pkt_size_system.cpu.l2cache.mem_side::total 350848 # Cumulative packet size per connected master and slave (bytes) 976system.membus.pkt_size::total 350848 # Cumulative packet size per connected master and slave (bytes) 977system.membus.snoops 0 # Total snoops (count) 978system.membus.snoop_fanout::samples 5827 # Request fanout histogram 979system.membus.snoop_fanout::mean 0 # Request fanout histogram 980system.membus.snoop_fanout::stdev 0 # Request fanout histogram 981system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 982system.membus.snoop_fanout::0 5827 100.00% 100.00% # Request fanout histogram 983system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 984system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 985system.membus.snoop_fanout::min_value 0 # Request fanout histogram 986system.membus.snoop_fanout::max_value 0 # Request fanout histogram 987system.membus.snoop_fanout::total 5827 # Request fanout histogram 988system.membus.reqLayer0.occupancy 7212001 # Layer occupancy (ticks) 989system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 990system.membus.respLayer1.occupancy 29752405 # Layer occupancy (ticks) 991system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 992 993---------- End Simulation Statistics ----------	542system.cpu.rob.rob_reads 615300578 # The number of ROB reads 543system.cpu.rob.rob_writes 699132843 # The number of ROB writes 544system.cpu.timesIdled 3156 # Number of times that the entire CPU went into an idle state and unscheduled itself 545system.cpu.idleCycles 199760 # Total number of cycles that the CPU has spent unscheduled due to idling 546system.cpu.committedInsts 132071192 # Number of Instructions Simulated 547system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated 548system.cpu.cpi 2.251344 # CPI: Cycles Per Instruction 549system.cpu.cpi_total 2.251344 # CPI: Total CPI of All Threads 550system.cpu.ipc 0.444179 # IPC: Instructions Per Cycle 551system.cpu.ipc_total 0.444179 # IPC: Total IPC of All Threads 552system.cpu.int_regfile_reads 456486870 # number of integer regfile reads 553system.cpu.int_regfile_writes 239256029 # number of integer regfile writes 554system.cpu.fp_regfile_reads 3277423 # number of floating regfile reads 555system.cpu.fp_regfile_writes 2057707 # number of floating regfile writes 556system.cpu.cc_regfile_reads 102994410 # number of cc regfile reads 557system.cpu.cc_regfile_writes 60201710 # number of cc regfile writes 558system.cpu.misc_regfile_reads 136869897 # number of misc regfile reads 559system.cpu.misc_regfile_writes 1689 # number of misc regfile writes 560system.cpu.dcache.tags.replacements 51 # number of replacements 561system.cpu.dcache.tags.tagsinuse 1444.566400 # Cycle average of tags in use 562system.cpu.dcache.tags.total_refs 67084714 # Total number of references to valid blocks. 563system.cpu.dcache.tags.sampled_refs 2000 # Sample count of references to valid blocks. 564system.cpu.dcache.tags.avg_refs 33542.357000 # Average number of references to valid blocks. 565system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 566system.cpu.dcache.tags.occ_blocks::cpu.data 1444.566400 # Average occupied blocks per requestor 567system.cpu.dcache.tags.occ_percent::cpu.data 0.352677 # Average percentage of cache occupancy 568system.cpu.dcache.tags.occ_percent::total 0.352677 # Average percentage of cache occupancy 569system.cpu.dcache.tags.occ_task_id_blocks::1024 1949 # Occupied blocks per task id 570system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id 571system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id 572system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id 573system.cpu.dcache.tags.age_task_id_blocks_1024::3 432 # Occupied blocks per task id 574system.cpu.dcache.tags.age_task_id_blocks_1024::4 1405 # Occupied blocks per task id 575system.cpu.dcache.tags.occ_task_id_percent::1024 0.475830 # Percentage of cache occupancy per task id 576system.cpu.dcache.tags.tag_accesses 134176300 # Number of tag accesses 577system.cpu.dcache.tags.data_accesses 134176300 # Number of data accesses 578system.cpu.dcache.ReadReq_hits::cpu.data 46570369 # number of ReadReq hits 579system.cpu.dcache.ReadReq_hits::total 46570369 # number of ReadReq hits 580system.cpu.dcache.WriteReq_hits::cpu.data 20513845 # number of WriteReq hits 581system.cpu.dcache.WriteReq_hits::total 20513845 # number of WriteReq hits 582system.cpu.dcache.demand_hits::cpu.data 67084214 # number of demand (read+write) hits 583system.cpu.dcache.demand_hits::total 67084214 # number of demand (read+write) hits 584system.cpu.dcache.overall_hits::cpu.data 67084214 # number of overall hits 585system.cpu.dcache.overall_hits::total 67084214 # number of overall hits 586system.cpu.dcache.ReadReq_misses::cpu.data 1050 # number of ReadReq misses 587system.cpu.dcache.ReadReq_misses::total 1050 # number of ReadReq misses 588system.cpu.dcache.WriteReq_misses::cpu.data 1886 # number of WriteReq misses 589system.cpu.dcache.WriteReq_misses::total 1886 # number of WriteReq misses 590system.cpu.dcache.demand_misses::cpu.data 2936 # number of demand (read+write) misses 591system.cpu.dcache.demand_misses::total 2936 # number of demand (read+write) misses 592system.cpu.dcache.overall_misses::cpu.data 2936 # number of overall misses 593system.cpu.dcache.overall_misses::total 2936 # number of overall misses 594system.cpu.dcache.ReadReq_miss_latency::cpu.data 66068903 # number of ReadReq miss cycles 595system.cpu.dcache.ReadReq_miss_latency::total 66068903 # number of ReadReq miss cycles 596system.cpu.dcache.WriteReq_miss_latency::cpu.data 130813345 # number of WriteReq miss cycles 597system.cpu.dcache.WriteReq_miss_latency::total 130813345 # number of WriteReq miss cycles 598system.cpu.dcache.demand_miss_latency::cpu.data 196882248 # number of demand (read+write) miss cycles 599system.cpu.dcache.demand_miss_latency::total 196882248 # number of demand (read+write) miss cycles 600system.cpu.dcache.overall_miss_latency::cpu.data 196882248 # number of overall miss cycles 601system.cpu.dcache.overall_miss_latency::total 196882248 # number of overall miss cycles 602system.cpu.dcache.ReadReq_accesses::cpu.data 46571419 # number of ReadReq accesses(hits+misses) 603system.cpu.dcache.ReadReq_accesses::total 46571419 # number of ReadReq accesses(hits+misses) 604system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) 605system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) 606system.cpu.dcache.demand_accesses::cpu.data 67087150 # number of demand (read+write) accesses 607system.cpu.dcache.demand_accesses::total 67087150 # number of demand (read+write) accesses 608system.cpu.dcache.overall_accesses::cpu.data 67087150 # number of overall (read+write) accesses 609system.cpu.dcache.overall_accesses::total 67087150 # number of overall (read+write) accesses 610system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses 611system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses 612system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000092 # miss rate for WriteReq accesses 613system.cpu.dcache.WriteReq_miss_rate::total 0.000092 # miss rate for WriteReq accesses 614system.cpu.dcache.demand_miss_rate::cpu.data 0.000044 # miss rate for demand accesses 615system.cpu.dcache.demand_miss_rate::total 0.000044 # miss rate for demand accesses 616system.cpu.dcache.overall_miss_rate::cpu.data 0.000044 # miss rate for overall accesses 617system.cpu.dcache.overall_miss_rate::total 0.000044 # miss rate for overall accesses 618system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62922.764762 # average ReadReq miss latency 619system.cpu.dcache.ReadReq_avg_miss_latency::total 62922.764762 # average ReadReq miss latency 620system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69360.204136 # average WriteReq miss latency 621system.cpu.dcache.WriteReq_avg_miss_latency::total 69360.204136 # average WriteReq miss latency 622system.cpu.dcache.demand_avg_miss_latency::cpu.data 67057.986376 # average overall miss latency 623system.cpu.dcache.demand_avg_miss_latency::total 67057.986376 # average overall miss latency 624system.cpu.dcache.overall_avg_miss_latency::cpu.data 67057.986376 # average overall miss latency 625system.cpu.dcache.overall_avg_miss_latency::total 67057.986376 # average overall miss latency 626system.cpu.dcache.blocked_cycles::no_mshrs 241 # number of cycles access was blocked 627system.cpu.dcache.blocked_cycles::no_targets 39 # number of cycles access was blocked 628system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked 629system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked 630system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.200000 # average number of cycles each access was blocked 631system.cpu.dcache.avg_blocked_cycles::no_targets 19.500000 # average number of cycles each access was blocked 632system.cpu.dcache.fast_writes 0 # number of fast writes performed 633system.cpu.dcache.cache_copies 0 # number of cache copies performed 634system.cpu.dcache.writebacks::writebacks 10 # number of writebacks 635system.cpu.dcache.writebacks::total 10 # number of writebacks 636system.cpu.dcache.ReadReq_mshr_hits::cpu.data 588 # number of ReadReq MSHR hits 637system.cpu.dcache.ReadReq_mshr_hits::total 588 # number of ReadReq MSHR hits 638system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits 639system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits 640system.cpu.dcache.demand_mshr_hits::cpu.data 589 # number of demand (read+write) MSHR hits 641system.cpu.dcache.demand_mshr_hits::total 589 # number of demand (read+write) MSHR hits 642system.cpu.dcache.overall_mshr_hits::cpu.data 589 # number of overall MSHR hits 643system.cpu.dcache.overall_mshr_hits::total 589 # number of overall MSHR hits 644system.cpu.dcache.ReadReq_mshr_misses::cpu.data 462 # number of ReadReq MSHR misses 645system.cpu.dcache.ReadReq_mshr_misses::total 462 # number of ReadReq MSHR misses 646system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1885 # number of WriteReq MSHR misses 647system.cpu.dcache.WriteReq_mshr_misses::total 1885 # number of WriteReq MSHR misses 648system.cpu.dcache.demand_mshr_misses::cpu.data 2347 # number of demand (read+write) MSHR misses 649system.cpu.dcache.demand_mshr_misses::total 2347 # number of demand (read+write) MSHR misses 650system.cpu.dcache.overall_mshr_misses::cpu.data 2347 # number of overall MSHR misses 651system.cpu.dcache.overall_mshr_misses::total 2347 # number of overall MSHR misses 652system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36319250 # number of ReadReq MSHR miss cycles 653system.cpu.dcache.ReadReq_mshr_miss_latency::total 36319250 # number of ReadReq MSHR miss cycles 654system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127241905 # number of WriteReq MSHR miss cycles 655system.cpu.dcache.WriteReq_mshr_miss_latency::total 127241905 # number of WriteReq MSHR miss cycles 656system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163561155 # number of demand (read+write) MSHR miss cycles 657system.cpu.dcache.demand_mshr_miss_latency::total 163561155 # number of demand (read+write) MSHR miss cycles 658system.cpu.dcache.overall_mshr_miss_latency::cpu.data 163561155 # number of overall MSHR miss cycles 659system.cpu.dcache.overall_mshr_miss_latency::total 163561155 # number of overall MSHR miss cycles 660system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses 661system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses 662system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000092 # mshr miss rate for WriteReq accesses 663system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000092 # mshr miss rate for WriteReq accesses 664system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for demand accesses 665system.cpu.dcache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses 666system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for overall accesses 667system.cpu.dcache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses 668system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78613.095238 # average ReadReq mshr miss latency 669system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78613.095238 # average ReadReq mshr miss latency 670system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67502.336870 # average WriteReq mshr miss latency 671system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67502.336870 # average WriteReq mshr miss latency 672system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69689.456753 # average overall mshr miss latency 673system.cpu.dcache.demand_avg_mshr_miss_latency::total 69689.456753 # average overall mshr miss latency 674system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69689.456753 # average overall mshr miss latency 675system.cpu.dcache.overall_avg_mshr_miss_latency::total 69689.456753 # average overall mshr miss latency 676system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 677system.cpu.icache.tags.replacements 5861 # number of replacements 678system.cpu.icache.tags.tagsinuse 1662.434995 # Cycle average of tags in use 679system.cpu.icache.tags.total_refs 26645946 # Total number of references to valid blocks. 680system.cpu.icache.tags.sampled_refs 7838 # Sample count of references to valid blocks. 681system.cpu.icache.tags.avg_refs 3399.584843 # Average number of references to valid blocks. 682system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 683system.cpu.icache.tags.occ_blocks::cpu.inst 1662.434995 # Average occupied blocks per requestor 684system.cpu.icache.tags.occ_percent::cpu.inst 0.811736 # Average percentage of cache occupancy 685system.cpu.icache.tags.occ_percent::total 0.811736 # Average percentage of cache occupancy 686system.cpu.icache.tags.occ_task_id_blocks::1024 1977 # Occupied blocks per task id 687system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id 688system.cpu.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id 689system.cpu.icache.tags.age_task_id_blocks_1024::2 756 # Occupied blocks per task id 690system.cpu.icache.tags.age_task_id_blocks_1024::3 135 # Occupied blocks per task id 691system.cpu.icache.tags.age_task_id_blocks_1024::4 777 # Occupied blocks per task id 692system.cpu.icache.tags.occ_task_id_percent::1024 0.965332 # Percentage of cache occupancy per task id 693system.cpu.icache.tags.tag_accesses 53321296 # Number of tag accesses 694system.cpu.icache.tags.data_accesses 53321296 # Number of data accesses 695system.cpu.icache.ReadReq_hits::cpu.inst 26645946 # number of ReadReq hits 696system.cpu.icache.ReadReq_hits::total 26645946 # number of ReadReq hits 697system.cpu.icache.demand_hits::cpu.inst 26645946 # number of demand (read+write) hits 698system.cpu.icache.demand_hits::total 26645946 # number of demand (read+write) hits 699system.cpu.icache.overall_hits::cpu.inst 26645946 # number of overall hits 700system.cpu.icache.overall_hits::total 26645946 # number of overall hits 701system.cpu.icache.ReadReq_misses::cpu.inst 10610 # number of ReadReq misses 702system.cpu.icache.ReadReq_misses::total 10610 # number of ReadReq misses 703system.cpu.icache.demand_misses::cpu.inst 10610 # number of demand (read+write) misses 704system.cpu.icache.demand_misses::total 10610 # number of demand (read+write) misses 705system.cpu.icache.overall_misses::cpu.inst 10610 # number of overall misses 706system.cpu.icache.overall_misses::total 10610 # number of overall misses 707system.cpu.icache.ReadReq_miss_latency::cpu.inst 431026999 # number of ReadReq miss cycles 708system.cpu.icache.ReadReq_miss_latency::total 431026999 # number of ReadReq miss cycles 709system.cpu.icache.demand_miss_latency::cpu.inst 431026999 # number of demand (read+write) miss cycles 710system.cpu.icache.demand_miss_latency::total 431026999 # number of demand (read+write) miss cycles 711system.cpu.icache.overall_miss_latency::cpu.inst 431026999 # number of overall miss cycles 712system.cpu.icache.overall_miss_latency::total 431026999 # number of overall miss cycles 713system.cpu.icache.ReadReq_accesses::cpu.inst 26656556 # number of ReadReq accesses(hits+misses) 714system.cpu.icache.ReadReq_accesses::total 26656556 # number of ReadReq accesses(hits+misses) 715system.cpu.icache.demand_accesses::cpu.inst 26656556 # number of demand (read+write) accesses 716system.cpu.icache.demand_accesses::total 26656556 # number of demand (read+write) accesses 717system.cpu.icache.overall_accesses::cpu.inst 26656556 # number of overall (read+write) accesses 718system.cpu.icache.overall_accesses::total 26656556 # number of overall (read+write) accesses 719system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000398 # miss rate for ReadReq accesses 720system.cpu.icache.ReadReq_miss_rate::total 0.000398 # miss rate for ReadReq accesses 721system.cpu.icache.demand_miss_rate::cpu.inst 0.000398 # miss rate for demand accesses 722system.cpu.icache.demand_miss_rate::total 0.000398 # miss rate for demand accesses 723system.cpu.icache.overall_miss_rate::cpu.inst 0.000398 # miss rate for overall accesses 724system.cpu.icache.overall_miss_rate::total 0.000398 # miss rate for overall accesses 725system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40624.599340 # average ReadReq miss latency 726system.cpu.icache.ReadReq_avg_miss_latency::total 40624.599340 # average ReadReq miss latency 727system.cpu.icache.demand_avg_miss_latency::cpu.inst 40624.599340 # average overall miss latency 728system.cpu.icache.demand_avg_miss_latency::total 40624.599340 # average overall miss latency 729system.cpu.icache.overall_avg_miss_latency::cpu.inst 40624.599340 # average overall miss latency 730system.cpu.icache.overall_avg_miss_latency::total 40624.599340 # average overall miss latency 731system.cpu.icache.blocked_cycles::no_mshrs 1664 # number of cycles access was blocked 732system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 733system.cpu.icache.blocked::no_mshrs 27 # number of cycles access was blocked 734system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 735system.cpu.icache.avg_blocked_cycles::no_mshrs 61.629630 # average number of cycles each access was blocked 736system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 737system.cpu.icache.fast_writes 0 # number of fast writes performed 738system.cpu.icache.cache_copies 0 # number of cache copies performed 739system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2425 # number of ReadReq MSHR hits 740system.cpu.icache.ReadReq_mshr_hits::total 2425 # number of ReadReq MSHR hits 741system.cpu.icache.demand_mshr_hits::cpu.inst 2425 # number of demand (read+write) MSHR hits 742system.cpu.icache.demand_mshr_hits::total 2425 # number of demand (read+write) MSHR hits 743system.cpu.icache.overall_mshr_hits::cpu.inst 2425 # number of overall MSHR hits 744system.cpu.icache.overall_mshr_hits::total 2425 # number of overall MSHR hits 745system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8185 # number of ReadReq MSHR misses 746system.cpu.icache.ReadReq_mshr_misses::total 8185 # number of ReadReq MSHR misses 747system.cpu.icache.demand_mshr_misses::cpu.inst 8185 # number of demand (read+write) MSHR misses 748system.cpu.icache.demand_mshr_misses::total 8185 # number of demand (read+write) MSHR misses 749system.cpu.icache.overall_mshr_misses::cpu.inst 8185 # number of overall MSHR misses 750system.cpu.icache.overall_mshr_misses::total 8185 # number of overall MSHR misses 751system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 323320999 # number of ReadReq MSHR miss cycles 752system.cpu.icache.ReadReq_mshr_miss_latency::total 323320999 # number of ReadReq MSHR miss cycles 753system.cpu.icache.demand_mshr_miss_latency::cpu.inst 323320999 # number of demand (read+write) MSHR miss cycles 754system.cpu.icache.demand_mshr_miss_latency::total 323320999 # number of demand (read+write) MSHR miss cycles 755system.cpu.icache.overall_mshr_miss_latency::cpu.inst 323320999 # number of overall MSHR miss cycles 756system.cpu.icache.overall_mshr_miss_latency::total 323320999 # number of overall MSHR miss cycles 757system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for ReadReq accesses 758system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000307 # mshr miss rate for ReadReq accesses 759system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for demand accesses 760system.cpu.icache.demand_mshr_miss_rate::total 0.000307 # mshr miss rate for demand accesses 761system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for overall accesses 762system.cpu.icache.overall_mshr_miss_rate::total 0.000307 # mshr miss rate for overall accesses 763system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39501.649236 # average ReadReq mshr miss latency 764system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39501.649236 # average ReadReq mshr miss latency 765system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39501.649236 # average overall mshr miss latency 766system.cpu.icache.demand_avg_mshr_miss_latency::total 39501.649236 # average overall mshr miss latency 767system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39501.649236 # average overall mshr miss latency 768system.cpu.icache.overall_avg_mshr_miss_latency::total 39501.649236 # average overall mshr miss latency 769system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 770system.cpu.l2cache.tags.replacements 0 # number of replacements 771system.cpu.l2cache.tags.tagsinuse 2641.798011 # Cycle average of tags in use 772system.cpu.l2cache.tags.total_refs 4354 # Total number of references to valid blocks. 773system.cpu.l2cache.tags.sampled_refs 3951 # Sample count of references to valid blocks. 774system.cpu.l2cache.tags.avg_refs 1.101999 # Average number of references to valid blocks. 775system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 776system.cpu.l2cache.tags.occ_blocks::writebacks 1.181969 # Average occupied blocks per requestor 777system.cpu.l2cache.tags.occ_blocks::cpu.inst 2328.091219 # Average occupied blocks per requestor 778system.cpu.l2cache.tags.occ_blocks::cpu.data 312.524822 # Average occupied blocks per requestor 779system.cpu.l2cache.tags.occ_percent::writebacks 0.000036 # Average percentage of cache occupancy 780system.cpu.l2cache.tags.occ_percent::cpu.inst 0.071048 # Average percentage of cache occupancy 781system.cpu.l2cache.tags.occ_percent::cpu.data 0.009538 # Average percentage of cache occupancy 782system.cpu.l2cache.tags.occ_percent::total 0.080621 # Average percentage of cache occupancy 783system.cpu.l2cache.tags.occ_task_id_blocks::1024 3951 # Occupied blocks per task id 784system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 785system.cpu.l2cache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id 786system.cpu.l2cache.tags.age_task_id_blocks_1024::2 894 # Occupied blocks per task id 787system.cpu.l2cache.tags.age_task_id_blocks_1024::3 157 # Occupied blocks per task id 788system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2664 # Occupied blocks per task id 789system.cpu.l2cache.tags.occ_task_id_percent::1024 0.120575 # Percentage of cache occupancy per task id 790system.cpu.l2cache.tags.tag_accesses 87043 # Number of tag accesses 791system.cpu.l2cache.tags.data_accesses 87043 # Number of data accesses 792system.cpu.l2cache.ReadReq_hits::cpu.inst 4315 # number of ReadReq hits 793system.cpu.l2cache.ReadReq_hits::cpu.data 34 # number of ReadReq hits 794system.cpu.l2cache.ReadReq_hits::total 4349 # number of ReadReq hits 795system.cpu.l2cache.Writeback_hits::writebacks 10 # number of Writeback hits 796system.cpu.l2cache.Writeback_hits::total 10 # number of Writeback hits 797system.cpu.l2cache.UpgradeReq_hits::cpu.data 2 # number of UpgradeReq hits 798system.cpu.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits 799system.cpu.l2cache.ReadExReq_hits::cpu.data 5 # number of ReadExReq hits 800system.cpu.l2cache.ReadExReq_hits::total 5 # number of ReadExReq hits 801system.cpu.l2cache.demand_hits::cpu.inst 4315 # number of demand (read+write) hits 802system.cpu.l2cache.demand_hits::cpu.data 39 # number of demand (read+write) hits 803system.cpu.l2cache.demand_hits::total 4354 # number of demand (read+write) hits 804system.cpu.l2cache.overall_hits::cpu.inst 4315 # number of overall hits 805system.cpu.l2cache.overall_hits::cpu.data 39 # number of overall hits 806system.cpu.l2cache.overall_hits::total 4354 # number of overall hits 807system.cpu.l2cache.ReadReq_misses::cpu.inst 3522 # number of ReadReq misses 808system.cpu.l2cache.ReadReq_misses::cpu.data 428 # number of ReadReq misses 809system.cpu.l2cache.ReadReq_misses::total 3950 # number of ReadReq misses 810system.cpu.l2cache.UpgradeReq_misses::cpu.data 345 # number of UpgradeReq misses 811system.cpu.l2cache.UpgradeReq_misses::total 345 # number of UpgradeReq misses 812system.cpu.l2cache.ReadExReq_misses::cpu.data 1533 # number of ReadExReq misses 813system.cpu.l2cache.ReadExReq_misses::total 1533 # number of ReadExReq misses 814system.cpu.l2cache.demand_misses::cpu.inst 3522 # number of demand (read+write) misses 815system.cpu.l2cache.demand_misses::cpu.data 1961 # number of demand (read+write) misses 816system.cpu.l2cache.demand_misses::total 5483 # number of demand (read+write) misses 817system.cpu.l2cache.overall_misses::cpu.inst 3522 # number of overall misses 818system.cpu.l2cache.overall_misses::cpu.data 1961 # number of overall misses 819system.cpu.l2cache.overall_misses::total 5483 # number of overall misses 820system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 269302250 # number of ReadReq miss cycles 821system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35486250 # number of ReadReq miss cycles 822system.cpu.l2cache.ReadReq_miss_latency::total 304788500 # number of ReadReq miss cycles 823system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 114514250 # number of ReadExReq miss cycles 824system.cpu.l2cache.ReadExReq_miss_latency::total 114514250 # number of ReadExReq miss cycles 825system.cpu.l2cache.demand_miss_latency::cpu.inst 269302250 # number of demand (read+write) miss cycles 826system.cpu.l2cache.demand_miss_latency::cpu.data 150000500 # number of demand (read+write) miss cycles 827system.cpu.l2cache.demand_miss_latency::total 419302750 # number of demand (read+write) miss cycles 828system.cpu.l2cache.overall_miss_latency::cpu.inst 269302250 # number of overall miss cycles 829system.cpu.l2cache.overall_miss_latency::cpu.data 150000500 # number of overall miss cycles 830system.cpu.l2cache.overall_miss_latency::total 419302750 # number of overall miss cycles 831system.cpu.l2cache.ReadReq_accesses::cpu.inst 7837 # number of ReadReq accesses(hits+misses) 832system.cpu.l2cache.ReadReq_accesses::cpu.data 462 # number of ReadReq accesses(hits+misses) 833system.cpu.l2cache.ReadReq_accesses::total 8299 # number of ReadReq accesses(hits+misses) 834system.cpu.l2cache.Writeback_accesses::writebacks 10 # number of Writeback accesses(hits+misses) 835system.cpu.l2cache.Writeback_accesses::total 10 # number of Writeback accesses(hits+misses) 836system.cpu.l2cache.UpgradeReq_accesses::cpu.data 347 # number of UpgradeReq accesses(hits+misses) 837system.cpu.l2cache.UpgradeReq_accesses::total 347 # number of UpgradeReq accesses(hits+misses) 838system.cpu.l2cache.ReadExReq_accesses::cpu.data 1538 # number of ReadExReq accesses(hits+misses) 839system.cpu.l2cache.ReadExReq_accesses::total 1538 # number of ReadExReq accesses(hits+misses) 840system.cpu.l2cache.demand_accesses::cpu.inst 7837 # number of demand (read+write) accesses 841system.cpu.l2cache.demand_accesses::cpu.data 2000 # number of demand (read+write) accesses 842system.cpu.l2cache.demand_accesses::total 9837 # number of demand (read+write) accesses 843system.cpu.l2cache.overall_accesses::cpu.inst 7837 # number of overall (read+write) accesses 844system.cpu.l2cache.overall_accesses::cpu.data 2000 # number of overall (read+write) accesses 845system.cpu.l2cache.overall_accesses::total 9837 # number of overall (read+write) accesses 846system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.449407 # miss rate for ReadReq accesses 847system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.926407 # miss rate for ReadReq accesses 848system.cpu.l2cache.ReadReq_miss_rate::total 0.475961 # miss rate for ReadReq accesses 849system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.994236 # miss rate for UpgradeReq accesses 850system.cpu.l2cache.UpgradeReq_miss_rate::total 0.994236 # miss rate for UpgradeReq accesses 851system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996749 # miss rate for ReadExReq accesses 852system.cpu.l2cache.ReadExReq_miss_rate::total 0.996749 # miss rate for ReadExReq accesses 853system.cpu.l2cache.demand_miss_rate::cpu.inst 0.449407 # miss rate for demand accesses 854system.cpu.l2cache.demand_miss_rate::cpu.data 0.980500 # miss rate for demand accesses 855system.cpu.l2cache.demand_miss_rate::total 0.557385 # miss rate for demand accesses 856system.cpu.l2cache.overall_miss_rate::cpu.inst 0.449407 # miss rate for overall accesses 857system.cpu.l2cache.overall_miss_rate::cpu.data 0.980500 # miss rate for overall accesses 858system.cpu.l2cache.overall_miss_rate::total 0.557385 # miss rate for overall accesses 859system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76462.876207 # average ReadReq miss latency 860system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82911.799065 # average ReadReq miss latency 861system.cpu.l2cache.ReadReq_avg_miss_latency::total 77161.645570 # average ReadReq miss latency 862system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74699.445532 # average ReadExReq miss latency 863system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74699.445532 # average ReadExReq miss latency 864system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76462.876207 # average overall miss latency 865system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76491.840898 # average overall miss latency 866system.cpu.l2cache.demand_avg_miss_latency::total 76473.235455 # average overall miss latency 867system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76462.876207 # average overall miss latency 868system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76491.840898 # average overall miss latency 869system.cpu.l2cache.overall_avg_miss_latency::total 76473.235455 # average overall miss latency 870system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 871system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 872system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 873system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 874system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 875system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 876system.cpu.l2cache.fast_writes 0 # number of fast writes performed 877system.cpu.l2cache.cache_copies 0 # number of cache copies performed 878system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3522 # number of ReadReq MSHR misses 879system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 428 # number of ReadReq MSHR misses 880system.cpu.l2cache.ReadReq_mshr_misses::total 3950 # number of ReadReq MSHR misses 881system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 345 # number of UpgradeReq MSHR misses 882system.cpu.l2cache.UpgradeReq_mshr_misses::total 345 # number of UpgradeReq MSHR misses 883system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1533 # number of ReadExReq MSHR misses 884system.cpu.l2cache.ReadExReq_mshr_misses::total 1533 # number of ReadExReq MSHR misses 885system.cpu.l2cache.demand_mshr_misses::cpu.inst 3522 # number of demand (read+write) MSHR misses 886system.cpu.l2cache.demand_mshr_misses::cpu.data 1961 # number of demand (read+write) MSHR misses 887system.cpu.l2cache.demand_mshr_misses::total 5483 # number of demand (read+write) MSHR misses 888system.cpu.l2cache.overall_mshr_misses::cpu.inst 3522 # number of overall MSHR misses 889system.cpu.l2cache.overall_mshr_misses::cpu.data 1961 # number of overall MSHR misses 890system.cpu.l2cache.overall_mshr_misses::total 5483 # number of overall MSHR misses 891system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 225343750 # number of ReadReq MSHR miss cycles 892system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30127250 # number of ReadReq MSHR miss cycles 893system.cpu.l2cache.ReadReq_mshr_miss_latency::total 255471000 # number of ReadReq MSHR miss cycles 894system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6111844 # number of UpgradeReq MSHR miss cycles 895system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6111844 # number of UpgradeReq MSHR miss cycles 896system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 95336750 # number of ReadExReq MSHR miss cycles 897system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95336750 # number of ReadExReq MSHR miss cycles 898system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 225343750 # number of demand (read+write) MSHR miss cycles 899system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 125464000 # number of demand (read+write) MSHR miss cycles 900system.cpu.l2cache.demand_mshr_miss_latency::total 350807750 # number of demand (read+write) MSHR miss cycles 901system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 225343750 # number of overall MSHR miss cycles 902system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 125464000 # number of overall MSHR miss cycles 903system.cpu.l2cache.overall_mshr_miss_latency::total 350807750 # number of overall MSHR miss cycles 904system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.449407 # mshr miss rate for ReadReq accesses 905system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.926407 # mshr miss rate for ReadReq accesses 906system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.475961 # mshr miss rate for ReadReq accesses 907system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.994236 # mshr miss rate for UpgradeReq accesses 908system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.994236 # mshr miss rate for UpgradeReq accesses 909system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996749 # mshr miss rate for ReadExReq accesses 910system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996749 # mshr miss rate for ReadExReq accesses 911system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.449407 # mshr miss rate for demand accesses 912system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980500 # mshr miss rate for demand accesses 913system.cpu.l2cache.demand_mshr_miss_rate::total 0.557385 # mshr miss rate for demand accesses 914system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.449407 # mshr miss rate for overall accesses 915system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980500 # mshr miss rate for overall accesses 916system.cpu.l2cache.overall_mshr_miss_rate::total 0.557385 # mshr miss rate for overall accesses 917system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63981.757524 # average ReadReq mshr miss latency 918system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70390.771028 # average ReadReq mshr miss latency 919system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64676.202532 # average ReadReq mshr miss latency 920system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17715.489855 # average UpgradeReq mshr miss latency 921system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17715.489855 # average UpgradeReq mshr miss latency 922system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62189.660796 # average ReadExReq mshr miss latency 923system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62189.660796 # average ReadExReq mshr miss latency 924system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63981.757524 # average overall mshr miss latency 925system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63979.602244 # average overall mshr miss latency 926system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63980.986686 # average overall mshr miss latency 927system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63981.757524 # average overall mshr miss latency 928system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63979.602244 # average overall mshr miss latency 929system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63980.986686 # average overall mshr miss latency 930system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 931system.cpu.toL2Bus.trans_dist::ReadReq 8647 # Transaction distribution 932system.cpu.toL2Bus.trans_dist::ReadResp 8646 # Transaction distribution 933system.cpu.toL2Bus.trans_dist::Writeback 10 # Transaction distribution 934system.cpu.toL2Bus.trans_dist::UpgradeReq 347 # Transaction distribution 935system.cpu.toL2Bus.trans_dist::UpgradeResp 347 # Transaction distribution 936system.cpu.toL2Bus.trans_dist::ReadExReq 1538 # Transaction distribution 937system.cpu.toL2Bus.trans_dist::ReadExResp 1538 # Transaction distribution 938system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16021 # Packet count per connected master and slave (bytes) 939system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4704 # Packet count per connected master and slave (bytes) 940system.cpu.toL2Bus.pkt_count::total 20725 # Packet count per connected master and slave (bytes) 941system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 501504 # Cumulative packet size per connected master and slave (bytes) 942system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128640 # Cumulative packet size per connected master and slave (bytes) 943system.cpu.toL2Bus.pkt_size::total 630144 # Cumulative packet size per connected master and slave (bytes) 944system.cpu.toL2Bus.snoops 348 # Total snoops (count) 945system.cpu.toL2Bus.snoop_fanout::samples 10542 # Request fanout histogram 946system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram 947system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 948system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 949system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 950system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 951system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 952system.cpu.toL2Bus.snoop_fanout::3 10542 100.00% 100.00% # Request fanout histogram 953system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 954system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 955system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 956system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 957system.cpu.toL2Bus.snoop_fanout::total 10542 # Request fanout histogram 958system.cpu.toL2Bus.reqLayer0.occupancy 5281499 # Layer occupancy (ticks) 959system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 960system.cpu.toL2Bus.respLayer0.occupancy 12941000 # Layer occupancy (ticks) 961system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 962system.cpu.toL2Bus.respLayer1.occupancy 3566845 # Layer occupancy (ticks) 963system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 964system.membus.trans_dist::ReadReq 3949 # Transaction distribution 965system.membus.trans_dist::ReadResp 3949 # Transaction distribution 966system.membus.trans_dist::UpgradeReq 345 # Transaction distribution 967system.membus.trans_dist::UpgradeResp 345 # Transaction distribution 968system.membus.trans_dist::ReadExReq 1533 # Transaction distribution 969system.membus.trans_dist::ReadExResp 1533 # Transaction distribution 970system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11654 # Packet count per connected master and slave (bytes) 971system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11654 # Packet count per connected master and slave (bytes) 972system.membus.pkt_count::total 11654 # Packet count per connected master and slave (bytes) 973system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 350848 # Cumulative packet size per connected master and slave (bytes) 974system.membus.pkt_size_system.cpu.l2cache.mem_side::total 350848 # Cumulative packet size per connected master and slave (bytes) 975system.membus.pkt_size::total 350848 # Cumulative packet size per connected master and slave (bytes) 976system.membus.snoops 0 # Total snoops (count) 977system.membus.snoop_fanout::samples 5827 # Request fanout histogram 978system.membus.snoop_fanout::mean 0 # Request fanout histogram 979system.membus.snoop_fanout::stdev 0 # Request fanout histogram 980system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 981system.membus.snoop_fanout::0 5827 100.00% 100.00% # Request fanout histogram 982system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 983system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 984system.membus.snoop_fanout::min_value 0 # Request fanout histogram 985system.membus.snoop_fanout::max_value 0 # Request fanout histogram 986system.membus.snoop_fanout::total 5827 # Request fanout histogram 987system.membus.reqLayer0.occupancy 7212001 # Layer occupancy (ticks) 988system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 989system.membus.respLayer1.occupancy 29752405 # Layer occupancy (ticks) 990system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 991 992---------- End Simulation Statistics ----------