1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.144471 # Number of seconds simulated
4sim_ticks 144470654000 # Number of ticks simulated
5final_tick 144470654000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 75912 # Simulator instruction rate (inst/s)
8host_op_rate 127236 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 83039301 # Simulator tick rate (ticks/s)
10host_mem_usage 277792 # Number of bytes of host memory used
11host_seconds 1739.79 # Real time elapsed on the host
12sim_insts 132071192 # Number of instructions simulated
13sim_ops 221362962 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 216768 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 124992 # Number of bytes read from this memory
16system.physmem.bytes_read::total 341760 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 216768 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 216768 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 3387 # Number of read requests responded to by this memory
20system.physmem.num_reads::cpu.data 1953 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 5340 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 1500429 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 865172 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 2365602 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 1500429 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 1500429 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 1500429 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 865172 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 2365602 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.readReqs 5340 # Total number of read requests accepted by DRAM controller
31system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
32system.physmem.readBursts 5340 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
33system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
34system.physmem.bytesRead 341760 # Total number of bytes read from memory
35system.physmem.bytesWritten 0 # Total number of bytes written to memory
36system.physmem.bytesConsumedRd 341760 # bytesRead derated as per pkt->getSize()
37system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
38system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
39system.physmem.neitherReadNorWrite 152 # Reqs where no action is needed
40system.physmem.perBankRdReqs::0 286 # Track reads on a per bank basis
41system.physmem.perBankRdReqs::1 358 # Track reads on a per bank basis
42system.physmem.perBankRdReqs::2 449 # Track reads on a per bank basis
43system.physmem.perBankRdReqs::3 359 # Track reads on a per bank basis
44system.physmem.perBankRdReqs::4 325 # Track reads on a per bank basis
45system.physmem.perBankRdReqs::5 326 # Track reads on a per bank basis
46system.physmem.perBankRdReqs::6 398 # Track reads on a per bank basis
47system.physmem.perBankRdReqs::7 381 # Track reads on a per bank basis
48system.physmem.perBankRdReqs::8 337 # Track reads on a per bank basis
49system.physmem.perBankRdReqs::9 280 # Track reads on a per bank basis
50system.physmem.perBankRdReqs::10 229 # Track reads on a per bank basis
51system.physmem.perBankRdReqs::11 276 # Track reads on a per bank basis
52system.physmem.perBankRdReqs::12 207 # Track reads on a per bank basis
53system.physmem.perBankRdReqs::13 464 # Track reads on a per bank basis
54system.physmem.perBankRdReqs::14 383 # Track reads on a per bank basis
55system.physmem.perBankRdReqs::15 282 # Track reads on a per bank basis
56system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
57system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
58system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
59system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
60system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
61system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
62system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
63system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
64system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
65system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
66system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
67system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
68system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
69system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
70system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
71system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
72system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
73system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
74system.physmem.totGap 144470612000 # Total gap between requests
75system.physmem.readPktSize::0 0 # Categorize read packet sizes
76system.physmem.readPktSize::1 0 # Categorize read packet sizes
77system.physmem.readPktSize::2 0 # Categorize read packet sizes
78system.physmem.readPktSize::3 0 # Categorize read packet sizes
79system.physmem.readPktSize::4 0 # Categorize read packet sizes
80system.physmem.readPktSize::5 0 # Categorize read packet sizes
81system.physmem.readPktSize::6 5340 # Categorize read packet sizes
82system.physmem.writePktSize::0 0 # Categorize write packet sizes
83system.physmem.writePktSize::1 0 # Categorize write packet sizes
84system.physmem.writePktSize::2 0 # Categorize write packet sizes
85system.physmem.writePktSize::3 0 # Categorize write packet sizes
86system.physmem.writePktSize::4 0 # Categorize write packet sizes
87system.physmem.writePktSize::5 0 # Categorize write packet sizes
88system.physmem.writePktSize::6 0 # Categorize write packet sizes
89system.physmem.rdQLenPdf::0 4308 # What read queue length does an incoming req see
90system.physmem.rdQLenPdf::1 868 # What read queue length does an incoming req see
91system.physmem.rdQLenPdf::2 144 # What read queue length does an incoming req see
92system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see
93system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see

--- 44 unchanged lines hidden (view full) ---

145system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
153system.physmem.bytesPerActivate::samples 508 # Bytes accessed per row activation
154system.physmem.bytesPerActivate::mean 662.047244 # Bytes accessed per row activation
155system.physmem.bytesPerActivate::gmean 229.931754 # Bytes accessed per row activation
156system.physmem.bytesPerActivate::stdev 1294.319008 # Bytes accessed per row activation
157system.physmem.bytesPerActivate::64-65 181 35.63% 35.63% # Bytes accessed per row activation
158system.physmem.bytesPerActivate::128-129 78 15.35% 50.98% # Bytes accessed per row activation
159system.physmem.bytesPerActivate::192-193 41 8.07% 59.06% # Bytes accessed per row activation
160system.physmem.bytesPerActivate::256-257 18 3.54% 62.60% # Bytes accessed per row activation
161system.physmem.bytesPerActivate::320-321 27 5.31% 67.91% # Bytes accessed per row activation
162system.physmem.bytesPerActivate::384-385 9 1.77% 69.69% # Bytes accessed per row activation
163system.physmem.bytesPerActivate::448-449 15 2.95% 72.64% # Bytes accessed per row activation
164system.physmem.bytesPerActivate::512-513 11 2.17% 74.80% # Bytes accessed per row activation
165system.physmem.bytesPerActivate::576-577 9 1.77% 76.57% # Bytes accessed per row activation
166system.physmem.bytesPerActivate::640-641 6 1.18% 77.76% # Bytes accessed per row activation
167system.physmem.bytesPerActivate::704-705 4 0.79% 78.54% # Bytes accessed per row activation
168system.physmem.bytesPerActivate::768-769 6 1.18% 79.72% # Bytes accessed per row activation
169system.physmem.bytesPerActivate::832-833 5 0.98% 80.71% # Bytes accessed per row activation
170system.physmem.bytesPerActivate::896-897 4 0.79% 81.50% # Bytes accessed per row activation
171system.physmem.bytesPerActivate::960-961 6 1.18% 82.68% # Bytes accessed per row activation
172system.physmem.bytesPerActivate::1024-1025 5 0.98% 83.66% # Bytes accessed per row activation
173system.physmem.bytesPerActivate::1088-1089 3 0.59% 84.25% # Bytes accessed per row activation
174system.physmem.bytesPerActivate::1152-1153 3 0.59% 84.84% # Bytes accessed per row activation
175system.physmem.bytesPerActivate::1216-1217 4 0.79% 85.63% # Bytes accessed per row activation
176system.physmem.bytesPerActivate::1280-1281 1 0.20% 85.83% # Bytes accessed per row activation
177system.physmem.bytesPerActivate::1344-1345 4 0.79% 86.61% # Bytes accessed per row activation
178system.physmem.bytesPerActivate::1408-1409 4 0.79% 87.40% # Bytes accessed per row activation
179system.physmem.bytesPerActivate::1472-1473 3 0.59% 87.99% # Bytes accessed per row activation
180system.physmem.bytesPerActivate::1536-1537 1 0.20% 88.19% # Bytes accessed per row activation
181system.physmem.bytesPerActivate::1600-1601 3 0.59% 88.78% # Bytes accessed per row activation
182system.physmem.bytesPerActivate::1728-1729 1 0.20% 88.98% # Bytes accessed per row activation
183system.physmem.bytesPerActivate::1856-1857 2 0.39% 89.37% # Bytes accessed per row activation
184system.physmem.bytesPerActivate::1920-1921 6 1.18% 90.55% # Bytes accessed per row activation
185system.physmem.bytesPerActivate::1984-1985 1 0.20% 90.75% # Bytes accessed per row activation
186system.physmem.bytesPerActivate::2048-2049 1 0.20% 90.94% # Bytes accessed per row activation
187system.physmem.bytesPerActivate::2112-2113 1 0.20% 91.14% # Bytes accessed per row activation
188system.physmem.bytesPerActivate::2176-2177 1 0.20% 91.34% # Bytes accessed per row activation
189system.physmem.bytesPerActivate::2240-2241 3 0.59% 91.93% # Bytes accessed per row activation
190system.physmem.bytesPerActivate::2304-2305 2 0.39% 92.32% # Bytes accessed per row activation
191system.physmem.bytesPerActivate::2432-2433 3 0.59% 92.91% # Bytes accessed per row activation
192system.physmem.bytesPerActivate::2496-2497 1 0.20% 93.11% # Bytes accessed per row activation
193system.physmem.bytesPerActivate::2624-2625 2 0.39% 93.50% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::2688-2689 1 0.20% 93.70% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::2816-2817 4 0.79% 94.49% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::2880-2881 3 0.59% 95.08% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::3200-3201 1 0.20% 95.28% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::3392-3393 2 0.39% 95.67% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::3456-3457 1 0.20% 95.87% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::3520-3521 2 0.39% 96.26% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::3584-3585 1 0.20% 96.46% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::3648-3649 1 0.20% 96.65% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::4096-4097 1 0.20% 96.85% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::4160-4161 1 0.20% 97.05% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::4288-4289 2 0.39% 97.44% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::4480-4481 1 0.20% 97.64% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::4672-4673 1 0.20% 97.83% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::5312-5313 1 0.20% 98.03% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::5888-5889 1 0.20% 98.23% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::6400-6401 1 0.20% 98.43% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::6592-6593 1 0.20% 98.62% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::6912-6913 1 0.20% 98.82% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::8128-8129 1 0.20% 99.02% # Bytes accessed per row activation
214system.physmem.bytesPerActivate::8192-8193 5 0.98% 100.00% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::total 508 # Bytes accessed per row activation
216system.physmem.totQLat 12730250 # Total cycles spent in queuing delays
217system.physmem.totMemAccLat 118864000 # Sum of mem lat for all requests
218system.physmem.totBusLat 26700000 # Total cycles spent in databus access
219system.physmem.totBankLat 79433750 # Total cycles spent in bank access
220system.physmem.avgQLat 2383.94 # Average queueing delay per request
221system.physmem.avgBankLat 14875.23 # Average bank access latency per request
222system.physmem.avgBusLat 5000.00 # Average bus latency per request
223system.physmem.avgMemAccLat 22259.18 # Average memory access latency
224system.physmem.avgRdBW 2.37 # Average achieved read bandwidth in MB/s
225system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
226system.physmem.avgConsumedRdBW 2.37 # Average consumed read bandwidth in MB/s
227system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
228system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
229system.physmem.busUtil 0.02 # Data bus utilization in percentage
230system.physmem.avgRdQLen 0.00 # Average read queue length over time
231system.physmem.avgWrQLen 0.00 # Average write queue length over time
232system.physmem.readRowHits 4832 # Number of row buffer hits during reads
233system.physmem.writeRowHits 0 # Number of row buffer hits during writes
234system.physmem.readRowHitRate 90.49 # Row buffer hit rate for reads
235system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
236system.physmem.avgGap 27054421.72 # Average gap between requests
237system.membus.throughput 2365159 # Throughput (bytes/s)
238system.membus.trans_dist::ReadReq 3810 # Transaction distribution
239system.membus.trans_dist::ReadResp 3809 # Transaction distribution
240system.membus.trans_dist::UpgradeReq 152 # Transaction distribution
241system.membus.trans_dist::UpgradeResp 152 # Transaction distribution
242system.membus.trans_dist::ReadExReq 1530 # Transaction distribution
243system.membus.trans_dist::ReadExResp 1530 # Transaction distribution
244system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10983 # Packet count per connected master and slave (bytes)
245system.membus.pkt_count_system.cpu.l2cache.mem_side::total 10983 # Packet count per connected master and slave (bytes)
246system.membus.pkt_count::total 10983 # Packet count per connected master and slave (bytes)
247system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 341696 # Cumulative packet size per connected master and slave (bytes)
248system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 341696 # Cumulative packet size per connected master and slave (bytes)
249system.membus.tot_pkt_size::total 341696 # Cumulative packet size per connected master and slave (bytes)
250system.membus.data_through_bus 341696 # Total data (bytes)
251system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
252system.membus.reqLayer0.occupancy 6922500 # Layer occupancy (ticks)
253system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
254system.membus.respLayer1.occupancy 50657098 # Layer occupancy (ticks)
255system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
256system.cpu.branchPred.lookups 18662810 # Number of BP lookups
257system.cpu.branchPred.condPredicted 18662810 # Number of conditional branches predicted
258system.cpu.branchPred.condIncorrect 1489054 # Number of conditional branches incorrect
259system.cpu.branchPred.BTBLookups 11419999 # Number of BTB lookups
260system.cpu.branchPred.BTBHits 10818987 # Number of BTB hits
261system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
262system.cpu.branchPred.BTBHitPct 94.737197 # BTB Hit Percentage
263system.cpu.branchPred.usedRAS 1313526 # Number of times the RAS was used to get a target.
264system.cpu.branchPred.RASInCorrect 22992 # Number of incorrect RAS predictions.
265system.cpu.workload.num_syscalls 400 # Number of system calls
266system.cpu.numCycles 289223613 # number of cpu cycles simulated
267system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
268system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
269system.cpu.fetch.icacheStallCycles 23462367 # Number of cycles fetch is stalled on an Icache miss
270system.cpu.fetch.Insts 206597935 # Number of instructions fetch has processed
271system.cpu.fetch.Branches 18662810 # Number of branches that fetch encountered
272system.cpu.fetch.predictedBranches 12132513 # Number of branches that fetch has predicted taken
273system.cpu.fetch.Cycles 54232022 # Number of cycles fetch has run and was not squashing or blocked
274system.cpu.fetch.SquashCycles 15527864 # Number of cycles fetch has spent squashing
275system.cpu.fetch.BlockedCycles 178098132 # Number of cycles fetch has spent blocked
276system.cpu.fetch.MiscStallCycles 1461 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
277system.cpu.fetch.PendingTrapStallCycles 8383 # Number of stall cycles due to pending traps
278system.cpu.fetch.IcacheWaitRetryStallCycles 64 # Number of stall cycles due to full MSHR
279system.cpu.fetch.CacheLines 22359928 # Number of cache lines fetched
280system.cpu.fetch.IcacheSquashes 225896 # Number of outstanding Icache misses that were squashed
281system.cpu.fetch.rateDist::samples 269583947 # Number of instructions fetched each cycle (Total)
282system.cpu.fetch.rateDist::mean 1.268673 # Number of instructions fetched each cycle (Total)
283system.cpu.fetch.rateDist::stdev 2.756592 # Number of instructions fetched each cycle (Total)
284system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
285system.cpu.fetch.rateDist::0 216790408 80.42% 80.42% # Number of instructions fetched each cycle (Total)
286system.cpu.fetch.rateDist::1 2847266 1.06% 81.47% # Number of instructions fetched each cycle (Total)
287system.cpu.fetch.rateDist::2 2313368 0.86% 82.33% # Number of instructions fetched each cycle (Total)
288system.cpu.fetch.rateDist::3 2651625 0.98% 83.31% # Number of instructions fetched each cycle (Total)
289system.cpu.fetch.rateDist::4 3218833 1.19% 84.51% # Number of instructions fetched each cycle (Total)
290system.cpu.fetch.rateDist::5 3390708 1.26% 85.77% # Number of instructions fetched each cycle (Total)
291system.cpu.fetch.rateDist::6 3829918 1.42% 87.19% # Number of instructions fetched each cycle (Total)
292system.cpu.fetch.rateDist::7 2557961 0.95% 88.14% # Number of instructions fetched each cycle (Total)
293system.cpu.fetch.rateDist::8 31983860 11.86% 100.00% # Number of instructions fetched each cycle (Total)
294system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
295system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
296system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
297system.cpu.fetch.rateDist::total 269583947 # Number of instructions fetched each cycle (Total)
298system.cpu.fetch.branchRate 0.064527 # Number of branch fetches per cycle
299system.cpu.fetch.rate 0.714319 # Number of inst fetches per cycle
300system.cpu.decode.IdleCycles 36913432 # Number of cycles decode is idle
301system.cpu.decode.BlockedCycles 167057645 # Number of cycles decode is blocked
302system.cpu.decode.RunCycles 41544375 # Number of cycles decode is running
303system.cpu.decode.UnblockCycles 10286977 # Number of cycles decode is unblocking
304system.cpu.decode.SquashCycles 13781518 # Number of cycles decode is squashing
305system.cpu.decode.DecodedInsts 336085554 # Number of instructions handled by decode
306system.cpu.rename.SquashCycles 13781518 # Number of cycles rename is squashing
307system.cpu.rename.IdleCycles 44957189 # Number of cycles rename is idle
308system.cpu.rename.BlockCycles 116645963 # Number of cycles rename is blocking
309system.cpu.rename.serializeStallCycles 32240 # count of cycles rename stalled for serializing inst
310system.cpu.rename.RunCycles 42740267 # Number of cycles rename is running
311system.cpu.rename.UnblockCycles 51426770 # Number of cycles rename is unblocking
312system.cpu.rename.RenamedInsts 329706442 # Number of instructions processed by rename
313system.cpu.rename.ROBFullEvents 10945 # Number of times rename has blocked due to ROB full
314system.cpu.rename.IQFullEvents 26120234 # Number of times rename has blocked due to IQ full
315system.cpu.rename.LSQFullEvents 22717452 # Number of times rename has blocked due to LSQ full
316system.cpu.rename.FullRegisterEvents 239 # Number of times there has been no free registers
317system.cpu.rename.RenamedOperands 382540638 # Number of destination operands rename has renamed
318system.cpu.rename.RenameLookups 917473743 # Number of register rename lookups that rename has made
319system.cpu.rename.int_rename_lookups 909278159 # Number of integer rename lookups
320system.cpu.rename.fp_rename_lookups 8195584 # Number of floating rename lookups
321system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed
322system.cpu.rename.UndoneMaps 123111188 # Number of HB maps that are undone due to squashing
323system.cpu.rename.serializingInsts 2136 # count of serializing insts renamed
324system.cpu.rename.tempSerializingInsts 2172 # count of temporary serializing insts renamed
325system.cpu.rename.skidInsts 105032755 # count of insts added to the skid buffer
326system.cpu.memDep0.insertedLoads 84354587 # Number of loads inserted to the mem dependence unit.
327system.cpu.memDep0.insertedStores 30100906 # Number of stores inserted to the mem dependence unit.
328system.cpu.memDep0.conflictingLoads 58264869 # Number of conflicting loads.
329system.cpu.memDep0.conflictingStores 19038031 # Number of conflicting stores.
330system.cpu.iq.iqInstsAdded 322777816 # Number of instructions added to the IQ (excludes non-spec)
331system.cpu.iq.iqNonSpecInstsAdded 4259 # Number of non-speculative instructions added to the IQ
332system.cpu.iq.iqInstsIssued 260629412 # Number of instructions issued
333system.cpu.iq.iqSquashedInstsIssued 116539 # Number of squashed instructions issued
334system.cpu.iq.iqSquashedInstsExamined 101038886 # Number of squashed instructions iterated over during squash; mainly for profiling
335system.cpu.iq.iqSquashedOperandsExamined 209946848 # Number of squashed operands that are examined and possibly removed from graph
336system.cpu.iq.iqSquashedNonSpecRemoved 3014 # Number of squashed non-spec instructions that were removed
337system.cpu.iq.issued_per_cycle::samples 269583947 # Number of insts issued each cycle
338system.cpu.iq.issued_per_cycle::mean 0.966784 # Number of insts issued each cycle
339system.cpu.iq.issued_per_cycle::stdev 1.343888 # Number of insts issued each cycle
340system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
341system.cpu.iq.issued_per_cycle::0 143351146 53.17% 53.17% # Number of insts issued each cycle
342system.cpu.iq.issued_per_cycle::1 55555603 20.61% 73.78% # Number of insts issued each cycle
343system.cpu.iq.issued_per_cycle::2 34178684 12.68% 86.46% # Number of insts issued each cycle
344system.cpu.iq.issued_per_cycle::3 19029881 7.06% 93.52% # Number of insts issued each cycle
345system.cpu.iq.issued_per_cycle::4 10872516 4.03% 97.55% # Number of insts issued each cycle
346system.cpu.iq.issued_per_cycle::5 4173623 1.55% 99.10% # Number of insts issued each cycle
347system.cpu.iq.issued_per_cycle::6 1820350 0.68% 99.78% # Number of insts issued each cycle
348system.cpu.iq.issued_per_cycle::7 470633 0.17% 99.95% # Number of insts issued each cycle
349system.cpu.iq.issued_per_cycle::8 131511 0.05% 100.00% # Number of insts issued each cycle
350system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
351system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
352system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
353system.cpu.iq.issued_per_cycle::total 269583947 # Number of insts issued each cycle
354system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
355system.cpu.iq.fu_full::IntAlu 130095 4.79% 4.79% # attempts to use FU when none available
356system.cpu.iq.fu_full::IntMult 0 0.00% 4.79% # attempts to use FU when none available
357system.cpu.iq.fu_full::IntDiv 0 0.00% 4.79% # attempts to use FU when none available
358system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.79% # attempts to use FU when none available
359system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.79% # attempts to use FU when none available
360system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.79% # attempts to use FU when none available
361system.cpu.iq.fu_full::FloatMult 0 0.00% 4.79% # attempts to use FU when none available
362system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.79% # attempts to use FU when none available
363system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.79% # attempts to use FU when none available
364system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.79% # attempts to use FU when none available
365system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.79% # attempts to use FU when none available
366system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.79% # attempts to use FU when none available
367system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.79% # attempts to use FU when none available
368system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.79% # attempts to use FU when none available
369system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.79% # attempts to use FU when none available
370system.cpu.iq.fu_full::SimdMult 0 0.00% 4.79% # attempts to use FU when none available
371system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.79% # attempts to use FU when none available
372system.cpu.iq.fu_full::SimdShift 0 0.00% 4.79% # attempts to use FU when none available
373system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.79% # attempts to use FU when none available
374system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.79% # attempts to use FU when none available
375system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.79% # attempts to use FU when none available
376system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.79% # attempts to use FU when none available
377system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.79% # attempts to use FU when none available
378system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.79% # attempts to use FU when none available
379system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.79% # attempts to use FU when none available
380system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.79% # attempts to use FU when none available
381system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.79% # attempts to use FU when none available
382system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.79% # attempts to use FU when none available
383system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.79% # attempts to use FU when none available
384system.cpu.iq.fu_full::MemRead 2285309 84.07% 88.85% # attempts to use FU when none available
385system.cpu.iq.fu_full::MemWrite 303076 11.15% 100.00% # attempts to use FU when none available
386system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
387system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
388system.cpu.iq.FU_type_0::No_OpClass 1210969 0.46% 0.46% # Type of FU issued
389system.cpu.iq.FU_type_0::IntAlu 162174415 62.22% 62.69% # Type of FU issued
390system.cpu.iq.FU_type_0::IntMult 791156 0.30% 62.99% # Type of FU issued
391system.cpu.iq.FU_type_0::IntDiv 7035823 2.70% 65.69% # Type of FU issued
392system.cpu.iq.FU_type_0::FloatAdd 1446634 0.56% 66.25% # Type of FU issued
393system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.25% # Type of FU issued
394system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.25% # Type of FU issued
395system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.25% # Type of FU issued
396system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.25% # Type of FU issued
397system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.25% # Type of FU issued
398system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.25% # Type of FU issued
399system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.25% # Type of FU issued
400system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.25% # Type of FU issued
401system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.25% # Type of FU issued
402system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.25% # Type of FU issued
403system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.25% # Type of FU issued
404system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.25% # Type of FU issued
405system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.25% # Type of FU issued
406system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.25% # Type of FU issued
407system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.25% # Type of FU issued
408system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.25% # Type of FU issued
409system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.25% # Type of FU issued
410system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.25% # Type of FU issued
411system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.25% # Type of FU issued
412system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.25% # Type of FU issued
413system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.25% # Type of FU issued
414system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.25% # Type of FU issued
415system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.25% # Type of FU issued
416system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.25% # Type of FU issued
417system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.25% # Type of FU issued
418system.cpu.iq.FU_type_0::MemRead 65423127 25.10% 91.35% # Type of FU issued
419system.cpu.iq.FU_type_0::MemWrite 22547288 8.65% 100.00% # Type of FU issued
420system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
421system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
422system.cpu.iq.FU_type_0::total 260629412 # Type of FU issued
423system.cpu.iq.rate 0.901135 # Inst issue rate
424system.cpu.iq.fu_busy_cnt 2718480 # FU busy when requested
425system.cpu.iq.fu_busy_rate 0.010430 # FU busy rate (busy events/executed inst)
426system.cpu.iq.int_inst_queue_reads 788786495 # Number of integer instruction queue reads
427system.cpu.iq.int_inst_queue_writes 420497128 # Number of integer instruction queue writes
428system.cpu.iq.int_inst_queue_wakeup_accesses 255267923 # Number of integer instruction queue wakeup accesses
429system.cpu.iq.fp_inst_queue_reads 4891295 # Number of floating instruction queue reads
430system.cpu.iq.fp_inst_queue_writes 3603930 # Number of floating instruction queue writes
431system.cpu.iq.fp_inst_queue_wakeup_accesses 2350852 # Number of floating instruction queue wakeup accesses
432system.cpu.iq.int_alu_accesses 259675050 # Number of integer alu accesses
433system.cpu.iq.fp_alu_accesses 2461873 # Number of floating point alu accesses
434system.cpu.iew.lsq.thread0.forwLoads 18886019 # Number of loads that had data forwarded from stores
435system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
436system.cpu.iew.lsq.thread0.squashedLoads 27705000 # Number of loads squashed
437system.cpu.iew.lsq.thread0.ignoredResponses 26101 # Number of memory responses ignored because the instruction is squashed
438system.cpu.iew.lsq.thread0.memOrderViolation 285579 # Number of memory ordering violations
439system.cpu.iew.lsq.thread0.squashedStores 9585192 # Number of stores squashed
440system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
441system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
442system.cpu.iew.lsq.thread0.rescheduledLoads 50399 # Number of loads that were rescheduled
443system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked
444system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
445system.cpu.iew.iewSquashCycles 13781518 # Number of cycles IEW is squashing
446system.cpu.iew.iewBlockCycles 85016114 # Number of cycles IEW is blocking
447system.cpu.iew.iewUnblockCycles 5459108 # Number of cycles IEW is unblocking
448system.cpu.iew.iewDispatchedInsts 322782075 # Number of instructions dispatched to IQ
449system.cpu.iew.iewDispSquashedInsts 133200 # Number of squashed instructions skipped by dispatch
450system.cpu.iew.iewDispLoadInsts 84354587 # Number of dispatched load instructions
451system.cpu.iew.iewDispStoreInsts 30100909 # Number of dispatched store instructions
452system.cpu.iew.iewDispNonSpecInsts 2090 # Number of dispatched non-speculative instructions
453system.cpu.iew.iewIQFullEvents 2675714 # Number of times the IQ has become full, causing a stall
454system.cpu.iew.iewLSQFullEvents 13368 # Number of times the LSQ has become full, causing a stall
455system.cpu.iew.memOrderViolationEvents 285579 # Number of memory order violations
456system.cpu.iew.predictedTakenIncorrect 639541 # Number of branches that were predicted taken incorrectly
457system.cpu.iew.predictedNotTakenIncorrect 899945 # Number of branches that were predicted not taken incorrectly
458system.cpu.iew.branchMispredicts 1539486 # Number of branch mispredicts detected at execute
459system.cpu.iew.iewExecutedInsts 258853338 # Number of executed instructions
460system.cpu.iew.iewExecLoadInsts 64649488 # Number of load instructions executed
461system.cpu.iew.iewExecSquashedInsts 1776074 # Number of squashed instructions skipped in execute
462system.cpu.iew.exec_swp 0 # number of swp insts executed
463system.cpu.iew.exec_nop 0 # number of nop insts executed
464system.cpu.iew.exec_refs 86992429 # number of memory reference insts executed
465system.cpu.iew.exec_branches 14274182 # Number of branches executed
466system.cpu.iew.exec_stores 22342941 # Number of stores executed
467system.cpu.iew.exec_rate 0.894994 # Inst execution rate
468system.cpu.iew.wb_sent 258213659 # cumulative count of insts sent to commit
469system.cpu.iew.wb_count 257618775 # cumulative count of insts written-back
470system.cpu.iew.wb_producers 206032066 # num instructions producing a value
471system.cpu.iew.wb_consumers 369264105 # num instructions consuming a value
472system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
473system.cpu.iew.wb_rate 0.890725 # insts written-back per cycle
474system.cpu.iew.wb_fanout 0.557953 # average fanout of values written-back
475system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
476system.cpu.commit.commitSquashedInsts 101495618 # The number of squashed insts skipped by commit
477system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards
478system.cpu.commit.branchMispredicts 1490324 # The number of times a branch was mispredicted
479system.cpu.commit.committed_per_cycle::samples 255802429 # Number of insts commited each cycle
480system.cpu.commit.committed_per_cycle::mean 0.865367 # Number of insts commited each cycle
481system.cpu.commit.committed_per_cycle::stdev 1.654211 # Number of insts commited each cycle
482system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
483system.cpu.commit.committed_per_cycle::0 156431243 61.15% 61.15% # Number of insts commited each cycle
484system.cpu.commit.committed_per_cycle::1 57241672 22.38% 83.53% # Number of insts commited each cycle
485system.cpu.commit.committed_per_cycle::2 14031050 5.49% 89.02% # Number of insts commited each cycle
486system.cpu.commit.committed_per_cycle::3 12055371 4.71% 93.73% # Number of insts commited each cycle
487system.cpu.commit.committed_per_cycle::4 4173166 1.63% 95.36% # Number of insts commited each cycle
488system.cpu.commit.committed_per_cycle::5 2967121 1.16% 96.52% # Number of insts commited each cycle
489system.cpu.commit.committed_per_cycle::6 906774 0.35% 96.87% # Number of insts commited each cycle
490system.cpu.commit.committed_per_cycle::7 1044092 0.41% 97.28% # Number of insts commited each cycle
491system.cpu.commit.committed_per_cycle::8 6951940 2.72% 100.00% # Number of insts commited each cycle
492system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
493system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
494system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
495system.cpu.commit.committed_per_cycle::total 255802429 # Number of insts commited each cycle
496system.cpu.commit.committedInsts 132071192 # Number of instructions committed
497system.cpu.commit.committedOps 221362962 # Number of ops (including micro ops) committed
498system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
499system.cpu.commit.refs 77165304 # Number of memory references committed
500system.cpu.commit.loads 56649587 # Number of loads committed
501system.cpu.commit.membars 0 # Number of memory barriers committed
502system.cpu.commit.branches 12326938 # Number of branches committed
503system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
504system.cpu.commit.int_insts 220339553 # Number of committed integer instructions.
505system.cpu.commit.function_calls 797818 # Number of function calls committed.
506system.cpu.commit.bw_lim_events 6951940 # number cycles where commit BW limit reached
507system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
508system.cpu.rob.rob_reads 571709069 # The number of ROB reads
509system.cpu.rob.rob_writes 659523764 # The number of ROB writes
510system.cpu.timesIdled 5926858 # Number of times that the entire CPU went into an idle state and unscheduled itself
511system.cpu.idleCycles 19639666 # Total number of cycles that the CPU has spent unscheduled due to idling
512system.cpu.committedInsts 132071192 # Number of Instructions Simulated
513system.cpu.committedOps 221362962 # Number of Ops (including micro ops) Simulated
514system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated
515system.cpu.cpi 2.189907 # CPI: Cycles Per Instruction
516system.cpu.cpi_total 2.189907 # CPI: Total CPI of All Threads
517system.cpu.ipc 0.456640 # IPC: Instructions Per Cycle
518system.cpu.ipc_total 0.456640 # IPC: Total IPC of All Threads
519system.cpu.int_regfile_reads 554085462 # number of integer regfile reads
520system.cpu.int_regfile_writes 293886504 # number of integer regfile writes
521system.cpu.fp_regfile_reads 3218743 # number of floating regfile reads
522system.cpu.fp_regfile_writes 2010653 # number of floating regfile writes
523system.cpu.misc_regfile_reads 133373003 # number of misc regfile reads
524system.cpu.misc_regfile_writes 1689 # number of misc regfile writes
525system.cpu.toL2Bus.throughput 3891282 # Throughput (bytes/s)
526system.cpu.toL2Bus.trans_dist::ReadReq 7235 # Transaction distribution
527system.cpu.toL2Bus.trans_dist::ReadResp 7233 # Transaction distribution
528system.cpu.toL2Bus.trans_dist::Writeback 14 # Transaction distribution
529system.cpu.toL2Bus.trans_dist::UpgradeReq 153 # Transaction distribution
530system.cpu.toL2Bus.trans_dist::UpgradeResp 153 # Transaction distribution
531system.cpu.toL2Bus.trans_dist::ReadExReq 1537 # Transaction distribution
532system.cpu.toL2Bus.trans_dist::ReadExResp 1537 # Transaction distribution
533system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13393 # Packet count per connected master and slave (bytes)
534system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4315 # Packet count per connected master and slave (bytes)
535system.cpu.toL2Bus.pkt_count::total 17708 # Packet count per connected master and slave (bytes)
536system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 423616 # Cumulative packet size per connected master and slave (bytes)
537system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128704 # Cumulative packet size per connected master and slave (bytes)
538system.cpu.toL2Bus.tot_pkt_size::total 552320 # Cumulative packet size per connected master and slave (bytes)
539system.cpu.toL2Bus.data_through_bus 552320 # Total data (bytes)
540system.cpu.toL2Bus.snoop_data_through_bus 9856 # Total snoop data (bytes)
541system.cpu.toL2Bus.reqLayer0.occupancy 4483500 # Layer occupancy (ticks)
542system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
543system.cpu.toL2Bus.respLayer0.occupancy 10832250 # Layer occupancy (ticks)
544system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
545system.cpu.toL2Bus.respLayer1.occupancy 3515652 # Layer occupancy (ticks)
546system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
547system.cpu.icache.tags.replacements 4654 # number of replacements
548system.cpu.icache.tags.tagsinuse 1616.215170 # Cycle average of tags in use
549system.cpu.icache.tags.total_refs 22351029 # Total number of references to valid blocks.
550system.cpu.icache.tags.sampled_refs 6622 # Sample count of references to valid blocks.
551system.cpu.icache.tags.avg_refs 3375.268650 # Average number of references to valid blocks.
552system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
553system.cpu.icache.tags.occ_blocks::cpu.inst 1616.215170 # Average occupied blocks per requestor
554system.cpu.icache.tags.occ_percent::cpu.inst 0.789168 # Average percentage of cache occupancy
555system.cpu.icache.tags.occ_percent::total 0.789168 # Average percentage of cache occupancy
556system.cpu.icache.ReadReq_hits::cpu.inst 22351029 # number of ReadReq hits
557system.cpu.icache.ReadReq_hits::total 22351029 # number of ReadReq hits
558system.cpu.icache.demand_hits::cpu.inst 22351029 # number of demand (read+write) hits
559system.cpu.icache.demand_hits::total 22351029 # number of demand (read+write) hits
560system.cpu.icache.overall_hits::cpu.inst 22351029 # number of overall hits
561system.cpu.icache.overall_hits::total 22351029 # number of overall hits
562system.cpu.icache.ReadReq_misses::cpu.inst 8899 # number of ReadReq misses
563system.cpu.icache.ReadReq_misses::total 8899 # number of ReadReq misses
564system.cpu.icache.demand_misses::cpu.inst 8899 # number of demand (read+write) misses
565system.cpu.icache.demand_misses::total 8899 # number of demand (read+write) misses
566system.cpu.icache.overall_misses::cpu.inst 8899 # number of overall misses
567system.cpu.icache.overall_misses::total 8899 # number of overall misses
568system.cpu.icache.ReadReq_miss_latency::cpu.inst 351537500 # number of ReadReq miss cycles
569system.cpu.icache.ReadReq_miss_latency::total 351537500 # number of ReadReq miss cycles
570system.cpu.icache.demand_miss_latency::cpu.inst 351537500 # number of demand (read+write) miss cycles
571system.cpu.icache.demand_miss_latency::total 351537500 # number of demand (read+write) miss cycles
572system.cpu.icache.overall_miss_latency::cpu.inst 351537500 # number of overall miss cycles
573system.cpu.icache.overall_miss_latency::total 351537500 # number of overall miss cycles
574system.cpu.icache.ReadReq_accesses::cpu.inst 22359928 # number of ReadReq accesses(hits+misses)
575system.cpu.icache.ReadReq_accesses::total 22359928 # number of ReadReq accesses(hits+misses)
576system.cpu.icache.demand_accesses::cpu.inst 22359928 # number of demand (read+write) accesses
577system.cpu.icache.demand_accesses::total 22359928 # number of demand (read+write) accesses
578system.cpu.icache.overall_accesses::cpu.inst 22359928 # number of overall (read+write) accesses
579system.cpu.icache.overall_accesses::total 22359928 # number of overall (read+write) accesses
580system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000398 # miss rate for ReadReq accesses
581system.cpu.icache.ReadReq_miss_rate::total 0.000398 # miss rate for ReadReq accesses
582system.cpu.icache.demand_miss_rate::cpu.inst 0.000398 # miss rate for demand accesses
583system.cpu.icache.demand_miss_rate::total 0.000398 # miss rate for demand accesses
584system.cpu.icache.overall_miss_rate::cpu.inst 0.000398 # miss rate for overall accesses
585system.cpu.icache.overall_miss_rate::total 0.000398 # miss rate for overall accesses
586system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39503.034049 # average ReadReq miss latency
587system.cpu.icache.ReadReq_avg_miss_latency::total 39503.034049 # average ReadReq miss latency
588system.cpu.icache.demand_avg_miss_latency::cpu.inst 39503.034049 # average overall miss latency
589system.cpu.icache.demand_avg_miss_latency::total 39503.034049 # average overall miss latency
590system.cpu.icache.overall_avg_miss_latency::cpu.inst 39503.034049 # average overall miss latency
591system.cpu.icache.overall_avg_miss_latency::total 39503.034049 # average overall miss latency
592system.cpu.icache.blocked_cycles::no_mshrs 913 # number of cycles access was blocked
593system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
594system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked
595system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
596system.cpu.icache.avg_blocked_cycles::no_mshrs 53.705882 # average number of cycles each access was blocked
597system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
598system.cpu.icache.fast_writes 0 # number of fast writes performed
599system.cpu.icache.cache_copies 0 # number of cache copies performed
600system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2125 # number of ReadReq MSHR hits
601system.cpu.icache.ReadReq_mshr_hits::total 2125 # number of ReadReq MSHR hits
602system.cpu.icache.demand_mshr_hits::cpu.inst 2125 # number of demand (read+write) MSHR hits
603system.cpu.icache.demand_mshr_hits::total 2125 # number of demand (read+write) MSHR hits
604system.cpu.icache.overall_mshr_hits::cpu.inst 2125 # number of overall MSHR hits
605system.cpu.icache.overall_mshr_hits::total 2125 # number of overall MSHR hits
606system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6774 # number of ReadReq MSHR misses
607system.cpu.icache.ReadReq_mshr_misses::total 6774 # number of ReadReq MSHR misses
608system.cpu.icache.demand_mshr_misses::cpu.inst 6774 # number of demand (read+write) MSHR misses
609system.cpu.icache.demand_mshr_misses::total 6774 # number of demand (read+write) MSHR misses
610system.cpu.icache.overall_mshr_misses::cpu.inst 6774 # number of overall MSHR misses
611system.cpu.icache.overall_mshr_misses::total 6774 # number of overall MSHR misses
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616system.cpu.icache.overall_mshr_miss_latency::cpu.inst 261819250 # number of overall MSHR miss cycles
617system.cpu.icache.overall_mshr_miss_latency::total 261819250 # number of overall MSHR miss cycles
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622system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for overall accesses
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624system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38650.612637 # average ReadReq mshr miss latency
625system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38650.612637 # average ReadReq mshr miss latency
626system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38650.612637 # average overall mshr miss latency
627system.cpu.icache.demand_avg_mshr_miss_latency::total 38650.612637 # average overall mshr miss latency
628system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38650.612637 # average overall mshr miss latency
629system.cpu.icache.overall_avg_mshr_miss_latency::total 38650.612637 # average overall mshr miss latency
630system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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633system.cpu.l2cache.tags.total_refs 3276 # Total number of references to valid blocks.
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635system.cpu.l2cache.tags.avg_refs 0.859166 # Average number of references to valid blocks.
636system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
637system.cpu.l2cache.tags.occ_blocks::writebacks 1.748933 # Average occupied blocks per requestor
638system.cpu.l2cache.tags.occ_blocks::cpu.inst 2223.089774 # Average occupied blocks per requestor
639system.cpu.l2cache.tags.occ_blocks::cpu.data 312.384188 # Average occupied blocks per requestor
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641system.cpu.l2cache.tags.occ_percent::cpu.inst 0.067843 # Average percentage of cache occupancy
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648system.cpu.l2cache.Writeback_hits::total 14 # number of Writeback hits
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658system.cpu.l2cache.overall_hits::total 3277 # number of overall hits
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663system.cpu.l2cache.UpgradeReq_misses::total 152 # number of UpgradeReq misses
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687system.cpu.l2cache.Writeback_accesses::total 14 # number of Writeback accesses(hits+misses)
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702system.cpu.l2cache.UpgradeReq_miss_rate::total 0.993464 # miss rate for UpgradeReq accesses
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710system.cpu.l2cache.overall_miss_rate::total 0.619749 # miss rate for overall accesses
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712system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72919.621749 # average ReadReq miss latency
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714system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 63360.457516 # average ReadExReq miss latency
715system.cpu.l2cache.ReadExReq_avg_miss_latency::total 63360.457516 # average ReadExReq miss latency
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717system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65430.875576 # average overall miss latency
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719system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65691.484652 # average overall miss latency
720system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65430.875576 # average overall miss latency
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723system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
724system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
725system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
726system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
727system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
728system.cpu.l2cache.fast_writes 0 # number of fast writes performed
729system.cpu.l2cache.cache_copies 0 # number of cache copies performed
730system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3388 # number of ReadReq MSHR misses
731system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 423 # number of ReadReq MSHR misses
732system.cpu.l2cache.ReadReq_mshr_misses::total 3811 # number of ReadReq MSHR misses
733system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 152 # number of UpgradeReq MSHR misses
734system.cpu.l2cache.UpgradeReq_mshr_misses::total 152 # number of UpgradeReq MSHR misses
735system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1530 # number of ReadExReq MSHR misses
736system.cpu.l2cache.ReadExReq_mshr_misses::total 1530 # number of ReadExReq MSHR misses
737system.cpu.l2cache.demand_mshr_misses::cpu.inst 3388 # number of demand (read+write) MSHR misses
738system.cpu.l2cache.demand_mshr_misses::cpu.data 1953 # number of demand (read+write) MSHR misses
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741system.cpu.l2cache.overall_mshr_misses::cpu.data 1953 # number of overall MSHR misses
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747system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1520152 # number of UpgradeReq MSHR miss cycles
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749system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 77356000 # number of ReadExReq MSHR miss cycles
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757system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.917570 # mshr miss rate for ReadReq accesses
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759system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993464 # mshr miss rate for UpgradeReq accesses
760system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.993464 # mshr miss rate for UpgradeReq accesses
761system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995446 # mshr miss rate for ReadExReq accesses
762system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995446 # mshr miss rate for ReadExReq accesses
763system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.511782 # mshr miss rate for demand accesses
764system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.977477 # mshr miss rate for demand accesses
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766system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.511782 # mshr miss rate for overall accesses
767system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.977477 # mshr miss rate for overall accesses
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769system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53112.234357 # average ReadReq mshr miss latency
770system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60356.973995 # average ReadReq mshr miss latency
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773system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
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779system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53112.234357 # average overall mshr miss latency
780system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52681.515617 # average overall mshr miss latency
781system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52954.736941 # average overall mshr miss latency
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783system.cpu.dcache.tags.replacements 56 # number of replacements
784system.cpu.dcache.tags.tagsinuse 1433.333580 # Cycle average of tags in use
785system.cpu.dcache.tags.total_refs 66124025 # Total number of references to valid blocks.
786system.cpu.dcache.tags.sampled_refs 1997 # Sample count of references to valid blocks.
787system.cpu.dcache.tags.avg_refs 33111.680020 # Average number of references to valid blocks.
788system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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833system.cpu.dcache.ReadReq_avg_miss_latency::total 59849.914347 # average ReadReq miss latency
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838system.cpu.dcache.overall_avg_miss_latency::cpu.data 61756.843869 # average overall miss latency
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842system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
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845system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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861system.cpu.dcache.WriteReq_mshr_misses::total 1689 # number of WriteReq MSHR misses
862system.cpu.dcache.demand_mshr_misses::cpu.data 2151 # number of demand (read+write) MSHR misses
863system.cpu.dcache.demand_mshr_misses::total 2151 # number of demand (read+write) MSHR misses
864system.cpu.dcache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses
865system.cpu.dcache.overall_mshr_misses::total 2151 # number of overall MSHR misses
866system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31756250 # number of ReadReq MSHR miss cycles
867system.cpu.dcache.ReadReq_mshr_miss_latency::total 31756250 # number of ReadReq MSHR miss cycles
868system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 102039098 # number of WriteReq MSHR miss cycles
869system.cpu.dcache.WriteReq_mshr_miss_latency::total 102039098 # number of WriteReq MSHR miss cycles
870system.cpu.dcache.demand_mshr_miss_latency::cpu.data 133795348 # number of demand (read+write) MSHR miss cycles
871system.cpu.dcache.demand_mshr_miss_latency::total 133795348 # number of demand (read+write) MSHR miss cycles
872system.cpu.dcache.overall_mshr_miss_latency::cpu.data 133795348 # number of overall MSHR miss cycles
873system.cpu.dcache.overall_mshr_miss_latency::total 133795348 # number of overall MSHR miss cycles
874system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
875system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
876system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000082 # mshr miss rate for WriteReq accesses
877system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000082 # mshr miss rate for WriteReq accesses
878system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for demand accesses
879system.cpu.dcache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses
880system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for overall accesses
881system.cpu.dcache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses
882system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68736.471861 # average ReadReq mshr miss latency
883system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68736.471861 # average ReadReq mshr miss latency
884system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60413.912374 # average WriteReq mshr miss latency
885system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60413.912374 # average WriteReq mshr miss latency
886system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62201.463505 # average overall mshr miss latency
887system.cpu.dcache.demand_avg_mshr_miss_latency::total 62201.463505 # average overall mshr miss latency
888system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62201.463505 # average overall mshr miss latency
889system.cpu.dcache.overall_avg_mshr_miss_latency::total 62201.463505 # average overall mshr miss latency
890system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
891
892---------- End Simulation Statistics ----------