1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.087752 # Number of seconds simulated
4sim_ticks 87751730000 # Number of ticks simulated
5final_tick 87751730000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 56809 # Simulator instruction rate (inst/s)
8host_op_rate 95217 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 37745520 # Simulator tick rate (ticks/s)
10host_mem_usage 259224 # Number of bytes of host memory used
11host_seconds 2324.83 # Real time elapsed on the host
12sim_insts 132071227 # Number of instructions simulated
13sim_ops 221363017 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 345024 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 219584 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 0 # Number of bytes written to this memory
17system.physmem.num_reads 5391 # Number of read requests responded to by this memory
18system.physmem.num_writes 0 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 3931820 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 2502332 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_total 3931820 # Total bandwidth to/from this memory (bytes/s)
23system.cpu.workload.num_syscalls 400 # Number of system calls
24system.cpu.numCycles 175503461 # number of cpu cycles simulated
25system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
26system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
27system.cpu.BPredUnit.lookups 20929970 # Number of BP lookups
28system.cpu.BPredUnit.condPredicted 20929970 # Number of conditional branches predicted
29system.cpu.BPredUnit.condIncorrect 2208761 # Number of conditional branches incorrect
30system.cpu.BPredUnit.BTBLookups 15515509 # Number of BTB lookups
--- 287 unchanged lines hidden (view full) ---
318system.cpu.icache.overall_miss_latency::total 187306000 # number of overall miss cycles
319system.cpu.icache.ReadReq_accesses::cpu.inst 25822554 # number of ReadReq accesses(hits+misses)
320system.cpu.icache.ReadReq_accesses::total 25822554 # number of ReadReq accesses(hits+misses)
321system.cpu.icache.demand_accesses::cpu.inst 25822554 # number of demand (read+write) accesses
322system.cpu.icache.demand_accesses::total 25822554 # number of demand (read+write) accesses
323system.cpu.icache.overall_accesses::cpu.inst 25822554 # number of overall (read+write) accesses
324system.cpu.icache.overall_accesses::total 25822554 # number of overall (read+write) accesses
325system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000352 # miss rate for ReadReq accesses
326system.cpu.icache.demand_miss_rate::cpu.inst 0.000352 # miss rate for demand accesses
327system.cpu.icache.overall_miss_rate::cpu.inst 0.000352 # miss rate for overall accesses
328system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20598.922248 # average ReadReq miss latency
329system.cpu.icache.demand_avg_miss_latency::cpu.inst 20598.922248 # average overall miss latency
330system.cpu.icache.overall_avg_miss_latency::cpu.inst 20598.922248 # average overall miss latency
331system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
332system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
333system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
334system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
335system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
336system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
337system.cpu.icache.fast_writes 0 # number of fast writes performed
338system.cpu.icache.cache_copies 0 # number of cache copies performed
--- 11 unchanged lines hidden (view full) ---
350system.cpu.icache.overall_mshr_misses::total 7726 # number of overall MSHR misses
351system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130634500 # number of ReadReq MSHR miss cycles
352system.cpu.icache.ReadReq_mshr_miss_latency::total 130634500 # number of ReadReq MSHR miss cycles
353system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130634500 # number of demand (read+write) MSHR miss cycles
354system.cpu.icache.demand_mshr_miss_latency::total 130634500 # number of demand (read+write) MSHR miss cycles
355system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130634500 # number of overall MSHR miss cycles
356system.cpu.icache.overall_mshr_miss_latency::total 130634500 # number of overall MSHR miss cycles
357system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for ReadReq accesses
358system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for demand accesses
359system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for overall accesses
360system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16908.426094 # average ReadReq mshr miss latency
361system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16908.426094 # average overall mshr miss latency
362system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16908.426094 # average overall mshr miss latency
363system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
364system.cpu.dcache.replacements 56 # number of replacements
365system.cpu.dcache.tagsinuse 1426.584624 # Cycle average of tags in use
366system.cpu.dcache.total_refs 68642098 # Total number of references to valid blocks.
367system.cpu.dcache.sampled_refs 1997 # Sample count of references to valid blocks.
368system.cpu.dcache.avg_refs 34372.607912 # Average number of references to valid blocks.
369system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
370system.cpu.dcache.occ_blocks::cpu.data 1426.584624 # Average occupied blocks per requestor
--- 27 unchanged lines hidden (view full) ---
398system.cpu.dcache.ReadReq_accesses::total 48128652 # number of ReadReq accesses(hits+misses)
399system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses)
400system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses)
401system.cpu.dcache.demand_accesses::cpu.data 68644382 # number of demand (read+write) accesses
402system.cpu.dcache.demand_accesses::total 68644382 # number of demand (read+write) accesses
403system.cpu.dcache.overall_accesses::cpu.data 68644382 # number of overall (read+write) accesses
404system.cpu.dcache.overall_accesses::total 68644382 # number of overall (read+write) accesses
405system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000016 # miss rate for ReadReq accesses
406system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses
407system.cpu.dcache.demand_miss_rate::cpu.data 0.000036 # miss rate for demand accesses
408system.cpu.dcache.overall_miss_rate::cpu.data 0.000036 # miss rate for overall accesses
409system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32154.792746 # average ReadReq miss latency
410system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37945.804196 # average WriteReq miss latency
411system.cpu.dcache.demand_avg_miss_latency::cpu.data 36148.914791 # average overall miss latency
412system.cpu.dcache.overall_avg_miss_latency::cpu.data 36148.914791 # average overall miss latency
413system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
414system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
415system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
416system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
417system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
418system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
419system.cpu.dcache.fast_writes 0 # number of fast writes performed
420system.cpu.dcache.cache_copies 0 # number of cache copies performed
--- 19 unchanged lines hidden (view full) ---
440system.cpu.dcache.ReadReq_mshr_miss_latency::total 14546500 # number of ReadReq MSHR miss cycles
441system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59868000 # number of WriteReq MSHR miss cycles
442system.cpu.dcache.WriteReq_mshr_miss_latency::total 59868000 # number of WriteReq MSHR miss cycles
443system.cpu.dcache.demand_mshr_miss_latency::cpu.data 74414500 # number of demand (read+write) MSHR miss cycles
444system.cpu.dcache.demand_mshr_miss_latency::total 74414500 # number of demand (read+write) MSHR miss cycles
445system.cpu.dcache.overall_mshr_miss_latency::cpu.data 74414500 # number of overall MSHR miss cycles
446system.cpu.dcache.overall_mshr_miss_latency::total 74414500 # number of overall MSHR miss cycles
447system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses
448system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000083 # mshr miss rate for WriteReq accesses
449system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for demand accesses
450system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for overall accesses
451system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32985.260771 # average ReadReq mshr miss latency
452system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34949.211909 # average WriteReq mshr miss latency
453system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34547.121634 # average overall mshr miss latency
454system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34547.121634 # average overall mshr miss latency
455system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
456system.cpu.l2cache.replacements 0 # number of replacements
457system.cpu.l2cache.tagsinuse 2579.336511 # Cycle average of tags in use
458system.cpu.l2cache.total_refs 4173 # Total number of references to valid blocks.
459system.cpu.l2cache.sampled_refs 3841 # Sample count of references to valid blocks.
460system.cpu.l2cache.avg_refs 1.086436 # Average number of references to valid blocks.
461system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
462system.cpu.l2cache.occ_blocks::writebacks 1.713269 # Average occupied blocks per requestor
--- 52 unchanged lines hidden (view full) ---
515system.cpu.l2cache.demand_accesses::cpu.inst 7571 # number of demand (read+write) accesses
516system.cpu.l2cache.demand_accesses::cpu.data 1999 # number of demand (read+write) accesses
517system.cpu.l2cache.demand_accesses::total 9570 # number of demand (read+write) accesses
518system.cpu.l2cache.overall_accesses::cpu.inst 7571 # number of overall (read+write) accesses
519system.cpu.l2cache.overall_accesses::cpu.data 1999 # number of overall (read+write) accesses
520system.cpu.l2cache.overall_accesses::total 9570 # number of overall (read+write) accesses
521system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.453177 # miss rate for ReadReq accesses
522system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.929545 # miss rate for ReadReq accesses
523system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
524system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994869 # miss rate for ReadExReq accesses
525system.cpu.l2cache.demand_miss_rate::cpu.inst 0.453177 # miss rate for demand accesses
526system.cpu.l2cache.demand_miss_rate::cpu.data 0.980490 # miss rate for demand accesses
527system.cpu.l2cache.overall_miss_rate::cpu.inst 0.453177 # miss rate for overall accesses
528system.cpu.l2cache.overall_miss_rate::cpu.data 0.980490 # miss rate for overall accesses
529system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34251.967356 # average ReadReq miss latency
530system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34172.371638 # average ReadReq miss latency
531system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34168.923275 # average ReadExReq miss latency
532system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34251.967356 # average overall miss latency
533system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34169.642857 # average overall miss latency
534system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34251.967356 # average overall miss latency
535system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34169.642857 # average overall miss latency
536system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
537system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
538system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
539system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
540system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
541system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
542system.cpu.l2cache.fast_writes 0 # number of fast writes performed
543system.cpu.l2cache.cache_copies 0 # number of cache copies performed
--- 20 unchanged lines hidden (view full) ---
564system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106440500 # number of demand (read+write) MSHR miss cycles
565system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 60787000 # number of demand (read+write) MSHR miss cycles
566system.cpu.l2cache.demand_mshr_miss_latency::total 167227500 # number of demand (read+write) MSHR miss cycles
567system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106440500 # number of overall MSHR miss cycles
568system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 60787000 # number of overall MSHR miss cycles
569system.cpu.l2cache.overall_mshr_miss_latency::total 167227500 # number of overall MSHR miss cycles
570system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for ReadReq accesses
571system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.929545 # mshr miss rate for ReadReq accesses
572system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
573system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994869 # mshr miss rate for ReadExReq accesses
574system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for demand accesses
575system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980490 # mshr miss rate for demand accesses
576system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for overall accesses
577system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980490 # mshr miss rate for overall accesses
578system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31023.171087 # average ReadReq mshr miss latency
579system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30993.887531 # average ReadReq mshr miss latency
580system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
581system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31019.019987 # average ReadExReq mshr miss latency
582system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31023.171087 # average overall mshr miss latency
583system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31013.775510 # average overall mshr miss latency
584system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31023.171087 # average overall mshr miss latency
585system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31013.775510 # average overall mshr miss latency
586system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
587
588---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.087752 # Number of seconds simulated
4sim_ticks 87751730000 # Number of ticks simulated
5final_tick 87751730000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 56809 # Simulator instruction rate (inst/s)
8host_op_rate 95217 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 37745520 # Simulator tick rate (ticks/s)
10host_mem_usage 259224 # Number of bytes of host memory used
11host_seconds 2324.83 # Real time elapsed on the host
12sim_insts 132071227 # Number of instructions simulated
13sim_ops 221363017 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 345024 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 219584 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 0 # Number of bytes written to this memory
17system.physmem.num_reads 5391 # Number of read requests responded to by this memory
18system.physmem.num_writes 0 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 3931820 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 2502332 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_total 3931820 # Total bandwidth to/from this memory (bytes/s)
23system.cpu.workload.num_syscalls 400 # Number of system calls
24system.cpu.numCycles 175503461 # number of cpu cycles simulated
25system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
26system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
27system.cpu.BPredUnit.lookups 20929970 # Number of BP lookups
28system.cpu.BPredUnit.condPredicted 20929970 # Number of conditional branches predicted
29system.cpu.BPredUnit.condIncorrect 2208761 # Number of conditional branches incorrect
30system.cpu.BPredUnit.BTBLookups 15515509 # Number of BTB lookups
--- 287 unchanged lines hidden (view full) ---
318system.cpu.icache.overall_miss_latency::total 187306000 # number of overall miss cycles
319system.cpu.icache.ReadReq_accesses::cpu.inst 25822554 # number of ReadReq accesses(hits+misses)
320system.cpu.icache.ReadReq_accesses::total 25822554 # number of ReadReq accesses(hits+misses)
321system.cpu.icache.demand_accesses::cpu.inst 25822554 # number of demand (read+write) accesses
322system.cpu.icache.demand_accesses::total 25822554 # number of demand (read+write) accesses
323system.cpu.icache.overall_accesses::cpu.inst 25822554 # number of overall (read+write) accesses
324system.cpu.icache.overall_accesses::total 25822554 # number of overall (read+write) accesses
325system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000352 # miss rate for ReadReq accesses
326system.cpu.icache.demand_miss_rate::cpu.inst 0.000352 # miss rate for demand accesses
327system.cpu.icache.overall_miss_rate::cpu.inst 0.000352 # miss rate for overall accesses
328system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20598.922248 # average ReadReq miss latency
329system.cpu.icache.demand_avg_miss_latency::cpu.inst 20598.922248 # average overall miss latency
330system.cpu.icache.overall_avg_miss_latency::cpu.inst 20598.922248 # average overall miss latency
331system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
332system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
333system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
334system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
335system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
336system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
337system.cpu.icache.fast_writes 0 # number of fast writes performed
338system.cpu.icache.cache_copies 0 # number of cache copies performed
--- 11 unchanged lines hidden (view full) ---
350system.cpu.icache.overall_mshr_misses::total 7726 # number of overall MSHR misses
351system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130634500 # number of ReadReq MSHR miss cycles
352system.cpu.icache.ReadReq_mshr_miss_latency::total 130634500 # number of ReadReq MSHR miss cycles
353system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130634500 # number of demand (read+write) MSHR miss cycles
354system.cpu.icache.demand_mshr_miss_latency::total 130634500 # number of demand (read+write) MSHR miss cycles
355system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130634500 # number of overall MSHR miss cycles
356system.cpu.icache.overall_mshr_miss_latency::total 130634500 # number of overall MSHR miss cycles
357system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for ReadReq accesses
358system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for demand accesses
359system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for overall accesses
360system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16908.426094 # average ReadReq mshr miss latency
361system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16908.426094 # average overall mshr miss latency
362system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16908.426094 # average overall mshr miss latency
363system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
364system.cpu.dcache.replacements 56 # number of replacements
365system.cpu.dcache.tagsinuse 1426.584624 # Cycle average of tags in use
366system.cpu.dcache.total_refs 68642098 # Total number of references to valid blocks.
367system.cpu.dcache.sampled_refs 1997 # Sample count of references to valid blocks.
368system.cpu.dcache.avg_refs 34372.607912 # Average number of references to valid blocks.
369system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
370system.cpu.dcache.occ_blocks::cpu.data 1426.584624 # Average occupied blocks per requestor
--- 27 unchanged lines hidden (view full) ---
398system.cpu.dcache.ReadReq_accesses::total 48128652 # number of ReadReq accesses(hits+misses)
399system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses)
400system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses)
401system.cpu.dcache.demand_accesses::cpu.data 68644382 # number of demand (read+write) accesses
402system.cpu.dcache.demand_accesses::total 68644382 # number of demand (read+write) accesses
403system.cpu.dcache.overall_accesses::cpu.data 68644382 # number of overall (read+write) accesses
404system.cpu.dcache.overall_accesses::total 68644382 # number of overall (read+write) accesses
405system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000016 # miss rate for ReadReq accesses
406system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses
407system.cpu.dcache.demand_miss_rate::cpu.data 0.000036 # miss rate for demand accesses
408system.cpu.dcache.overall_miss_rate::cpu.data 0.000036 # miss rate for overall accesses
409system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32154.792746 # average ReadReq miss latency
410system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37945.804196 # average WriteReq miss latency
411system.cpu.dcache.demand_avg_miss_latency::cpu.data 36148.914791 # average overall miss latency
412system.cpu.dcache.overall_avg_miss_latency::cpu.data 36148.914791 # average overall miss latency
413system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
414system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
415system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
416system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
417system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
418system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
419system.cpu.dcache.fast_writes 0 # number of fast writes performed
420system.cpu.dcache.cache_copies 0 # number of cache copies performed
--- 19 unchanged lines hidden (view full) ---
440system.cpu.dcache.ReadReq_mshr_miss_latency::total 14546500 # number of ReadReq MSHR miss cycles
441system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59868000 # number of WriteReq MSHR miss cycles
442system.cpu.dcache.WriteReq_mshr_miss_latency::total 59868000 # number of WriteReq MSHR miss cycles
443system.cpu.dcache.demand_mshr_miss_latency::cpu.data 74414500 # number of demand (read+write) MSHR miss cycles
444system.cpu.dcache.demand_mshr_miss_latency::total 74414500 # number of demand (read+write) MSHR miss cycles
445system.cpu.dcache.overall_mshr_miss_latency::cpu.data 74414500 # number of overall MSHR miss cycles
446system.cpu.dcache.overall_mshr_miss_latency::total 74414500 # number of overall MSHR miss cycles
447system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses
448system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000083 # mshr miss rate for WriteReq accesses
449system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for demand accesses
450system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for overall accesses
451system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32985.260771 # average ReadReq mshr miss latency
452system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34949.211909 # average WriteReq mshr miss latency
453system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34547.121634 # average overall mshr miss latency
454system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34547.121634 # average overall mshr miss latency
455system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
456system.cpu.l2cache.replacements 0 # number of replacements
457system.cpu.l2cache.tagsinuse 2579.336511 # Cycle average of tags in use
458system.cpu.l2cache.total_refs 4173 # Total number of references to valid blocks.
459system.cpu.l2cache.sampled_refs 3841 # Sample count of references to valid blocks.
460system.cpu.l2cache.avg_refs 1.086436 # Average number of references to valid blocks.
461system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
462system.cpu.l2cache.occ_blocks::writebacks 1.713269 # Average occupied blocks per requestor
--- 52 unchanged lines hidden (view full) ---
515system.cpu.l2cache.demand_accesses::cpu.inst 7571 # number of demand (read+write) accesses
516system.cpu.l2cache.demand_accesses::cpu.data 1999 # number of demand (read+write) accesses
517system.cpu.l2cache.demand_accesses::total 9570 # number of demand (read+write) accesses
518system.cpu.l2cache.overall_accesses::cpu.inst 7571 # number of overall (read+write) accesses
519system.cpu.l2cache.overall_accesses::cpu.data 1999 # number of overall (read+write) accesses
520system.cpu.l2cache.overall_accesses::total 9570 # number of overall (read+write) accesses
521system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.453177 # miss rate for ReadReq accesses
522system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.929545 # miss rate for ReadReq accesses
523system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
524system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994869 # miss rate for ReadExReq accesses
525system.cpu.l2cache.demand_miss_rate::cpu.inst 0.453177 # miss rate for demand accesses
526system.cpu.l2cache.demand_miss_rate::cpu.data 0.980490 # miss rate for demand accesses
527system.cpu.l2cache.overall_miss_rate::cpu.inst 0.453177 # miss rate for overall accesses
528system.cpu.l2cache.overall_miss_rate::cpu.data 0.980490 # miss rate for overall accesses
529system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34251.967356 # average ReadReq miss latency
530system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34172.371638 # average ReadReq miss latency
531system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34168.923275 # average ReadExReq miss latency
532system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34251.967356 # average overall miss latency
533system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34169.642857 # average overall miss latency
534system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34251.967356 # average overall miss latency
535system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34169.642857 # average overall miss latency
536system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
537system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
538system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
539system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
540system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
541system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
542system.cpu.l2cache.fast_writes 0 # number of fast writes performed
543system.cpu.l2cache.cache_copies 0 # number of cache copies performed
--- 20 unchanged lines hidden (view full) ---
564system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106440500 # number of demand (read+write) MSHR miss cycles
565system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 60787000 # number of demand (read+write) MSHR miss cycles
566system.cpu.l2cache.demand_mshr_miss_latency::total 167227500 # number of demand (read+write) MSHR miss cycles
567system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106440500 # number of overall MSHR miss cycles
568system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 60787000 # number of overall MSHR miss cycles
569system.cpu.l2cache.overall_mshr_miss_latency::total 167227500 # number of overall MSHR miss cycles
570system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for ReadReq accesses
571system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.929545 # mshr miss rate for ReadReq accesses
572system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
573system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994869 # mshr miss rate for ReadExReq accesses
574system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for demand accesses
575system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980490 # mshr miss rate for demand accesses
576system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for overall accesses
577system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980490 # mshr miss rate for overall accesses
578system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31023.171087 # average ReadReq mshr miss latency
579system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30993.887531 # average ReadReq mshr miss latency
580system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
581system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31019.019987 # average ReadExReq mshr miss latency
582system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31023.171087 # average overall mshr miss latency
583system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31013.775510 # average overall mshr miss latency
584system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31023.171087 # average overall mshr miss latency
585system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31013.775510 # average overall mshr miss latency
586system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
587
588---------- End Simulation Statistics ----------