1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.144377 # Number of seconds simulated
4sim_ticks 144377116000 # Number of ticks simulated
5final_tick 144377116000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 66784 # Simulator instruction rate (inst/s)
8host_op_rate 111936 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 73006862 # Simulator tick rate (ticks/s)
10host_mem_usage 319660 # Number of bytes of host memory used
11host_seconds 1977.58 # Real time elapsed on the host
12sim_insts 132071192 # Number of instructions simulated
13sim_ops 221363384 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 217984 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 125056 # Number of bytes read from this memory
18system.physmem.bytes_read::total 343040 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 217984 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 217984 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 3406 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 1954 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 5360 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 1509824 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 866176 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 2376000 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 1509824 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 1509824 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 1509824 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 866176 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 2376000 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.readReqs 5361 # Number of read requests accepted
33system.physmem.writeReqs 0 # Number of write requests accepted
34system.physmem.readBursts 5361 # Number of DRAM read bursts, including those serviced by the write queue
35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
36system.physmem.bytesReadDRAM 343104 # Total number of bytes read from DRAM
37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
39system.physmem.bytesReadSys 343104 # Total read bytes from the system interface side
40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
43system.physmem.neitherReadNorWriteReqs 150 # Number of requests that are neither read nor write
44system.physmem.perBankRdBursts::0 281 # Per bank write bursts
45system.physmem.perBankRdBursts::1 346 # Per bank write bursts
46system.physmem.perBankRdBursts::2 449 # Per bank write bursts
47system.physmem.perBankRdBursts::3 351 # Per bank write bursts
48system.physmem.perBankRdBursts::4 335 # Per bank write bursts
49system.physmem.perBankRdBursts::5 328 # Per bank write bursts
50system.physmem.perBankRdBursts::6 398 # Per bank write bursts
51system.physmem.perBankRdBursts::7 381 # Per bank write bursts
52system.physmem.perBankRdBursts::8 343 # Per bank write bursts
53system.physmem.perBankRdBursts::9 292 # Per bank write bursts
54system.physmem.perBankRdBursts::10 228 # Per bank write bursts
55system.physmem.perBankRdBursts::11 284 # Per bank write bursts
56system.physmem.perBankRdBursts::12 208 # Per bank write bursts
57system.physmem.perBankRdBursts::13 469 # Per bank write bursts
58system.physmem.perBankRdBursts::14 386 # Per bank write bursts
59system.physmem.perBankRdBursts::15 282 # Per bank write bursts
60system.physmem.perBankWrBursts::0 0 # Per bank write bursts
61system.physmem.perBankWrBursts::1 0 # Per bank write bursts
62system.physmem.perBankWrBursts::2 0 # Per bank write bursts
63system.physmem.perBankWrBursts::3 0 # Per bank write bursts
64system.physmem.perBankWrBursts::4 0 # Per bank write bursts
65system.physmem.perBankWrBursts::5 0 # Per bank write bursts
66system.physmem.perBankWrBursts::6 0 # Per bank write bursts
67system.physmem.perBankWrBursts::7 0 # Per bank write bursts
68system.physmem.perBankWrBursts::8 0 # Per bank write bursts
69system.physmem.perBankWrBursts::9 0 # Per bank write bursts
70system.physmem.perBankWrBursts::10 0 # Per bank write bursts
71system.physmem.perBankWrBursts::11 0 # Per bank write bursts
72system.physmem.perBankWrBursts::12 0 # Per bank write bursts
73system.physmem.perBankWrBursts::13 0 # Per bank write bursts
74system.physmem.perBankWrBursts::14 0 # Per bank write bursts
75system.physmem.perBankWrBursts::15 0 # Per bank write bursts
76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
78system.physmem.totGap 144377080000 # Total gap between requests
79system.physmem.readPktSize::0 0 # Read request sizes (log2)
80system.physmem.readPktSize::1 0 # Read request sizes (log2)
81system.physmem.readPktSize::2 0 # Read request sizes (log2)
82system.physmem.readPktSize::3 0 # Read request sizes (log2)
83system.physmem.readPktSize::4 0 # Read request sizes (log2)
84system.physmem.readPktSize::5 0 # Read request sizes (log2)
85system.physmem.readPktSize::6 5361 # Read request sizes (log2)
86system.physmem.writePktSize::0 0 # Write request sizes (log2)
87system.physmem.writePktSize::1 0 # Write request sizes (log2)
88system.physmem.writePktSize::2 0 # Write request sizes (log2)
89system.physmem.writePktSize::3 0 # Write request sizes (log2)
90system.physmem.writePktSize::4 0 # Write request sizes (log2)
91system.physmem.writePktSize::5 0 # Write request sizes (log2)
92system.physmem.writePktSize::6 0 # Write request sizes (log2)
93system.physmem.rdQLenPdf::0 4312 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::1 880 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::2 145 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see

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181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
189system.physmem.bytesPerActivate::samples 327 # Bytes accessed per row activation
190system.physmem.bytesPerActivate::mean 508.672783 # Bytes accessed per row activation
191system.physmem.bytesPerActivate::gmean 294.998238 # Bytes accessed per row activation
192system.physmem.bytesPerActivate::stdev 425.682375 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::0-127 88 26.91% 26.91% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::128-255 53 16.21% 43.12% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::256-383 28 8.56% 51.68% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::384-511 16 4.89% 56.57% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::512-639 9 2.75% 59.33% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::640-767 6 1.83% 61.16% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::768-895 3 0.92% 62.08% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::896-1023 3 0.92% 63.00% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::1024-1151 121 37.00% 100.00% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::total 327 # Bytes accessed per row activation
203system.physmem.totQLat 28551000 # Total ticks spent queuing
204system.physmem.totMemAccLat 139987250 # Total ticks spent from burst creation until serviced by the DRAM
205system.physmem.totBusLat 26805000 # Total ticks spent in databus transfers
206system.physmem.totBankLat 84631250 # Total ticks spent accessing banks
207system.physmem.avgQLat 5325.69 # Average queueing delay per DRAM burst
208system.physmem.avgBankLat 15786.47 # Average bank access latency per DRAM burst
209system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
210system.physmem.avgMemAccLat 26112.15 # Average memory access latency per DRAM burst
211system.physmem.avgRdBW 2.38 # Average DRAM read bandwidth in MiByte/s
212system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
213system.physmem.avgRdBWSys 2.38 # Average system read bandwidth in MiByte/s
214system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
215system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
216system.physmem.busUtil 0.02 # Data bus utilization in percentage
217system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
218system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
219system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing
220system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
221system.physmem.readRowHits 4274 # Number of row buffer hits during reads
222system.physmem.writeRowHits 0 # Number of row buffer hits during writes
223system.physmem.readRowHitRate 79.72 # Row buffer hit rate for reads
224system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
225system.physmem.avgGap 26930997.95 # Average gap between requests
226system.physmem.pageHitRate 79.72 # Row buffer hit rate, read and write combined
227system.physmem.prechargeAllPercent 0.40 # Percentage of time for which DRAM has all the banks in precharge state
228system.membus.throughput 2375113 # Throughput (bytes/s)
229system.membus.trans_dist::ReadReq 3828 # Transaction distribution
230system.membus.trans_dist::ReadResp 3825 # Transaction distribution
231system.membus.trans_dist::UpgradeReq 150 # Transaction distribution
232system.membus.trans_dist::UpgradeResp 150 # Transaction distribution
233system.membus.trans_dist::ReadExReq 1533 # Transaction distribution
234system.membus.trans_dist::ReadExResp 1533 # Transaction distribution
235system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11019 # Packet count per connected master and slave (bytes)
236system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11019 # Packet count per connected master and slave (bytes)
237system.membus.pkt_count::total 11019 # Packet count per connected master and slave (bytes)
238system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 342912 # Cumulative packet size per connected master and slave (bytes)
239system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342912 # Cumulative packet size per connected master and slave (bytes)
240system.membus.tot_pkt_size::total 342912 # Cumulative packet size per connected master and slave (bytes)
241system.membus.data_through_bus 342912 # Total data (bytes)
242system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
243system.membus.reqLayer0.occupancy 6993500 # Layer occupancy (ticks)
244system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
245system.membus.respLayer1.occupancy 50706850 # Layer occupancy (ticks)
246system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
247system.cpu_clk_domain.clock 500 # Clock period in ticks
248system.cpu.branchPred.lookups 18662333 # Number of BP lookups
249system.cpu.branchPred.condPredicted 18662333 # Number of conditional branches predicted
250system.cpu.branchPred.condIncorrect 1490477 # Number of conditional branches incorrect
251system.cpu.branchPred.BTBLookups 11407057 # Number of BTB lookups
252system.cpu.branchPred.BTBHits 10802916 # Number of BTB hits
253system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
254system.cpu.branchPred.BTBHitPct 94.703796 # BTB Hit Percentage
255system.cpu.branchPred.usedRAS 1319575 # Number of times the RAS was used to get a target.
256system.cpu.branchPred.RASInCorrect 23217 # Number of incorrect RAS predictions.
257system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
258system.cpu.workload.num_syscalls 400 # Number of system calls
259system.cpu.numCycles 289035036 # number of cpu cycles simulated
260system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
261system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
262system.cpu.fetch.icacheStallCycles 23466628 # Number of cycles fetch is stalled on an Icache miss
263system.cpu.fetch.Insts 206674196 # Number of instructions fetch has processed
264system.cpu.fetch.Branches 18662333 # Number of branches that fetch encountered
265system.cpu.fetch.predictedBranches 12122491 # Number of branches that fetch has predicted taken
266system.cpu.fetch.Cycles 54224578 # Number of cycles fetch has run and was not squashing or blocked
267system.cpu.fetch.SquashCycles 15529649 # Number of cycles fetch has spent squashing
268system.cpu.fetch.BlockedCycles 177872737 # Number of cycles fetch has spent blocked
269system.cpu.fetch.MiscStallCycles 1739 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
270system.cpu.fetch.PendingTrapStallCycles 9780 # Number of stall cycles due to pending traps
271system.cpu.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR
272system.cpu.fetch.CacheLines 22363082 # Number of cache lines fetched
273system.cpu.fetch.IcacheSquashes 227556 # Number of outstanding Icache misses that were squashed
274system.cpu.fetch.rateDist::samples 269352720 # Number of instructions fetched each cycle (Total)
275system.cpu.fetch.rateDist::mean 1.269654 # Number of instructions fetched each cycle (Total)
276system.cpu.fetch.rateDist::stdev 2.757498 # Number of instructions fetched each cycle (Total)
277system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
278system.cpu.fetch.rateDist::0 216567147 80.40% 80.40% # Number of instructions fetched each cycle (Total)
279system.cpu.fetch.rateDist::1 2849140 1.06% 81.46% # Number of instructions fetched each cycle (Total)
280system.cpu.fetch.rateDist::2 2312743 0.86% 82.32% # Number of instructions fetched each cycle (Total)
281system.cpu.fetch.rateDist::3 2640443 0.98% 83.30% # Number of instructions fetched each cycle (Total)
282system.cpu.fetch.rateDist::4 3223496 1.20% 84.50% # Number of instructions fetched each cycle (Total)
283system.cpu.fetch.rateDist::5 3388678 1.26% 85.75% # Number of instructions fetched each cycle (Total)
284system.cpu.fetch.rateDist::6 3828931 1.42% 87.18% # Number of instructions fetched each cycle (Total)
285system.cpu.fetch.rateDist::7 2559342 0.95% 88.13% # Number of instructions fetched each cycle (Total)
286system.cpu.fetch.rateDist::8 31982800 11.87% 100.00% # Number of instructions fetched each cycle (Total)
287system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
288system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
289system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
290system.cpu.fetch.rateDist::total 269352720 # Number of instructions fetched each cycle (Total)
291system.cpu.fetch.branchRate 0.064568 # Number of branch fetches per cycle
292system.cpu.fetch.rate 0.715049 # Number of inst fetches per cycle
293system.cpu.decode.IdleCycles 36872291 # Number of cycles decode is idle
294system.cpu.decode.BlockedCycles 166882879 # Number of cycles decode is blocked
295system.cpu.decode.RunCycles 41583049 # Number of cycles decode is running
296system.cpu.decode.UnblockCycles 10237266 # Number of cycles decode is unblocking
297system.cpu.decode.SquashCycles 13777235 # Number of cycles decode is squashing
298system.cpu.decode.DecodedInsts 336030589 # Number of instructions handled by decode
299system.cpu.rename.SquashCycles 13777235 # Number of cycles rename is squashing
300system.cpu.rename.IdleCycles 44927552 # Number of cycles rename is idle
301system.cpu.rename.BlockCycles 116592006 # Number of cycles rename is blocking
302system.cpu.rename.serializeStallCycles 33482 # count of cycles rename stalled for serializing inst
303system.cpu.rename.RunCycles 42725844 # Number of cycles rename is running
304system.cpu.rename.UnblockCycles 51296601 # Number of cycles rename is unblocking
305system.cpu.rename.RenamedInsts 329644603 # Number of instructions processed by rename
306system.cpu.rename.ROBFullEvents 10793 # Number of times rename has blocked due to ROB full
307system.cpu.rename.IQFullEvents 25973281 # Number of times rename has blocked due to IQ full
308system.cpu.rename.LSQFullEvents 22738118 # Number of times rename has blocked due to LSQ full
309system.cpu.rename.RenamedOperands 382392326 # Number of destination operands rename has renamed
310system.cpu.rename.RenameLookups 917644681 # Number of register rename lookups that rename has made
311system.cpu.rename.int_rename_lookups 605892364 # Number of integer rename lookups
312system.cpu.rename.fp_rename_lookups 4122807 # Number of floating rename lookups
313system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed
314system.cpu.rename.UndoneMaps 122962876 # Number of HB maps that are undone due to squashing
315system.cpu.rename.serializingInsts 2119 # count of serializing insts renamed
316system.cpu.rename.tempSerializingInsts 2126 # count of temporary serializing insts renamed
317system.cpu.rename.skidInsts 104910685 # count of insts added to the skid buffer
318system.cpu.memDep0.insertedLoads 84442386 # Number of loads inserted to the mem dependence unit.
319system.cpu.memDep0.insertedStores 30099715 # Number of stores inserted to the mem dependence unit.
320system.cpu.memDep0.conflictingLoads 58118082 # Number of conflicting loads.
321system.cpu.memDep0.conflictingStores 18905602 # Number of conflicting stores.
322system.cpu.iq.iqInstsAdded 322699954 # Number of instructions added to the IQ (excludes non-spec)
323system.cpu.iq.iqNonSpecInstsAdded 4280 # Number of non-speculative instructions added to the IQ
324system.cpu.iq.iqInstsIssued 260615725 # Number of instructions issued
325system.cpu.iq.iqSquashedInstsIssued 114961 # Number of squashed instructions issued
326system.cpu.iq.iqSquashedInstsExamined 100953398 # Number of squashed instructions iterated over during squash; mainly for profiling
327system.cpu.iq.iqSquashedOperandsExamined 209924725 # Number of squashed operands that are examined and possibly removed from graph
328system.cpu.iq.iqSquashedNonSpecRemoved 3035 # Number of squashed non-spec instructions that were removed
329system.cpu.iq.issued_per_cycle::samples 269352720 # Number of insts issued each cycle
330system.cpu.iq.issued_per_cycle::mean 0.967563 # Number of insts issued each cycle
331system.cpu.iq.issued_per_cycle::stdev 1.344835 # Number of insts issued each cycle
332system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
333system.cpu.iq.issued_per_cycle::0 143250903 53.18% 53.18% # Number of insts issued each cycle
334system.cpu.iq.issued_per_cycle::1 55370436 20.56% 73.74% # Number of insts issued each cycle
335system.cpu.iq.issued_per_cycle::2 34176648 12.69% 86.43% # Number of insts issued each cycle
336system.cpu.iq.issued_per_cycle::3 19094867 7.09% 93.52% # Number of insts issued each cycle
337system.cpu.iq.issued_per_cycle::4 10869897 4.04% 97.55% # Number of insts issued each cycle
338system.cpu.iq.issued_per_cycle::5 4155062 1.54% 99.10% # Number of insts issued each cycle
339system.cpu.iq.issued_per_cycle::6 1825131 0.68% 99.77% # Number of insts issued each cycle
340system.cpu.iq.issued_per_cycle::7 476500 0.18% 99.95% # Number of insts issued each cycle
341system.cpu.iq.issued_per_cycle::8 133276 0.05% 100.00% # Number of insts issued each cycle
342system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
343system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
344system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
345system.cpu.iq.issued_per_cycle::total 269352720 # Number of insts issued each cycle
346system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
347system.cpu.iq.fu_full::IntAlu 130941 4.84% 4.84% # attempts to use FU when none available
348system.cpu.iq.fu_full::IntMult 0 0.00% 4.84% # attempts to use FU when none available
349system.cpu.iq.fu_full::IntDiv 0 0.00% 4.84% # attempts to use FU when none available
350system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.84% # attempts to use FU when none available
351system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.84% # attempts to use FU when none available
352system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.84% # attempts to use FU when none available
353system.cpu.iq.fu_full::FloatMult 0 0.00% 4.84% # attempts to use FU when none available
354system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.84% # attempts to use FU when none available
355system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.84% # attempts to use FU when none available
356system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.84% # attempts to use FU when none available
357system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.84% # attempts to use FU when none available
358system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.84% # attempts to use FU when none available
359system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.84% # attempts to use FU when none available
360system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.84% # attempts to use FU when none available
361system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.84% # attempts to use FU when none available
362system.cpu.iq.fu_full::SimdMult 0 0.00% 4.84% # attempts to use FU when none available
363system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.84% # attempts to use FU when none available
364system.cpu.iq.fu_full::SimdShift 0 0.00% 4.84% # attempts to use FU when none available
365system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.84% # attempts to use FU when none available
366system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.84% # attempts to use FU when none available
367system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.84% # attempts to use FU when none available
368system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.84% # attempts to use FU when none available
369system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.84% # attempts to use FU when none available
370system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.84% # attempts to use FU when none available
371system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.84% # attempts to use FU when none available
372system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.84% # attempts to use FU when none available
373system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.84% # attempts to use FU when none available
374system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.84% # attempts to use FU when none available
375system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.84% # attempts to use FU when none available
376system.cpu.iq.fu_full::MemRead 2275620 84.10% 88.94% # attempts to use FU when none available
377system.cpu.iq.fu_full::MemWrite 299199 11.06% 100.00% # attempts to use FU when none available
378system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
379system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
380system.cpu.iq.FU_type_0::No_OpClass 1210799 0.46% 0.46% # Type of FU issued
381system.cpu.iq.FU_type_0::IntAlu 162097443 62.20% 62.66% # Type of FU issued
382system.cpu.iq.FU_type_0::IntMult 790400 0.30% 62.97% # Type of FU issued
383system.cpu.iq.FU_type_0::IntDiv 7035783 2.70% 65.67% # Type of FU issued
384system.cpu.iq.FU_type_0::FloatAdd 1447528 0.56% 66.22% # Type of FU issued
385system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.22% # Type of FU issued
386system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.22% # Type of FU issued
387system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.22% # Type of FU issued
388system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.22% # Type of FU issued
389system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.22% # Type of FU issued
390system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.22% # Type of FU issued
391system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.22% # Type of FU issued
392system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.22% # Type of FU issued
393system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.22% # Type of FU issued
394system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.22% # Type of FU issued
395system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.22% # Type of FU issued
396system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.22% # Type of FU issued
397system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.22% # Type of FU issued
398system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.22% # Type of FU issued
399system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.22% # Type of FU issued
400system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.22% # Type of FU issued
401system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.22% # Type of FU issued
402system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.22% # Type of FU issued
403system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.22% # Type of FU issued
404system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.22% # Type of FU issued
405system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.22% # Type of FU issued
406system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.22% # Type of FU issued
407system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.22% # Type of FU issued
408system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.22% # Type of FU issued
409system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.22% # Type of FU issued
410system.cpu.iq.FU_type_0::MemRead 65478586 25.12% 91.35% # Type of FU issued
411system.cpu.iq.FU_type_0::MemWrite 22555186 8.65% 100.00% # Type of FU issued
412system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
413system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
414system.cpu.iq.FU_type_0::total 260615725 # Type of FU issued
415system.cpu.iq.rate 0.901675 # Inst issue rate
416system.cpu.iq.fu_busy_cnt 2705760 # FU busy when requested
417system.cpu.iq.fu_busy_rate 0.010382 # FU busy rate (busy events/executed inst)
418system.cpu.iq.int_inst_queue_reads 788512519 # Number of integer instruction queue reads
419system.cpu.iq.int_inst_queue_writes 420334227 # Number of integer instruction queue writes
420system.cpu.iq.int_inst_queue_wakeup_accesses 255242293 # Number of integer instruction queue wakeup accesses
421system.cpu.iq.fp_inst_queue_reads 4892372 # Number of floating instruction queue reads
422system.cpu.iq.fp_inst_queue_writes 3608187 # Number of floating instruction queue writes
423system.cpu.iq.fp_inst_queue_wakeup_accesses 2352192 # Number of floating instruction queue wakeup accesses
424system.cpu.iq.int_alu_accesses 259648600 # Number of integer alu accesses
425system.cpu.iq.fp_alu_accesses 2462086 # Number of floating point alu accesses
426system.cpu.iew.lsq.thread0.forwLoads 18920241 # Number of loads that had data forwarded from stores
427system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
428system.cpu.iew.lsq.thread0.squashedLoads 27792799 # Number of loads squashed
429system.cpu.iew.lsq.thread0.ignoredResponses 26588 # Number of memory responses ignored because the instruction is squashed
430system.cpu.iew.lsq.thread0.memOrderViolation 290410 # Number of memory ordering violations
431system.cpu.iew.lsq.thread0.squashedStores 9583998 # Number of stores squashed
432system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
433system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
434system.cpu.iew.lsq.thread0.rescheduledLoads 49921 # Number of loads that were rescheduled
435system.cpu.iew.lsq.thread0.cacheBlocked 17 # Number of times an access to memory failed due to the cache being blocked
436system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
437system.cpu.iew.iewSquashCycles 13777235 # Number of cycles IEW is squashing
438system.cpu.iew.iewBlockCycles 85064772 # Number of cycles IEW is blocking
439system.cpu.iew.iewUnblockCycles 5446513 # Number of cycles IEW is unblocking
440system.cpu.iew.iewDispatchedInsts 322704234 # Number of instructions dispatched to IQ
441system.cpu.iew.iewDispSquashedInsts 135340 # Number of squashed instructions skipped by dispatch
442system.cpu.iew.iewDispLoadInsts 84442386 # Number of dispatched load instructions
443system.cpu.iew.iewDispStoreInsts 30099715 # Number of dispatched store instructions
444system.cpu.iew.iewDispNonSpecInsts 2049 # Number of dispatched non-speculative instructions
445system.cpu.iew.iewIQFullEvents 2678194 # Number of times the IQ has become full, causing a stall
446system.cpu.iew.iewLSQFullEvents 12950 # Number of times the LSQ has become full, causing a stall
447system.cpu.iew.memOrderViolationEvents 290410 # Number of memory order violations
448system.cpu.iew.predictedTakenIncorrect 639185 # Number of branches that were predicted taken incorrectly
449system.cpu.iew.predictedNotTakenIncorrect 902051 # Number of branches that were predicted not taken incorrectly
450system.cpu.iew.branchMispredicts 1541236 # Number of branch mispredicts detected at execute
451system.cpu.iew.iewExecutedInsts 258833919 # Number of executed instructions
452system.cpu.iew.iewExecLoadInsts 64703526 # Number of load instructions executed
453system.cpu.iew.iewExecSquashedInsts 1781806 # Number of squashed instructions skipped in execute
454system.cpu.iew.exec_swp 0 # number of swp insts executed
455system.cpu.iew.exec_nop 0 # number of nop insts executed
456system.cpu.iew.exec_refs 87053484 # number of memory reference insts executed
457system.cpu.iew.exec_branches 14272898 # Number of branches executed
458system.cpu.iew.exec_stores 22349958 # Number of stores executed
459system.cpu.iew.exec_rate 0.895511 # Inst execution rate
460system.cpu.iew.wb_sent 258192676 # cumulative count of insts sent to commit
461system.cpu.iew.wb_count 257594485 # cumulative count of insts written-back
462system.cpu.iew.wb_producers 206043233 # num instructions producing a value
463system.cpu.iew.wb_consumers 369200904 # num instructions consuming a value
464system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
465system.cpu.iew.wb_rate 0.891222 # insts written-back per cycle
466system.cpu.iew.wb_fanout 0.558079 # average fanout of values written-back
467system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
468system.cpu.commit.commitSquashedInsts 101415579 # The number of squashed insts skipped by commit
469system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards
470system.cpu.commit.branchMispredicts 1491917 # The number of times a branch was mispredicted
471system.cpu.commit.committed_per_cycle::samples 255575485 # Number of insts commited each cycle
472system.cpu.commit.committed_per_cycle::mean 0.866137 # Number of insts commited each cycle
473system.cpu.commit.committed_per_cycle::stdev 1.656618 # Number of insts commited each cycle
474system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
475system.cpu.commit.committed_per_cycle::0 156360594 61.18% 61.18% # Number of insts commited each cycle
476system.cpu.commit.committed_per_cycle::1 57109316 22.35% 83.53% # Number of insts commited each cycle
477system.cpu.commit.committed_per_cycle::2 13985683 5.47% 89.00% # Number of insts commited each cycle
478system.cpu.commit.committed_per_cycle::3 12037857 4.71% 93.71% # Number of insts commited each cycle
479system.cpu.commit.committed_per_cycle::4 4182593 1.64% 95.34% # Number of insts commited each cycle
480system.cpu.commit.committed_per_cycle::5 2963821 1.16% 96.50% # Number of insts commited each cycle
481system.cpu.commit.committed_per_cycle::6 909345 0.36% 96.86% # Number of insts commited each cycle
482system.cpu.commit.committed_per_cycle::7 1046624 0.41% 97.27% # Number of insts commited each cycle
483system.cpu.commit.committed_per_cycle::8 6979652 2.73% 100.00% # Number of insts commited each cycle
484system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
485system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
486system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
487system.cpu.commit.committed_per_cycle::total 255575485 # Number of insts commited each cycle
488system.cpu.commit.committedInsts 132071192 # Number of instructions committed
489system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed
490system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
491system.cpu.commit.refs 77165304 # Number of memory references committed
492system.cpu.commit.loads 56649587 # Number of loads committed
493system.cpu.commit.membars 0 # Number of memory barriers committed
494system.cpu.commit.branches 12326938 # Number of branches committed
495system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
496system.cpu.commit.int_insts 219019985 # Number of committed integer instructions.
497system.cpu.commit.function_calls 797818 # Number of function calls committed.
498system.cpu.commit.bw_lim_events 6979652 # number cycles where commit BW limit reached
499system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
500system.cpu.rob.rob_reads 571374796 # The number of ROB reads
501system.cpu.rob.rob_writes 659361249 # The number of ROB writes
502system.cpu.timesIdled 5927783 # Number of times that the entire CPU went into an idle state and unscheduled itself
503system.cpu.idleCycles 19682316 # Total number of cycles that the CPU has spent unscheduled due to idling
504system.cpu.committedInsts 132071192 # Number of Instructions Simulated
505system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated
506system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated
507system.cpu.cpi 2.188479 # CPI: Cycles Per Instruction
508system.cpu.cpi_total 2.188479 # CPI: Total CPI of All Threads
509system.cpu.ipc 0.456938 # IPC: Instructions Per Cycle
510system.cpu.ipc_total 0.456938 # IPC: Total IPC of All Threads
511system.cpu.int_regfile_reads 451403378 # number of integer regfile reads
512system.cpu.int_regfile_writes 234040975 # number of integer regfile writes
513system.cpu.fp_regfile_reads 3219859 # number of floating regfile reads
514system.cpu.fp_regfile_writes 2011879 # number of floating regfile writes
515system.cpu.cc_regfile_reads 102824885 # number of cc regfile reads
516system.cpu.cc_regfile_writes 59817361 # number of cc regfile writes
517system.cpu.misc_regfile_reads 133392985 # number of misc regfile reads
518system.cpu.misc_regfile_writes 1689 # number of misc regfile writes
519system.cpu.toL2Bus.throughput 3846371 # Throughput (bytes/s)
520system.cpu.toL2Bus.trans_dist::ReadReq 7125 # Transaction distribution
521system.cpu.toL2Bus.trans_dist::ReadResp 7121 # Transaction distribution
522system.cpu.toL2Bus.trans_dist::Writeback 15 # Transaction distribution
523system.cpu.toL2Bus.trans_dist::UpgradeReq 150 # Transaction distribution
524system.cpu.toL2Bus.trans_dist::UpgradeResp 150 # Transaction distribution
525system.cpu.toL2Bus.trans_dist::ReadExReq 1541 # Transaction distribution
526system.cpu.toL2Bus.trans_dist::ReadExResp 1541 # Transaction distribution
527system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13184 # Packet count per connected master and slave (bytes)
528system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4308 # Packet count per connected master and slave (bytes)
529system.cpu.toL2Bus.pkt_count::total 17492 # Packet count per connected master and slave (bytes)
530system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 417024 # Cumulative packet size per connected master and slave (bytes)
531system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128640 # Cumulative packet size per connected master and slave (bytes)
532system.cpu.toL2Bus.tot_pkt_size::total 545664 # Cumulative packet size per connected master and slave (bytes)
533system.cpu.toL2Bus.data_through_bus 545664 # Total data (bytes)
534system.cpu.toL2Bus.snoop_data_through_bus 9664 # Total snoop data (bytes)
535system.cpu.toL2Bus.reqLayer0.occupancy 4430500 # Layer occupancy (ticks)
536system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
537system.cpu.toL2Bus.respLayer0.occupancy 10573999 # Layer occupancy (ticks)
538system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
539system.cpu.toL2Bus.respLayer1.occupancy 3437150 # Layer occupancy (ticks)
540system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
541system.cpu.icache.tags.replacements 4547 # number of replacements
542system.cpu.icache.tags.tagsinuse 1629.451963 # Cycle average of tags in use
543system.cpu.icache.tags.total_refs 22354297 # Total number of references to valid blocks.
544system.cpu.icache.tags.sampled_refs 6517 # Sample count of references to valid blocks.
545system.cpu.icache.tags.avg_refs 3430.151450 # Average number of references to valid blocks.
546system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
547system.cpu.icache.tags.occ_blocks::cpu.inst 1629.451963 # Average occupied blocks per requestor
548system.cpu.icache.tags.occ_percent::cpu.inst 0.795631 # Average percentage of cache occupancy
549system.cpu.icache.tags.occ_percent::total 0.795631 # Average percentage of cache occupancy
550system.cpu.icache.tags.occ_task_id_blocks::1024 1970 # Occupied blocks per task id
551system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id
552system.cpu.icache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id
553system.cpu.icache.tags.age_task_id_blocks_1024::2 757 # Occupied blocks per task id
554system.cpu.icache.tags.age_task_id_blocks_1024::3 125 # Occupied blocks per task id
555system.cpu.icache.tags.age_task_id_blocks_1024::4 807 # Occupied blocks per task id
556system.cpu.icache.tags.occ_task_id_percent::1024 0.961914 # Percentage of cache occupancy per task id
557system.cpu.icache.tags.tag_accesses 44732829 # Number of tag accesses
558system.cpu.icache.tags.data_accesses 44732829 # Number of data accesses
559system.cpu.icache.ReadReq_hits::cpu.inst 22354297 # number of ReadReq hits
560system.cpu.icache.ReadReq_hits::total 22354297 # number of ReadReq hits
561system.cpu.icache.demand_hits::cpu.inst 22354297 # number of demand (read+write) hits
562system.cpu.icache.demand_hits::total 22354297 # number of demand (read+write) hits
563system.cpu.icache.overall_hits::cpu.inst 22354297 # number of overall hits
564system.cpu.icache.overall_hits::total 22354297 # number of overall hits
565system.cpu.icache.ReadReq_misses::cpu.inst 8784 # number of ReadReq misses
566system.cpu.icache.ReadReq_misses::total 8784 # number of ReadReq misses
567system.cpu.icache.demand_misses::cpu.inst 8784 # number of demand (read+write) misses
568system.cpu.icache.demand_misses::total 8784 # number of demand (read+write) misses
569system.cpu.icache.overall_misses::cpu.inst 8784 # number of overall misses
570system.cpu.icache.overall_misses::total 8784 # number of overall misses
571system.cpu.icache.ReadReq_miss_latency::cpu.inst 365846249 # number of ReadReq miss cycles
572system.cpu.icache.ReadReq_miss_latency::total 365846249 # number of ReadReq miss cycles
573system.cpu.icache.demand_miss_latency::cpu.inst 365846249 # number of demand (read+write) miss cycles
574system.cpu.icache.demand_miss_latency::total 365846249 # number of demand (read+write) miss cycles
575system.cpu.icache.overall_miss_latency::cpu.inst 365846249 # number of overall miss cycles
576system.cpu.icache.overall_miss_latency::total 365846249 # number of overall miss cycles
577system.cpu.icache.ReadReq_accesses::cpu.inst 22363081 # number of ReadReq accesses(hits+misses)
578system.cpu.icache.ReadReq_accesses::total 22363081 # number of ReadReq accesses(hits+misses)
579system.cpu.icache.demand_accesses::cpu.inst 22363081 # number of demand (read+write) accesses
580system.cpu.icache.demand_accesses::total 22363081 # number of demand (read+write) accesses
581system.cpu.icache.overall_accesses::cpu.inst 22363081 # number of overall (read+write) accesses
582system.cpu.icache.overall_accesses::total 22363081 # number of overall (read+write) accesses
583system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000393 # miss rate for ReadReq accesses
584system.cpu.icache.ReadReq_miss_rate::total 0.000393 # miss rate for ReadReq accesses
585system.cpu.icache.demand_miss_rate::cpu.inst 0.000393 # miss rate for demand accesses
586system.cpu.icache.demand_miss_rate::total 0.000393 # miss rate for demand accesses
587system.cpu.icache.overall_miss_rate::cpu.inst 0.000393 # miss rate for overall accesses
588system.cpu.icache.overall_miss_rate::total 0.000393 # miss rate for overall accesses
589system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41649.163138 # average ReadReq miss latency
590system.cpu.icache.ReadReq_avg_miss_latency::total 41649.163138 # average ReadReq miss latency
591system.cpu.icache.demand_avg_miss_latency::cpu.inst 41649.163138 # average overall miss latency
592system.cpu.icache.demand_avg_miss_latency::total 41649.163138 # average overall miss latency
593system.cpu.icache.overall_avg_miss_latency::cpu.inst 41649.163138 # average overall miss latency
594system.cpu.icache.overall_avg_miss_latency::total 41649.163138 # average overall miss latency
595system.cpu.icache.blocked_cycles::no_mshrs 800 # number of cycles access was blocked
596system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
597system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked
598system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
599system.cpu.icache.avg_blocked_cycles::no_mshrs 57.142857 # average number of cycles each access was blocked
600system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
601system.cpu.icache.fast_writes 0 # number of fast writes performed
602system.cpu.icache.cache_copies 0 # number of cache copies performed
603system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2116 # number of ReadReq MSHR hits
604system.cpu.icache.ReadReq_mshr_hits::total 2116 # number of ReadReq MSHR hits
605system.cpu.icache.demand_mshr_hits::cpu.inst 2116 # number of demand (read+write) MSHR hits
606system.cpu.icache.demand_mshr_hits::total 2116 # number of demand (read+write) MSHR hits
607system.cpu.icache.overall_mshr_hits::cpu.inst 2116 # number of overall MSHR hits
608system.cpu.icache.overall_mshr_hits::total 2116 # number of overall MSHR hits
609system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6668 # number of ReadReq MSHR misses
610system.cpu.icache.ReadReq_mshr_misses::total 6668 # number of ReadReq MSHR misses
611system.cpu.icache.demand_mshr_misses::cpu.inst 6668 # number of demand (read+write) MSHR misses
612system.cpu.icache.demand_mshr_misses::total 6668 # number of demand (read+write) MSHR misses
613system.cpu.icache.overall_mshr_misses::cpu.inst 6668 # number of overall MSHR misses
614system.cpu.icache.overall_mshr_misses::total 6668 # number of overall MSHR misses
615system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 272166001 # number of ReadReq MSHR miss cycles
616system.cpu.icache.ReadReq_mshr_miss_latency::total 272166001 # number of ReadReq MSHR miss cycles
617system.cpu.icache.demand_mshr_miss_latency::cpu.inst 272166001 # number of demand (read+write) MSHR miss cycles
618system.cpu.icache.demand_mshr_miss_latency::total 272166001 # number of demand (read+write) MSHR miss cycles
619system.cpu.icache.overall_mshr_miss_latency::cpu.inst 272166001 # number of overall MSHR miss cycles
620system.cpu.icache.overall_mshr_miss_latency::total 272166001 # number of overall MSHR miss cycles
621system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000298 # mshr miss rate for ReadReq accesses
622system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000298 # mshr miss rate for ReadReq accesses
623system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000298 # mshr miss rate for demand accesses
624system.cpu.icache.demand_mshr_miss_rate::total 0.000298 # mshr miss rate for demand accesses
625system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000298 # mshr miss rate for overall accesses
626system.cpu.icache.overall_mshr_miss_rate::total 0.000298 # mshr miss rate for overall accesses
627system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40816.736803 # average ReadReq mshr miss latency
628system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40816.736803 # average ReadReq mshr miss latency
629system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40816.736803 # average overall mshr miss latency
630system.cpu.icache.demand_avg_mshr_miss_latency::total 40816.736803 # average overall mshr miss latency
631system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40816.736803 # average overall mshr miss latency
632system.cpu.icache.overall_avg_mshr_miss_latency::total 40816.736803 # average overall mshr miss latency
633system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
634system.cpu.l2cache.tags.replacements 0 # number of replacements
635system.cpu.l2cache.tags.tagsinuse 2545.733703 # Cycle average of tags in use
636system.cpu.l2cache.tags.total_refs 3149 # Total number of references to valid blocks.
637system.cpu.l2cache.tags.sampled_refs 3831 # Sample count of references to valid blocks.
638system.cpu.l2cache.tags.avg_refs 0.821979 # Average number of references to valid blocks.
639system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
640system.cpu.l2cache.tags.occ_blocks::writebacks 1.666971 # Average occupied blocks per requestor
641system.cpu.l2cache.tags.occ_blocks::cpu.inst 2237.371026 # Average occupied blocks per requestor
642system.cpu.l2cache.tags.occ_blocks::cpu.data 306.695706 # Average occupied blocks per requestor
643system.cpu.l2cache.tags.occ_percent::writebacks 0.000051 # Average percentage of cache occupancy
644system.cpu.l2cache.tags.occ_percent::cpu.inst 0.068279 # Average percentage of cache occupancy
645system.cpu.l2cache.tags.occ_percent::cpu.data 0.009360 # Average percentage of cache occupancy
646system.cpu.l2cache.tags.occ_percent::total 0.077690 # Average percentage of cache occupancy
647system.cpu.l2cache.tags.occ_task_id_blocks::1024 3831 # Occupied blocks per task id
648system.cpu.l2cache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
649system.cpu.l2cache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id
650system.cpu.l2cache.tags.age_task_id_blocks_1024::2 881 # Occupied blocks per task id
651system.cpu.l2cache.tags.age_task_id_blocks_1024::3 143 # Occupied blocks per task id
652system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2568 # Occupied blocks per task id
653system.cpu.l2cache.tags.occ_task_id_percent::1024 0.116913 # Percentage of cache occupancy per task id
654system.cpu.l2cache.tags.tag_accesses 74812 # Number of tag accesses
655system.cpu.l2cache.tags.data_accesses 74812 # Number of data accesses
656system.cpu.l2cache.ReadReq_hits::cpu.inst 3110 # number of ReadReq hits
657system.cpu.l2cache.ReadReq_hits::cpu.data 36 # number of ReadReq hits
658system.cpu.l2cache.ReadReq_hits::total 3146 # number of ReadReq hits
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660system.cpu.l2cache.Writeback_hits::total 15 # number of Writeback hits
661system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
662system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
663system.cpu.l2cache.demand_hits::cpu.inst 3110 # number of demand (read+write) hits
664system.cpu.l2cache.demand_hits::cpu.data 44 # number of demand (read+write) hits
665system.cpu.l2cache.demand_hits::total 3154 # number of demand (read+write) hits
666system.cpu.l2cache.overall_hits::cpu.inst 3110 # number of overall hits
667system.cpu.l2cache.overall_hits::cpu.data 44 # number of overall hits
668system.cpu.l2cache.overall_hits::total 3154 # number of overall hits
669system.cpu.l2cache.ReadReq_misses::cpu.inst 3407 # number of ReadReq misses
670system.cpu.l2cache.ReadReq_misses::cpu.data 421 # number of ReadReq misses
671system.cpu.l2cache.ReadReq_misses::total 3828 # number of ReadReq misses
672system.cpu.l2cache.UpgradeReq_misses::cpu.data 150 # number of UpgradeReq misses
673system.cpu.l2cache.UpgradeReq_misses::total 150 # number of UpgradeReq misses
674system.cpu.l2cache.ReadExReq_misses::cpu.data 1533 # number of ReadExReq misses
675system.cpu.l2cache.ReadExReq_misses::total 1533 # number of ReadExReq misses
676system.cpu.l2cache.demand_misses::cpu.inst 3407 # number of demand (read+write) misses
677system.cpu.l2cache.demand_misses::cpu.data 1954 # number of demand (read+write) misses
678system.cpu.l2cache.demand_misses::total 5361 # number of demand (read+write) misses
679system.cpu.l2cache.overall_misses::cpu.inst 3407 # number of overall misses
680system.cpu.l2cache.overall_misses::cpu.data 1954 # number of overall misses
681system.cpu.l2cache.overall_misses::total 5361 # number of overall misses
682system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 234241000 # number of ReadReq miss cycles
683system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32796500 # number of ReadReq miss cycles
684system.cpu.l2cache.ReadReq_miss_latency::total 267037500 # number of ReadReq miss cycles
685system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104661000 # number of ReadExReq miss cycles
686system.cpu.l2cache.ReadExReq_miss_latency::total 104661000 # number of ReadExReq miss cycles
687system.cpu.l2cache.demand_miss_latency::cpu.inst 234241000 # number of demand (read+write) miss cycles
688system.cpu.l2cache.demand_miss_latency::cpu.data 137457500 # number of demand (read+write) miss cycles
689system.cpu.l2cache.demand_miss_latency::total 371698500 # number of demand (read+write) miss cycles
690system.cpu.l2cache.overall_miss_latency::cpu.inst 234241000 # number of overall miss cycles
691system.cpu.l2cache.overall_miss_latency::cpu.data 137457500 # number of overall miss cycles
692system.cpu.l2cache.overall_miss_latency::total 371698500 # number of overall miss cycles
693system.cpu.l2cache.ReadReq_accesses::cpu.inst 6517 # number of ReadReq accesses(hits+misses)
694system.cpu.l2cache.ReadReq_accesses::cpu.data 457 # number of ReadReq accesses(hits+misses)
695system.cpu.l2cache.ReadReq_accesses::total 6974 # number of ReadReq accesses(hits+misses)
696system.cpu.l2cache.Writeback_accesses::writebacks 15 # number of Writeback accesses(hits+misses)
697system.cpu.l2cache.Writeback_accesses::total 15 # number of Writeback accesses(hits+misses)
698system.cpu.l2cache.UpgradeReq_accesses::cpu.data 150 # number of UpgradeReq accesses(hits+misses)
699system.cpu.l2cache.UpgradeReq_accesses::total 150 # number of UpgradeReq accesses(hits+misses)
700system.cpu.l2cache.ReadExReq_accesses::cpu.data 1541 # number of ReadExReq accesses(hits+misses)
701system.cpu.l2cache.ReadExReq_accesses::total 1541 # number of ReadExReq accesses(hits+misses)
702system.cpu.l2cache.demand_accesses::cpu.inst 6517 # number of demand (read+write) accesses
703system.cpu.l2cache.demand_accesses::cpu.data 1998 # number of demand (read+write) accesses
704system.cpu.l2cache.demand_accesses::total 8515 # number of demand (read+write) accesses
705system.cpu.l2cache.overall_accesses::cpu.inst 6517 # number of overall (read+write) accesses
706system.cpu.l2cache.overall_accesses::cpu.data 1998 # number of overall (read+write) accesses
707system.cpu.l2cache.overall_accesses::total 8515 # number of overall (read+write) accesses
708system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.522787 # miss rate for ReadReq accesses
709system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.921225 # miss rate for ReadReq accesses
710system.cpu.l2cache.ReadReq_miss_rate::total 0.548896 # miss rate for ReadReq accesses
711system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
712system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
713system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994809 # miss rate for ReadExReq accesses
714system.cpu.l2cache.ReadExReq_miss_rate::total 0.994809 # miss rate for ReadExReq accesses
715system.cpu.l2cache.demand_miss_rate::cpu.inst 0.522787 # miss rate for demand accesses
716system.cpu.l2cache.demand_miss_rate::cpu.data 0.977978 # miss rate for demand accesses
717system.cpu.l2cache.demand_miss_rate::total 0.629595 # miss rate for demand accesses
718system.cpu.l2cache.overall_miss_rate::cpu.inst 0.522787 # miss rate for overall accesses
719system.cpu.l2cache.overall_miss_rate::cpu.data 0.977978 # miss rate for overall accesses
720system.cpu.l2cache.overall_miss_rate::total 0.629595 # miss rate for overall accesses
721system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68752.861755 # average ReadReq miss latency
722system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77901.425178 # average ReadReq miss latency
723system.cpu.l2cache.ReadReq_avg_miss_latency::total 69759.012539 # average ReadReq miss latency
724system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68272.015656 # average ReadExReq miss latency
725system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68272.015656 # average ReadExReq miss latency
726system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68752.861755 # average overall miss latency
727system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70346.724667 # average overall miss latency
728system.cpu.l2cache.demand_avg_miss_latency::total 69333.799664 # average overall miss latency
729system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68752.861755 # average overall miss latency
730system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70346.724667 # average overall miss latency
731system.cpu.l2cache.overall_avg_miss_latency::total 69333.799664 # average overall miss latency
732system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
733system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
734system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
735system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
736system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
737system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
738system.cpu.l2cache.fast_writes 0 # number of fast writes performed
739system.cpu.l2cache.cache_copies 0 # number of cache copies performed
740system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3407 # number of ReadReq MSHR misses
741system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 421 # number of ReadReq MSHR misses
742system.cpu.l2cache.ReadReq_mshr_misses::total 3828 # number of ReadReq MSHR misses
743system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 150 # number of UpgradeReq MSHR misses
744system.cpu.l2cache.UpgradeReq_mshr_misses::total 150 # number of UpgradeReq MSHR misses
745system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1533 # number of ReadExReq MSHR misses
746system.cpu.l2cache.ReadExReq_mshr_misses::total 1533 # number of ReadExReq MSHR misses
747system.cpu.l2cache.demand_mshr_misses::cpu.inst 3407 # number of demand (read+write) MSHR misses
748system.cpu.l2cache.demand_mshr_misses::cpu.data 1954 # number of demand (read+write) MSHR misses
749system.cpu.l2cache.demand_mshr_misses::total 5361 # number of demand (read+write) MSHR misses
750system.cpu.l2cache.overall_mshr_misses::cpu.inst 3407 # number of overall MSHR misses
751system.cpu.l2cache.overall_mshr_misses::cpu.data 1954 # number of overall MSHR misses
752system.cpu.l2cache.overall_mshr_misses::total 5361 # number of overall MSHR misses
753system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 191583500 # number of ReadReq MSHR miss cycles
754system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27592500 # number of ReadReq MSHR miss cycles
755system.cpu.l2cache.ReadReq_mshr_miss_latency::total 219176000 # number of ReadReq MSHR miss cycles
756system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1500150 # number of UpgradeReq MSHR miss cycles
757system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1500150 # number of UpgradeReq MSHR miss cycles
758system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 85063500 # number of ReadExReq MSHR miss cycles
759system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 85063500 # number of ReadExReq MSHR miss cycles
760system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 191583500 # number of demand (read+write) MSHR miss cycles
761system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 112656000 # number of demand (read+write) MSHR miss cycles
762system.cpu.l2cache.demand_mshr_miss_latency::total 304239500 # number of demand (read+write) MSHR miss cycles
763system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 191583500 # number of overall MSHR miss cycles
764system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 112656000 # number of overall MSHR miss cycles
765system.cpu.l2cache.overall_mshr_miss_latency::total 304239500 # number of overall MSHR miss cycles
766system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.522787 # mshr miss rate for ReadReq accesses
767system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.921225 # mshr miss rate for ReadReq accesses
768system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.548896 # mshr miss rate for ReadReq accesses
769system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
770system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
771system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994809 # mshr miss rate for ReadExReq accesses
772system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994809 # mshr miss rate for ReadExReq accesses
773system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.522787 # mshr miss rate for demand accesses
774system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.977978 # mshr miss rate for demand accesses
775system.cpu.l2cache.demand_mshr_miss_rate::total 0.629595 # mshr miss rate for demand accesses
776system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.522787 # mshr miss rate for overall accesses
777system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.977978 # mshr miss rate for overall accesses
778system.cpu.l2cache.overall_mshr_miss_rate::total 0.629595 # mshr miss rate for overall accesses
779system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56232.315820 # average ReadReq mshr miss latency
780system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65540.380048 # average ReadReq mshr miss latency
781system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57256.008359 # average ReadReq mshr miss latency
782system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
783system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
784system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55488.258317 # average ReadExReq mshr miss latency
785system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55488.258317 # average ReadExReq mshr miss latency
786system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56232.315820 # average overall mshr miss latency
787system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57654.042989 # average overall mshr miss latency
788system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56750.512964 # average overall mshr miss latency
789system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56232.315820 # average overall mshr miss latency
790system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57654.042989 # average overall mshr miss latency
791system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56750.512964 # average overall mshr miss latency
792system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
793system.cpu.dcache.tags.replacements 57 # number of replacements
794system.cpu.dcache.tags.tagsinuse 1432.023881 # Cycle average of tags in use
795system.cpu.dcache.tags.total_refs 66143701 # Total number of references to valid blocks.
796system.cpu.dcache.tags.sampled_refs 1995 # Sample count of references to valid blocks.
797system.cpu.dcache.tags.avg_refs 33154.737343 # Average number of references to valid blocks.
798system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
799system.cpu.dcache.tags.occ_blocks::cpu.data 1432.023881 # Average occupied blocks per requestor
800system.cpu.dcache.tags.occ_percent::cpu.data 0.349615 # Average percentage of cache occupancy
801system.cpu.dcache.tags.occ_percent::total 0.349615 # Average percentage of cache occupancy
802system.cpu.dcache.tags.occ_task_id_blocks::1024 1938 # Occupied blocks per task id
803system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id
804system.cpu.dcache.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id
805system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
806system.cpu.dcache.tags.age_task_id_blocks_1024::3 427 # Occupied blocks per task id
807system.cpu.dcache.tags.age_task_id_blocks_1024::4 1393 # Occupied blocks per task id
808system.cpu.dcache.tags.occ_task_id_percent::1024 0.473145 # Percentage of cache occupancy per task id
809system.cpu.dcache.tags.tag_accesses 132294203 # Number of tag accesses
810system.cpu.dcache.tags.data_accesses 132294203 # Number of data accesses
811system.cpu.dcache.ReadReq_hits::cpu.data 45629460 # number of ReadReq hits
812system.cpu.dcache.ReadReq_hits::total 45629460 # number of ReadReq hits
813system.cpu.dcache.WriteReq_hits::cpu.data 20514040 # number of WriteReq hits
814system.cpu.dcache.WriteReq_hits::total 20514040 # number of WriteReq hits
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816system.cpu.dcache.demand_hits::total 66143500 # number of demand (read+write) hits
817system.cpu.dcache.overall_hits::cpu.data 66143500 # number of overall hits
818system.cpu.dcache.overall_hits::total 66143500 # number of overall hits
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820system.cpu.dcache.ReadReq_misses::total 913 # number of ReadReq misses
821system.cpu.dcache.WriteReq_misses::cpu.data 1691 # number of WriteReq misses
822system.cpu.dcache.WriteReq_misses::total 1691 # number of WriteReq misses
823system.cpu.dcache.demand_misses::cpu.data 2604 # number of demand (read+write) misses
824system.cpu.dcache.demand_misses::total 2604 # number of demand (read+write) misses
825system.cpu.dcache.overall_misses::cpu.data 2604 # number of overall misses
826system.cpu.dcache.overall_misses::total 2604 # number of overall misses
827system.cpu.dcache.ReadReq_miss_latency::cpu.data 59632801 # number of ReadReq miss cycles
828system.cpu.dcache.ReadReq_miss_latency::total 59632801 # number of ReadReq miss cycles
829system.cpu.dcache.WriteReq_miss_latency::cpu.data 113805150 # number of WriteReq miss cycles
830system.cpu.dcache.WriteReq_miss_latency::total 113805150 # number of WriteReq miss cycles
831system.cpu.dcache.demand_miss_latency::cpu.data 173437951 # number of demand (read+write) miss cycles
832system.cpu.dcache.demand_miss_latency::total 173437951 # number of demand (read+write) miss cycles
833system.cpu.dcache.overall_miss_latency::cpu.data 173437951 # number of overall miss cycles
834system.cpu.dcache.overall_miss_latency::total 173437951 # number of overall miss cycles
835system.cpu.dcache.ReadReq_accesses::cpu.data 45630373 # number of ReadReq accesses(hits+misses)
836system.cpu.dcache.ReadReq_accesses::total 45630373 # number of ReadReq accesses(hits+misses)
837system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
838system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
839system.cpu.dcache.demand_accesses::cpu.data 66146104 # number of demand (read+write) accesses
840system.cpu.dcache.demand_accesses::total 66146104 # number of demand (read+write) accesses
841system.cpu.dcache.overall_accesses::cpu.data 66146104 # number of overall (read+write) accesses
842system.cpu.dcache.overall_accesses::total 66146104 # number of overall (read+write) accesses
843system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses
844system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses
845system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000082 # miss rate for WriteReq accesses
846system.cpu.dcache.WriteReq_miss_rate::total 0.000082 # miss rate for WriteReq accesses
847system.cpu.dcache.demand_miss_rate::cpu.data 0.000039 # miss rate for demand accesses
848system.cpu.dcache.demand_miss_rate::total 0.000039 # miss rate for demand accesses
849system.cpu.dcache.overall_miss_rate::cpu.data 0.000039 # miss rate for overall accesses
850system.cpu.dcache.overall_miss_rate::total 0.000039 # miss rate for overall accesses
851system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65315.225630 # average ReadReq miss latency
852system.cpu.dcache.ReadReq_avg_miss_latency::total 65315.225630 # average ReadReq miss latency
853system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67300.502661 # average WriteReq miss latency
854system.cpu.dcache.WriteReq_avg_miss_latency::total 67300.502661 # average WriteReq miss latency
855system.cpu.dcache.demand_avg_miss_latency::cpu.data 66604.435868 # average overall miss latency
856system.cpu.dcache.demand_avg_miss_latency::total 66604.435868 # average overall miss latency
857system.cpu.dcache.overall_avg_miss_latency::cpu.data 66604.435868 # average overall miss latency
858system.cpu.dcache.overall_avg_miss_latency::total 66604.435868 # average overall miss latency
859system.cpu.dcache.blocked_cycles::no_mshrs 319 # number of cycles access was blocked
860system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
861system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked
862system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
863system.cpu.dcache.avg_blocked_cycles::no_mshrs 79.750000 # average number of cycles each access was blocked
864system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
865system.cpu.dcache.fast_writes 0 # number of fast writes performed
866system.cpu.dcache.cache_copies 0 # number of cache copies performed
867system.cpu.dcache.writebacks::writebacks 15 # number of writebacks
868system.cpu.dcache.writebacks::total 15 # number of writebacks
869system.cpu.dcache.ReadReq_mshr_hits::cpu.data 455 # number of ReadReq MSHR hits
870system.cpu.dcache.ReadReq_mshr_hits::total 455 # number of ReadReq MSHR hits
871system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits
872system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits
873system.cpu.dcache.demand_mshr_hits::cpu.data 456 # number of demand (read+write) MSHR hits
874system.cpu.dcache.demand_mshr_hits::total 456 # number of demand (read+write) MSHR hits
875system.cpu.dcache.overall_mshr_hits::cpu.data 456 # number of overall MSHR hits
876system.cpu.dcache.overall_mshr_hits::total 456 # number of overall MSHR hits
877system.cpu.dcache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses
878system.cpu.dcache.ReadReq_mshr_misses::total 458 # number of ReadReq MSHR misses
879system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1690 # number of WriteReq MSHR misses
880system.cpu.dcache.WriteReq_mshr_misses::total 1690 # number of WriteReq MSHR misses
881system.cpu.dcache.demand_mshr_misses::cpu.data 2148 # number of demand (read+write) MSHR misses
882system.cpu.dcache.demand_mshr_misses::total 2148 # number of demand (read+write) MSHR misses
883system.cpu.dcache.overall_mshr_misses::cpu.data 2148 # number of overall MSHR misses
884system.cpu.dcache.overall_mshr_misses::total 2148 # number of overall MSHR misses
885system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33615250 # number of ReadReq MSHR miss cycles
886system.cpu.dcache.ReadReq_mshr_miss_latency::total 33615250 # number of ReadReq MSHR miss cycles
887system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 109709600 # number of WriteReq MSHR miss cycles
888system.cpu.dcache.WriteReq_mshr_miss_latency::total 109709600 # number of WriteReq MSHR miss cycles
889system.cpu.dcache.demand_mshr_miss_latency::cpu.data 143324850 # number of demand (read+write) MSHR miss cycles
890system.cpu.dcache.demand_mshr_miss_latency::total 143324850 # number of demand (read+write) MSHR miss cycles
891system.cpu.dcache.overall_mshr_miss_latency::cpu.data 143324850 # number of overall MSHR miss cycles
892system.cpu.dcache.overall_mshr_miss_latency::total 143324850 # number of overall MSHR miss cycles
893system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
894system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
895system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000082 # mshr miss rate for WriteReq accesses
896system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000082 # mshr miss rate for WriteReq accesses
897system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses
898system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses
899system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses
900system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses
901system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73395.742358 # average ReadReq mshr miss latency
902system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73395.742358 # average ReadReq mshr miss latency
903system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64916.923077 # average WriteReq mshr miss latency
904system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64916.923077 # average WriteReq mshr miss latency
905system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66724.790503 # average overall mshr miss latency
906system.cpu.dcache.demand_avg_mshr_miss_latency::total 66724.790503 # average overall mshr miss latency
907system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66724.790503 # average overall mshr miss latency
908system.cpu.dcache.overall_avg_mshr_miss_latency::total 66724.790503 # average overall mshr miss latency
909system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
910
911---------- End Simulation Statistics ----------