1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.144463 # Number of seconds simulated
4sim_ticks 144463317000 # Number of ticks simulated
5final_tick 144463317000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 66822 # Simulator instruction rate (inst/s)
8host_op_rate 111999 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 73091533 # Simulator tick rate (ticks/s)
10host_mem_usage 308580 # Number of bytes of host memory used
11host_seconds 1976.47 # Real time elapsed on the host
12sim_insts 132071192 # Number of instructions simulated
13sim_ops 221363384 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 217088 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 125568 # Number of bytes read from this memory
16system.physmem.bytes_read::total 342656 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 217088 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 217088 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 3392 # Number of read requests responded to by this memory
20system.physmem.num_reads::cpu.data 1962 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 5354 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 1502721 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 869203 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 2371924 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 1502721 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 1502721 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 1502721 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 869203 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 2371924 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.readReqs 5354 # Number of read requests accepted
31system.physmem.writeReqs 0 # Number of write requests accepted
32system.physmem.readBursts 5354 # Number of DRAM read bursts, including those serviced by the write queue
33system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
34system.physmem.bytesReadDRAM 342656 # Total number of bytes read from DRAM
35system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
36system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
37system.physmem.bytesReadSys 342656 # Total read bytes from the system interface side
38system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
39system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
40system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
41system.physmem.neitherReadNorWriteReqs 163 # Number of requests that are neither read nor write
42system.physmem.perBankRdBursts::0 289 # Per bank write bursts
43system.physmem.perBankRdBursts::1 357 # Per bank write bursts
44system.physmem.perBankRdBursts::2 453 # Per bank write bursts
45system.physmem.perBankRdBursts::3 356 # Per bank write bursts
46system.physmem.perBankRdBursts::4 332 # Per bank write bursts
47system.physmem.perBankRdBursts::5 326 # Per bank write bursts
48system.physmem.perBankRdBursts::6 402 # Per bank write bursts
49system.physmem.perBankRdBursts::7 377 # Per bank write bursts
50system.physmem.perBankRdBursts::8 341 # Per bank write bursts
51system.physmem.perBankRdBursts::9 276 # Per bank write bursts
52system.physmem.perBankRdBursts::10 232 # Per bank write bursts
53system.physmem.perBankRdBursts::11 277 # Per bank write bursts
54system.physmem.perBankRdBursts::12 205 # Per bank write bursts
55system.physmem.perBankRdBursts::13 465 # Per bank write bursts
56system.physmem.perBankRdBursts::14 384 # Per bank write bursts
57system.physmem.perBankRdBursts::15 282 # Per bank write bursts
58system.physmem.perBankWrBursts::0 0 # Per bank write bursts
59system.physmem.perBankWrBursts::1 0 # Per bank write bursts
60system.physmem.perBankWrBursts::2 0 # Per bank write bursts
61system.physmem.perBankWrBursts::3 0 # Per bank write bursts
62system.physmem.perBankWrBursts::4 0 # Per bank write bursts
63system.physmem.perBankWrBursts::5 0 # Per bank write bursts
64system.physmem.perBankWrBursts::6 0 # Per bank write bursts
65system.physmem.perBankWrBursts::7 0 # Per bank write bursts
66system.physmem.perBankWrBursts::8 0 # Per bank write bursts
67system.physmem.perBankWrBursts::9 0 # Per bank write bursts
68system.physmem.perBankWrBursts::10 0 # Per bank write bursts
69system.physmem.perBankWrBursts::11 0 # Per bank write bursts
70system.physmem.perBankWrBursts::12 0 # Per bank write bursts
71system.physmem.perBankWrBursts::13 0 # Per bank write bursts
72system.physmem.perBankWrBursts::14 0 # Per bank write bursts
73system.physmem.perBankWrBursts::15 0 # Per bank write bursts
74system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
75system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
76system.physmem.totGap 144463266500 # Total gap between requests
77system.physmem.readPktSize::0 0 # Read request sizes (log2)
78system.physmem.readPktSize::1 0 # Read request sizes (log2)
79system.physmem.readPktSize::2 0 # Read request sizes (log2)
80system.physmem.readPktSize::3 0 # Read request sizes (log2)
81system.physmem.readPktSize::4 0 # Read request sizes (log2)
82system.physmem.readPktSize::5 0 # Read request sizes (log2)
83system.physmem.readPktSize::6 5354 # Read request sizes (log2)
84system.physmem.writePktSize::0 0 # Write request sizes (log2)
85system.physmem.writePktSize::1 0 # Write request sizes (log2)
86system.physmem.writePktSize::2 0 # Write request sizes (log2)
87system.physmem.writePktSize::3 0 # Write request sizes (log2)
88system.physmem.writePktSize::4 0 # Write request sizes (log2)
89system.physmem.writePktSize::5 0 # Write request sizes (log2)
90system.physmem.writePktSize::6 0 # Write request sizes (log2)
91system.physmem.rdQLenPdf::0 4302 # What read queue length does an incoming req see
92system.physmem.rdQLenPdf::1 874 # What read queue length does an incoming req see
93system.physmem.rdQLenPdf::2 155 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see

--- 42 unchanged lines hidden (view full) ---

147system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
155system.physmem.bytesPerActivate::samples 957 # Bytes accessed per row activation
156system.physmem.bytesPerActivate::mean 353.103448 # Bytes accessed per row activation
157system.physmem.bytesPerActivate::gmean 172.307957 # Bytes accessed per row activation
158system.physmem.bytesPerActivate::stdev 612.115437 # Bytes accessed per row activation
159system.physmem.bytesPerActivate::64 385 40.23% 40.23% # Bytes accessed per row activation
160system.physmem.bytesPerActivate::128 164 17.14% 57.37% # Bytes accessed per row activation
161system.physmem.bytesPerActivate::192 81 8.46% 65.83% # Bytes accessed per row activation
162system.physmem.bytesPerActivate::256 46 4.81% 70.64% # Bytes accessed per row activation
163system.physmem.bytesPerActivate::320 43 4.49% 75.13% # Bytes accessed per row activation
164system.physmem.bytesPerActivate::384 20 2.09% 77.22% # Bytes accessed per row activation
165system.physmem.bytesPerActivate::448 26 2.72% 79.94% # Bytes accessed per row activation
166system.physmem.bytesPerActivate::512 19 1.99% 81.92% # Bytes accessed per row activation
167system.physmem.bytesPerActivate::576 17 1.78% 83.70% # Bytes accessed per row activation
168system.physmem.bytesPerActivate::640 26 2.72% 86.42% # Bytes accessed per row activation
169system.physmem.bytesPerActivate::704 27 2.82% 89.24% # Bytes accessed per row activation
170system.physmem.bytesPerActivate::768 7 0.73% 89.97% # Bytes accessed per row activation
171system.physmem.bytesPerActivate::832 7 0.73% 90.70% # Bytes accessed per row activation
172system.physmem.bytesPerActivate::896 7 0.73% 91.43% # Bytes accessed per row activation
173system.physmem.bytesPerActivate::960 3 0.31% 91.75% # Bytes accessed per row activation
174system.physmem.bytesPerActivate::1024 5 0.52% 92.27% # Bytes accessed per row activation
175system.physmem.bytesPerActivate::1088 6 0.63% 92.89% # Bytes accessed per row activation
176system.physmem.bytesPerActivate::1152 6 0.63% 93.52% # Bytes accessed per row activation
177system.physmem.bytesPerActivate::1216 4 0.42% 93.94% # Bytes accessed per row activation
178system.physmem.bytesPerActivate::1280 2 0.21% 94.15% # Bytes accessed per row activation
179system.physmem.bytesPerActivate::1344 2 0.21% 94.36% # Bytes accessed per row activation
180system.physmem.bytesPerActivate::1408 3 0.31% 94.67% # Bytes accessed per row activation
181system.physmem.bytesPerActivate::1472 7 0.73% 95.40% # Bytes accessed per row activation
182system.physmem.bytesPerActivate::1536 1 0.10% 95.51% # Bytes accessed per row activation
183system.physmem.bytesPerActivate::1600 5 0.52% 96.03% # Bytes accessed per row activation
184system.physmem.bytesPerActivate::1664 4 0.42% 96.45% # Bytes accessed per row activation
185system.physmem.bytesPerActivate::1728 2 0.21% 96.66% # Bytes accessed per row activation
186system.physmem.bytesPerActivate::1792 2 0.21% 96.87% # Bytes accessed per row activation
187system.physmem.bytesPerActivate::1856 2 0.21% 97.07% # Bytes accessed per row activation
188system.physmem.bytesPerActivate::1920 3 0.31% 97.39% # Bytes accessed per row activation
189system.physmem.bytesPerActivate::1984 2 0.21% 97.60% # Bytes accessed per row activation
190system.physmem.bytesPerActivate::2112 1 0.10% 97.70% # Bytes accessed per row activation
191system.physmem.bytesPerActivate::2176 1 0.10% 97.81% # Bytes accessed per row activation
192system.physmem.bytesPerActivate::2240 1 0.10% 97.91% # Bytes accessed per row activation
193system.physmem.bytesPerActivate::2304 1 0.10% 98.01% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::2368 1 0.10% 98.12% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::2432 2 0.21% 98.33% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::2496 1 0.10% 98.43% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::2816 2 0.21% 98.64% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::2880 3 0.31% 98.96% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::3072 1 0.10% 99.06% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::3328 1 0.10% 99.16% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::3456 1 0.10% 99.27% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::3584 1 0.10% 99.37% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::4160 1 0.10% 99.48% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::4352 1 0.10% 99.58% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::4736 1 0.10% 99.69% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::5312 1 0.10% 99.79% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::5696 1 0.10% 99.90% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::5952 1 0.10% 100.00% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::total 957 # Bytes accessed per row activation
210system.physmem.totQLat 28805000 # Total ticks spent queuing
211system.physmem.totMemAccLat 137868750 # Total ticks spent from burst creation until serviced by the DRAM
212system.physmem.totBusLat 26770000 # Total ticks spent in databus transfers
213system.physmem.totBankLat 82293750 # Total ticks spent accessing banks
214system.physmem.avgQLat 5380.09 # Average queueing delay per DRAM burst
215system.physmem.avgBankLat 15370.52 # Average bank access latency per DRAM burst
216system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
217system.physmem.avgMemAccLat 25750.61 # Average memory access latency per DRAM burst
218system.physmem.avgRdBW 2.37 # Average DRAM read bandwidth in MiByte/s
219system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
220system.physmem.avgRdBWSys 2.37 # Average system read bandwidth in MiByte/s
221system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
222system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
223system.physmem.busUtil 0.02 # Data bus utilization in percentage
224system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
225system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
226system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing
227system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
228system.physmem.readRowHits 4397 # Number of row buffer hits during reads
229system.physmem.writeRowHits 0 # Number of row buffer hits during writes
230system.physmem.readRowHitRate 82.13 # Row buffer hit rate for reads
231system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
232system.physmem.avgGap 26982306.03 # Average gap between requests
233system.physmem.pageHitRate 82.13 # Row buffer hit rate, read and write combined
234system.physmem.prechargeAllPercent 0.41 # Percentage of time for which DRAM has all the banks in precharge state
235system.membus.throughput 2371924 # Throughput (bytes/s)
236system.membus.trans_dist::ReadReq 3822 # Transaction distribution
237system.membus.trans_dist::ReadResp 3822 # Transaction distribution
238system.membus.trans_dist::UpgradeReq 163 # Transaction distribution
239system.membus.trans_dist::UpgradeResp 163 # Transaction distribution
240system.membus.trans_dist::ReadExReq 1532 # Transaction distribution
241system.membus.trans_dist::ReadExResp 1532 # Transaction distribution
242system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11034 # Packet count per connected master and slave (bytes)
243system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11034 # Packet count per connected master and slave (bytes)
244system.membus.pkt_count::total 11034 # Packet count per connected master and slave (bytes)
245system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 342656 # Cumulative packet size per connected master and slave (bytes)
246system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342656 # Cumulative packet size per connected master and slave (bytes)
247system.membus.tot_pkt_size::total 342656 # Cumulative packet size per connected master and slave (bytes)
248system.membus.data_through_bus 342656 # Total data (bytes)
249system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
250system.membus.reqLayer0.occupancy 6948500 # Layer occupancy (ticks)
251system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
252system.membus.respLayer1.occupancy 50662837 # Layer occupancy (ticks)
253system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
254system.cpu.branchPred.lookups 18648234 # Number of BP lookups
255system.cpu.branchPred.condPredicted 18648234 # Number of conditional branches predicted
256system.cpu.branchPred.condIncorrect 1490176 # Number of conditional branches incorrect
257system.cpu.branchPred.BTBLookups 11407549 # Number of BTB lookups
258system.cpu.branchPred.BTBHits 10790529 # Number of BTB hits
259system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
260system.cpu.branchPred.BTBHitPct 94.591126 # BTB Hit Percentage
261system.cpu.branchPred.usedRAS 1320367 # Number of times the RAS was used to get a target.
262system.cpu.branchPred.RASInCorrect 22841 # Number of incorrect RAS predictions.
263system.cpu.workload.num_syscalls 400 # Number of system calls
264system.cpu.numCycles 289221873 # number of cpu cycles simulated
265system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
266system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
267system.cpu.fetch.icacheStallCycles 23458037 # Number of cycles fetch is stalled on an Icache miss
268system.cpu.fetch.Insts 206724223 # Number of instructions fetch has processed
269system.cpu.fetch.Branches 18648234 # Number of branches that fetch encountered
270system.cpu.fetch.predictedBranches 12110896 # Number of branches that fetch has predicted taken
271system.cpu.fetch.Cycles 54209099 # Number of cycles fetch has run and was not squashing or blocked
272system.cpu.fetch.SquashCycles 15518775 # Number of cycles fetch has spent squashing
273system.cpu.fetch.BlockedCycles 178161359 # Number of cycles fetch has spent blocked
274system.cpu.fetch.MiscStallCycles 1571 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
275system.cpu.fetch.PendingTrapStallCycles 9111 # Number of stall cycles due to pending traps
276system.cpu.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR
277system.cpu.fetch.CacheLines 22353213 # Number of cache lines fetched
278system.cpu.fetch.IcacheSquashes 224062 # Number of outstanding Icache misses that were squashed
279system.cpu.fetch.rateDist::samples 269612466 # Number of instructions fetched each cycle (Total)
280system.cpu.fetch.rateDist::mean 1.268180 # Number of instructions fetched each cycle (Total)
281system.cpu.fetch.rateDist::stdev 2.756310 # Number of instructions fetched each cycle (Total)
282system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
283system.cpu.fetch.rateDist::0 216842558 80.43% 80.43% # Number of instructions fetched each cycle (Total)
284system.cpu.fetch.rateDist::1 2848142 1.06% 81.48% # Number of instructions fetched each cycle (Total)
285system.cpu.fetch.rateDist::2 2312056 0.86% 82.34% # Number of instructions fetched each cycle (Total)
286system.cpu.fetch.rateDist::3 2633842 0.98% 83.32% # Number of instructions fetched each cycle (Total)
287system.cpu.fetch.rateDist::4 3218714 1.19% 84.51% # Number of instructions fetched each cycle (Total)
288system.cpu.fetch.rateDist::5 3388946 1.26% 85.77% # Number of instructions fetched each cycle (Total)
289system.cpu.fetch.rateDist::6 3831195 1.42% 87.19% # Number of instructions fetched each cycle (Total)
290system.cpu.fetch.rateDist::7 2559437 0.95% 88.14% # Number of instructions fetched each cycle (Total)
291system.cpu.fetch.rateDist::8 31977576 11.86% 100.00% # Number of instructions fetched each cycle (Total)
292system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
293system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
294system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
295system.cpu.fetch.rateDist::total 269612466 # Number of instructions fetched each cycle (Total)
296system.cpu.fetch.branchRate 0.064477 # Number of branch fetches per cycle
297system.cpu.fetch.rate 0.714760 # Number of inst fetches per cycle
298system.cpu.decode.IdleCycles 36899349 # Number of cycles decode is idle
299system.cpu.decode.BlockedCycles 167130008 # Number of cycles decode is blocked
300system.cpu.decode.RunCycles 41545231 # Number of cycles decode is running
301system.cpu.decode.UnblockCycles 10264627 # Number of cycles decode is unblocking
302system.cpu.decode.SquashCycles 13773251 # Number of cycles decode is squashing
303system.cpu.decode.DecodedInsts 336001478 # Number of instructions handled by decode
304system.cpu.rename.SquashCycles 13773251 # Number of cycles rename is squashing
305system.cpu.rename.IdleCycles 44972476 # Number of cycles rename is idle
306system.cpu.rename.BlockCycles 116686700 # Number of cycles rename is blocking
307system.cpu.rename.serializeStallCycles 32545 # count of cycles rename stalled for serializing inst
308system.cpu.rename.RunCycles 42701692 # Number of cycles rename is running
309system.cpu.rename.UnblockCycles 51445802 # Number of cycles rename is unblocking
310system.cpu.rename.RenamedInsts 329633797 # Number of instructions processed by rename
311system.cpu.rename.ROBFullEvents 10827 # Number of times rename has blocked due to ROB full
312system.cpu.rename.IQFullEvents 26123597 # Number of times rename has blocked due to IQ full
313system.cpu.rename.LSQFullEvents 22730551 # Number of times rename has blocked due to LSQ full
314system.cpu.rename.RenamedOperands 382342114 # Number of destination operands rename has renamed
315system.cpu.rename.RenameLookups 917586762 # Number of register rename lookups that rename has made
316system.cpu.rename.int_rename_lookups 605878307 # Number of integer rename lookups
317system.cpu.rename.fp_rename_lookups 4127660 # Number of floating rename lookups
318system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed
319system.cpu.rename.UndoneMaps 122912664 # Number of HB maps that are undone due to squashing
320system.cpu.rename.serializingInsts 2051 # count of serializing insts renamed
321system.cpu.rename.tempSerializingInsts 2042 # count of temporary serializing insts renamed
322system.cpu.rename.skidInsts 105140053 # count of insts added to the skid buffer
323system.cpu.memDep0.insertedLoads 84507278 # Number of loads inserted to the mem dependence unit.
324system.cpu.memDep0.insertedStores 30107186 # Number of stores inserted to the mem dependence unit.
325system.cpu.memDep0.conflictingLoads 58355212 # Number of conflicting loads.
326system.cpu.memDep0.conflictingStores 18979888 # Number of conflicting stores.
327system.cpu.iq.iqInstsAdded 322730912 # Number of instructions added to the IQ (excludes non-spec)
328system.cpu.iq.iqNonSpecInstsAdded 4069 # Number of non-speculative instructions added to the IQ
329system.cpu.iq.iqInstsIssued 260501997 # Number of instructions issued
330system.cpu.iq.iqSquashedInstsIssued 116055 # Number of squashed instructions issued
331system.cpu.iq.iqSquashedInstsExamined 100987198 # Number of squashed instructions iterated over during squash; mainly for profiling
332system.cpu.iq.iqSquashedOperandsExamined 210203666 # Number of squashed operands that are examined and possibly removed from graph
333system.cpu.iq.iqSquashedNonSpecRemoved 2824 # Number of squashed non-spec instructions that were removed
334system.cpu.iq.issued_per_cycle::samples 269612466 # Number of insts issued each cycle
335system.cpu.iq.issued_per_cycle::mean 0.966209 # Number of insts issued each cycle
336system.cpu.iq.issued_per_cycle::stdev 1.343680 # Number of insts issued each cycle
337system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
338system.cpu.iq.issued_per_cycle::0 143429906 53.20% 53.20% # Number of insts issued each cycle
339system.cpu.iq.issued_per_cycle::1 55567349 20.61% 73.81% # Number of insts issued each cycle
340system.cpu.iq.issued_per_cycle::2 34108146 12.65% 86.46% # Number of insts issued each cycle
341system.cpu.iq.issued_per_cycle::3 19044984 7.06% 93.52% # Number of insts issued each cycle
342system.cpu.iq.issued_per_cycle::4 10887633 4.04% 97.56% # Number of insts issued each cycle
343system.cpu.iq.issued_per_cycle::5 4152281 1.54% 99.10% # Number of insts issued each cycle
344system.cpu.iq.issued_per_cycle::6 1816698 0.67% 99.78% # Number of insts issued each cycle
345system.cpu.iq.issued_per_cycle::7 472473 0.18% 99.95% # Number of insts issued each cycle
346system.cpu.iq.issued_per_cycle::8 132996 0.05% 100.00% # Number of insts issued each cycle
347system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
348system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
349system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
350system.cpu.iq.issued_per_cycle::total 269612466 # Number of insts issued each cycle
351system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
352system.cpu.iq.fu_full::IntAlu 130605 4.82% 4.82% # attempts to use FU when none available
353system.cpu.iq.fu_full::IntMult 0 0.00% 4.82% # attempts to use FU when none available
354system.cpu.iq.fu_full::IntDiv 0 0.00% 4.82% # attempts to use FU when none available
355system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.82% # attempts to use FU when none available
356system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.82% # attempts to use FU when none available
357system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.82% # attempts to use FU when none available
358system.cpu.iq.fu_full::FloatMult 0 0.00% 4.82% # attempts to use FU when none available
359system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.82% # attempts to use FU when none available
360system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.82% # attempts to use FU when none available
361system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.82% # attempts to use FU when none available
362system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.82% # attempts to use FU when none available
363system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.82% # attempts to use FU when none available
364system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.82% # attempts to use FU when none available
365system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.82% # attempts to use FU when none available
366system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.82% # attempts to use FU when none available
367system.cpu.iq.fu_full::SimdMult 0 0.00% 4.82% # attempts to use FU when none available
368system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.82% # attempts to use FU when none available
369system.cpu.iq.fu_full::SimdShift 0 0.00% 4.82% # attempts to use FU when none available
370system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.82% # attempts to use FU when none available
371system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.82% # attempts to use FU when none available
372system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.82% # attempts to use FU when none available
373system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.82% # attempts to use FU when none available
374system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.82% # attempts to use FU when none available
375system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.82% # attempts to use FU when none available
376system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.82% # attempts to use FU when none available
377system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.82% # attempts to use FU when none available
378system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.82% # attempts to use FU when none available
379system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.82% # attempts to use FU when none available
380system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.82% # attempts to use FU when none available
381system.cpu.iq.fu_full::MemRead 2279077 84.03% 88.85% # attempts to use FU when none available
382system.cpu.iq.fu_full::MemWrite 302412 11.15% 100.00% # attempts to use FU when none available
383system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
384system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
385system.cpu.iq.FU_type_0::No_OpClass 1210810 0.46% 0.46% # Type of FU issued
386system.cpu.iq.FU_type_0::IntAlu 162055945 62.21% 62.67% # Type of FU issued
387system.cpu.iq.FU_type_0::IntMult 789191 0.30% 62.98% # Type of FU issued
388system.cpu.iq.FU_type_0::IntDiv 7035649 2.70% 65.68% # Type of FU issued
389system.cpu.iq.FU_type_0::FloatAdd 1445882 0.56% 66.23% # Type of FU issued
390system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.23% # Type of FU issued
391system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.23% # Type of FU issued
392system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.23% # Type of FU issued
393system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.23% # Type of FU issued
394system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.23% # Type of FU issued
395system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.23% # Type of FU issued
396system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.23% # Type of FU issued
397system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.23% # Type of FU issued
398system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.23% # Type of FU issued
399system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.23% # Type of FU issued
400system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.23% # Type of FU issued
401system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.23% # Type of FU issued
402system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.23% # Type of FU issued
403system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.23% # Type of FU issued
404system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.23% # Type of FU issued
405system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.23% # Type of FU issued
406system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.23% # Type of FU issued
407system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.23% # Type of FU issued
408system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.23% # Type of FU issued
409system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.23% # Type of FU issued
410system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.23% # Type of FU issued
411system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.23% # Type of FU issued
412system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.23% # Type of FU issued
413system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.23% # Type of FU issued
414system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.23% # Type of FU issued
415system.cpu.iq.FU_type_0::MemRead 65414515 25.11% 91.34% # Type of FU issued
416system.cpu.iq.FU_type_0::MemWrite 22550005 8.66% 100.00% # Type of FU issued
417system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
418system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
419system.cpu.iq.FU_type_0::total 260501997 # Type of FU issued
420system.cpu.iq.rate 0.900700 # Inst issue rate
421system.cpu.iq.fu_busy_cnt 2712094 # FU busy when requested
422system.cpu.iq.fu_busy_rate 0.010411 # FU busy rate (busy events/executed inst)
423system.cpu.iq.int_inst_queue_reads 788557581 # Number of integer instruction queue reads
424system.cpu.iq.int_inst_queue_writes 420384882 # Number of integer instruction queue writes
425system.cpu.iq.int_inst_queue_wakeup_accesses 255147074 # Number of integer instruction queue wakeup accesses
426system.cpu.iq.fp_inst_queue_reads 4887028 # Number of floating instruction queue reads
427system.cpu.iq.fp_inst_queue_writes 3615221 # Number of floating instruction queue writes
428system.cpu.iq.fp_inst_queue_wakeup_accesses 2349564 # Number of floating instruction queue wakeup accesses
429system.cpu.iq.int_alu_accesses 259544029 # Number of integer alu accesses
430system.cpu.iq.fp_alu_accesses 2459252 # Number of floating point alu accesses
431system.cpu.iew.lsq.thread0.forwLoads 18903383 # Number of loads that had data forwarded from stores
432system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
433system.cpu.iew.lsq.thread0.squashedLoads 27857691 # Number of loads squashed
434system.cpu.iew.lsq.thread0.ignoredResponses 25993 # Number of memory responses ignored because the instruction is squashed
435system.cpu.iew.lsq.thread0.memOrderViolation 283319 # Number of memory ordering violations
436system.cpu.iew.lsq.thread0.squashedStores 9591469 # Number of stores squashed
437system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
438system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
439system.cpu.iew.lsq.thread0.rescheduledLoads 49752 # Number of loads that were rescheduled
440system.cpu.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked
441system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
442system.cpu.iew.iewSquashCycles 13773251 # Number of cycles IEW is squashing
443system.cpu.iew.iewBlockCycles 85040641 # Number of cycles IEW is blocking
444system.cpu.iew.iewUnblockCycles 5471570 # Number of cycles IEW is unblocking
445system.cpu.iew.iewDispatchedInsts 322734981 # Number of instructions dispatched to IQ
446system.cpu.iew.iewDispSquashedInsts 133239 # Number of squashed instructions skipped by dispatch
447system.cpu.iew.iewDispLoadInsts 84507278 # Number of dispatched load instructions
448system.cpu.iew.iewDispStoreInsts 30107186 # Number of dispatched store instructions
449system.cpu.iew.iewDispNonSpecInsts 1979 # Number of dispatched non-speculative instructions
450system.cpu.iew.iewIQFullEvents 2708196 # Number of times the IQ has become full, causing a stall
451system.cpu.iew.iewLSQFullEvents 13910 # Number of times the LSQ has become full, causing a stall
452system.cpu.iew.memOrderViolationEvents 283319 # Number of memory order violations
453system.cpu.iew.predictedTakenIncorrect 639398 # Number of branches that were predicted taken incorrectly
454system.cpu.iew.predictedNotTakenIncorrect 901241 # Number of branches that were predicted not taken incorrectly
455system.cpu.iew.branchMispredicts 1540639 # Number of branch mispredicts detected at execute
456system.cpu.iew.iewExecutedInsts 258732431 # Number of executed instructions
457system.cpu.iew.iewExecLoadInsts 64645019 # Number of load instructions executed
458system.cpu.iew.iewExecSquashedInsts 1769566 # Number of squashed instructions skipped in execute
459system.cpu.iew.exec_swp 0 # number of swp insts executed
460system.cpu.iew.exec_nop 0 # number of nop insts executed
461system.cpu.iew.exec_refs 86992194 # number of memory reference insts executed
462system.cpu.iew.exec_branches 14265860 # Number of branches executed
463system.cpu.iew.exec_stores 22347175 # Number of stores executed
464system.cpu.iew.exec_rate 0.894581 # Inst execution rate
465system.cpu.iew.wb_sent 258096694 # cumulative count of insts sent to commit
466system.cpu.iew.wb_count 257496638 # cumulative count of insts written-back
467system.cpu.iew.wb_producers 205928299 # num instructions producing a value
468system.cpu.iew.wb_consumers 369130532 # num instructions consuming a value
469system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
470system.cpu.iew.wb_rate 0.890308 # insts written-back per cycle
471system.cpu.iew.wb_fanout 0.557874 # average fanout of values written-back
472system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
473system.cpu.commit.commitSquashedInsts 101448847 # The number of squashed insts skipped by commit
474system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards
475system.cpu.commit.branchMispredicts 1491529 # The number of times a branch was mispredicted
476system.cpu.commit.committed_per_cycle::samples 255839215 # Number of insts commited each cycle
477system.cpu.commit.committed_per_cycle::mean 0.865244 # Number of insts commited each cycle
478system.cpu.commit.committed_per_cycle::stdev 1.654327 # Number of insts commited each cycle
479system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
480system.cpu.commit.committed_per_cycle::0 156486613 61.17% 61.17% # Number of insts commited each cycle
481system.cpu.commit.committed_per_cycle::1 57197635 22.36% 83.52% # Number of insts commited each cycle
482system.cpu.commit.committed_per_cycle::2 14067876 5.50% 89.02% # Number of insts commited each cycle
483system.cpu.commit.committed_per_cycle::3 12054069 4.71% 93.73% # Number of insts commited each cycle
484system.cpu.commit.committed_per_cycle::4 4176262 1.63% 95.37% # Number of insts commited each cycle
485system.cpu.commit.committed_per_cycle::5 2944385 1.15% 96.52% # Number of insts commited each cycle
486system.cpu.commit.committed_per_cycle::6 904563 0.35% 96.87% # Number of insts commited each cycle
487system.cpu.commit.committed_per_cycle::7 1049057 0.41% 97.28% # Number of insts commited each cycle
488system.cpu.commit.committed_per_cycle::8 6958755 2.72% 100.00% # Number of insts commited each cycle
489system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
490system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
491system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
492system.cpu.commit.committed_per_cycle::total 255839215 # Number of insts commited each cycle
493system.cpu.commit.committedInsts 132071192 # Number of instructions committed
494system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed
495system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
496system.cpu.commit.refs 77165304 # Number of memory references committed
497system.cpu.commit.loads 56649587 # Number of loads committed
498system.cpu.commit.membars 0 # Number of memory barriers committed
499system.cpu.commit.branches 12326938 # Number of branches committed
500system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
501system.cpu.commit.int_insts 219019985 # Number of committed integer instructions.
502system.cpu.commit.function_calls 797818 # Number of function calls committed.
503system.cpu.commit.bw_lim_events 6958755 # number cycles where commit BW limit reached
504system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
505system.cpu.rob.rob_reads 571692691 # The number of ROB reads
506system.cpu.rob.rob_writes 659422929 # The number of ROB writes
507system.cpu.timesIdled 5933064 # Number of times that the entire CPU went into an idle state and unscheduled itself
508system.cpu.idleCycles 19609407 # Total number of cycles that the CPU has spent unscheduled due to idling
509system.cpu.committedInsts 132071192 # Number of Instructions Simulated
510system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated
511system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated
512system.cpu.cpi 2.189894 # CPI: Cycles Per Instruction
513system.cpu.cpi_total 2.189894 # CPI: Total CPI of All Threads
514system.cpu.ipc 0.456643 # IPC: Instructions Per Cycle
515system.cpu.ipc_total 0.456643 # IPC: Total IPC of All Threads
516system.cpu.int_regfile_reads 451224157 # number of integer regfile reads
517system.cpu.int_regfile_writes 233957254 # number of integer regfile writes
518system.cpu.fp_regfile_reads 3215586 # number of floating regfile reads
519system.cpu.fp_regfile_writes 2009211 # number of floating regfile writes
520system.cpu.cc_regfile_reads 102809518 # number of cc regfile reads
521system.cpu.cc_regfile_writes 59799385 # number of cc regfile writes
522system.cpu.misc_regfile_reads 133324418 # number of misc regfile reads
523system.cpu.misc_regfile_writes 1689 # number of misc regfile writes
524system.cpu.toL2Bus.throughput 3898568 # Throughput (bytes/s)
525system.cpu.toL2Bus.trans_dist::ReadReq 7250 # Transaction distribution
526system.cpu.toL2Bus.trans_dist::ReadResp 7248 # Transaction distribution
527system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution
528system.cpu.toL2Bus.trans_dist::UpgradeReq 163 # Transaction distribution
529system.cpu.toL2Bus.trans_dist::UpgradeResp 163 # Transaction distribution
530system.cpu.toL2Bus.trans_dist::ReadExReq 1539 # Transaction distribution
531system.cpu.toL2Bus.trans_dist::ReadExResp 1539 # Transaction distribution
532system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13403 # Packet count per connected master and slave (bytes)
533system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4348 # Packet count per connected master and slave (bytes)
534system.cpu.toL2Bus.pkt_count::total 17751 # Packet count per connected master and slave (bytes)
535system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 423616 # Cumulative packet size per connected master and slave (bytes)
536system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129088 # Cumulative packet size per connected master and slave (bytes)
537system.cpu.toL2Bus.tot_pkt_size::total 552704 # Cumulative packet size per connected master and slave (bytes)
538system.cpu.toL2Bus.data_through_bus 552704 # Total data (bytes)
539system.cpu.toL2Bus.snoop_data_through_bus 10496 # Total snoop data (bytes)
540system.cpu.toL2Bus.reqLayer0.occupancy 4495500 # Layer occupancy (ticks)
541system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
542system.cpu.toL2Bus.respLayer0.occupancy 10760250 # Layer occupancy (ticks)
543system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
544system.cpu.toL2Bus.respLayer1.occupancy 3467413 # Layer occupancy (ticks)
545system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
546system.cpu.icache.tags.replacements 4653 # number of replacements
547system.cpu.icache.tags.tagsinuse 1619.938452 # Cycle average of tags in use
548system.cpu.icache.tags.total_refs 22344301 # Total number of references to valid blocks.
549system.cpu.icache.tags.sampled_refs 6620 # Sample count of references to valid blocks.
550system.cpu.icache.tags.avg_refs 3375.272054 # Average number of references to valid blocks.
551system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
552system.cpu.icache.tags.occ_blocks::cpu.inst 1619.938452 # Average occupied blocks per requestor
553system.cpu.icache.tags.occ_percent::cpu.inst 0.790986 # Average percentage of cache occupancy
554system.cpu.icache.tags.occ_percent::total 0.790986 # Average percentage of cache occupancy
555system.cpu.icache.ReadReq_hits::cpu.inst 22344301 # number of ReadReq hits
556system.cpu.icache.ReadReq_hits::total 22344301 # number of ReadReq hits
557system.cpu.icache.demand_hits::cpu.inst 22344301 # number of demand (read+write) hits
558system.cpu.icache.demand_hits::total 22344301 # number of demand (read+write) hits
559system.cpu.icache.overall_hits::cpu.inst 22344301 # number of overall hits
560system.cpu.icache.overall_hits::total 22344301 # number of overall hits
561system.cpu.icache.ReadReq_misses::cpu.inst 8911 # number of ReadReq misses
562system.cpu.icache.ReadReq_misses::total 8911 # number of ReadReq misses
563system.cpu.icache.demand_misses::cpu.inst 8911 # number of demand (read+write) misses
564system.cpu.icache.demand_misses::total 8911 # number of demand (read+write) misses
565system.cpu.icache.overall_misses::cpu.inst 8911 # number of overall misses
566system.cpu.icache.overall_misses::total 8911 # number of overall misses
567system.cpu.icache.ReadReq_miss_latency::cpu.inst 368225749 # number of ReadReq miss cycles
568system.cpu.icache.ReadReq_miss_latency::total 368225749 # number of ReadReq miss cycles
569system.cpu.icache.demand_miss_latency::cpu.inst 368225749 # number of demand (read+write) miss cycles
570system.cpu.icache.demand_miss_latency::total 368225749 # number of demand (read+write) miss cycles
571system.cpu.icache.overall_miss_latency::cpu.inst 368225749 # number of overall miss cycles
572system.cpu.icache.overall_miss_latency::total 368225749 # number of overall miss cycles
573system.cpu.icache.ReadReq_accesses::cpu.inst 22353212 # number of ReadReq accesses(hits+misses)
574system.cpu.icache.ReadReq_accesses::total 22353212 # number of ReadReq accesses(hits+misses)
575system.cpu.icache.demand_accesses::cpu.inst 22353212 # number of demand (read+write) accesses
576system.cpu.icache.demand_accesses::total 22353212 # number of demand (read+write) accesses
577system.cpu.icache.overall_accesses::cpu.inst 22353212 # number of overall (read+write) accesses
578system.cpu.icache.overall_accesses::total 22353212 # number of overall (read+write) accesses
579system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000399 # miss rate for ReadReq accesses
580system.cpu.icache.ReadReq_miss_rate::total 0.000399 # miss rate for ReadReq accesses
581system.cpu.icache.demand_miss_rate::cpu.inst 0.000399 # miss rate for demand accesses
582system.cpu.icache.demand_miss_rate::total 0.000399 # miss rate for demand accesses
583system.cpu.icache.overall_miss_rate::cpu.inst 0.000399 # miss rate for overall accesses
584system.cpu.icache.overall_miss_rate::total 0.000399 # miss rate for overall accesses
585system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41322.606778 # average ReadReq miss latency
586system.cpu.icache.ReadReq_avg_miss_latency::total 41322.606778 # average ReadReq miss latency
587system.cpu.icache.demand_avg_miss_latency::cpu.inst 41322.606778 # average overall miss latency
588system.cpu.icache.demand_avg_miss_latency::total 41322.606778 # average overall miss latency
589system.cpu.icache.overall_avg_miss_latency::cpu.inst 41322.606778 # average overall miss latency
590system.cpu.icache.overall_avg_miss_latency::total 41322.606778 # average overall miss latency
591system.cpu.icache.blocked_cycles::no_mshrs 877 # number of cycles access was blocked
592system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
593system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked
594system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
595system.cpu.icache.avg_blocked_cycles::no_mshrs 43.850000 # average number of cycles each access was blocked
596system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
597system.cpu.icache.fast_writes 0 # number of fast writes performed
598system.cpu.icache.cache_copies 0 # number of cache copies performed
599system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2127 # number of ReadReq MSHR hits
600system.cpu.icache.ReadReq_mshr_hits::total 2127 # number of ReadReq MSHR hits
601system.cpu.icache.demand_mshr_hits::cpu.inst 2127 # number of demand (read+write) MSHR hits
602system.cpu.icache.demand_mshr_hits::total 2127 # number of demand (read+write) MSHR hits
603system.cpu.icache.overall_mshr_hits::cpu.inst 2127 # number of overall MSHR hits
604system.cpu.icache.overall_mshr_hits::total 2127 # number of overall MSHR hits
605system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6784 # number of ReadReq MSHR misses
606system.cpu.icache.ReadReq_mshr_misses::total 6784 # number of ReadReq MSHR misses
607system.cpu.icache.demand_mshr_misses::cpu.inst 6784 # number of demand (read+write) MSHR misses
608system.cpu.icache.demand_mshr_misses::total 6784 # number of demand (read+write) MSHR misses
609system.cpu.icache.overall_mshr_misses::cpu.inst 6784 # number of overall MSHR misses
610system.cpu.icache.overall_mshr_misses::total 6784 # number of overall MSHR misses
611system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 271661249 # number of ReadReq MSHR miss cycles
612system.cpu.icache.ReadReq_mshr_miss_latency::total 271661249 # number of ReadReq MSHR miss cycles
613system.cpu.icache.demand_mshr_miss_latency::cpu.inst 271661249 # number of demand (read+write) MSHR miss cycles
614system.cpu.icache.demand_mshr_miss_latency::total 271661249 # number of demand (read+write) MSHR miss cycles
615system.cpu.icache.overall_mshr_miss_latency::cpu.inst 271661249 # number of overall MSHR miss cycles
616system.cpu.icache.overall_mshr_miss_latency::total 271661249 # number of overall MSHR miss cycles
617system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for ReadReq accesses
618system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000303 # mshr miss rate for ReadReq accesses
619system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for demand accesses
620system.cpu.icache.demand_mshr_miss_rate::total 0.000303 # mshr miss rate for demand accesses
621system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for overall accesses
622system.cpu.icache.overall_mshr_miss_rate::total 0.000303 # mshr miss rate for overall accesses
623system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40044.405808 # average ReadReq mshr miss latency
624system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40044.405808 # average ReadReq mshr miss latency
625system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40044.405808 # average overall mshr miss latency
626system.cpu.icache.demand_avg_mshr_miss_latency::total 40044.405808 # average overall mshr miss latency
627system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40044.405808 # average overall mshr miss latency
628system.cpu.icache.overall_avg_mshr_miss_latency::total 40044.405808 # average overall mshr miss latency
629system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
630system.cpu.l2cache.tags.replacements 0 # number of replacements
631system.cpu.l2cache.tags.tagsinuse 2543.926921 # Cycle average of tags in use
632system.cpu.l2cache.tags.total_refs 3266 # Total number of references to valid blocks.
633system.cpu.l2cache.tags.sampled_refs 3826 # Sample count of references to valid blocks.
634system.cpu.l2cache.tags.avg_refs 0.853633 # Average number of references to valid blocks.
635system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
636system.cpu.l2cache.tags.occ_blocks::writebacks 1.725256 # Average occupied blocks per requestor
637system.cpu.l2cache.tags.occ_blocks::cpu.inst 2230.334816 # Average occupied blocks per requestor
638system.cpu.l2cache.tags.occ_blocks::cpu.data 311.866849 # Average occupied blocks per requestor
639system.cpu.l2cache.tags.occ_percent::writebacks 0.000053 # Average percentage of cache occupancy
640system.cpu.l2cache.tags.occ_percent::cpu.inst 0.068064 # Average percentage of cache occupancy
641system.cpu.l2cache.tags.occ_percent::cpu.data 0.009517 # Average percentage of cache occupancy
642system.cpu.l2cache.tags.occ_percent::total 0.077634 # Average percentage of cache occupancy
643system.cpu.l2cache.ReadReq_hits::cpu.inst 3227 # number of ReadReq hits
644system.cpu.l2cache.ReadReq_hits::cpu.data 36 # number of ReadReq hits
645system.cpu.l2cache.ReadReq_hits::total 3263 # number of ReadReq hits
646system.cpu.l2cache.Writeback_hits::writebacks 13 # number of Writeback hits
647system.cpu.l2cache.Writeback_hits::total 13 # number of Writeback hits
648system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # number of ReadExReq hits
649system.cpu.l2cache.ReadExReq_hits::total 7 # number of ReadExReq hits
650system.cpu.l2cache.demand_hits::cpu.inst 3227 # number of demand (read+write) hits
651system.cpu.l2cache.demand_hits::cpu.data 43 # number of demand (read+write) hits
652system.cpu.l2cache.demand_hits::total 3270 # number of demand (read+write) hits
653system.cpu.l2cache.overall_hits::cpu.inst 3227 # number of overall hits
654system.cpu.l2cache.overall_hits::cpu.data 43 # number of overall hits
655system.cpu.l2cache.overall_hits::total 3270 # number of overall hits
656system.cpu.l2cache.ReadReq_misses::cpu.inst 3393 # number of ReadReq misses
657system.cpu.l2cache.ReadReq_misses::cpu.data 430 # number of ReadReq misses
658system.cpu.l2cache.ReadReq_misses::total 3823 # number of ReadReq misses
659system.cpu.l2cache.UpgradeReq_misses::cpu.data 163 # number of UpgradeReq misses
660system.cpu.l2cache.UpgradeReq_misses::total 163 # number of UpgradeReq misses
661system.cpu.l2cache.ReadExReq_misses::cpu.data 1532 # number of ReadExReq misses
662system.cpu.l2cache.ReadExReq_misses::total 1532 # number of ReadExReq misses
663system.cpu.l2cache.demand_misses::cpu.inst 3393 # number of demand (read+write) misses
664system.cpu.l2cache.demand_misses::cpu.data 1962 # number of demand (read+write) misses
665system.cpu.l2cache.demand_misses::total 5355 # number of demand (read+write) misses
666system.cpu.l2cache.overall_misses::cpu.inst 3393 # number of overall misses
667system.cpu.l2cache.overall_misses::cpu.data 1962 # number of overall misses
668system.cpu.l2cache.overall_misses::total 5355 # number of overall misses
669system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 232439500 # number of ReadReq miss cycles
670system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32755500 # number of ReadReq miss cycles
671system.cpu.l2cache.ReadReq_miss_latency::total 265195000 # number of ReadReq miss cycles
672system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104434000 # number of ReadExReq miss cycles
673system.cpu.l2cache.ReadExReq_miss_latency::total 104434000 # number of ReadExReq miss cycles
674system.cpu.l2cache.demand_miss_latency::cpu.inst 232439500 # number of demand (read+write) miss cycles
675system.cpu.l2cache.demand_miss_latency::cpu.data 137189500 # number of demand (read+write) miss cycles
676system.cpu.l2cache.demand_miss_latency::total 369629000 # number of demand (read+write) miss cycles
677system.cpu.l2cache.overall_miss_latency::cpu.inst 232439500 # number of overall miss cycles
678system.cpu.l2cache.overall_miss_latency::cpu.data 137189500 # number of overall miss cycles
679system.cpu.l2cache.overall_miss_latency::total 369629000 # number of overall miss cycles
680system.cpu.l2cache.ReadReq_accesses::cpu.inst 6620 # number of ReadReq accesses(hits+misses)
681system.cpu.l2cache.ReadReq_accesses::cpu.data 466 # number of ReadReq accesses(hits+misses)
682system.cpu.l2cache.ReadReq_accesses::total 7086 # number of ReadReq accesses(hits+misses)
683system.cpu.l2cache.Writeback_accesses::writebacks 13 # number of Writeback accesses(hits+misses)
684system.cpu.l2cache.Writeback_accesses::total 13 # number of Writeback accesses(hits+misses)
685system.cpu.l2cache.UpgradeReq_accesses::cpu.data 163 # number of UpgradeReq accesses(hits+misses)
686system.cpu.l2cache.UpgradeReq_accesses::total 163 # number of UpgradeReq accesses(hits+misses)
687system.cpu.l2cache.ReadExReq_accesses::cpu.data 1539 # number of ReadExReq accesses(hits+misses)
688system.cpu.l2cache.ReadExReq_accesses::total 1539 # number of ReadExReq accesses(hits+misses)
689system.cpu.l2cache.demand_accesses::cpu.inst 6620 # number of demand (read+write) accesses
690system.cpu.l2cache.demand_accesses::cpu.data 2005 # number of demand (read+write) accesses
691system.cpu.l2cache.demand_accesses::total 8625 # number of demand (read+write) accesses
692system.cpu.l2cache.overall_accesses::cpu.inst 6620 # number of overall (read+write) accesses
693system.cpu.l2cache.overall_accesses::cpu.data 2005 # number of overall (read+write) accesses
694system.cpu.l2cache.overall_accesses::total 8625 # number of overall (read+write) accesses
695system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.512538 # miss rate for ReadReq accesses
696system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.922747 # miss rate for ReadReq accesses
697system.cpu.l2cache.ReadReq_miss_rate::total 0.539515 # miss rate for ReadReq accesses
698system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
699system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
700system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995452 # miss rate for ReadExReq accesses
701system.cpu.l2cache.ReadExReq_miss_rate::total 0.995452 # miss rate for ReadExReq accesses
702system.cpu.l2cache.demand_miss_rate::cpu.inst 0.512538 # miss rate for demand accesses
703system.cpu.l2cache.demand_miss_rate::cpu.data 0.978554 # miss rate for demand accesses
704system.cpu.l2cache.demand_miss_rate::total 0.620870 # miss rate for demand accesses
705system.cpu.l2cache.overall_miss_rate::cpu.inst 0.512538 # miss rate for overall accesses
706system.cpu.l2cache.overall_miss_rate::cpu.data 0.978554 # miss rate for overall accesses
707system.cpu.l2cache.overall_miss_rate::total 0.620870 # miss rate for overall accesses
708system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68505.599764 # average ReadReq miss latency
709system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76175.581395 # average ReadReq miss latency
710system.cpu.l2cache.ReadReq_avg_miss_latency::total 69368.297149 # average ReadReq miss latency
711system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68168.407311 # average ReadExReq miss latency
712system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68168.407311 # average ReadExReq miss latency
713system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68505.599764 # average overall miss latency
714system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69923.292559 # average overall miss latency
715system.cpu.l2cache.demand_avg_miss_latency::total 69025.023343 # average overall miss latency
716system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68505.599764 # average overall miss latency
717system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69923.292559 # average overall miss latency
718system.cpu.l2cache.overall_avg_miss_latency::total 69025.023343 # average overall miss latency
719system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
720system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
721system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
722system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
723system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
724system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
725system.cpu.l2cache.fast_writes 0 # number of fast writes performed
726system.cpu.l2cache.cache_copies 0 # number of cache copies performed
727system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3393 # number of ReadReq MSHR misses
728system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 430 # number of ReadReq MSHR misses
729system.cpu.l2cache.ReadReq_mshr_misses::total 3823 # number of ReadReq MSHR misses
730system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 163 # number of UpgradeReq MSHR misses
731system.cpu.l2cache.UpgradeReq_mshr_misses::total 163 # number of UpgradeReq MSHR misses
732system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1532 # number of ReadExReq MSHR misses
733system.cpu.l2cache.ReadExReq_mshr_misses::total 1532 # number of ReadExReq MSHR misses
734system.cpu.l2cache.demand_mshr_misses::cpu.inst 3393 # number of demand (read+write) MSHR misses
735system.cpu.l2cache.demand_mshr_misses::cpu.data 1962 # number of demand (read+write) MSHR misses
736system.cpu.l2cache.demand_mshr_misses::total 5355 # number of demand (read+write) MSHR misses
737system.cpu.l2cache.overall_mshr_misses::cpu.inst 3393 # number of overall MSHR misses
738system.cpu.l2cache.overall_mshr_misses::cpu.data 1962 # number of overall MSHR misses
739system.cpu.l2cache.overall_mshr_misses::total 5355 # number of overall MSHR misses
740system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 189922000 # number of ReadReq MSHR miss cycles
741system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27426500 # number of ReadReq MSHR miss cycles
742system.cpu.l2cache.ReadReq_mshr_miss_latency::total 217348500 # number of ReadReq MSHR miss cycles
743system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1630163 # number of UpgradeReq MSHR miss cycles
744system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1630163 # number of UpgradeReq MSHR miss cycles
745system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 84874000 # number of ReadExReq MSHR miss cycles
746system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 84874000 # number of ReadExReq MSHR miss cycles
747system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 189922000 # number of demand (read+write) MSHR miss cycles
748system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 112300500 # number of demand (read+write) MSHR miss cycles
749system.cpu.l2cache.demand_mshr_miss_latency::total 302222500 # number of demand (read+write) MSHR miss cycles
750system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 189922000 # number of overall MSHR miss cycles
751system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 112300500 # number of overall MSHR miss cycles
752system.cpu.l2cache.overall_mshr_miss_latency::total 302222500 # number of overall MSHR miss cycles
753system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for ReadReq accesses
754system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.922747 # mshr miss rate for ReadReq accesses
755system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.539515 # mshr miss rate for ReadReq accesses
756system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
757system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
758system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995452 # mshr miss rate for ReadExReq accesses
759system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995452 # mshr miss rate for ReadExReq accesses
760system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for demand accesses
761system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.978554 # mshr miss rate for demand accesses
762system.cpu.l2cache.demand_mshr_miss_rate::total 0.620870 # mshr miss rate for demand accesses
763system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for overall accesses
764system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.978554 # mshr miss rate for overall accesses
765system.cpu.l2cache.overall_mshr_miss_rate::total 0.620870 # mshr miss rate for overall accesses
766system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55974.653699 # average ReadReq mshr miss latency
767system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63782.558140 # average ReadReq mshr miss latency
768system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56852.864243 # average ReadReq mshr miss latency
769system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
770system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
771system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55400.783290 # average ReadExReq mshr miss latency
772system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55400.783290 # average ReadExReq mshr miss latency
773system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55974.653699 # average overall mshr miss latency
774system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57237.767584 # average overall mshr miss latency
775system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56437.441643 # average overall mshr miss latency
776system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55974.653699 # average overall mshr miss latency
777system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57237.767584 # average overall mshr miss latency
778system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56437.441643 # average overall mshr miss latency
779system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
780system.cpu.dcache.tags.replacements 57 # number of replacements
781system.cpu.dcache.tags.tagsinuse 1438.861304 # Cycle average of tags in use
782system.cpu.dcache.tags.total_refs 66102355 # Total number of references to valid blocks.
783system.cpu.dcache.tags.sampled_refs 2004 # Sample count of references to valid blocks.
784system.cpu.dcache.tags.avg_refs 32985.207086 # Average number of references to valid blocks.
785system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
786system.cpu.dcache.tags.occ_blocks::cpu.data 1438.861304 # Average occupied blocks per requestor
787system.cpu.dcache.tags.occ_percent::cpu.data 0.351284 # Average percentage of cache occupancy
788system.cpu.dcache.tags.occ_percent::total 0.351284 # Average percentage of cache occupancy
789system.cpu.dcache.ReadReq_hits::cpu.data 45588096 # number of ReadReq hits
790system.cpu.dcache.ReadReq_hits::total 45588096 # number of ReadReq hits
791system.cpu.dcache.WriteReq_hits::cpu.data 20514029 # number of WriteReq hits
792system.cpu.dcache.WriteReq_hits::total 20514029 # number of WriteReq hits
793system.cpu.dcache.demand_hits::cpu.data 66102125 # number of demand (read+write) hits
794system.cpu.dcache.demand_hits::total 66102125 # number of demand (read+write) hits
795system.cpu.dcache.overall_hits::cpu.data 66102125 # number of overall hits
796system.cpu.dcache.overall_hits::total 66102125 # number of overall hits
797system.cpu.dcache.ReadReq_misses::cpu.data 935 # number of ReadReq misses
798system.cpu.dcache.ReadReq_misses::total 935 # number of ReadReq misses
799system.cpu.dcache.WriteReq_misses::cpu.data 1702 # number of WriteReq misses
800system.cpu.dcache.WriteReq_misses::total 1702 # number of WriteReq misses
801system.cpu.dcache.demand_misses::cpu.data 2637 # number of demand (read+write) misses
802system.cpu.dcache.demand_misses::total 2637 # number of demand (read+write) misses
803system.cpu.dcache.overall_misses::cpu.data 2637 # number of overall misses
804system.cpu.dcache.overall_misses::total 2637 # number of overall misses
805system.cpu.dcache.ReadReq_miss_latency::cpu.data 62763567 # number of ReadReq miss cycles
806system.cpu.dcache.ReadReq_miss_latency::total 62763567 # number of ReadReq miss cycles
807system.cpu.dcache.WriteReq_miss_latency::cpu.data 113907163 # number of WriteReq miss cycles
808system.cpu.dcache.WriteReq_miss_latency::total 113907163 # number of WriteReq miss cycles
809system.cpu.dcache.demand_miss_latency::cpu.data 176670730 # number of demand (read+write) miss cycles
810system.cpu.dcache.demand_miss_latency::total 176670730 # number of demand (read+write) miss cycles
811system.cpu.dcache.overall_miss_latency::cpu.data 176670730 # number of overall miss cycles
812system.cpu.dcache.overall_miss_latency::total 176670730 # number of overall miss cycles
813system.cpu.dcache.ReadReq_accesses::cpu.data 45589031 # number of ReadReq accesses(hits+misses)
814system.cpu.dcache.ReadReq_accesses::total 45589031 # number of ReadReq accesses(hits+misses)
815system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
816system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
817system.cpu.dcache.demand_accesses::cpu.data 66104762 # number of demand (read+write) accesses
818system.cpu.dcache.demand_accesses::total 66104762 # number of demand (read+write) accesses
819system.cpu.dcache.overall_accesses::cpu.data 66104762 # number of overall (read+write) accesses
820system.cpu.dcache.overall_accesses::total 66104762 # number of overall (read+write) accesses
821system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses
822system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses
823system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses
824system.cpu.dcache.WriteReq_miss_rate::total 0.000083 # miss rate for WriteReq accesses
825system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses
826system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses
827system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses
828system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses
829system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67126.809626 # average ReadReq miss latency
830system.cpu.dcache.ReadReq_avg_miss_latency::total 67126.809626 # average ReadReq miss latency
831system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66925.477673 # average WriteReq miss latency
832system.cpu.dcache.WriteReq_avg_miss_latency::total 66925.477673 # average WriteReq miss latency
833system.cpu.dcache.demand_avg_miss_latency::cpu.data 66996.863860 # average overall miss latency
834system.cpu.dcache.demand_avg_miss_latency::total 66996.863860 # average overall miss latency
835system.cpu.dcache.overall_avg_miss_latency::cpu.data 66996.863860 # average overall miss latency
836system.cpu.dcache.overall_avg_miss_latency::total 66996.863860 # average overall miss latency
837system.cpu.dcache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked
838system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
839system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked
840system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
841system.cpu.dcache.avg_blocked_cycles::no_mshrs 77 # average number of cycles each access was blocked
842system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
843system.cpu.dcache.fast_writes 0 # number of fast writes performed
844system.cpu.dcache.cache_copies 0 # number of cache copies performed
845system.cpu.dcache.writebacks::writebacks 13 # number of writebacks
846system.cpu.dcache.writebacks::total 13 # number of writebacks
847system.cpu.dcache.ReadReq_mshr_hits::cpu.data 468 # number of ReadReq MSHR hits
848system.cpu.dcache.ReadReq_mshr_hits::total 468 # number of ReadReq MSHR hits
849system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits
850system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits
851system.cpu.dcache.demand_mshr_hits::cpu.data 469 # number of demand (read+write) MSHR hits
852system.cpu.dcache.demand_mshr_hits::total 469 # number of demand (read+write) MSHR hits
853system.cpu.dcache.overall_mshr_hits::cpu.data 469 # number of overall MSHR hits
854system.cpu.dcache.overall_mshr_hits::total 469 # number of overall MSHR hits
855system.cpu.dcache.ReadReq_mshr_misses::cpu.data 467 # number of ReadReq MSHR misses
856system.cpu.dcache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses
857system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1701 # number of WriteReq MSHR misses
858system.cpu.dcache.WriteReq_mshr_misses::total 1701 # number of WriteReq MSHR misses
859system.cpu.dcache.demand_mshr_misses::cpu.data 2168 # number of demand (read+write) MSHR misses
860system.cpu.dcache.demand_mshr_misses::total 2168 # number of demand (read+write) MSHR misses
861system.cpu.dcache.overall_mshr_misses::cpu.data 2168 # number of overall MSHR misses
862system.cpu.dcache.overall_mshr_misses::total 2168 # number of overall MSHR misses
863system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33590500 # number of ReadReq MSHR miss cycles
864system.cpu.dcache.ReadReq_mshr_miss_latency::total 33590500 # number of ReadReq MSHR miss cycles
865system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 109769587 # number of WriteReq MSHR miss cycles
866system.cpu.dcache.WriteReq_mshr_miss_latency::total 109769587 # number of WriteReq MSHR miss cycles
867system.cpu.dcache.demand_mshr_miss_latency::cpu.data 143360087 # number of demand (read+write) MSHR miss cycles
868system.cpu.dcache.demand_mshr_miss_latency::total 143360087 # number of demand (read+write) MSHR miss cycles
869system.cpu.dcache.overall_mshr_miss_latency::cpu.data 143360087 # number of overall MSHR miss cycles
870system.cpu.dcache.overall_mshr_miss_latency::total 143360087 # number of overall MSHR miss cycles
871system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
872system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
873system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000083 # mshr miss rate for WriteReq accesses
874system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000083 # mshr miss rate for WriteReq accesses
875system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for demand accesses
876system.cpu.dcache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses
877system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for overall accesses
878system.cpu.dcache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses
879system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71928.265525 # average ReadReq mshr miss latency
880system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71928.265525 # average ReadReq mshr miss latency
881system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64532.385068 # average WriteReq mshr miss latency
882system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64532.385068 # average WriteReq mshr miss latency
883system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66125.501384 # average overall mshr miss latency
884system.cpu.dcache.demand_avg_mshr_miss_latency::total 66125.501384 # average overall mshr miss latency
885system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66125.501384 # average overall mshr miss latency
886system.cpu.dcache.overall_avg_mshr_miss_latency::total 66125.501384 # average overall mshr miss latency
887system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
888
889---------- End Simulation Statistics ----------