1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.144337 # Number of seconds simulated
4sim_ticks 144337151000 # Number of ticks simulated
5final_tick 144337151000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 53269 # Simulator instruction rate (inst/s)
8host_op_rate 89284 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 58216660 # Simulator tick rate (ticks/s)
10host_mem_usage 281036 # Number of bytes of host memory used
11host_seconds 2479.31 # Real time elapsed on the host
12sim_insts 132071192 # Number of instructions simulated
13sim_ops 221363384 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 217984 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 125184 # Number of bytes read from this memory
16system.physmem.bytes_read::total 343168 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 217984 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 217984 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 3406 # Number of read requests responded to by this memory
20system.physmem.num_reads::cpu.data 1956 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 5362 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 1510242 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 867303 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 2377545 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 1510242 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 1510242 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 1510242 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 867303 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 2377545 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.readReqs 5363 # Total number of read requests accepted by DRAM controller
31system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
32system.physmem.readBursts 5363 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
33system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
34system.physmem.bytesRead 343168 # Total number of bytes read from memory
35system.physmem.bytesWritten 0 # Total number of bytes written to memory
36system.physmem.bytesConsumedRd 343168 # bytesRead derated as per pkt->getSize()
37system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
38system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
39system.physmem.neitherReadNorWrite 155 # Reqs where no action is needed
40system.physmem.perBankRdReqs::0 287 # Track reads on a per bank basis
41system.physmem.perBankRdReqs::1 360 # Track reads on a per bank basis
42system.physmem.perBankRdReqs::2 449 # Track reads on a per bank basis
43system.physmem.perBankRdReqs::3 361 # Track reads on a per bank basis
44system.physmem.perBankRdReqs::4 329 # Track reads on a per bank basis
45system.physmem.perBankRdReqs::5 326 # Track reads on a per bank basis
46system.physmem.perBankRdReqs::6 396 # Track reads on a per bank basis
47system.physmem.perBankRdReqs::7 379 # Track reads on a per bank basis
48system.physmem.perBankRdReqs::8 340 # Track reads on a per bank basis
49system.physmem.perBankRdReqs::9 277 # Track reads on a per bank basis
50system.physmem.perBankRdReqs::10 230 # Track reads on a per bank basis
51system.physmem.perBankRdReqs::11 279 # Track reads on a per bank basis
52system.physmem.perBankRdReqs::12 206 # Track reads on a per bank basis
53system.physmem.perBankRdReqs::13 469 # Track reads on a per bank basis
54system.physmem.perBankRdReqs::14 390 # Track reads on a per bank basis
55system.physmem.perBankRdReqs::15 285 # Track reads on a per bank basis
56system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
57system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
58system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
59system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
60system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
61system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
62system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
63system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
64system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
65system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
66system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
67system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
68system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
69system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
70system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
71system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
72system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
73system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
74system.physmem.totGap 144337117000 # Total gap between requests
75system.physmem.readPktSize::0 0 # Categorize read packet sizes
76system.physmem.readPktSize::1 0 # Categorize read packet sizes
77system.physmem.readPktSize::2 0 # Categorize read packet sizes
78system.physmem.readPktSize::3 0 # Categorize read packet sizes
79system.physmem.readPktSize::4 0 # Categorize read packet sizes
80system.physmem.readPktSize::5 0 # Categorize read packet sizes
81system.physmem.readPktSize::6 5363 # Categorize read packet sizes
82system.physmem.writePktSize::0 0 # Categorize write packet sizes
83system.physmem.writePktSize::1 0 # Categorize write packet sizes
84system.physmem.writePktSize::2 0 # Categorize write packet sizes
85system.physmem.writePktSize::3 0 # Categorize write packet sizes
86system.physmem.writePktSize::4 0 # Categorize write packet sizes
87system.physmem.writePktSize::5 0 # Categorize write packet sizes
88system.physmem.writePktSize::6 0 # Categorize write packet sizes
89system.physmem.rdQLenPdf::0 4337 # What read queue length does an incoming req see
90system.physmem.rdQLenPdf::1 861 # What read queue length does an incoming req see
91system.physmem.rdQLenPdf::2 143 # What read queue length does an incoming req see
92system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see
93system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see

--- 44 unchanged lines hidden (view full) ---

145system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
153system.physmem.bytesPerActivate::samples 502 # Bytes accessed per row activation
154system.physmem.bytesPerActivate::mean 668.557769 # Bytes accessed per row activation
155system.physmem.bytesPerActivate::gmean 237.238454 # Bytes accessed per row activation
156system.physmem.bytesPerActivate::stdev 1295.396575 # Bytes accessed per row activation
157system.physmem.bytesPerActivate::64-65 170 33.86% 33.86% # Bytes accessed per row activation
158system.physmem.bytesPerActivate::128-129 76 15.14% 49.00% # Bytes accessed per row activation
159system.physmem.bytesPerActivate::192-193 42 8.37% 57.37% # Bytes accessed per row activation
160system.physmem.bytesPerActivate::256-257 23 4.58% 61.95% # Bytes accessed per row activation
161system.physmem.bytesPerActivate::320-321 26 5.18% 67.13% # Bytes accessed per row activation
162system.physmem.bytesPerActivate::384-385 11 2.19% 69.32% # Bytes accessed per row activation
163system.physmem.bytesPerActivate::448-449 16 3.19% 72.51% # Bytes accessed per row activation
164system.physmem.bytesPerActivate::512-513 9 1.79% 74.30% # Bytes accessed per row activation
165system.physmem.bytesPerActivate::576-577 9 1.79% 76.10% # Bytes accessed per row activation
166system.physmem.bytesPerActivate::640-641 7 1.39% 77.49% # Bytes accessed per row activation
167system.physmem.bytesPerActivate::704-705 3 0.60% 78.09% # Bytes accessed per row activation
168system.physmem.bytesPerActivate::768-769 8 1.59% 79.68% # Bytes accessed per row activation
169system.physmem.bytesPerActivate::832-833 5 1.00% 80.68% # Bytes accessed per row activation
170system.physmem.bytesPerActivate::896-897 3 0.60% 81.27% # Bytes accessed per row activation
171system.physmem.bytesPerActivate::960-961 4 0.80% 82.07% # Bytes accessed per row activation
172system.physmem.bytesPerActivate::1024-1025 5 1.00% 83.07% # Bytes accessed per row activation
173system.physmem.bytesPerActivate::1088-1089 4 0.80% 83.86% # Bytes accessed per row activation
174system.physmem.bytesPerActivate::1152-1153 5 1.00% 84.86% # Bytes accessed per row activation
175system.physmem.bytesPerActivate::1216-1217 2 0.40% 85.26% # Bytes accessed per row activation
176system.physmem.bytesPerActivate::1280-1281 2 0.40% 85.66% # Bytes accessed per row activation
177system.physmem.bytesPerActivate::1344-1345 3 0.60% 86.25% # Bytes accessed per row activation
178system.physmem.bytesPerActivate::1408-1409 5 1.00% 87.25% # Bytes accessed per row activation
179system.physmem.bytesPerActivate::1472-1473 3 0.60% 87.85% # Bytes accessed per row activation
180system.physmem.bytesPerActivate::1536-1537 1 0.20% 88.05% # Bytes accessed per row activation
181system.physmem.bytesPerActivate::1600-1601 2 0.40% 88.45% # Bytes accessed per row activation
182system.physmem.bytesPerActivate::1664-1665 1 0.20% 88.65% # Bytes accessed per row activation
183system.physmem.bytesPerActivate::1728-1729 1 0.20% 88.84% # Bytes accessed per row activation
184system.physmem.bytesPerActivate::1792-1793 2 0.40% 89.24% # Bytes accessed per row activation
185system.physmem.bytesPerActivate::1856-1857 4 0.80% 90.04% # Bytes accessed per row activation
186system.physmem.bytesPerActivate::1920-1921 4 0.80% 90.84% # Bytes accessed per row activation
187system.physmem.bytesPerActivate::1984-1985 1 0.20% 91.04% # Bytes accessed per row activation
188system.physmem.bytesPerActivate::2048-2049 2 0.40% 91.43% # Bytes accessed per row activation
189system.physmem.bytesPerActivate::2176-2177 1 0.20% 91.63% # Bytes accessed per row activation
190system.physmem.bytesPerActivate::2240-2241 4 0.80% 92.43% # Bytes accessed per row activation
191system.physmem.bytesPerActivate::2304-2305 1 0.20% 92.63% # Bytes accessed per row activation
192system.physmem.bytesPerActivate::2432-2433 2 0.40% 93.03% # Bytes accessed per row activation
193system.physmem.bytesPerActivate::2496-2497 2 0.40% 93.43% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::2624-2625 1 0.20% 93.63% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::2688-2689 1 0.20% 93.82% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::2816-2817 5 1.00% 94.82% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::2880-2881 1 0.20% 95.02% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::2944-2945 1 0.20% 95.22% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::3264-3265 1 0.20% 95.42% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::3328-3329 1 0.20% 95.62% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::3392-3393 1 0.20% 95.82% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::3520-3521 2 0.40% 96.22% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::3584-3585 1 0.20% 96.41% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::3648-3649 1 0.20% 96.61% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::4224-4225 1 0.20% 96.81% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::4352-4353 2 0.40% 97.21% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::4480-4481 1 0.20% 97.41% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::4544-4545 1 0.20% 97.61% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::4672-4673 1 0.20% 97.81% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::5312-5313 1 0.20% 98.01% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::5888-5889 1 0.20% 98.21% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::6336-6337 1 0.20% 98.41% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::6592-6593 1 0.20% 98.61% # Bytes accessed per row activation
214system.physmem.bytesPerActivate::6912-6913 1 0.20% 98.80% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::8128-8129 1 0.20% 99.00% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::8192-8193 5 1.00% 100.00% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::total 502 # Bytes accessed per row activation
218system.physmem.totQLat 12663500 # Total cycles spent in queuing delays
219system.physmem.totMemAccLat 119173500 # Sum of mem lat for all requests
220system.physmem.totBusLat 26815000 # Total cycles spent in databus access
221system.physmem.totBankLat 79695000 # Total cycles spent in bank access
222system.physmem.avgQLat 2361.27 # Average queueing delay per request
223system.physmem.avgBankLat 14860.15 # Average bank access latency per request
224system.physmem.avgBusLat 5000.00 # Average bus latency per request
225system.physmem.avgMemAccLat 22221.42 # Average memory access latency
226system.physmem.avgRdBW 2.38 # Average achieved read bandwidth in MB/s
227system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
228system.physmem.avgConsumedRdBW 2.38 # Average consumed read bandwidth in MB/s
229system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
230system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
231system.physmem.busUtil 0.02 # Data bus utilization in percentage
232system.physmem.avgRdQLen 0.00 # Average read queue length over time
233system.physmem.avgWrQLen 0.00 # Average write queue length over time
234system.physmem.readRowHits 4861 # Number of row buffer hits during reads
235system.physmem.writeRowHits 0 # Number of row buffer hits during writes
236system.physmem.readRowHitRate 90.64 # Row buffer hit rate for reads
237system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
238system.physmem.avgGap 26913503.08 # Average gap between requests
239system.membus.throughput 2376658 # Throughput (bytes/s)
240system.membus.trans_dist::ReadReq 3834 # Transaction distribution
241system.membus.trans_dist::ReadResp 3831 # Transaction distribution
242system.membus.trans_dist::UpgradeReq 155 # Transaction distribution
243system.membus.trans_dist::UpgradeResp 155 # Transaction distribution
244system.membus.trans_dist::ReadExReq 1529 # Transaction distribution
245system.membus.trans_dist::ReadExResp 1529 # Transaction distribution
246system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11033 # Packet count per connected master and slave (bytes)
247system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11033 # Packet count per connected master and slave (bytes)
248system.membus.pkt_count::total 11033 # Packet count per connected master and slave (bytes)
249system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 343040 # Cumulative packet size per connected master and slave (bytes)
250system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 343040 # Cumulative packet size per connected master and slave (bytes)
251system.membus.tot_pkt_size::total 343040 # Cumulative packet size per connected master and slave (bytes)
252system.membus.data_through_bus 343040 # Total data (bytes)
253system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
254system.membus.reqLayer0.occupancy 6992500 # Layer occupancy (ticks)
255system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
256system.membus.respLayer1.occupancy 50918345 # Layer occupancy (ticks)
257system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
258system.cpu.branchPred.lookups 18643049 # Number of BP lookups
259system.cpu.branchPred.condPredicted 18643049 # Number of conditional branches predicted
260system.cpu.branchPred.condIncorrect 1490032 # Number of conditional branches incorrect
261system.cpu.branchPred.BTBLookups 11410311 # Number of BTB lookups
262system.cpu.branchPred.BTBHits 10785937 # Number of BTB hits
263system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
264system.cpu.branchPred.BTBHitPct 94.527984 # BTB Hit Percentage
265system.cpu.branchPred.usedRAS 1319504 # Number of times the RAS was used to get a target.
266system.cpu.branchPred.RASInCorrect 23183 # Number of incorrect RAS predictions.
267system.cpu.workload.num_syscalls 400 # Number of system calls
268system.cpu.numCycles 288958648 # number of cpu cycles simulated
269system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
270system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
271system.cpu.fetch.icacheStallCycles 23449793 # Number of cycles fetch is stalled on an Icache miss
272system.cpu.fetch.Insts 206693383 # Number of instructions fetch has processed
273system.cpu.fetch.Branches 18643049 # Number of branches that fetch encountered
274system.cpu.fetch.predictedBranches 12105441 # Number of branches that fetch has predicted taken
275system.cpu.fetch.Cycles 54202283 # Number of cycles fetch has run and was not squashing or blocked
276system.cpu.fetch.SquashCycles 15520862 # Number of cycles fetch has spent squashing
277system.cpu.fetch.BlockedCycles 177854698 # Number of cycles fetch has spent blocked
278system.cpu.fetch.MiscStallCycles 1763 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
279system.cpu.fetch.PendingTrapStallCycles 10399 # Number of stall cycles due to pending traps
280system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR
281system.cpu.fetch.CacheLines 22344440 # Number of cache lines fetched
282system.cpu.fetch.IcacheSquashes 223501 # Number of outstanding Icache misses that were squashed
283system.cpu.fetch.rateDist::samples 269290807 # Number of instructions fetched each cycle (Total)
284system.cpu.fetch.rateDist::mean 1.269558 # Number of instructions fetched each cycle (Total)
285system.cpu.fetch.rateDist::stdev 2.757533 # Number of instructions fetched each cycle (Total)
286system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
287system.cpu.fetch.rateDist::0 216527174 80.41% 80.41% # Number of instructions fetched each cycle (Total)
288system.cpu.fetch.rateDist::1 2848467 1.06% 81.46% # Number of instructions fetched each cycle (Total)
289system.cpu.fetch.rateDist::2 2311919 0.86% 82.32% # Number of instructions fetched each cycle (Total)
290system.cpu.fetch.rateDist::3 2635919 0.98% 83.30% # Number of instructions fetched each cycle (Total)
291system.cpu.fetch.rateDist::4 3216253 1.19% 84.50% # Number of instructions fetched each cycle (Total)
292system.cpu.fetch.rateDist::5 3385278 1.26% 85.75% # Number of instructions fetched each cycle (Total)
293system.cpu.fetch.rateDist::6 3830479 1.42% 87.18% # Number of instructions fetched each cycle (Total)
294system.cpu.fetch.rateDist::7 2556488 0.95% 88.12% # Number of instructions fetched each cycle (Total)
295system.cpu.fetch.rateDist::8 31978830 11.88% 100.00% # Number of instructions fetched each cycle (Total)
296system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
297system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
298system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
299system.cpu.fetch.rateDist::total 269290807 # Number of instructions fetched each cycle (Total)
300system.cpu.fetch.branchRate 0.064518 # Number of branch fetches per cycle
301system.cpu.fetch.rate 0.715304 # Number of inst fetches per cycle
302system.cpu.decode.IdleCycles 36876726 # Number of cycles decode is idle
303system.cpu.decode.BlockedCycles 166835214 # Number of cycles decode is blocked
304system.cpu.decode.RunCycles 41579224 # Number of cycles decode is running
305system.cpu.decode.UnblockCycles 10227847 # Number of cycles decode is unblocking
306system.cpu.decode.SquashCycles 13771796 # Number of cycles decode is squashing
307system.cpu.decode.DecodedInsts 335978319 # Number of instructions handled by decode
308system.cpu.rename.SquashCycles 13771796 # Number of cycles rename is squashing
309system.cpu.rename.IdleCycles 44930870 # Number of cycles rename is idle
310system.cpu.rename.BlockCycles 116571073 # Number of cycles rename is blocking
311system.cpu.rename.serializeStallCycles 32723 # count of cycles rename stalled for serializing inst
312system.cpu.rename.RunCycles 42705730 # Number of cycles rename is running
313system.cpu.rename.UnblockCycles 51278615 # Number of cycles rename is unblocking
314system.cpu.rename.RenamedInsts 329616563 # Number of instructions processed by rename
315system.cpu.rename.ROBFullEvents 10879 # Number of times rename has blocked due to ROB full
316system.cpu.rename.IQFullEvents 26000887 # Number of times rename has blocked due to IQ full
317system.cpu.rename.LSQFullEvents 22678374 # Number of times rename has blocked due to LSQ full
318system.cpu.rename.FullRegisterEvents 233 # Number of times there has been no free registers
319system.cpu.rename.RenamedOperands 382329747 # Number of destination operands rename has renamed
320system.cpu.rename.RenameLookups 917574423 # Number of register rename lookups that rename has made
321system.cpu.rename.int_rename_lookups 909394709 # Number of integer rename lookups
322system.cpu.rename.fp_rename_lookups 8179714 # Number of floating rename lookups
323system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed
324system.cpu.rename.UndoneMaps 122900297 # Number of HB maps that are undone due to squashing
325system.cpu.rename.serializingInsts 2069 # count of serializing insts renamed
326system.cpu.rename.tempSerializingInsts 2059 # count of temporary serializing insts renamed
327system.cpu.rename.skidInsts 104883276 # count of insts added to the skid buffer
328system.cpu.memDep0.insertedLoads 84491863 # Number of loads inserted to the mem dependence unit.
329system.cpu.memDep0.insertedStores 30099442 # Number of stores inserted to the mem dependence unit.
330system.cpu.memDep0.conflictingLoads 58238424 # Number of conflicting loads.
331system.cpu.memDep0.conflictingStores 18921052 # Number of conflicting stores.
332system.cpu.iq.iqInstsAdded 322680217 # Number of instructions added to the IQ (excludes non-spec)
333system.cpu.iq.iqNonSpecInstsAdded 4268 # Number of non-speculative instructions added to the IQ
334system.cpu.iq.iqInstsIssued 260554825 # Number of instructions issued
335system.cpu.iq.iqSquashedInstsIssued 118516 # Number of squashed instructions issued
336system.cpu.iq.iqSquashedInstsExamined 100936987 # Number of squashed instructions iterated over during squash; mainly for profiling
337system.cpu.iq.iqSquashedOperandsExamined 209936629 # Number of squashed operands that are examined and possibly removed from graph
338system.cpu.iq.iqSquashedNonSpecRemoved 3023 # Number of squashed non-spec instructions that were removed
339system.cpu.iq.issued_per_cycle::samples 269290807 # Number of insts issued each cycle
340system.cpu.iq.issued_per_cycle::mean 0.967559 # Number of insts issued each cycle
341system.cpu.iq.issued_per_cycle::stdev 1.344978 # Number of insts issued each cycle
342system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
343system.cpu.iq.issued_per_cycle::0 143216984 53.18% 53.18% # Number of insts issued each cycle
344system.cpu.iq.issued_per_cycle::1 55392011 20.57% 73.75% # Number of insts issued each cycle
345system.cpu.iq.issued_per_cycle::2 34136175 12.68% 86.43% # Number of insts issued each cycle
346system.cpu.iq.issued_per_cycle::3 19056796 7.08% 93.51% # Number of insts issued each cycle
347system.cpu.iq.issued_per_cycle::4 10890988 4.04% 97.55% # Number of insts issued each cycle
348system.cpu.iq.issued_per_cycle::5 4174840 1.55% 99.10% # Number of insts issued each cycle
349system.cpu.iq.issued_per_cycle::6 1812715 0.67% 99.77% # Number of insts issued each cycle
350system.cpu.iq.issued_per_cycle::7 476750 0.18% 99.95% # Number of insts issued each cycle
351system.cpu.iq.issued_per_cycle::8 133548 0.05% 100.00% # Number of insts issued each cycle
352system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
353system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
354system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
355system.cpu.iq.issued_per_cycle::total 269290807 # Number of insts issued each cycle
356system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
357system.cpu.iq.fu_full::IntAlu 129590 4.77% 4.77% # attempts to use FU when none available
358system.cpu.iq.fu_full::IntMult 0 0.00% 4.77% # attempts to use FU when none available
359system.cpu.iq.fu_full::IntDiv 0 0.00% 4.77% # attempts to use FU when none available
360system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.77% # attempts to use FU when none available
361system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.77% # attempts to use FU when none available
362system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.77% # attempts to use FU when none available
363system.cpu.iq.fu_full::FloatMult 0 0.00% 4.77% # attempts to use FU when none available
364system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.77% # attempts to use FU when none available
365system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.77% # attempts to use FU when none available
366system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.77% # attempts to use FU when none available
367system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.77% # attempts to use FU when none available
368system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.77% # attempts to use FU when none available
369system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.77% # attempts to use FU when none available
370system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.77% # attempts to use FU when none available
371system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.77% # attempts to use FU when none available
372system.cpu.iq.fu_full::SimdMult 0 0.00% 4.77% # attempts to use FU when none available
373system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.77% # attempts to use FU when none available
374system.cpu.iq.fu_full::SimdShift 0 0.00% 4.77% # attempts to use FU when none available
375system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.77% # attempts to use FU when none available
376system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.77% # attempts to use FU when none available
377system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.77% # attempts to use FU when none available
378system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.77% # attempts to use FU when none available
379system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.77% # attempts to use FU when none available
380system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.77% # attempts to use FU when none available
381system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.77% # attempts to use FU when none available
382system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.77% # attempts to use FU when none available
383system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.77% # attempts to use FU when none available
384system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.77% # attempts to use FU when none available
385system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.77% # attempts to use FU when none available
386system.cpu.iq.fu_full::MemRead 2286947 84.14% 88.91% # attempts to use FU when none available
387system.cpu.iq.fu_full::MemWrite 301448 11.09% 100.00% # attempts to use FU when none available
388system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
389system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
390system.cpu.iq.FU_type_0::No_OpClass 1210947 0.46% 0.46% # Type of FU issued
391system.cpu.iq.FU_type_0::IntAlu 162062843 62.20% 62.66% # Type of FU issued
392system.cpu.iq.FU_type_0::IntMult 788599 0.30% 62.97% # Type of FU issued
393system.cpu.iq.FU_type_0::IntDiv 7035610 2.70% 65.67% # Type of FU issued
394system.cpu.iq.FU_type_0::FloatAdd 1446949 0.56% 66.22% # Type of FU issued
395system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.22% # Type of FU issued
396system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.22% # Type of FU issued
397system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.22% # Type of FU issued
398system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.22% # Type of FU issued
399system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.22% # Type of FU issued
400system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.22% # Type of FU issued
401system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.22% # Type of FU issued
402system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.22% # Type of FU issued
403system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.22% # Type of FU issued
404system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.22% # Type of FU issued
405system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.22% # Type of FU issued
406system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.22% # Type of FU issued
407system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.22% # Type of FU issued
408system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.22% # Type of FU issued
409system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.22% # Type of FU issued
410system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.22% # Type of FU issued
411system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.22% # Type of FU issued
412system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.22% # Type of FU issued
413system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.22% # Type of FU issued
414system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.22% # Type of FU issued
415system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.22% # Type of FU issued
416system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.22% # Type of FU issued
417system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.22% # Type of FU issued
418system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.22% # Type of FU issued
419system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.22% # Type of FU issued
420system.cpu.iq.FU_type_0::MemRead 65458478 25.12% 91.34% # Type of FU issued
421system.cpu.iq.FU_type_0::MemWrite 22551399 8.66% 100.00% # Type of FU issued
422system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
423system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
424system.cpu.iq.FU_type_0::total 260554825 # Type of FU issued
425system.cpu.iq.rate 0.901703 # Inst issue rate
426system.cpu.iq.fu_busy_cnt 2717985 # FU busy when requested
427system.cpu.iq.fu_busy_rate 0.010432 # FU busy rate (busy events/executed inst)
428system.cpu.iq.int_inst_queue_reads 788349726 # Number of integer instruction queue reads
429system.cpu.iq.int_inst_queue_writes 420314001 # Number of integer instruction queue writes
430system.cpu.iq.int_inst_queue_wakeup_accesses 255192171 # Number of integer instruction queue wakeup accesses
431system.cpu.iq.fp_inst_queue_reads 4887232 # Number of floating instruction queue reads
432system.cpu.iq.fp_inst_queue_writes 3589351 # Number of floating instruction queue writes
433system.cpu.iq.fp_inst_queue_wakeup_accesses 2349681 # Number of floating instruction queue wakeup accesses
434system.cpu.iq.int_alu_accesses 259602149 # Number of integer alu accesses
435system.cpu.iq.fp_alu_accesses 2459714 # Number of floating point alu accesses
436system.cpu.iew.lsq.thread0.forwLoads 18922789 # Number of loads that had data forwarded from stores
437system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
438system.cpu.iew.lsq.thread0.squashedLoads 27842276 # Number of loads squashed
439system.cpu.iew.lsq.thread0.ignoredResponses 26598 # Number of memory responses ignored because the instruction is squashed
440system.cpu.iew.lsq.thread0.memOrderViolation 287421 # Number of memory ordering violations
441system.cpu.iew.lsq.thread0.squashedStores 9583725 # Number of stores squashed
442system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
443system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
444system.cpu.iew.lsq.thread0.rescheduledLoads 49875 # Number of loads that were rescheduled
445system.cpu.iew.lsq.thread0.cacheBlocked 33 # Number of times an access to memory failed due to the cache being blocked
446system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
447system.cpu.iew.iewSquashCycles 13771796 # Number of cycles IEW is squashing
448system.cpu.iew.iewBlockCycles 85093935 # Number of cycles IEW is blocking
449system.cpu.iew.iewUnblockCycles 5458597 # Number of cycles IEW is unblocking
450system.cpu.iew.iewDispatchedInsts 322684485 # Number of instructions dispatched to IQ
451system.cpu.iew.iewDispSquashedInsts 133416 # Number of squashed instructions skipped by dispatch
452system.cpu.iew.iewDispLoadInsts 84491863 # Number of dispatched load instructions
453system.cpu.iew.iewDispStoreInsts 30099442 # Number of dispatched store instructions
454system.cpu.iew.iewDispNonSpecInsts 2045 # Number of dispatched non-speculative instructions
455system.cpu.iew.iewIQFullEvents 2689496 # Number of times the IQ has become full, causing a stall
456system.cpu.iew.iewLSQFullEvents 13828 # Number of times the LSQ has become full, causing a stall
457system.cpu.iew.memOrderViolationEvents 287421 # Number of memory order violations
458system.cpu.iew.predictedTakenIncorrect 641114 # Number of branches that were predicted taken incorrectly
459system.cpu.iew.predictedNotTakenIncorrect 899581 # Number of branches that were predicted not taken incorrectly
460system.cpu.iew.branchMispredicts 1540695 # Number of branch mispredicts detected at execute
461system.cpu.iew.iewExecutedInsts 258780587 # Number of executed instructions
462system.cpu.iew.iewExecLoadInsts 64687693 # Number of load instructions executed
463system.cpu.iew.iewExecSquashedInsts 1774238 # Number of squashed instructions skipped in execute
464system.cpu.iew.exec_swp 0 # number of swp insts executed
465system.cpu.iew.exec_nop 0 # number of nop insts executed
466system.cpu.iew.exec_refs 87035311 # number of memory reference insts executed
467system.cpu.iew.exec_branches 14266808 # Number of branches executed
468system.cpu.iew.exec_stores 22347618 # Number of stores executed
469system.cpu.iew.exec_rate 0.895563 # Inst execution rate
470system.cpu.iew.wb_sent 258140928 # cumulative count of insts sent to commit
471system.cpu.iew.wb_count 257541852 # cumulative count of insts written-back
472system.cpu.iew.wb_producers 206006710 # num instructions producing a value
473system.cpu.iew.wb_consumers 369206768 # num instructions consuming a value
474system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
475system.cpu.iew.wb_rate 0.891276 # insts written-back per cycle
476system.cpu.iew.wb_fanout 0.557971 # average fanout of values written-back
477system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
478system.cpu.commit.commitSquashedInsts 101393272 # The number of squashed insts skipped by commit
479system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards
480system.cpu.commit.branchMispredicts 1491544 # The number of times a branch was mispredicted
481system.cpu.commit.committed_per_cycle::samples 255519011 # Number of insts commited each cycle
482system.cpu.commit.committed_per_cycle::mean 0.866328 # Number of insts commited each cycle
483system.cpu.commit.committed_per_cycle::stdev 1.656610 # Number of insts commited each cycle
484system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
485system.cpu.commit.committed_per_cycle::0 156315570 61.18% 61.18% # Number of insts commited each cycle
486system.cpu.commit.committed_per_cycle::1 57071451 22.34% 83.51% # Number of insts commited each cycle
487system.cpu.commit.committed_per_cycle::2 14008929 5.48% 88.99% # Number of insts commited each cycle
488system.cpu.commit.committed_per_cycle::3 12048530 4.72% 93.71% # Number of insts commited each cycle
489system.cpu.commit.committed_per_cycle::4 4172669 1.63% 95.34% # Number of insts commited each cycle
490system.cpu.commit.committed_per_cycle::5 2970306 1.16% 96.50% # Number of insts commited each cycle
491system.cpu.commit.committed_per_cycle::6 908783 0.36% 96.86% # Number of insts commited each cycle
492system.cpu.commit.committed_per_cycle::7 1048603 0.41% 97.27% # Number of insts commited each cycle
493system.cpu.commit.committed_per_cycle::8 6974170 2.73% 100.00% # Number of insts commited each cycle
494system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
495system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
496system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
497system.cpu.commit.committed_per_cycle::total 255519011 # Number of insts commited each cycle
498system.cpu.commit.committedInsts 132071192 # Number of instructions committed
499system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed
500system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
501system.cpu.commit.refs 77165304 # Number of memory references committed
502system.cpu.commit.loads 56649587 # Number of loads committed
503system.cpu.commit.membars 0 # Number of memory barriers committed
504system.cpu.commit.branches 12326938 # Number of branches committed
505system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
506system.cpu.commit.int_insts 220339553 # Number of committed integer instructions.
507system.cpu.commit.function_calls 797818 # Number of function calls committed.
508system.cpu.commit.bw_lim_events 6974170 # number cycles where commit BW limit reached
509system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
510system.cpu.rob.rob_reads 571301497 # The number of ROB reads
511system.cpu.rob.rob_writes 659310607 # The number of ROB writes
512system.cpu.timesIdled 5931768 # Number of times that the entire CPU went into an idle state and unscheduled itself
513system.cpu.idleCycles 19667841 # Total number of cycles that the CPU has spent unscheduled due to idling
514system.cpu.committedInsts 132071192 # Number of Instructions Simulated
515system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated
516system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated
517system.cpu.cpi 2.187901 # CPI: Cycles Per Instruction
518system.cpu.cpi_total 2.187901 # CPI: Total CPI of All Threads
519system.cpu.ipc 0.457059 # IPC: Instructions Per Cycle
520system.cpu.ipc_total 0.457059 # IPC: Total IPC of All Threads
521system.cpu.int_regfile_reads 554180321 # number of integer regfile reads
522system.cpu.int_regfile_writes 293821719 # number of integer regfile writes
523system.cpu.fp_regfile_reads 3217923 # number of floating regfile reads
524system.cpu.fp_regfile_writes 2009376 # number of floating regfile writes
525system.cpu.misc_regfile_reads 133360565 # number of misc regfile reads
526system.cpu.misc_regfile_writes 1689 # number of misc regfile writes
527system.cpu.toL2Bus.throughput 3892220 # Throughput (bytes/s)
528system.cpu.toL2Bus.trans_dist::ReadReq 7233 # Transaction distribution
529system.cpu.toL2Bus.trans_dist::ReadResp 7229 # Transaction distribution
530system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution
531system.cpu.toL2Bus.trans_dist::UpgradeReq 156 # Transaction distribution
532system.cpu.toL2Bus.trans_dist::UpgradeResp 156 # Transaction distribution
533system.cpu.toL2Bus.trans_dist::ReadExReq 1536 # Transaction distribution
534system.cpu.toL2Bus.trans_dist::ReadExResp 1536 # Transaction distribution
535system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13381 # Packet count per connected master and slave (bytes)
536system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4322 # Packet count per connected master and slave (bytes)
537system.cpu.toL2Bus.pkt_count::total 17703 # Packet count per connected master and slave (bytes)
538system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 423168 # Cumulative packet size per connected master and slave (bytes)
539system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128640 # Cumulative packet size per connected master and slave (bytes)
540system.cpu.toL2Bus.tot_pkt_size::total 551808 # Cumulative packet size per connected master and slave (bytes)
541system.cpu.toL2Bus.data_through_bus 551808 # Total data (bytes)
542system.cpu.toL2Bus.snoop_data_through_bus 9984 # Total snoop data (bytes)
543system.cpu.toL2Bus.reqLayer0.occupancy 4482000 # Layer occupancy (ticks)
544system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
545system.cpu.toL2Bus.respLayer0.occupancy 10834750 # Layer occupancy (ticks)
546system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
547system.cpu.toL2Bus.respLayer1.occupancy 3517155 # Layer occupancy (ticks)
548system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
549system.cpu.icache.tags.replacements 4647 # number of replacements
550system.cpu.icache.tags.tagsinuse 1626.526470 # Cycle average of tags in use
551system.cpu.icache.tags.total_refs 22335617 # Total number of references to valid blocks.
552system.cpu.icache.tags.sampled_refs 6612 # Sample count of references to valid blocks.
553system.cpu.icache.tags.avg_refs 3378.042498 # Average number of references to valid blocks.
554system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
555system.cpu.icache.tags.occ_blocks::cpu.inst 1626.526470 # Average occupied blocks per requestor
556system.cpu.icache.tags.occ_percent::cpu.inst 0.794202 # Average percentage of cache occupancy
557system.cpu.icache.tags.occ_percent::total 0.794202 # Average percentage of cache occupancy
558system.cpu.icache.ReadReq_hits::cpu.inst 22335617 # number of ReadReq hits
559system.cpu.icache.ReadReq_hits::total 22335617 # number of ReadReq hits
560system.cpu.icache.demand_hits::cpu.inst 22335617 # number of demand (read+write) hits
561system.cpu.icache.demand_hits::total 22335617 # number of demand (read+write) hits
562system.cpu.icache.overall_hits::cpu.inst 22335617 # number of overall hits
563system.cpu.icache.overall_hits::total 22335617 # number of overall hits
564system.cpu.icache.ReadReq_misses::cpu.inst 8823 # number of ReadReq misses
565system.cpu.icache.ReadReq_misses::total 8823 # number of ReadReq misses
566system.cpu.icache.demand_misses::cpu.inst 8823 # number of demand (read+write) misses
567system.cpu.icache.demand_misses::total 8823 # number of demand (read+write) misses
568system.cpu.icache.overall_misses::cpu.inst 8823 # number of overall misses
569system.cpu.icache.overall_misses::total 8823 # number of overall misses
570system.cpu.icache.ReadReq_miss_latency::cpu.inst 351986000 # number of ReadReq miss cycles
571system.cpu.icache.ReadReq_miss_latency::total 351986000 # number of ReadReq miss cycles
572system.cpu.icache.demand_miss_latency::cpu.inst 351986000 # number of demand (read+write) miss cycles
573system.cpu.icache.demand_miss_latency::total 351986000 # number of demand (read+write) miss cycles
574system.cpu.icache.overall_miss_latency::cpu.inst 351986000 # number of overall miss cycles
575system.cpu.icache.overall_miss_latency::total 351986000 # number of overall miss cycles
576system.cpu.icache.ReadReq_accesses::cpu.inst 22344440 # number of ReadReq accesses(hits+misses)
577system.cpu.icache.ReadReq_accesses::total 22344440 # number of ReadReq accesses(hits+misses)
578system.cpu.icache.demand_accesses::cpu.inst 22344440 # number of demand (read+write) accesses
579system.cpu.icache.demand_accesses::total 22344440 # number of demand (read+write) accesses
580system.cpu.icache.overall_accesses::cpu.inst 22344440 # number of overall (read+write) accesses
581system.cpu.icache.overall_accesses::total 22344440 # number of overall (read+write) accesses
582system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000395 # miss rate for ReadReq accesses
583system.cpu.icache.ReadReq_miss_rate::total 0.000395 # miss rate for ReadReq accesses
584system.cpu.icache.demand_miss_rate::cpu.inst 0.000395 # miss rate for demand accesses
585system.cpu.icache.demand_miss_rate::total 0.000395 # miss rate for demand accesses
586system.cpu.icache.overall_miss_rate::cpu.inst 0.000395 # miss rate for overall accesses
587system.cpu.icache.overall_miss_rate::total 0.000395 # miss rate for overall accesses
588system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39894.140315 # average ReadReq miss latency
589system.cpu.icache.ReadReq_avg_miss_latency::total 39894.140315 # average ReadReq miss latency
590system.cpu.icache.demand_avg_miss_latency::cpu.inst 39894.140315 # average overall miss latency
591system.cpu.icache.demand_avg_miss_latency::total 39894.140315 # average overall miss latency
592system.cpu.icache.overall_avg_miss_latency::cpu.inst 39894.140315 # average overall miss latency
593system.cpu.icache.overall_avg_miss_latency::total 39894.140315 # average overall miss latency
594system.cpu.icache.blocked_cycles::no_mshrs 978 # number of cycles access was blocked
595system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
596system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked
597system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
598system.cpu.icache.avg_blocked_cycles::no_mshrs 57.529412 # average number of cycles each access was blocked
599system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
600system.cpu.icache.fast_writes 0 # number of fast writes performed
601system.cpu.icache.cache_copies 0 # number of cache copies performed
602system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2054 # number of ReadReq MSHR hits
603system.cpu.icache.ReadReq_mshr_hits::total 2054 # number of ReadReq MSHR hits
604system.cpu.icache.demand_mshr_hits::cpu.inst 2054 # number of demand (read+write) MSHR hits
605system.cpu.icache.demand_mshr_hits::total 2054 # number of demand (read+write) MSHR hits
606system.cpu.icache.overall_mshr_hits::cpu.inst 2054 # number of overall MSHR hits
607system.cpu.icache.overall_mshr_hits::total 2054 # number of overall MSHR hits
608system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6769 # number of ReadReq MSHR misses
609system.cpu.icache.ReadReq_mshr_misses::total 6769 # number of ReadReq MSHR misses
610system.cpu.icache.demand_mshr_misses::cpu.inst 6769 # number of demand (read+write) MSHR misses
611system.cpu.icache.demand_mshr_misses::total 6769 # number of demand (read+write) MSHR misses
612system.cpu.icache.overall_mshr_misses::cpu.inst 6769 # number of overall MSHR misses
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616system.cpu.icache.demand_mshr_miss_latency::cpu.inst 262790750 # number of demand (read+write) MSHR miss cycles
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618system.cpu.icache.overall_mshr_miss_latency::cpu.inst 262790750 # number of overall MSHR miss cycles
619system.cpu.icache.overall_mshr_miss_latency::total 262790750 # number of overall MSHR miss cycles
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622system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for demand accesses
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627system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38822.684296 # average ReadReq mshr miss latency
628system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38822.684296 # average overall mshr miss latency
629system.cpu.icache.demand_avg_mshr_miss_latency::total 38822.684296 # average overall mshr miss latency
630system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38822.684296 # average overall mshr miss latency
631system.cpu.icache.overall_avg_mshr_miss_latency::total 38822.684296 # average overall mshr miss latency
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637system.cpu.l2cache.tags.avg_refs 0.846635 # Average number of references to valid blocks.
638system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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640system.cpu.l2cache.tags.occ_blocks::cpu.inst 2240.158867 # Average occupied blocks per requestor
641system.cpu.l2cache.tags.occ_blocks::cpu.data 312.330146 # Average occupied blocks per requestor
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650system.cpu.l2cache.Writeback_hits::total 13 # number of Writeback hits
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665system.cpu.l2cache.UpgradeReq_misses::total 155 # number of UpgradeReq misses
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689system.cpu.l2cache.Writeback_accesses::total 13 # number of Writeback accesses(hits+misses)
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704system.cpu.l2cache.UpgradeReq_miss_rate::total 0.993590 # miss rate for UpgradeReq accesses
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712system.cpu.l2cache.overall_miss_rate::total 0.622780 # miss rate for overall accesses
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714system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72496.495327 # average ReadReq miss latency
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716system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 63233.158927 # average ReadExReq miss latency
717system.cpu.l2cache.ReadExReq_avg_miss_latency::total 63233.158927 # average ReadExReq miss latency
718system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65687.848547 # average overall miss latency
719system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65259.070005 # average overall miss latency
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721system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65687.848547 # average overall miss latency
722system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65259.070005 # average overall miss latency
723system.cpu.l2cache.overall_avg_miss_latency::total 65531.413125 # average overall miss latency
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725system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
726system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
727system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
728system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
729system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
730system.cpu.l2cache.fast_writes 0 # number of fast writes performed
731system.cpu.l2cache.cache_copies 0 # number of cache copies performed
732system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3407 # number of ReadReq MSHR misses
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734system.cpu.l2cache.ReadReq_mshr_misses::total 3835 # number of ReadReq MSHR misses
735system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 155 # number of UpgradeReq MSHR misses
736system.cpu.l2cache.UpgradeReq_mshr_misses::total 155 # number of UpgradeReq MSHR misses
737system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1529 # number of ReadExReq MSHR misses
738system.cpu.l2cache.ReadExReq_mshr_misses::total 1529 # number of ReadExReq MSHR misses
739system.cpu.l2cache.demand_mshr_misses::cpu.inst 3407 # number of demand (read+write) MSHR misses
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743system.cpu.l2cache.overall_mshr_misses::cpu.data 1957 # number of overall MSHR misses
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749system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1550155 # number of UpgradeReq MSHR miss cycles
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751system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 77075500 # number of ReadExReq MSHR miss cycles
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759system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.922414 # mshr miss rate for ReadReq accesses
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761system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993590 # mshr miss rate for UpgradeReq accesses
762system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.993590 # mshr miss rate for UpgradeReq accesses
763system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995443 # mshr miss rate for ReadExReq accesses
764system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995443 # mshr miss rate for ReadExReq accesses
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766system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.978500 # mshr miss rate for demand accesses
767system.cpu.l2cache.demand_mshr_miss_rate::total 0.622780 # mshr miss rate for demand accesses
768system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.515197 # mshr miss rate for overall accesses
769system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.978500 # mshr miss rate for overall accesses
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772system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60010.514019 # average ReadReq mshr miss latency
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781system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53097.446434 # average overall mshr miss latency
782system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52508.942259 # average overall mshr miss latency
783system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52882.736764 # average overall mshr miss latency
784system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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786system.cpu.dcache.tags.tagsinuse 1431.071362 # Cycle average of tags in use
787system.cpu.dcache.tags.total_refs 66125332 # Total number of references to valid blocks.
788system.cpu.dcache.tags.sampled_refs 1997 # Sample count of references to valid blocks.
789system.cpu.dcache.tags.avg_refs 33112.334502 # Average number of references to valid blocks.
790system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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833system.cpu.dcache.overall_miss_rate::total 0.000039 # miss rate for overall accesses
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835system.cpu.dcache.ReadReq_avg_miss_latency::total 60298.690710 # average ReadReq miss latency
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837system.cpu.dcache.WriteReq_avg_miss_latency::total 62657.209096 # average WriteReq miss latency
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839system.cpu.dcache.demand_avg_miss_latency::total 61829.738113 # average overall miss latency
840system.cpu.dcache.overall_avg_miss_latency::cpu.data 61829.738113 # average overall miss latency
841system.cpu.dcache.overall_avg_miss_latency::total 61829.738113 # average overall miss latency
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847system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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849system.cpu.dcache.cache_copies 0 # number of cache copies performed
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851system.cpu.dcache.writebacks::total 13 # number of writebacks
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853system.cpu.dcache.ReadReq_mshr_hits::total 450 # number of ReadReq MSHR hits
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855system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits
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862system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1691 # number of WriteReq MSHR misses
863system.cpu.dcache.WriteReq_mshr_misses::total 1691 # number of WriteReq MSHR misses
864system.cpu.dcache.demand_mshr_misses::cpu.data 2156 # number of demand (read+write) MSHR misses
865system.cpu.dcache.demand_mshr_misses::total 2156 # number of demand (read+write) MSHR misses
866system.cpu.dcache.overall_mshr_misses::cpu.data 2156 # number of overall MSHR misses
867system.cpu.dcache.overall_mshr_misses::total 2156 # number of overall MSHR misses
868system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31923750 # number of ReadReq MSHR miss cycles
869system.cpu.dcache.ReadReq_mshr_miss_latency::total 31923750 # number of ReadReq MSHR miss cycles
870system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101848595 # number of WriteReq MSHR miss cycles
871system.cpu.dcache.WriteReq_mshr_miss_latency::total 101848595 # number of WriteReq MSHR miss cycles
872system.cpu.dcache.demand_mshr_miss_latency::cpu.data 133772345 # number of demand (read+write) MSHR miss cycles
873system.cpu.dcache.demand_mshr_miss_latency::total 133772345 # number of demand (read+write) MSHR miss cycles
874system.cpu.dcache.overall_mshr_miss_latency::cpu.data 133772345 # number of overall MSHR miss cycles
875system.cpu.dcache.overall_mshr_miss_latency::total 133772345 # number of overall MSHR miss cycles
876system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
877system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
878system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000082 # mshr miss rate for WriteReq accesses
879system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000082 # mshr miss rate for WriteReq accesses
880system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for demand accesses
881system.cpu.dcache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses
882system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for overall accesses
883system.cpu.dcache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses
884system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68653.225806 # average ReadReq mshr miss latency
885system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68653.225806 # average ReadReq mshr miss latency
886system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60229.801892 # average WriteReq mshr miss latency
887system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60229.801892 # average WriteReq mshr miss latency
888system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62046.542208 # average overall mshr miss latency
889system.cpu.dcache.demand_avg_mshr_miss_latency::total 62046.542208 # average overall mshr miss latency
890system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62046.542208 # average overall mshr miss latency
891system.cpu.dcache.overall_avg_mshr_miss_latency::total 62046.542208 # average overall mshr miss latency
892system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
893
894---------- End Simulation Statistics ----------