1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.082836 # Number of seconds simulated
4sim_ticks 82836235000 # Number of ticks simulated
5final_tick 82836235000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 70076 # Simulator instruction rate (inst/s)
8host_op_rate 117454 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 43952394 # Simulator tick rate (ticks/s)
10host_mem_usage 275820 # Number of bytes of host memory used
11host_seconds 1884.68 # Real time elapsed on the host
12sim_insts 132071192 # Number of instructions simulated
13sim_ops 221362961 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 218368 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 124544 # Number of bytes read from this memory
16system.physmem.bytes_read::total 342912 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 218368 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 218368 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 3412 # Number of read requests responded to by this memory

--- 53 unchanged lines hidden (view full) ---

73system.physmem.totGap 82836206000 # Total gap between requests
74system.physmem.readPktSize::0 0 # Categorize read packet sizes
75system.physmem.readPktSize::1 0 # Categorize read packet sizes
76system.physmem.readPktSize::2 0 # Categorize read packet sizes
77system.physmem.readPktSize::3 0 # Categorize read packet sizes
78system.physmem.readPktSize::4 0 # Categorize read packet sizes
79system.physmem.readPktSize::5 0 # Categorize read packet sizes
80system.physmem.readPktSize::6 5362 # Categorize read packet sizes
81system.physmem.writePktSize::0 0 # Categorize write packet sizes
82system.physmem.writePktSize::1 0 # Categorize write packet sizes
83system.physmem.writePktSize::2 0 # Categorize write packet sizes
84system.physmem.writePktSize::3 0 # Categorize write packet sizes
85system.physmem.writePktSize::4 0 # Categorize write packet sizes
86system.physmem.writePktSize::5 0 # Categorize write packet sizes
87system.physmem.writePktSize::6 0 # Categorize write packet sizes
88system.physmem.rdQLenPdf::0 4169 # What read queue length does an incoming req see
89system.physmem.rdQLenPdf::1 943 # What read queue length does an incoming req see
90system.physmem.rdQLenPdf::2 199 # What read queue length does an incoming req see
91system.physmem.rdQLenPdf::3 43 # What read queue length does an incoming req see
92system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
93system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see

--- 16 unchanged lines hidden (view full) ---

112system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
120system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
121system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
122system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
123system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
124system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
125system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
126system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
127system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see

--- 16 unchanged lines hidden (view full) ---

144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
152system.physmem.totQLat 15721750 # Total cycles spent in queuing delays
153system.physmem.totMemAccLat 132180500 # Sum of mem lat for all requests
154system.physmem.totBusLat 26795000 # Total cycles spent in databus access
155system.physmem.totBankLat 89663750 # Total cycles spent in bank access
156system.physmem.avgQLat 2932.07 # Average queueing delay per request
157system.physmem.avgBankLat 16722.07 # Average bank access latency per request
158system.physmem.avgBusLat 4997.20 # Average bus latency per request
159system.physmem.avgMemAccLat 24651.34 # Average memory access latency
160system.physmem.avgRdBW 4.14 # Average achieved read bandwidth in MB/s
161system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
162system.physmem.avgConsumedRdBW 4.14 # Average consumed read bandwidth in MB/s
163system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
164system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
165system.physmem.busUtil 0.03 # Data bus utilization in percentage
166system.physmem.avgRdQLen 0.00 # Average read queue length over time
167system.physmem.avgWrQLen 0.00 # Average write queue length over time

--- 460 unchanged lines hidden (view full) ---

628system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1555 # number of ReadExReq MSHR misses
629system.cpu.l2cache.ReadExReq_mshr_misses::total 1555 # number of ReadExReq MSHR misses
630system.cpu.l2cache.demand_mshr_misses::cpu.inst 3413 # number of demand (read+write) MSHR misses
631system.cpu.l2cache.demand_mshr_misses::cpu.data 1949 # number of demand (read+write) MSHR misses
632system.cpu.l2cache.demand_mshr_misses::total 5362 # number of demand (read+write) MSHR misses
633system.cpu.l2cache.overall_mshr_misses::cpu.inst 3413 # number of overall MSHR misses
634system.cpu.l2cache.overall_mshr_misses::cpu.data 1949 # number of overall MSHR misses
635system.cpu.l2cache.overall_mshr_misses::total 5362 # number of overall MSHR misses
636system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 121265541 # number of ReadReq MSHR miss cycles
637system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18645311 # number of ReadReq MSHR miss cycles
638system.cpu.l2cache.ReadReq_mshr_miss_latency::total 139910852 # number of ReadReq MSHR miss cycles
639system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1530153 # number of UpgradeReq MSHR miss cycles
640system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1530153 # number of UpgradeReq MSHR miss cycles
641system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49241002 # number of ReadExReq MSHR miss cycles
642system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49241002 # number of ReadExReq MSHR miss cycles
643system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 121265541 # number of demand (read+write) MSHR miss cycles
644system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67886313 # number of demand (read+write) MSHR miss cycles
645system.cpu.l2cache.demand_mshr_miss_latency::total 189151854 # number of demand (read+write) MSHR miss cycles
646system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 121265541 # number of overall MSHR miss cycles
647system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67886313 # number of overall MSHR miss cycles
648system.cpu.l2cache.overall_mshr_miss_latency::total 189151854 # number of overall MSHR miss cycles
649system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.496581 # mshr miss rate for ReadReq accesses
650system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.929245 # mshr miss rate for ReadReq accesses
651system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.521721 # mshr miss rate for ReadReq accesses
652system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
653system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
654system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995519 # mshr miss rate for ReadExReq accesses
655system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995519 # mshr miss rate for ReadExReq accesses
656system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.496581 # mshr miss rate for demand accesses
657system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.981370 # mshr miss rate for demand accesses
658system.cpu.l2cache.demand_mshr_miss_rate::total 0.605260 # mshr miss rate for demand accesses
659system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496581 # mshr miss rate for overall accesses
660system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.981370 # mshr miss rate for overall accesses
661system.cpu.l2cache.overall_mshr_miss_rate::total 0.605260 # mshr miss rate for overall accesses
662system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35530.483739 # average ReadReq mshr miss latency
663system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47323.124365 # average ReadReq mshr miss latency
664system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36750.946152 # average ReadReq mshr miss latency
665system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
666system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
667system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31666.239228 # average ReadExReq mshr miss latency
668system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31666.239228 # average ReadExReq mshr miss latency
669system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35530.483739 # average overall mshr miss latency
670system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34831.356080 # average overall mshr miss latency
671system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35276.362178 # average overall mshr miss latency
672system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35530.483739 # average overall mshr miss latency
673system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34831.356080 # average overall mshr miss latency
674system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35276.362178 # average overall mshr miss latency
675system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
676system.cpu.dcache.replacements 56 # number of replacements
677system.cpu.dcache.tagsinuse 1416.460930 # Cycle average of tags in use
678system.cpu.dcache.total_refs 67604390 # Total number of references to valid blocks.
679system.cpu.dcache.sampled_refs 1983 # Sample count of references to valid blocks.
680system.cpu.dcache.avg_refs 34091.976803 # Average number of references to valid blocks.
681system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
682system.cpu.dcache.occ_blocks::cpu.data 1416.460930 # Average occupied blocks per requestor

--- 103 unchanged lines hidden ---