| config.ini (11680:b4d943429dc6) | config.ini (11959:c000bfbbdadd) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 6 unchanged lines hidden (view full) --- 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 6 unchanged lines hidden (view full) --- 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true |
| 23kvm_vm=Null |
|
| 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 --- 29 unchanged lines hidden (view full) --- 60LQEntries=32 61LSQCheckLoads=true 62LSQDepCheckShift=4 63SQEntries=32 64SSITSize=1024 65activity=0 66backComSize=5 67branchPred=system.cpu.branchPred | 24load_addr_mask=1099511627775 25load_offset=0 26mem_mode=timing 27mem_ranges= 28memories=system.physmem 29mmap_using_noreserve=false 30multi_thread=false 31num_work_ids=16 --- 29 unchanged lines hidden (view full) --- 61LQEntries=32 62LSQCheckLoads=true 63LSQDepCheckShift=4 64SQEntries=32 65SSITSize=1024 66activity=0 67backComSize=5 68branchPred=system.cpu.branchPred |
| 68cachePorts=200 | 69cacheStorePorts=200 |
| 69checker=Null 70clk_domain=system.cpu_clk_domain 71commitToDecodeDelay=1 72commitToFetchDelay=1 73commitToIEWDelay=1 74commitToRenameDelay=1 75commitWidth=8 76cpu_id=0 --- 57 unchanged lines hidden (view full) --- 134smtLSQThreshold=100 135smtNumFetchingThreads=1 136smtROBPolicy=Partitioned 137smtROBThreshold=100 138socket_id=0 139squashWidth=8 140store_set_clear_period=250000 141switched_out=false | 70checker=Null 71clk_domain=system.cpu_clk_domain 72commitToDecodeDelay=1 73commitToFetchDelay=1 74commitToIEWDelay=1 75commitToRenameDelay=1 76commitWidth=8 77cpu_id=0 --- 57 unchanged lines hidden (view full) --- 135smtLSQThreshold=100 136smtNumFetchingThreads=1 137smtROBPolicy=Partitioned 138smtROBThreshold=100 139socket_id=0 140squashWidth=8 141store_set_clear_period=250000 142switched_out=false |
| 143syscallRetryLatency=10000 |
|
| 142system=system 143tracer=system.cpu.tracer 144trapLatency=13 145wbWidth=8 146workload=system.cpu.workload 147dcache_port=system.cpu.dcache.cpu_side 148icache_port=system.cpu.icache.cpu_side 149 --- 28 unchanged lines hidden (view full) --- 178 179[system.cpu.dcache] 180type=Cache 181children=tags 182addr_ranges=0:18446744073709551615:0:0:0:0 183assoc=2 184clk_domain=system.cpu_clk_domain 185clusivity=mostly_incl | 144system=system 145tracer=system.cpu.tracer 146trapLatency=13 147wbWidth=8 148workload=system.cpu.workload 149dcache_port=system.cpu.dcache.cpu_side 150icache_port=system.cpu.icache.cpu_side 151 --- 28 unchanged lines hidden (view full) --- 180 181[system.cpu.dcache] 182type=Cache 183children=tags 184addr_ranges=0:18446744073709551615:0:0:0:0 185assoc=2 186clk_domain=system.cpu_clk_domain 187clusivity=mostly_incl |
| 188data_latency=2 |
|
| 186default_p_state=UNDEFINED 187demand_mshr_reserve=1 188eventq_index=0 | 189default_p_state=UNDEFINED 190demand_mshr_reserve=1 191eventq_index=0 |
| 189hit_latency=2 | |
| 190is_read_only=false 191max_miss_count=0 192mshrs=4 193p_state_clk_gate_bins=20 194p_state_clk_gate_max=1000000000000 195p_state_clk_gate_min=1000 196power_model=Null 197prefetch_on_access=false 198prefetcher=Null 199response_latency=2 200sequential_access=false 201size=262144 202system=system | 192is_read_only=false 193max_miss_count=0 194mshrs=4 195p_state_clk_gate_bins=20 196p_state_clk_gate_max=1000000000000 197p_state_clk_gate_min=1000 198power_model=Null 199prefetch_on_access=false 200prefetcher=Null 201response_latency=2 202sequential_access=false 203size=262144 204system=system |
| 205tag_latency=2 |
|
| 203tags=system.cpu.dcache.tags 204tgts_per_mshr=20 205write_buffers=8 206writeback_clean=false 207cpu_side=system.cpu.dcache_port 208mem_side=system.cpu.toL2Bus.slave[1] 209 210[system.cpu.dcache.tags] 211type=LRU 212assoc=2 213block_size=64 214clk_domain=system.cpu_clk_domain | 206tags=system.cpu.dcache.tags 207tgts_per_mshr=20 208write_buffers=8 209writeback_clean=false 210cpu_side=system.cpu.dcache_port 211mem_side=system.cpu.toL2Bus.slave[1] 212 213[system.cpu.dcache.tags] 214type=LRU 215assoc=2 216block_size=64 217clk_domain=system.cpu_clk_domain |
| 218data_latency=2 |
|
| 215default_p_state=UNDEFINED 216eventq_index=0 | 219default_p_state=UNDEFINED 220eventq_index=0 |
| 217hit_latency=2 | |
| 218p_state_clk_gate_bins=20 219p_state_clk_gate_max=1000000000000 220p_state_clk_gate_min=1000 221power_model=Null 222sequential_access=false 223size=262144 | 221p_state_clk_gate_bins=20 222p_state_clk_gate_max=1000000000000 223p_state_clk_gate_min=1000 224power_model=Null 225sequential_access=false 226size=262144 |
| 227tag_latency=2 |
|
| 224 225[system.cpu.dtb] 226type=X86TLB 227children=walker 228eventq_index=0 229size=64 230walker=system.cpu.dtb.walker 231 --- 76 unchanged lines hidden (view full) --- 308type=OpDesc 309eventq_index=0 310opClass=FloatCvt 311opLat=2 312pipelined=true 313 314[system.cpu.fuPool.FUList3] 315type=FUDesc | 228 229[system.cpu.dtb] 230type=X86TLB 231children=walker 232eventq_index=0 233size=64 234walker=system.cpu.dtb.walker 235 --- 76 unchanged lines hidden (view full) --- 312type=OpDesc 313eventq_index=0 314opClass=FloatCvt 315opLat=2 316pipelined=true 317 318[system.cpu.fuPool.FUList3] 319type=FUDesc |
| 316children=opList0 opList1 opList2 | 320children=opList0 opList1 opList2 opList3 opList4 |
| 317count=2 318eventq_index=0 | 321count=2 322eventq_index=0 |
| 319opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 | 323opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 |
| 320 321[system.cpu.fuPool.FUList3.opList0] 322type=OpDesc 323eventq_index=0 324opClass=FloatMult 325opLat=4 326pipelined=true 327 328[system.cpu.fuPool.FUList3.opList1] 329type=OpDesc 330eventq_index=0 | 324 325[system.cpu.fuPool.FUList3.opList0] 326type=OpDesc 327eventq_index=0 328opClass=FloatMult 329opLat=4 330pipelined=true 331 332[system.cpu.fuPool.FUList3.opList1] 333type=OpDesc 334eventq_index=0 |
| 335opClass=FloatMultAcc 336opLat=5 337pipelined=true 338 339[system.cpu.fuPool.FUList3.opList2] 340type=OpDesc 341eventq_index=0 342opClass=FloatMisc 343opLat=3 344pipelined=true 345 346[system.cpu.fuPool.FUList3.opList3] 347type=OpDesc 348eventq_index=0 |
|
| 331opClass=FloatDiv 332opLat=12 333pipelined=false 334 | 349opClass=FloatDiv 350opLat=12 351pipelined=false 352 |
| 335[system.cpu.fuPool.FUList3.opList2] | 353[system.cpu.fuPool.FUList3.opList4] |
| 336type=OpDesc 337eventq_index=0 338opClass=FloatSqrt 339opLat=24 340pipelined=false 341 342[system.cpu.fuPool.FUList4] 343type=FUDesc | 354type=OpDesc 355eventq_index=0 356opClass=FloatSqrt 357opLat=24 358pipelined=false 359 360[system.cpu.fuPool.FUList4] 361type=FUDesc |
| 344children=opList | 362children=opList0 opList1 |
| 345count=0 346eventq_index=0 | 363count=0 364eventq_index=0 |
| 347opList=system.cpu.fuPool.FUList4.opList | 365opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 |
| 348 | 366 |
| 349[system.cpu.fuPool.FUList4.opList] | 367[system.cpu.fuPool.FUList4.opList0] |
| 350type=OpDesc 351eventq_index=0 352opClass=MemRead 353opLat=1 354pipelined=true 355 | 368type=OpDesc 369eventq_index=0 370opClass=MemRead 371opLat=1 372pipelined=true 373 |
| 374[system.cpu.fuPool.FUList4.opList1] 375type=OpDesc 376eventq_index=0 377opClass=FloatMemRead 378opLat=1 379pipelined=true 380 |
|
| 356[system.cpu.fuPool.FUList5] 357type=FUDesc 358children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 359count=4 360eventq_index=0 361opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 362 363[system.cpu.fuPool.FUList5.opList00] --- 133 unchanged lines hidden (view full) --- 497type=OpDesc 498eventq_index=0 499opClass=SimdFloatSqrt 500opLat=1 501pipelined=true 502 503[system.cpu.fuPool.FUList6] 504type=FUDesc | 381[system.cpu.fuPool.FUList5] 382type=FUDesc 383children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 384count=4 385eventq_index=0 386opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 387 388[system.cpu.fuPool.FUList5.opList00] --- 133 unchanged lines hidden (view full) --- 522type=OpDesc 523eventq_index=0 524opClass=SimdFloatSqrt 525opLat=1 526pipelined=true 527 528[system.cpu.fuPool.FUList6] 529type=FUDesc |
| 505children=opList | 530children=opList0 opList1 |
| 506count=0 507eventq_index=0 | 531count=0 532eventq_index=0 |
| 508opList=system.cpu.fuPool.FUList6.opList | 533opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 |
| 509 | 534 |
| 510[system.cpu.fuPool.FUList6.opList] | 535[system.cpu.fuPool.FUList6.opList0] |
| 511type=OpDesc 512eventq_index=0 513opClass=MemWrite 514opLat=1 515pipelined=true 516 | 536type=OpDesc 537eventq_index=0 538opClass=MemWrite 539opLat=1 540pipelined=true 541 |
| 542[system.cpu.fuPool.FUList6.opList1] 543type=OpDesc 544eventq_index=0 545opClass=FloatMemWrite 546opLat=1 547pipelined=true 548 |
|
| 517[system.cpu.fuPool.FUList7] 518type=FUDesc | 549[system.cpu.fuPool.FUList7] 550type=FUDesc |
| 519children=opList0 opList1 | 551children=opList0 opList1 opList2 opList3 |
| 520count=4 521eventq_index=0 | 552count=4 553eventq_index=0 |
| 522opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 | 554opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 |
| 523 524[system.cpu.fuPool.FUList7.opList0] 525type=OpDesc 526eventq_index=0 527opClass=MemRead 528opLat=1 529pipelined=true 530 531[system.cpu.fuPool.FUList7.opList1] 532type=OpDesc 533eventq_index=0 534opClass=MemWrite 535opLat=1 536pipelined=true 537 | 555 556[system.cpu.fuPool.FUList7.opList0] 557type=OpDesc 558eventq_index=0 559opClass=MemRead 560opLat=1 561pipelined=true 562 563[system.cpu.fuPool.FUList7.opList1] 564type=OpDesc 565eventq_index=0 566opClass=MemWrite 567opLat=1 568pipelined=true 569 |
| 570[system.cpu.fuPool.FUList7.opList2] 571type=OpDesc 572eventq_index=0 573opClass=FloatMemRead 574opLat=1 575pipelined=true 576 577[system.cpu.fuPool.FUList7.opList3] 578type=OpDesc 579eventq_index=0 580opClass=FloatMemWrite 581opLat=1 582pipelined=true 583 |
|
| 538[system.cpu.fuPool.FUList8] 539type=FUDesc 540children=opList 541count=1 542eventq_index=0 543opList=system.cpu.fuPool.FUList8.opList 544 545[system.cpu.fuPool.FUList8.opList] --- 5 unchanged lines hidden (view full) --- 551 552[system.cpu.icache] 553type=Cache 554children=tags 555addr_ranges=0:18446744073709551615:0:0:0:0 556assoc=2 557clk_domain=system.cpu_clk_domain 558clusivity=mostly_incl | 584[system.cpu.fuPool.FUList8] 585type=FUDesc 586children=opList 587count=1 588eventq_index=0 589opList=system.cpu.fuPool.FUList8.opList 590 591[system.cpu.fuPool.FUList8.opList] --- 5 unchanged lines hidden (view full) --- 597 598[system.cpu.icache] 599type=Cache 600children=tags 601addr_ranges=0:18446744073709551615:0:0:0:0 602assoc=2 603clk_domain=system.cpu_clk_domain 604clusivity=mostly_incl |
| 605data_latency=2 |
|
| 559default_p_state=UNDEFINED 560demand_mshr_reserve=1 561eventq_index=0 | 606default_p_state=UNDEFINED 607demand_mshr_reserve=1 608eventq_index=0 |
| 562hit_latency=2 | |
| 563is_read_only=true 564max_miss_count=0 565mshrs=4 566p_state_clk_gate_bins=20 567p_state_clk_gate_max=1000000000000 568p_state_clk_gate_min=1000 569power_model=Null 570prefetch_on_access=false 571prefetcher=Null 572response_latency=2 573sequential_access=false 574size=131072 575system=system | 609is_read_only=true 610max_miss_count=0 611mshrs=4 612p_state_clk_gate_bins=20 613p_state_clk_gate_max=1000000000000 614p_state_clk_gate_min=1000 615power_model=Null 616prefetch_on_access=false 617prefetcher=Null 618response_latency=2 619sequential_access=false 620size=131072 621system=system |
| 622tag_latency=2 |
|
| 576tags=system.cpu.icache.tags 577tgts_per_mshr=20 578write_buffers=8 579writeback_clean=true 580cpu_side=system.cpu.icache_port 581mem_side=system.cpu.toL2Bus.slave[0] 582 583[system.cpu.icache.tags] 584type=LRU 585assoc=2 586block_size=64 587clk_domain=system.cpu_clk_domain | 623tags=system.cpu.icache.tags 624tgts_per_mshr=20 625write_buffers=8 626writeback_clean=true 627cpu_side=system.cpu.icache_port 628mem_side=system.cpu.toL2Bus.slave[0] 629 630[system.cpu.icache.tags] 631type=LRU 632assoc=2 633block_size=64 634clk_domain=system.cpu_clk_domain |
| 635data_latency=2 |
|
| 588default_p_state=UNDEFINED 589eventq_index=0 | 636default_p_state=UNDEFINED 637eventq_index=0 |
| 590hit_latency=2 | |
| 591p_state_clk_gate_bins=20 592p_state_clk_gate_max=1000000000000 593p_state_clk_gate_min=1000 594power_model=Null 595sequential_access=false 596size=131072 | 638p_state_clk_gate_bins=20 639p_state_clk_gate_max=1000000000000 640p_state_clk_gate_min=1000 641power_model=Null 642sequential_access=false 643size=131072 |
| 644tag_latency=2 |
|
| 597 598[system.cpu.interrupts] 599type=X86LocalApic 600clk_domain=system.cpu.apic_clk_domain 601default_p_state=UNDEFINED 602eventq_index=0 603int_latency=1000 604p_state_clk_gate_bins=20 --- 33 unchanged lines hidden (view full) --- 638 639[system.cpu.l2cache] 640type=Cache 641children=tags 642addr_ranges=0:18446744073709551615:0:0:0:0 643assoc=8 644clk_domain=system.cpu_clk_domain 645clusivity=mostly_incl | 645 646[system.cpu.interrupts] 647type=X86LocalApic 648clk_domain=system.cpu.apic_clk_domain 649default_p_state=UNDEFINED 650eventq_index=0 651int_latency=1000 652p_state_clk_gate_bins=20 --- 33 unchanged lines hidden (view full) --- 686 687[system.cpu.l2cache] 688type=Cache 689children=tags 690addr_ranges=0:18446744073709551615:0:0:0:0 691assoc=8 692clk_domain=system.cpu_clk_domain 693clusivity=mostly_incl |
| 694data_latency=20 |
|
| 646default_p_state=UNDEFINED 647demand_mshr_reserve=1 648eventq_index=0 | 695default_p_state=UNDEFINED 696demand_mshr_reserve=1 697eventq_index=0 |
| 649hit_latency=20 | |
| 650is_read_only=false 651max_miss_count=0 652mshrs=20 653p_state_clk_gate_bins=20 654p_state_clk_gate_max=1000000000000 655p_state_clk_gate_min=1000 656power_model=Null 657prefetch_on_access=false 658prefetcher=Null 659response_latency=20 660sequential_access=false 661size=2097152 662system=system | 698is_read_only=false 699max_miss_count=0 700mshrs=20 701p_state_clk_gate_bins=20 702p_state_clk_gate_max=1000000000000 703p_state_clk_gate_min=1000 704power_model=Null 705prefetch_on_access=false 706prefetcher=Null 707response_latency=20 708sequential_access=false 709size=2097152 710system=system |
| 711tag_latency=20 |
|
| 663tags=system.cpu.l2cache.tags 664tgts_per_mshr=12 665write_buffers=8 666writeback_clean=false 667cpu_side=system.cpu.toL2Bus.master[0] 668mem_side=system.membus.slave[1] 669 670[system.cpu.l2cache.tags] 671type=LRU 672assoc=8 673block_size=64 674clk_domain=system.cpu_clk_domain | 712tags=system.cpu.l2cache.tags 713tgts_per_mshr=12 714write_buffers=8 715writeback_clean=false 716cpu_side=system.cpu.toL2Bus.master[0] 717mem_side=system.membus.slave[1] 718 719[system.cpu.l2cache.tags] 720type=LRU 721assoc=8 722block_size=64 723clk_domain=system.cpu_clk_domain |
| 724data_latency=20 |
|
| 675default_p_state=UNDEFINED 676eventq_index=0 | 725default_p_state=UNDEFINED 726eventq_index=0 |
| 677hit_latency=20 | |
| 678p_state_clk_gate_bins=20 679p_state_clk_gate_max=1000000000000 680p_state_clk_gate_min=1000 681power_model=Null 682sequential_access=false 683size=2097152 | 727p_state_clk_gate_bins=20 728p_state_clk_gate_max=1000000000000 729p_state_clk_gate_min=1000 730power_model=Null 731sequential_access=false 732size=2097152 |
| 733tag_latency=20 |
|
| 684 685[system.cpu.toL2Bus] 686type=CoherentXBar 687children=snoop_filter 688clk_domain=system.cpu_clk_domain 689default_p_state=UNDEFINED 690eventq_index=0 691forward_latency=0 --- 19 unchanged lines hidden (view full) --- 711max_capacity=8388608 712system=system 713 714[system.cpu.tracer] 715type=ExeTracer 716eventq_index=0 717 718[system.cpu.workload] | 734 735[system.cpu.toL2Bus] 736type=CoherentXBar 737children=snoop_filter 738clk_domain=system.cpu_clk_domain 739default_p_state=UNDEFINED 740eventq_index=0 741forward_latency=0 --- 19 unchanged lines hidden (view full) --- 761max_capacity=8388608 762system=system 763 764[system.cpu.tracer] 765type=ExeTracer 766eventq_index=0 767 768[system.cpu.workload] |
| 719type=LiveProcess | 769type=Process |
| 720cmd=twolf smred 721cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing 722drivers= 723egid=100 724env= 725errout=cerr 726euid=100 727eventq_index=0 | 770cmd=twolf smred 771cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing 772drivers= 773egid=100 774env= 775errout=cerr 776euid=100 777eventq_index=0 |
| 728executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/twolf | 778executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/twolf |
| 729gid=100 730input=cin 731kvmInSE=false | 779gid=100 780input=cin 781kvmInSE=false |
| 732max_stack_size=67108864 | 782maxStackSize=67108864 |
| 733output=cout | 783output=cout |
| 784pgid=100 |
|
| 734pid=100 | 785pid=100 |
| 735ppid=99 | 786ppid=0 |
| 736simpoint=0 737system=system 738uid=100 739useArchPT=false 740 741[system.cpu_clk_domain] 742type=SrcClockDomain 743clock=500 --- 130 unchanged lines hidden --- | 787simpoint=0 788system=system 789uid=100 790useArchPT=false 791 792[system.cpu_clk_domain] 793type=SrcClockDomain 794clock=500 --- 130 unchanged lines hidden --- |