Cross Reference: /gem5/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini

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config.ini (11680:b4d943429dc6)	config.ini (11959:c000bfbbdadd)
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true	1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true
	23kvm_vm=Null
23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 51domain_id=-1 52eventq_index=0 53init_perf_level=0 54voltage_domain=system.voltage_domain 55 56[system.cpu] 57type=DerivO3CPU 58children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 59LFSTSize=1024 60LQEntries=32 61LSQCheckLoads=true 62LSQDepCheckShift=4 63SQEntries=32 64SSITSize=1024 65activity=0 66backComSize=5 67branchPred=system.cpu.branchPred	24load_addr_mask=1099511627775 25load_offset=0 26mem_mode=timing 27mem_ranges= 28memories=system.physmem 29mmap_using_noreserve=false 30multi_thread=false 31num_work_ids=16 32p_state_clk_gate_bins=20 33p_state_clk_gate_max=1000000000000 34p_state_clk_gate_min=1000 35power_model=Null 36readfile= 37symbolfile= 38thermal_components= 39thermal_model=Null 40work_begin_ckpt_count=0 41work_begin_cpu_id_exit=-1 42work_begin_exit_count=0 43work_cpus_ckpt_count=0 44work_end_ckpt_count=0 45work_end_exit_count=0 46work_item_id=-1 47system_port=system.membus.slave[0] 48 49[system.clk_domain] 50type=SrcClockDomain 51clock=1000 52domain_id=-1 53eventq_index=0 54init_perf_level=0 55voltage_domain=system.voltage_domain 56 57[system.cpu] 58type=DerivO3CPU 59children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 60LFSTSize=1024 61LQEntries=32 62LSQCheckLoads=true 63LSQDepCheckShift=4 64SQEntries=32 65SSITSize=1024 66activity=0 67backComSize=5 68branchPred=system.cpu.branchPred
68cachePorts=200	69cacheStorePorts=200
69checker=Null 70clk_domain=system.cpu_clk_domain 71commitToDecodeDelay=1 72commitToFetchDelay=1 73commitToIEWDelay=1 74commitToRenameDelay=1 75commitWidth=8 76cpu_id=0 77decodeToFetchDelay=1 78decodeToRenameDelay=1 79decodeWidth=8 80default_p_state=UNDEFINED 81dispatchWidth=8 82do_checkpoint_insts=true 83do_quiesce=true 84do_statistics_insts=true 85dtb=system.cpu.dtb 86eventq_index=0 87fetchBufferSize=64 88fetchQueueSize=32 89fetchToDecodeDelay=1 90fetchTrapLatency=1 91fetchWidth=8 92forwardComSize=5 93fuPool=system.cpu.fuPool 94function_trace=false 95function_trace_start=0 96iewToCommitDelay=1 97iewToDecodeDelay=1 98iewToFetchDelay=1 99iewToRenameDelay=1 100interrupts=system.cpu.interrupts 101isa=system.cpu.isa 102issueToExecuteDelay=1 103issueWidth=8 104itb=system.cpu.itb 105max_insts_all_threads=0 106max_insts_any_thread=0 107max_loads_all_threads=0 108max_loads_any_thread=0 109needsTSO=true 110numIQEntries=64 111numPhysCCRegs=1280 112numPhysFloatRegs=256 113numPhysIntRegs=256 114numROBEntries=192 115numRobs=1 116numThreads=1 117p_state_clk_gate_bins=20 118p_state_clk_gate_max=1000000000000 119p_state_clk_gate_min=1000 120power_model=Null 121profile=0 122progress_interval=0 123renameToDecodeDelay=1 124renameToFetchDelay=1 125renameToIEWDelay=2 126renameToROBDelay=1 127renameWidth=8 128simpoint_start_insts= 129smtCommitPolicy=RoundRobin 130smtFetchPolicy=SingleThread 131smtIQPolicy=Partitioned 132smtIQThreshold=100 133smtLSQPolicy=Partitioned 134smtLSQThreshold=100 135smtNumFetchingThreads=1 136smtROBPolicy=Partitioned 137smtROBThreshold=100 138socket_id=0 139squashWidth=8 140store_set_clear_period=250000 141switched_out=false	70checker=Null 71clk_domain=system.cpu_clk_domain 72commitToDecodeDelay=1 73commitToFetchDelay=1 74commitToIEWDelay=1 75commitToRenameDelay=1 76commitWidth=8 77cpu_id=0 78decodeToFetchDelay=1 79decodeToRenameDelay=1 80decodeWidth=8 81default_p_state=UNDEFINED 82dispatchWidth=8 83do_checkpoint_insts=true 84do_quiesce=true 85do_statistics_insts=true 86dtb=system.cpu.dtb 87eventq_index=0 88fetchBufferSize=64 89fetchQueueSize=32 90fetchToDecodeDelay=1 91fetchTrapLatency=1 92fetchWidth=8 93forwardComSize=5 94fuPool=system.cpu.fuPool 95function_trace=false 96function_trace_start=0 97iewToCommitDelay=1 98iewToDecodeDelay=1 99iewToFetchDelay=1 100iewToRenameDelay=1 101interrupts=system.cpu.interrupts 102isa=system.cpu.isa 103issueToExecuteDelay=1 104issueWidth=8 105itb=system.cpu.itb 106max_insts_all_threads=0 107max_insts_any_thread=0 108max_loads_all_threads=0 109max_loads_any_thread=0 110needsTSO=true 111numIQEntries=64 112numPhysCCRegs=1280 113numPhysFloatRegs=256 114numPhysIntRegs=256 115numROBEntries=192 116numRobs=1 117numThreads=1 118p_state_clk_gate_bins=20 119p_state_clk_gate_max=1000000000000 120p_state_clk_gate_min=1000 121power_model=Null 122profile=0 123progress_interval=0 124renameToDecodeDelay=1 125renameToFetchDelay=1 126renameToIEWDelay=2 127renameToROBDelay=1 128renameWidth=8 129simpoint_start_insts= 130smtCommitPolicy=RoundRobin 131smtFetchPolicy=SingleThread 132smtIQPolicy=Partitioned 133smtIQThreshold=100 134smtLSQPolicy=Partitioned 135smtLSQThreshold=100 136smtNumFetchingThreads=1 137smtROBPolicy=Partitioned 138smtROBThreshold=100 139socket_id=0 140squashWidth=8 141store_set_clear_period=250000 142switched_out=false
	143syscallRetryLatency=10000
142system=system 143tracer=system.cpu.tracer 144trapLatency=13 145wbWidth=8 146workload=system.cpu.workload 147dcache_port=system.cpu.dcache.cpu_side 148icache_port=system.cpu.icache.cpu_side 149 150[system.cpu.apic_clk_domain] 151type=DerivedClockDomain 152clk_divider=16 153clk_domain=system.cpu_clk_domain 154eventq_index=0 155 156[system.cpu.branchPred] 157type=TournamentBP 158BTBEntries=4096 159BTBTagSize=16 160RASSize=16 161choiceCtrBits=2 162choicePredictorSize=8192 163eventq_index=0 164globalCtrBits=2 165globalPredictorSize=8192 166indirectHashGHR=true 167indirectHashTargets=true 168indirectPathLength=3 169indirectSets=256 170indirectTagSize=16 171indirectWays=2 172instShiftAmt=2 173localCtrBits=2 174localHistoryTableSize=2048 175localPredictorSize=2048 176numThreads=1 177useIndirect=true 178 179[system.cpu.dcache] 180type=Cache 181children=tags 182addr_ranges=0:18446744073709551615:0:0:0:0 183assoc=2 184clk_domain=system.cpu_clk_domain 185clusivity=mostly_incl	144system=system 145tracer=system.cpu.tracer 146trapLatency=13 147wbWidth=8 148workload=system.cpu.workload 149dcache_port=system.cpu.dcache.cpu_side 150icache_port=system.cpu.icache.cpu_side 151 152[system.cpu.apic_clk_domain] 153type=DerivedClockDomain 154clk_divider=16 155clk_domain=system.cpu_clk_domain 156eventq_index=0 157 158[system.cpu.branchPred] 159type=TournamentBP 160BTBEntries=4096 161BTBTagSize=16 162RASSize=16 163choiceCtrBits=2 164choicePredictorSize=8192 165eventq_index=0 166globalCtrBits=2 167globalPredictorSize=8192 168indirectHashGHR=true 169indirectHashTargets=true 170indirectPathLength=3 171indirectSets=256 172indirectTagSize=16 173indirectWays=2 174instShiftAmt=2 175localCtrBits=2 176localHistoryTableSize=2048 177localPredictorSize=2048 178numThreads=1 179useIndirect=true 180 181[system.cpu.dcache] 182type=Cache 183children=tags 184addr_ranges=0:18446744073709551615:0:0:0:0 185assoc=2 186clk_domain=system.cpu_clk_domain 187clusivity=mostly_incl
	188data_latency=2
186default_p_state=UNDEFINED 187demand_mshr_reserve=1 188eventq_index=0	189default_p_state=UNDEFINED 190demand_mshr_reserve=1 191eventq_index=0
189hit_latency=2
190is_read_only=false 191max_miss_count=0 192mshrs=4 193p_state_clk_gate_bins=20 194p_state_clk_gate_max=1000000000000 195p_state_clk_gate_min=1000 196power_model=Null 197prefetch_on_access=false 198prefetcher=Null 199response_latency=2 200sequential_access=false 201size=262144 202system=system	192is_read_only=false 193max_miss_count=0 194mshrs=4 195p_state_clk_gate_bins=20 196p_state_clk_gate_max=1000000000000 197p_state_clk_gate_min=1000 198power_model=Null 199prefetch_on_access=false 200prefetcher=Null 201response_latency=2 202sequential_access=false 203size=262144 204system=system
	205tag_latency=2
203tags=system.cpu.dcache.tags 204tgts_per_mshr=20 205write_buffers=8 206writeback_clean=false 207cpu_side=system.cpu.dcache_port 208mem_side=system.cpu.toL2Bus.slave[1] 209 210[system.cpu.dcache.tags] 211type=LRU 212assoc=2 213block_size=64 214clk_domain=system.cpu_clk_domain	206tags=system.cpu.dcache.tags 207tgts_per_mshr=20 208write_buffers=8 209writeback_clean=false 210cpu_side=system.cpu.dcache_port 211mem_side=system.cpu.toL2Bus.slave[1] 212 213[system.cpu.dcache.tags] 214type=LRU 215assoc=2 216block_size=64 217clk_domain=system.cpu_clk_domain
	218data_latency=2
215default_p_state=UNDEFINED 216eventq_index=0	219default_p_state=UNDEFINED 220eventq_index=0
217hit_latency=2
218p_state_clk_gate_bins=20 219p_state_clk_gate_max=1000000000000 220p_state_clk_gate_min=1000 221power_model=Null 222sequential_access=false 223size=262144	221p_state_clk_gate_bins=20 222p_state_clk_gate_max=1000000000000 223p_state_clk_gate_min=1000 224power_model=Null 225sequential_access=false 226size=262144
	227tag_latency=2
224 225[system.cpu.dtb] 226type=X86TLB 227children=walker 228eventq_index=0 229size=64 230walker=system.cpu.dtb.walker 231 232[system.cpu.dtb.walker] 233type=X86PagetableWalker 234clk_domain=system.cpu_clk_domain 235default_p_state=UNDEFINED 236eventq_index=0 237num_squash_per_cycle=4 238p_state_clk_gate_bins=20 239p_state_clk_gate_max=1000000000000 240p_state_clk_gate_min=1000 241power_model=Null 242system=system 243port=system.cpu.toL2Bus.slave[3] 244 245[system.cpu.fuPool] 246type=FUPool 247children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 248FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 249eventq_index=0 250 251[system.cpu.fuPool.FUList0] 252type=FUDesc 253children=opList 254count=6 255eventq_index=0 256opList=system.cpu.fuPool.FUList0.opList 257 258[system.cpu.fuPool.FUList0.opList] 259type=OpDesc 260eventq_index=0 261opClass=IntAlu 262opLat=1 263pipelined=true 264 265[system.cpu.fuPool.FUList1] 266type=FUDesc 267children=opList0 opList1 268count=2 269eventq_index=0 270opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 271 272[system.cpu.fuPool.FUList1.opList0] 273type=OpDesc 274eventq_index=0 275opClass=IntMult 276opLat=3 277pipelined=true 278 279[system.cpu.fuPool.FUList1.opList1] 280type=OpDesc 281eventq_index=0 282opClass=IntDiv 283opLat=1 284pipelined=false 285 286[system.cpu.fuPool.FUList2] 287type=FUDesc 288children=opList0 opList1 opList2 289count=4 290eventq_index=0 291opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 292 293[system.cpu.fuPool.FUList2.opList0] 294type=OpDesc 295eventq_index=0 296opClass=FloatAdd 297opLat=2 298pipelined=true 299 300[system.cpu.fuPool.FUList2.opList1] 301type=OpDesc 302eventq_index=0 303opClass=FloatCmp 304opLat=2 305pipelined=true 306 307[system.cpu.fuPool.FUList2.opList2] 308type=OpDesc 309eventq_index=0 310opClass=FloatCvt 311opLat=2 312pipelined=true 313 314[system.cpu.fuPool.FUList3] 315type=FUDesc	228 229[system.cpu.dtb] 230type=X86TLB 231children=walker 232eventq_index=0 233size=64 234walker=system.cpu.dtb.walker 235 236[system.cpu.dtb.walker] 237type=X86PagetableWalker 238clk_domain=system.cpu_clk_domain 239default_p_state=UNDEFINED 240eventq_index=0 241num_squash_per_cycle=4 242p_state_clk_gate_bins=20 243p_state_clk_gate_max=1000000000000 244p_state_clk_gate_min=1000 245power_model=Null 246system=system 247port=system.cpu.toL2Bus.slave[3] 248 249[system.cpu.fuPool] 250type=FUPool 251children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 252FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 253eventq_index=0 254 255[system.cpu.fuPool.FUList0] 256type=FUDesc 257children=opList 258count=6 259eventq_index=0 260opList=system.cpu.fuPool.FUList0.opList 261 262[system.cpu.fuPool.FUList0.opList] 263type=OpDesc 264eventq_index=0 265opClass=IntAlu 266opLat=1 267pipelined=true 268 269[system.cpu.fuPool.FUList1] 270type=FUDesc 271children=opList0 opList1 272count=2 273eventq_index=0 274opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 275 276[system.cpu.fuPool.FUList1.opList0] 277type=OpDesc 278eventq_index=0 279opClass=IntMult 280opLat=3 281pipelined=true 282 283[system.cpu.fuPool.FUList1.opList1] 284type=OpDesc 285eventq_index=0 286opClass=IntDiv 287opLat=1 288pipelined=false 289 290[system.cpu.fuPool.FUList2] 291type=FUDesc 292children=opList0 opList1 opList2 293count=4 294eventq_index=0 295opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 296 297[system.cpu.fuPool.FUList2.opList0] 298type=OpDesc 299eventq_index=0 300opClass=FloatAdd 301opLat=2 302pipelined=true 303 304[system.cpu.fuPool.FUList2.opList1] 305type=OpDesc 306eventq_index=0 307opClass=FloatCmp 308opLat=2 309pipelined=true 310 311[system.cpu.fuPool.FUList2.opList2] 312type=OpDesc 313eventq_index=0 314opClass=FloatCvt 315opLat=2 316pipelined=true 317 318[system.cpu.fuPool.FUList3] 319type=FUDesc
316children=opList0 opList1 opList2	320children=opList0 opList1 opList2 opList3 opList4
317count=2 318eventq_index=0	321count=2 322eventq_index=0
319opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2	323opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4
320 321[system.cpu.fuPool.FUList3.opList0] 322type=OpDesc 323eventq_index=0 324opClass=FloatMult 325opLat=4 326pipelined=true 327 328[system.cpu.fuPool.FUList3.opList1] 329type=OpDesc 330eventq_index=0	324 325[system.cpu.fuPool.FUList3.opList0] 326type=OpDesc 327eventq_index=0 328opClass=FloatMult 329opLat=4 330pipelined=true 331 332[system.cpu.fuPool.FUList3.opList1] 333type=OpDesc 334eventq_index=0
	335opClass=FloatMultAcc 336opLat=5 337pipelined=true 338 339[system.cpu.fuPool.FUList3.opList2] 340type=OpDesc 341eventq_index=0 342opClass=FloatMisc 343opLat=3 344pipelined=true 345 346[system.cpu.fuPool.FUList3.opList3] 347type=OpDesc 348eventq_index=0
331opClass=FloatDiv 332opLat=12 333pipelined=false 334	349opClass=FloatDiv 350opLat=12 351pipelined=false 352
335[system.cpu.fuPool.FUList3.opList2]	353[system.cpu.fuPool.FUList3.opList4]
336type=OpDesc 337eventq_index=0 338opClass=FloatSqrt 339opLat=24 340pipelined=false 341 342[system.cpu.fuPool.FUList4] 343type=FUDesc	354type=OpDesc 355eventq_index=0 356opClass=FloatSqrt 357opLat=24 358pipelined=false 359 360[system.cpu.fuPool.FUList4] 361type=FUDesc
344children=opList	362children=opList0 opList1
345count=0 346eventq_index=0	363count=0 364eventq_index=0
347opList=system.cpu.fuPool.FUList4.opList	365opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1
348	366
349[system.cpu.fuPool.FUList4.opList]	367[system.cpu.fuPool.FUList4.opList0]
350type=OpDesc 351eventq_index=0 352opClass=MemRead 353opLat=1 354pipelined=true 355	368type=OpDesc 369eventq_index=0 370opClass=MemRead 371opLat=1 372pipelined=true 373
	374[system.cpu.fuPool.FUList4.opList1] 375type=OpDesc 376eventq_index=0 377opClass=FloatMemRead 378opLat=1 379pipelined=true 380
356[system.cpu.fuPool.FUList5] 357type=FUDesc 358children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 359count=4 360eventq_index=0 361opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 362 363[system.cpu.fuPool.FUList5.opList00] 364type=OpDesc 365eventq_index=0 366opClass=SimdAdd 367opLat=1 368pipelined=true 369 370[system.cpu.fuPool.FUList5.opList01] 371type=OpDesc 372eventq_index=0 373opClass=SimdAddAcc 374opLat=1 375pipelined=true 376 377[system.cpu.fuPool.FUList5.opList02] 378type=OpDesc 379eventq_index=0 380opClass=SimdAlu 381opLat=1 382pipelined=true 383 384[system.cpu.fuPool.FUList5.opList03] 385type=OpDesc 386eventq_index=0 387opClass=SimdCmp 388opLat=1 389pipelined=true 390 391[system.cpu.fuPool.FUList5.opList04] 392type=OpDesc 393eventq_index=0 394opClass=SimdCvt 395opLat=1 396pipelined=true 397 398[system.cpu.fuPool.FUList5.opList05] 399type=OpDesc 400eventq_index=0 401opClass=SimdMisc 402opLat=1 403pipelined=true 404 405[system.cpu.fuPool.FUList5.opList06] 406type=OpDesc 407eventq_index=0 408opClass=SimdMult 409opLat=1 410pipelined=true 411 412[system.cpu.fuPool.FUList5.opList07] 413type=OpDesc 414eventq_index=0 415opClass=SimdMultAcc 416opLat=1 417pipelined=true 418 419[system.cpu.fuPool.FUList5.opList08] 420type=OpDesc 421eventq_index=0 422opClass=SimdShift 423opLat=1 424pipelined=true 425 426[system.cpu.fuPool.FUList5.opList09] 427type=OpDesc 428eventq_index=0 429opClass=SimdShiftAcc 430opLat=1 431pipelined=true 432 433[system.cpu.fuPool.FUList5.opList10] 434type=OpDesc 435eventq_index=0 436opClass=SimdSqrt 437opLat=1 438pipelined=true 439 440[system.cpu.fuPool.FUList5.opList11] 441type=OpDesc 442eventq_index=0 443opClass=SimdFloatAdd 444opLat=1 445pipelined=true 446 447[system.cpu.fuPool.FUList5.opList12] 448type=OpDesc 449eventq_index=0 450opClass=SimdFloatAlu 451opLat=1 452pipelined=true 453 454[system.cpu.fuPool.FUList5.opList13] 455type=OpDesc 456eventq_index=0 457opClass=SimdFloatCmp 458opLat=1 459pipelined=true 460 461[system.cpu.fuPool.FUList5.opList14] 462type=OpDesc 463eventq_index=0 464opClass=SimdFloatCvt 465opLat=1 466pipelined=true 467 468[system.cpu.fuPool.FUList5.opList15] 469type=OpDesc 470eventq_index=0 471opClass=SimdFloatDiv 472opLat=1 473pipelined=true 474 475[system.cpu.fuPool.FUList5.opList16] 476type=OpDesc 477eventq_index=0 478opClass=SimdFloatMisc 479opLat=1 480pipelined=true 481 482[system.cpu.fuPool.FUList5.opList17] 483type=OpDesc 484eventq_index=0 485opClass=SimdFloatMult 486opLat=1 487pipelined=true 488 489[system.cpu.fuPool.FUList5.opList18] 490type=OpDesc 491eventq_index=0 492opClass=SimdFloatMultAcc 493opLat=1 494pipelined=true 495 496[system.cpu.fuPool.FUList5.opList19] 497type=OpDesc 498eventq_index=0 499opClass=SimdFloatSqrt 500opLat=1 501pipelined=true 502 503[system.cpu.fuPool.FUList6] 504type=FUDesc	381[system.cpu.fuPool.FUList5] 382type=FUDesc 383children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 384count=4 385eventq_index=0 386opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 387 388[system.cpu.fuPool.FUList5.opList00] 389type=OpDesc 390eventq_index=0 391opClass=SimdAdd 392opLat=1 393pipelined=true 394 395[system.cpu.fuPool.FUList5.opList01] 396type=OpDesc 397eventq_index=0 398opClass=SimdAddAcc 399opLat=1 400pipelined=true 401 402[system.cpu.fuPool.FUList5.opList02] 403type=OpDesc 404eventq_index=0 405opClass=SimdAlu 406opLat=1 407pipelined=true 408 409[system.cpu.fuPool.FUList5.opList03] 410type=OpDesc 411eventq_index=0 412opClass=SimdCmp 413opLat=1 414pipelined=true 415 416[system.cpu.fuPool.FUList5.opList04] 417type=OpDesc 418eventq_index=0 419opClass=SimdCvt 420opLat=1 421pipelined=true 422 423[system.cpu.fuPool.FUList5.opList05] 424type=OpDesc 425eventq_index=0 426opClass=SimdMisc 427opLat=1 428pipelined=true 429 430[system.cpu.fuPool.FUList5.opList06] 431type=OpDesc 432eventq_index=0 433opClass=SimdMult 434opLat=1 435pipelined=true 436 437[system.cpu.fuPool.FUList5.opList07] 438type=OpDesc 439eventq_index=0 440opClass=SimdMultAcc 441opLat=1 442pipelined=true 443 444[system.cpu.fuPool.FUList5.opList08] 445type=OpDesc 446eventq_index=0 447opClass=SimdShift 448opLat=1 449pipelined=true 450 451[system.cpu.fuPool.FUList5.opList09] 452type=OpDesc 453eventq_index=0 454opClass=SimdShiftAcc 455opLat=1 456pipelined=true 457 458[system.cpu.fuPool.FUList5.opList10] 459type=OpDesc 460eventq_index=0 461opClass=SimdSqrt 462opLat=1 463pipelined=true 464 465[system.cpu.fuPool.FUList5.opList11] 466type=OpDesc 467eventq_index=0 468opClass=SimdFloatAdd 469opLat=1 470pipelined=true 471 472[system.cpu.fuPool.FUList5.opList12] 473type=OpDesc 474eventq_index=0 475opClass=SimdFloatAlu 476opLat=1 477pipelined=true 478 479[system.cpu.fuPool.FUList5.opList13] 480type=OpDesc 481eventq_index=0 482opClass=SimdFloatCmp 483opLat=1 484pipelined=true 485 486[system.cpu.fuPool.FUList5.opList14] 487type=OpDesc 488eventq_index=0 489opClass=SimdFloatCvt 490opLat=1 491pipelined=true 492 493[system.cpu.fuPool.FUList5.opList15] 494type=OpDesc 495eventq_index=0 496opClass=SimdFloatDiv 497opLat=1 498pipelined=true 499 500[system.cpu.fuPool.FUList5.opList16] 501type=OpDesc 502eventq_index=0 503opClass=SimdFloatMisc 504opLat=1 505pipelined=true 506 507[system.cpu.fuPool.FUList5.opList17] 508type=OpDesc 509eventq_index=0 510opClass=SimdFloatMult 511opLat=1 512pipelined=true 513 514[system.cpu.fuPool.FUList5.opList18] 515type=OpDesc 516eventq_index=0 517opClass=SimdFloatMultAcc 518opLat=1 519pipelined=true 520 521[system.cpu.fuPool.FUList5.opList19] 522type=OpDesc 523eventq_index=0 524opClass=SimdFloatSqrt 525opLat=1 526pipelined=true 527 528[system.cpu.fuPool.FUList6] 529type=FUDesc
505children=opList	530children=opList0 opList1
506count=0 507eventq_index=0	531count=0 532eventq_index=0
508opList=system.cpu.fuPool.FUList6.opList	533opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
509	534
510[system.cpu.fuPool.FUList6.opList]	535[system.cpu.fuPool.FUList6.opList0]
511type=OpDesc 512eventq_index=0 513opClass=MemWrite 514opLat=1 515pipelined=true 516	536type=OpDesc 537eventq_index=0 538opClass=MemWrite 539opLat=1 540pipelined=true 541
	542[system.cpu.fuPool.FUList6.opList1] 543type=OpDesc 544eventq_index=0 545opClass=FloatMemWrite 546opLat=1 547pipelined=true 548
517[system.cpu.fuPool.FUList7] 518type=FUDesc	549[system.cpu.fuPool.FUList7] 550type=FUDesc
519children=opList0 opList1	551children=opList0 opList1 opList2 opList3
520count=4 521eventq_index=0	552count=4 553eventq_index=0
522opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1	554opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3
523 524[system.cpu.fuPool.FUList7.opList0] 525type=OpDesc 526eventq_index=0 527opClass=MemRead 528opLat=1 529pipelined=true 530 531[system.cpu.fuPool.FUList7.opList1] 532type=OpDesc 533eventq_index=0 534opClass=MemWrite 535opLat=1 536pipelined=true 537	555 556[system.cpu.fuPool.FUList7.opList0] 557type=OpDesc 558eventq_index=0 559opClass=MemRead 560opLat=1 561pipelined=true 562 563[system.cpu.fuPool.FUList7.opList1] 564type=OpDesc 565eventq_index=0 566opClass=MemWrite 567opLat=1 568pipelined=true 569
	570[system.cpu.fuPool.FUList7.opList2] 571type=OpDesc 572eventq_index=0 573opClass=FloatMemRead 574opLat=1 575pipelined=true 576 577[system.cpu.fuPool.FUList7.opList3] 578type=OpDesc 579eventq_index=0 580opClass=FloatMemWrite 581opLat=1 582pipelined=true 583
538[system.cpu.fuPool.FUList8] 539type=FUDesc 540children=opList 541count=1 542eventq_index=0 543opList=system.cpu.fuPool.FUList8.opList 544 545[system.cpu.fuPool.FUList8.opList] 546type=OpDesc 547eventq_index=0 548opClass=IprAccess 549opLat=3 550pipelined=false 551 552[system.cpu.icache] 553type=Cache 554children=tags 555addr_ranges=0:18446744073709551615:0:0:0:0 556assoc=2 557clk_domain=system.cpu_clk_domain 558clusivity=mostly_incl	584[system.cpu.fuPool.FUList8] 585type=FUDesc 586children=opList 587count=1 588eventq_index=0 589opList=system.cpu.fuPool.FUList8.opList 590 591[system.cpu.fuPool.FUList8.opList] 592type=OpDesc 593eventq_index=0 594opClass=IprAccess 595opLat=3 596pipelined=false 597 598[system.cpu.icache] 599type=Cache 600children=tags 601addr_ranges=0:18446744073709551615:0:0:0:0 602assoc=2 603clk_domain=system.cpu_clk_domain 604clusivity=mostly_incl
	605data_latency=2
559default_p_state=UNDEFINED 560demand_mshr_reserve=1 561eventq_index=0	606default_p_state=UNDEFINED 607demand_mshr_reserve=1 608eventq_index=0
562hit_latency=2
563is_read_only=true 564max_miss_count=0 565mshrs=4 566p_state_clk_gate_bins=20 567p_state_clk_gate_max=1000000000000 568p_state_clk_gate_min=1000 569power_model=Null 570prefetch_on_access=false 571prefetcher=Null 572response_latency=2 573sequential_access=false 574size=131072 575system=system	609is_read_only=true 610max_miss_count=0 611mshrs=4 612p_state_clk_gate_bins=20 613p_state_clk_gate_max=1000000000000 614p_state_clk_gate_min=1000 615power_model=Null 616prefetch_on_access=false 617prefetcher=Null 618response_latency=2 619sequential_access=false 620size=131072 621system=system
	622tag_latency=2
576tags=system.cpu.icache.tags 577tgts_per_mshr=20 578write_buffers=8 579writeback_clean=true 580cpu_side=system.cpu.icache_port 581mem_side=system.cpu.toL2Bus.slave[0] 582 583[system.cpu.icache.tags] 584type=LRU 585assoc=2 586block_size=64 587clk_domain=system.cpu_clk_domain	623tags=system.cpu.icache.tags 624tgts_per_mshr=20 625write_buffers=8 626writeback_clean=true 627cpu_side=system.cpu.icache_port 628mem_side=system.cpu.toL2Bus.slave[0] 629 630[system.cpu.icache.tags] 631type=LRU 632assoc=2 633block_size=64 634clk_domain=system.cpu_clk_domain
	635data_latency=2
588default_p_state=UNDEFINED 589eventq_index=0	636default_p_state=UNDEFINED 637eventq_index=0
590hit_latency=2
591p_state_clk_gate_bins=20 592p_state_clk_gate_max=1000000000000 593p_state_clk_gate_min=1000 594power_model=Null 595sequential_access=false 596size=131072	638p_state_clk_gate_bins=20 639p_state_clk_gate_max=1000000000000 640p_state_clk_gate_min=1000 641power_model=Null 642sequential_access=false 643size=131072
	644tag_latency=2
597 598[system.cpu.interrupts] 599type=X86LocalApic 600clk_domain=system.cpu.apic_clk_domain 601default_p_state=UNDEFINED 602eventq_index=0 603int_latency=1000 604p_state_clk_gate_bins=20 605p_state_clk_gate_max=1000000000000 606p_state_clk_gate_min=1000 607pio_addr=2305843009213693952 608pio_latency=100000 609power_model=Null 610system=system 611int_master=system.membus.slave[2] 612int_slave=system.membus.master[2] 613pio=system.membus.master[1] 614 615[system.cpu.isa] 616type=X86ISA 617eventq_index=0 618 619[system.cpu.itb] 620type=X86TLB 621children=walker 622eventq_index=0 623size=64 624walker=system.cpu.itb.walker 625 626[system.cpu.itb.walker] 627type=X86PagetableWalker 628clk_domain=system.cpu_clk_domain 629default_p_state=UNDEFINED 630eventq_index=0 631num_squash_per_cycle=4 632p_state_clk_gate_bins=20 633p_state_clk_gate_max=1000000000000 634p_state_clk_gate_min=1000 635power_model=Null 636system=system 637port=system.cpu.toL2Bus.slave[2] 638 639[system.cpu.l2cache] 640type=Cache 641children=tags 642addr_ranges=0:18446744073709551615:0:0:0:0 643assoc=8 644clk_domain=system.cpu_clk_domain 645clusivity=mostly_incl	645 646[system.cpu.interrupts] 647type=X86LocalApic 648clk_domain=system.cpu.apic_clk_domain 649default_p_state=UNDEFINED 650eventq_index=0 651int_latency=1000 652p_state_clk_gate_bins=20 653p_state_clk_gate_max=1000000000000 654p_state_clk_gate_min=1000 655pio_addr=2305843009213693952 656pio_latency=100000 657power_model=Null 658system=system 659int_master=system.membus.slave[2] 660int_slave=system.membus.master[2] 661pio=system.membus.master[1] 662 663[system.cpu.isa] 664type=X86ISA 665eventq_index=0 666 667[system.cpu.itb] 668type=X86TLB 669children=walker 670eventq_index=0 671size=64 672walker=system.cpu.itb.walker 673 674[system.cpu.itb.walker] 675type=X86PagetableWalker 676clk_domain=system.cpu_clk_domain 677default_p_state=UNDEFINED 678eventq_index=0 679num_squash_per_cycle=4 680p_state_clk_gate_bins=20 681p_state_clk_gate_max=1000000000000 682p_state_clk_gate_min=1000 683power_model=Null 684system=system 685port=system.cpu.toL2Bus.slave[2] 686 687[system.cpu.l2cache] 688type=Cache 689children=tags 690addr_ranges=0:18446744073709551615:0:0:0:0 691assoc=8 692clk_domain=system.cpu_clk_domain 693clusivity=mostly_incl
	694data_latency=20
646default_p_state=UNDEFINED 647demand_mshr_reserve=1 648eventq_index=0	695default_p_state=UNDEFINED 696demand_mshr_reserve=1 697eventq_index=0
649hit_latency=20
650is_read_only=false 651max_miss_count=0 652mshrs=20 653p_state_clk_gate_bins=20 654p_state_clk_gate_max=1000000000000 655p_state_clk_gate_min=1000 656power_model=Null 657prefetch_on_access=false 658prefetcher=Null 659response_latency=20 660sequential_access=false 661size=2097152 662system=system	698is_read_only=false 699max_miss_count=0 700mshrs=20 701p_state_clk_gate_bins=20 702p_state_clk_gate_max=1000000000000 703p_state_clk_gate_min=1000 704power_model=Null 705prefetch_on_access=false 706prefetcher=Null 707response_latency=20 708sequential_access=false 709size=2097152 710system=system
	711tag_latency=20
663tags=system.cpu.l2cache.tags 664tgts_per_mshr=12 665write_buffers=8 666writeback_clean=false 667cpu_side=system.cpu.toL2Bus.master[0] 668mem_side=system.membus.slave[1] 669 670[system.cpu.l2cache.tags] 671type=LRU 672assoc=8 673block_size=64 674clk_domain=system.cpu_clk_domain	712tags=system.cpu.l2cache.tags 713tgts_per_mshr=12 714write_buffers=8 715writeback_clean=false 716cpu_side=system.cpu.toL2Bus.master[0] 717mem_side=system.membus.slave[1] 718 719[system.cpu.l2cache.tags] 720type=LRU 721assoc=8 722block_size=64 723clk_domain=system.cpu_clk_domain
	724data_latency=20
675default_p_state=UNDEFINED 676eventq_index=0	725default_p_state=UNDEFINED 726eventq_index=0
677hit_latency=20
678p_state_clk_gate_bins=20 679p_state_clk_gate_max=1000000000000 680p_state_clk_gate_min=1000 681power_model=Null 682sequential_access=false 683size=2097152	727p_state_clk_gate_bins=20 728p_state_clk_gate_max=1000000000000 729p_state_clk_gate_min=1000 730power_model=Null 731sequential_access=false 732size=2097152
	733tag_latency=20
684 685[system.cpu.toL2Bus] 686type=CoherentXBar 687children=snoop_filter 688clk_domain=system.cpu_clk_domain 689default_p_state=UNDEFINED 690eventq_index=0 691forward_latency=0 692frontend_latency=1 693p_state_clk_gate_bins=20 694p_state_clk_gate_max=1000000000000 695p_state_clk_gate_min=1000 696point_of_coherency=false 697power_model=Null 698response_latency=1 699snoop_filter=system.cpu.toL2Bus.snoop_filter 700snoop_response_latency=1 701system=system 702use_default_range=false 703width=32 704master=system.cpu.l2cache.cpu_side 705slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 706 707[system.cpu.toL2Bus.snoop_filter] 708type=SnoopFilter 709eventq_index=0 710lookup_latency=0 711max_capacity=8388608 712system=system 713 714[system.cpu.tracer] 715type=ExeTracer 716eventq_index=0 717 718[system.cpu.workload]	734 735[system.cpu.toL2Bus] 736type=CoherentXBar 737children=snoop_filter 738clk_domain=system.cpu_clk_domain 739default_p_state=UNDEFINED 740eventq_index=0 741forward_latency=0 742frontend_latency=1 743p_state_clk_gate_bins=20 744p_state_clk_gate_max=1000000000000 745p_state_clk_gate_min=1000 746point_of_coherency=false 747power_model=Null 748response_latency=1 749snoop_filter=system.cpu.toL2Bus.snoop_filter 750snoop_response_latency=1 751system=system 752use_default_range=false 753width=32 754master=system.cpu.l2cache.cpu_side 755slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 756 757[system.cpu.toL2Bus.snoop_filter] 758type=SnoopFilter 759eventq_index=0 760lookup_latency=0 761max_capacity=8388608 762system=system 763 764[system.cpu.tracer] 765type=ExeTracer 766eventq_index=0 767 768[system.cpu.workload]
719type=LiveProcess	769type=Process
720cmd=twolf smred 721cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing 722drivers= 723egid=100 724env= 725errout=cerr 726euid=100 727eventq_index=0	770cmd=twolf smred 771cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing 772drivers= 773egid=100 774env= 775errout=cerr 776euid=100 777eventq_index=0
728executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/twolf	778executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/twolf
729gid=100 730input=cin 731kvmInSE=false	779gid=100 780input=cin 781kvmInSE=false
732max_stack_size=67108864	782maxStackSize=67108864
733output=cout	783output=cout
	784pgid=100
734pid=100	785pid=100
735ppid=99	786ppid=0
736simpoint=0 737system=system 738uid=100 739useArchPT=false 740 741[system.cpu_clk_domain] 742type=SrcClockDomain 743clock=500 744domain_id=-1 745eventq_index=0 746init_perf_level=0 747voltage_domain=system.voltage_domain 748 749[system.dvfs_handler] 750type=DVFSHandler 751domains= 752enable=false 753eventq_index=0 754sys_clk_domain=system.clk_domain 755transition_latency=100000000 756 757[system.membus] 758type=CoherentXBar 759children=snoop_filter 760clk_domain=system.clk_domain 761default_p_state=UNDEFINED 762eventq_index=0 763forward_latency=4 764frontend_latency=3 765p_state_clk_gate_bins=20 766p_state_clk_gate_max=1000000000000 767p_state_clk_gate_min=1000 768point_of_coherency=true 769power_model=Null 770response_latency=2 771snoop_filter=system.membus.snoop_filter 772snoop_response_latency=4 773system=system 774use_default_range=false 775width=16 776master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 777slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 778 779[system.membus.snoop_filter] 780type=SnoopFilter 781eventq_index=0 782lookup_latency=1 783max_capacity=8388608 784system=system 785 786[system.physmem] 787type=DRAMCtrl 788IDD0=0.055000 789IDD02=0.000000 790IDD2N=0.032000 791IDD2N2=0.000000 792IDD2P0=0.000000 793IDD2P02=0.000000 794IDD2P1=0.032000 795IDD2P12=0.000000 796IDD3N=0.038000 797IDD3N2=0.000000 798IDD3P0=0.000000 799IDD3P02=0.000000 800IDD3P1=0.038000 801IDD3P12=0.000000 802IDD4R=0.157000 803IDD4R2=0.000000 804IDD4W=0.125000 805IDD4W2=0.000000 806IDD5=0.235000 807IDD52=0.000000 808IDD6=0.020000 809IDD62=0.000000 810VDD=1.500000 811VDD2=0.000000 812activation_limit=4 813addr_mapping=RoRaBaCoCh 814bank_groups_per_rank=0 815banks_per_rank=8 816burst_length=8 817channels=1 818clk_domain=system.clk_domain 819conf_table_reported=true 820default_p_state=UNDEFINED 821device_bus_width=8 822device_rowbuffer_size=1024 823device_size=536870912 824devices_per_rank=8 825dll=true 826eventq_index=0 827in_addr_map=true 828kvm_map=true 829max_accesses_per_row=16 830mem_sched_policy=frfcfs 831min_writes_per_switch=16 832null=false 833p_state_clk_gate_bins=20 834p_state_clk_gate_max=1000000000000 835p_state_clk_gate_min=1000 836page_policy=open_adaptive 837power_model=Null 838range=0:134217727:0:0:0:0 839ranks_per_channel=2 840read_buffer_size=32 841static_backend_latency=10000 842static_frontend_latency=10000 843tBURST=5000 844tCCD_L=0 845tCK=1250 846tCL=13750 847tCS=2500 848tRAS=35000 849tRCD=13750 850tREFI=7800000 851tRFC=260000 852tRP=13750 853tRRD=6000 854tRRD_L=0 855tRTP=7500 856tRTW=2500 857tWR=15000 858tWTR=7500 859tXAW=30000 860tXP=6000 861tXPDLL=0 862tXS=270000 863tXSDLL=0 864write_buffer_size=64 865write_high_thresh_perc=85 866write_low_thresh_perc=50 867port=system.membus.master[0] 868 869[system.voltage_domain] 870type=VoltageDomain 871eventq_index=0 872voltage=1.000000 873	787simpoint=0 788system=system 789uid=100 790useArchPT=false 791 792[system.cpu_clk_domain] 793type=SrcClockDomain 794clock=500 795domain_id=-1 796eventq_index=0 797init_perf_level=0 798voltage_domain=system.voltage_domain 799 800[system.dvfs_handler] 801type=DVFSHandler 802domains= 803enable=false 804eventq_index=0 805sys_clk_domain=system.clk_domain 806transition_latency=100000000 807 808[system.membus] 809type=CoherentXBar 810children=snoop_filter 811clk_domain=system.clk_domain 812default_p_state=UNDEFINED 813eventq_index=0 814forward_latency=4 815frontend_latency=3 816p_state_clk_gate_bins=20 817p_state_clk_gate_max=1000000000000 818p_state_clk_gate_min=1000 819point_of_coherency=true 820power_model=Null 821response_latency=2 822snoop_filter=system.membus.snoop_filter 823snoop_response_latency=4 824system=system 825use_default_range=false 826width=16 827master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 828slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 829 830[system.membus.snoop_filter] 831type=SnoopFilter 832eventq_index=0 833lookup_latency=1 834max_capacity=8388608 835system=system 836 837[system.physmem] 838type=DRAMCtrl 839IDD0=0.055000 840IDD02=0.000000 841IDD2N=0.032000 842IDD2N2=0.000000 843IDD2P0=0.000000 844IDD2P02=0.000000 845IDD2P1=0.032000 846IDD2P12=0.000000 847IDD3N=0.038000 848IDD3N2=0.000000 849IDD3P0=0.000000 850IDD3P02=0.000000 851IDD3P1=0.038000 852IDD3P12=0.000000 853IDD4R=0.157000 854IDD4R2=0.000000 855IDD4W=0.125000 856IDD4W2=0.000000 857IDD5=0.235000 858IDD52=0.000000 859IDD6=0.020000 860IDD62=0.000000 861VDD=1.500000 862VDD2=0.000000 863activation_limit=4 864addr_mapping=RoRaBaCoCh 865bank_groups_per_rank=0 866banks_per_rank=8 867burst_length=8 868channels=1 869clk_domain=system.clk_domain 870conf_table_reported=true 871default_p_state=UNDEFINED 872device_bus_width=8 873device_rowbuffer_size=1024 874device_size=536870912 875devices_per_rank=8 876dll=true 877eventq_index=0 878in_addr_map=true 879kvm_map=true 880max_accesses_per_row=16 881mem_sched_policy=frfcfs 882min_writes_per_switch=16 883null=false 884p_state_clk_gate_bins=20 885p_state_clk_gate_max=1000000000000 886p_state_clk_gate_min=1000 887page_policy=open_adaptive 888power_model=Null 889range=0:134217727:0:0:0:0 890ranks_per_channel=2 891read_buffer_size=32 892static_backend_latency=10000 893static_frontend_latency=10000 894tBURST=5000 895tCCD_L=0 896tCK=1250 897tCL=13750 898tCS=2500 899tRAS=35000 900tRCD=13750 901tREFI=7800000 902tRFC=260000 903tRP=13750 904tRRD=6000 905tRRD_L=0 906tRTP=7500 907tRTW=2500 908tWR=15000 909tWTR=7500 910tXAW=30000 911tXP=6000 912tXPDLL=0 913tXS=270000 914tXSDLL=0 915write_buffer_size=64 916write_high_thresh_perc=85 917write_low_thresh_perc=50 918port=system.membus.master[0] 919 920[system.voltage_domain] 921type=VoltageDomain 922eventq_index=0 923voltage=1.000000 924