| stats.txt (9978:81d7551dd3be) | stats.txt (9988:0b2e590c85be) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.074220 # Number of seconds simulated 4sim_ticks 74219948500 # Number of ticks simulated 5final_tick 74219948500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.074220 # Number of seconds simulated 4sim_ticks 74219948500 # Number of ticks simulated 5final_tick 74219948500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 110839 # Simulator instruction rate (inst/s) 8host_op_rate 121359 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 47744278 # Simulator tick rate (ticks/s) 10host_mem_usage 278976 # Number of bytes of host memory used 11host_seconds 1554.53 # Real time elapsed on the host | 7host_inst_rate 84730 # Simulator instruction rate (inst/s) 8host_op_rate 92772 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 36497737 # Simulator tick rate (ticks/s) 10host_mem_usage 298520 # Number of bytes of host memory used 11host_seconds 2033.55 # Real time elapsed on the host |
| 12sim_insts 172303021 # Number of instructions simulated 13sim_ops 188656503 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 131072 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 111680 # Number of bytes read from this memory 16system.physmem.bytes_read::total 242752 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 131072 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 131072 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 2048 # Number of read requests responded to by this memory --- 172 unchanged lines hidden (view full) --- 192system.physmem.bytesPerActivate::3008-3009 1 0.14% 99.16% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::3200-3201 1 0.14% 99.30% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::3392-3393 1 0.14% 99.44% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::3648-3649 1 0.14% 99.58% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::3712-3713 1 0.14% 99.72% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::6656-6657 1 0.14% 99.86% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::8192-8193 1 0.14% 100.00% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::total 717 # Bytes accessed per row activation | 12sim_insts 172303021 # Number of instructions simulated 13sim_ops 188656503 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 131072 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 111680 # Number of bytes read from this memory 16system.physmem.bytes_read::total 242752 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 131072 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 131072 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 2048 # Number of read requests responded to by this memory --- 172 unchanged lines hidden (view full) --- 192system.physmem.bytesPerActivate::3008-3009 1 0.14% 99.16% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::3200-3201 1 0.14% 99.30% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::3392-3393 1 0.14% 99.44% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::3648-3649 1 0.14% 99.58% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::3712-3713 1 0.14% 99.72% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::6656-6657 1 0.14% 99.86% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::8192-8193 1 0.14% 100.00% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::total 717 # Bytes accessed per row activation |
| 200system.physmem.totQLat 25205500 # Total ticks spent queuing 201system.physmem.totMemAccLat 100715500 # Total ticks spent from burst creation until serviced by the DRAM | 200system.physmem.totQLat 25203500 # Total ticks spent queuing 201system.physmem.totMemAccLat 100713500 # Total ticks spent from burst creation until serviced by the DRAM |
| 202system.physmem.totBusLat 18970000 # Total ticks spent in databus transfers 203system.physmem.totBankLat 56540000 # Total ticks spent accessing banks | 202system.physmem.totBusLat 18970000 # Total ticks spent in databus transfers 203system.physmem.totBankLat 56540000 # Total ticks spent accessing banks |
| 204system.physmem.avgQLat 6643.52 # Average queueing delay per DRAM burst | 204system.physmem.avgQLat 6642.99 # Average queueing delay per DRAM burst |
| 205system.physmem.avgBankLat 14902.48 # Average bank access latency per DRAM burst 206system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 205system.physmem.avgBankLat 14902.48 # Average bank access latency per DRAM burst 206system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 207system.physmem.avgMemAccLat 26545.99 # Average memory access latency per DRAM burst | 207system.physmem.avgMemAccLat 26545.47 # Average memory access latency per DRAM burst |
| 208system.physmem.avgRdBW 3.27 # Average DRAM read bandwidth in MiByte/s 209system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 210system.physmem.avgRdBWSys 3.27 # Average system read bandwidth in MiByte/s 211system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 212system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 213system.physmem.busUtil 0.03 # Data bus utilization in percentage 214system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 215system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 12 unchanged lines hidden (view full) --- 228system.membus.trans_dist::ReadExReq 1071 # Transaction distribution 229system.membus.trans_dist::ReadExResp 1071 # Transaction distribution 230system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7587 # Packet count per connected master and slave (bytes) 231system.membus.pkt_count::total 7587 # Packet count per connected master and slave (bytes) 232system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 242752 # Cumulative packet size per connected master and slave (bytes) 233system.membus.tot_pkt_size::total 242752 # Cumulative packet size per connected master and slave (bytes) 234system.membus.data_through_bus 242752 # Total data (bytes) 235system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 208system.physmem.avgRdBW 3.27 # Average DRAM read bandwidth in MiByte/s 209system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 210system.physmem.avgRdBWSys 3.27 # Average system read bandwidth in MiByte/s 211system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 212system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 213system.physmem.busUtil 0.03 # Data bus utilization in percentage 214system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 215system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 12 unchanged lines hidden (view full) --- 228system.membus.trans_dist::ReadExReq 1071 # Transaction distribution 229system.membus.trans_dist::ReadExResp 1071 # Transaction distribution 230system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7587 # Packet count per connected master and slave (bytes) 231system.membus.pkt_count::total 7587 # Packet count per connected master and slave (bytes) 232system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 242752 # Cumulative packet size per connected master and slave (bytes) 233system.membus.tot_pkt_size::total 242752 # Cumulative packet size per connected master and slave (bytes) 234system.membus.data_through_bus 242752 # Total data (bytes) 235system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 236system.membus.reqLayer0.occupancy 4683500 # Layer occupancy (ticks) | 236system.membus.reqLayer0.occupancy 4682500 # Layer occupancy (ticks) |
| 237system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 237system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 238system.membus.respLayer1.occupancy 35533250 # Layer occupancy (ticks) | 238system.membus.respLayer1.occupancy 35532750 # Layer occupancy (ticks) |
| 239system.membus.respLayer1.utilization 0.0 # Layer utilization (%) | 239system.membus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 240system.cpu.branchPred.lookups 94784279 # Number of BP lookups 241system.cpu.branchPred.condPredicted 74784012 # Number of conditional branches predicted | 240system.cpu.branchPred.lookups 94784274 # Number of BP lookups 241system.cpu.branchPred.condPredicted 74784006 # Number of conditional branches predicted |
| 242system.cpu.branchPred.condIncorrect 6281562 # Number of conditional branches incorrect | 242system.cpu.branchPred.condIncorrect 6281562 # Number of conditional branches incorrect |
| 243system.cpu.branchPred.BTBLookups 44678427 # Number of BTB lookups | 243system.cpu.branchPred.BTBLookups 44678423 # Number of BTB lookups |
| 244system.cpu.branchPred.BTBHits 43050018 # Number of BTB hits 245system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 244system.cpu.branchPred.BTBHits 43050018 # Number of BTB hits 245system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 246system.cpu.branchPred.BTBHitPct 96.355268 # BTB Hit Percentage 247system.cpu.branchPred.usedRAS 4356637 # Number of times the RAS was used to get a target. | 246system.cpu.branchPred.BTBHitPct 96.355276 # BTB Hit Percentage 247system.cpu.branchPred.usedRAS 4356639 # Number of times the RAS was used to get a target. |
| 248system.cpu.branchPred.RASInCorrect 88400 # Number of incorrect RAS predictions. 249system.cpu.dtb.inst_hits 0 # ITB inst hits 250system.cpu.dtb.inst_misses 0 # ITB inst misses 251system.cpu.dtb.read_hits 0 # DTB read hits 252system.cpu.dtb.read_misses 0 # DTB read misses 253system.cpu.dtb.write_hits 0 # DTB write hits 254system.cpu.dtb.write_misses 0 # DTB write misses 255system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed --- 31 unchanged lines hidden (view full) --- 287system.cpu.itb.inst_accesses 0 # ITB inst accesses 288system.cpu.itb.hits 0 # DTB hits 289system.cpu.itb.misses 0 # DTB misses 290system.cpu.itb.accesses 0 # DTB accesses 291system.cpu.workload.num_syscalls 400 # Number of system calls 292system.cpu.numCycles 148439898 # number of cpu cycles simulated 293system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 294system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 248system.cpu.branchPred.RASInCorrect 88400 # Number of incorrect RAS predictions. 249system.cpu.dtb.inst_hits 0 # ITB inst hits 250system.cpu.dtb.inst_misses 0 # ITB inst misses 251system.cpu.dtb.read_hits 0 # DTB read hits 252system.cpu.dtb.read_misses 0 # DTB read misses 253system.cpu.dtb.write_hits 0 # DTB write hits 254system.cpu.dtb.write_misses 0 # DTB write misses 255system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed --- 31 unchanged lines hidden (view full) --- 287system.cpu.itb.inst_accesses 0 # ITB inst accesses 288system.cpu.itb.hits 0 # DTB hits 289system.cpu.itb.misses 0 # DTB misses 290system.cpu.itb.accesses 0 # DTB accesses 291system.cpu.workload.num_syscalls 400 # Number of system calls 292system.cpu.numCycles 148439898 # number of cpu cycles simulated 293system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 294system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 295system.cpu.fetch.icacheStallCycles 39656913 # Number of cycles fetch is stalled on an Icache miss 296system.cpu.fetch.Insts 380179952 # Number of instructions fetch has processed 297system.cpu.fetch.Branches 94784279 # Number of branches that fetch encountered 298system.cpu.fetch.predictedBranches 47406655 # Number of branches that fetch has predicted taken 299system.cpu.fetch.Cycles 80370667 # Number of cycles fetch has run and was not squashing or blocked 300system.cpu.fetch.SquashCycles 27283129 # Number of cycles fetch has spent squashing 301system.cpu.fetch.BlockedCycles 7220970 # Number of cycles fetch has spent blocked | 295system.cpu.fetch.icacheStallCycles 39656921 # Number of cycles fetch is stalled on an Icache miss 296system.cpu.fetch.Insts 380179930 # Number of instructions fetch has processed 297system.cpu.fetch.Branches 94784274 # Number of branches that fetch encountered 298system.cpu.fetch.predictedBranches 47406657 # Number of branches that fetch has predicted taken 299system.cpu.fetch.Cycles 80370665 # Number of cycles fetch has run and was not squashing or blocked 300system.cpu.fetch.SquashCycles 27283127 # Number of cycles fetch has spent squashing 301system.cpu.fetch.BlockedCycles 7220968 # Number of cycles fetch has spent blocked |
| 302system.cpu.fetch.MiscStallCycles 44 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 303system.cpu.fetch.PendingTrapStallCycles 6188 # Number of stall cycles due to pending traps 304system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions 305system.cpu.fetch.IcacheWaitRetryStallCycles 50 # Number of stall cycles due to full MSHR | 302system.cpu.fetch.MiscStallCycles 44 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 303system.cpu.fetch.PendingTrapStallCycles 6188 # Number of stall cycles due to pending traps 304system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions 305system.cpu.fetch.IcacheWaitRetryStallCycles 50 # Number of stall cycles due to full MSHR |
| 306system.cpu.fetch.CacheLines 36850892 # Number of cache lines fetched | 306system.cpu.fetch.CacheLines 36850894 # Number of cache lines fetched |
| 307system.cpu.fetch.IcacheSquashes 1831983 # Number of outstanding Icache misses that were squashed | 307system.cpu.fetch.IcacheSquashes 1831983 # Number of outstanding Icache misses that were squashed |
| 308system.cpu.fetch.rateDist::samples 148240575 # Number of instructions fetched each cycle (Total) | 308system.cpu.fetch.rateDist::samples 148240577 # Number of instructions fetched each cycle (Total) |
| 309system.cpu.fetch.rateDist::mean 2.801601 # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::stdev 3.152871 # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 309system.cpu.fetch.rateDist::mean 2.801601 # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::stdev 3.152871 # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 312system.cpu.fetch.rateDist::0 68038754 45.90% 45.90% # Number of instructions fetched each cycle (Total) | 312system.cpu.fetch.rateDist::0 68038757 45.90% 45.90% # Number of instructions fetched each cycle (Total) |
| 313system.cpu.fetch.rateDist::1 5265463 3.55% 49.45% # Number of instructions fetched each cycle (Total) | 313system.cpu.fetch.rateDist::1 5265463 3.55% 49.45% # Number of instructions fetched each cycle (Total) |
| 314system.cpu.fetch.rateDist::2 10540667 7.11% 56.56% # Number of instructions fetched each cycle (Total) | 314system.cpu.fetch.rateDist::2 10540668 7.11% 56.56% # Number of instructions fetched each cycle (Total) |
| 315system.cpu.fetch.rateDist::3 10285704 6.94% 63.50% # Number of instructions fetched each cycle (Total) 316system.cpu.fetch.rateDist::4 8660470 5.84% 69.34% # Number of instructions fetched each cycle (Total) | 315system.cpu.fetch.rateDist::3 10285704 6.94% 63.50% # Number of instructions fetched each cycle (Total) 316system.cpu.fetch.rateDist::4 8660470 5.84% 69.34% # Number of instructions fetched each cycle (Total) |
| 317system.cpu.fetch.rateDist::5 6545128 4.42% 73.76% # Number of instructions fetched each cycle (Total) | 317system.cpu.fetch.rateDist::5 6545129 4.42% 73.76% # Number of instructions fetched each cycle (Total) |
| 318system.cpu.fetch.rateDist::6 6246382 4.21% 77.97% # Number of instructions fetched each cycle (Total) | 318system.cpu.fetch.rateDist::6 6246382 4.21% 77.97% # Number of instructions fetched each cycle (Total) |
| 319system.cpu.fetch.rateDist::7 8002829 5.40% 83.37% # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.rateDist::8 24655178 16.63% 100.00% # Number of instructions fetched each cycle (Total) | 319system.cpu.fetch.rateDist::7 8002830 5.40% 83.37% # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.rateDist::8 24655174 16.63% 100.00% # Number of instructions fetched each cycle (Total) |
| 321system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 321system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 324system.cpu.fetch.rateDist::total 148240575 # Number of instructions fetched each cycle (Total) | 324system.cpu.fetch.rateDist::total 148240577 # Number of instructions fetched each cycle (Total) |
| 325system.cpu.fetch.branchRate 0.638536 # Number of branch fetches per cycle 326system.cpu.fetch.rate 2.561171 # Number of inst fetches per cycle | 325system.cpu.fetch.branchRate 0.638536 # Number of branch fetches per cycle 326system.cpu.fetch.rate 2.561171 # Number of inst fetches per cycle |
| 327system.cpu.decode.IdleCycles 45513789 # Number of cycles decode is idle 328system.cpu.decode.BlockedCycles 5886753 # Number of cycles decode is blocked 329system.cpu.decode.RunCycles 74804125 # Number of cycles decode is running | 327system.cpu.decode.IdleCycles 45513795 # Number of cycles decode is idle 328system.cpu.decode.BlockedCycles 5886752 # Number of cycles decode is blocked 329system.cpu.decode.RunCycles 74804124 # Number of cycles decode is running |
| 330system.cpu.decode.UnblockCycles 1203493 # Number of cycles decode is unblocking | 330system.cpu.decode.UnblockCycles 1203493 # Number of cycles decode is unblocking |
| 331system.cpu.decode.SquashCycles 20832415 # Number of cycles decode is squashing 332system.cpu.decode.BranchResolved 14327913 # Number of times decode resolved a branch | 331system.cpu.decode.SquashCycles 20832413 # Number of cycles decode is squashing 332system.cpu.decode.BranchResolved 14327914 # Number of times decode resolved a branch |
| 333system.cpu.decode.BranchMispred 164349 # Number of times decode detected a branch misprediction | 333system.cpu.decode.BranchMispred 164349 # Number of times decode detected a branch misprediction |
| 334system.cpu.decode.DecodedInsts 392779898 # Number of instructions handled by decode | 334system.cpu.decode.DecodedInsts 392779880 # Number of instructions handled by decode |
| 335system.cpu.decode.SquashedInsts 733794 # Number of squashed instructions handled by decode | 335system.cpu.decode.SquashedInsts 733794 # Number of squashed instructions handled by decode |
| 336system.cpu.rename.SquashCycles 20832415 # Number of cycles rename is squashing 337system.cpu.rename.IdleCycles 50900742 # Number of cycles rename is idle | 336system.cpu.rename.SquashCycles 20832413 # Number of cycles rename is squashing 337system.cpu.rename.IdleCycles 50900748 # Number of cycles rename is idle |
| 338system.cpu.rename.BlockCycles 730699 # Number of cycles rename is blocking | 338system.cpu.rename.BlockCycles 730699 # Number of cycles rename is blocking |
| 339system.cpu.rename.serializeStallCycles 603190 # count of cycles rename stalled for serializing inst 340system.cpu.rename.RunCycles 70558310 # Number of cycles rename is running 341system.cpu.rename.UnblockCycles 4615219 # Number of cycles rename is unblocking 342system.cpu.rename.RenamedInsts 371308094 # Number of instructions processed by rename | 339system.cpu.rename.serializeStallCycles 603191 # count of cycles rename stalled for serializing inst 340system.cpu.rename.RunCycles 70558309 # Number of cycles rename is running 341system.cpu.rename.UnblockCycles 4615217 # Number of cycles rename is unblocking 342system.cpu.rename.RenamedInsts 371308082 # Number of instructions processed by rename |
| 343system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full | 343system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full |
| 344system.cpu.rename.IQFullEvents 339277 # Number of times rename has blocked due to IQ full | 344system.cpu.rename.IQFullEvents 339275 # Number of times rename has blocked due to IQ full |
| 345system.cpu.rename.LSQFullEvents 3661219 # Number of times rename has blocked due to LSQ full | 345system.cpu.rename.LSQFullEvents 3661219 # Number of times rename has blocked due to LSQ full |
| 346system.cpu.rename.FullRegisterEvents 233 # Number of times there has been no free registers 347system.cpu.rename.RenamedOperands 631703486 # Number of destination operands rename has renamed 348system.cpu.rename.RenameLookups 1581699955 # Number of register rename lookups that rename has made 349system.cpu.rename.int_rename_lookups 1506871299 # Number of integer rename lookups | 346system.cpu.rename.FullRegisterEvents 231 # Number of times there has been no free registers 347system.cpu.rename.RenamedOperands 631703471 # Number of destination operands rename has renamed 348system.cpu.rename.RenameLookups 1581699910 # Number of register rename lookups that rename has made 349system.cpu.rename.int_rename_lookups 1506871257 # Number of integer rename lookups |
| 350system.cpu.rename.fp_rename_lookups 3203425 # Number of floating rename lookups 351system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed | 350system.cpu.rename.fp_rename_lookups 3203425 # Number of floating rename lookups 351system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed |
| 352system.cpu.rename.UndoneMaps 333659347 # Number of HB maps that are undone due to squashing | 352system.cpu.rename.UndoneMaps 333659332 # Number of HB maps that are undone due to squashing |
| 353system.cpu.rename.serializingInsts 25072 # count of serializing insts renamed 354system.cpu.rename.tempSerializingInsts 25068 # count of temporary serializing insts renamed 355system.cpu.rename.skidInsts 13010245 # count of insts added to the skid buffer | 353system.cpu.rename.serializingInsts 25072 # count of serializing insts renamed 354system.cpu.rename.tempSerializingInsts 25068 # count of temporary serializing insts renamed 355system.cpu.rename.skidInsts 13010245 # count of insts added to the skid buffer |
| 356system.cpu.memDep0.insertedLoads 43012685 # Number of loads inserted to the mem dependence unit. | 356system.cpu.memDep0.insertedLoads 43012682 # Number of loads inserted to the mem dependence unit. |
| 357system.cpu.memDep0.insertedStores 16416405 # Number of stores inserted to the mem dependence unit. 358system.cpu.memDep0.conflictingLoads 5733542 # Number of conflicting loads. 359system.cpu.memDep0.conflictingStores 3666500 # Number of conflicting stores. | 357system.cpu.memDep0.insertedStores 16416405 # Number of stores inserted to the mem dependence unit. 358system.cpu.memDep0.conflictingLoads 5733542 # Number of conflicting loads. 359system.cpu.memDep0.conflictingStores 3666500 # Number of conflicting stores. |
| 360system.cpu.iq.iqInstsAdded 329190158 # Number of instructions added to the IQ (excludes non-spec) | 360system.cpu.iq.iqInstsAdded 329190147 # Number of instructions added to the IQ (excludes non-spec) |
| 361system.cpu.iq.iqNonSpecInstsAdded 47154 # Number of non-speculative instructions added to the IQ | 361system.cpu.iq.iqNonSpecInstsAdded 47154 # Number of non-speculative instructions added to the IQ |
| 362system.cpu.iq.iqInstsIssued 249456619 # Number of instructions issued 363system.cpu.iq.iqSquashedInstsIssued 789371 # Number of squashed instructions issued 364system.cpu.iq.iqSquashedInstsExamined 139503403 # Number of squashed instructions iterated over during squash; mainly for profiling 365system.cpu.iq.iqSquashedOperandsExamined 362002811 # Number of squashed operands that are examined and possibly removed from graph | 362system.cpu.iq.iqInstsIssued 249456617 # Number of instructions issued 363system.cpu.iq.iqSquashedInstsIssued 789368 # Number of squashed instructions issued 364system.cpu.iq.iqSquashedInstsExamined 139503392 # Number of squashed instructions iterated over during squash; mainly for profiling 365system.cpu.iq.iqSquashedOperandsExamined 362002773 # Number of squashed operands that are examined and possibly removed from graph |
| 366system.cpu.iq.iqSquashedNonSpecRemoved 1938 # Number of squashed non-spec instructions that were removed | 366system.cpu.iq.iqSquashedNonSpecRemoved 1938 # Number of squashed non-spec instructions that were removed |
| 367system.cpu.iq.issued_per_cycle::samples 148240575 # Number of insts issued each cycle | 367system.cpu.iq.issued_per_cycle::samples 148240577 # Number of insts issued each cycle |
| 368system.cpu.iq.issued_per_cycle::mean 1.682782 # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::stdev 1.761427 # Number of insts issued each cycle 370system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 368system.cpu.iq.issued_per_cycle::mean 1.682782 # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::stdev 1.761427 # Number of insts issued each cycle 370system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 371system.cpu.iq.issued_per_cycle::0 56059831 37.82% 37.82% # Number of insts issued each cycle | 371system.cpu.iq.issued_per_cycle::0 56059832 37.82% 37.82% # Number of insts issued each cycle |
| 372system.cpu.iq.issued_per_cycle::1 22638796 15.27% 53.09% # Number of insts issued each cycle | 372system.cpu.iq.issued_per_cycle::1 22638796 15.27% 53.09% # Number of insts issued each cycle |
| 373system.cpu.iq.issued_per_cycle::2 24824163 16.75% 69.83% # Number of insts issued each cycle | 373system.cpu.iq.issued_per_cycle::2 24824164 16.75% 69.83% # Number of insts issued each cycle |
| 374system.cpu.iq.issued_per_cycle::3 20343400 13.72% 83.56% # Number of insts issued each cycle | 374system.cpu.iq.issued_per_cycle::3 20343400 13.72% 83.56% # Number of insts issued each cycle |
| 375system.cpu.iq.issued_per_cycle::4 12534795 8.46% 92.01% # Number of insts issued each cycle | 375system.cpu.iq.issued_per_cycle::4 12534797 8.46% 92.01% # Number of insts issued each cycle |
| 376system.cpu.iq.issued_per_cycle::5 6516114 4.40% 96.41% # Number of insts issued each cycle | 376system.cpu.iq.issued_per_cycle::5 6516114 4.40% 96.41% # Number of insts issued each cycle |
| 377system.cpu.iq.issued_per_cycle::6 4026097 2.72% 99.12% # Number of insts issued each cycle | 377system.cpu.iq.issued_per_cycle::6 4026095 2.72% 99.12% # Number of insts issued each cycle |
| 378system.cpu.iq.issued_per_cycle::7 1116067 0.75% 99.88% # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::8 181312 0.12% 100.00% # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 378system.cpu.iq.issued_per_cycle::7 1116067 0.75% 99.88% # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::8 181312 0.12% 100.00% # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 383system.cpu.iq.issued_per_cycle::total 148240575 # Number of insts issued each cycle | 383system.cpu.iq.issued_per_cycle::total 148240577 # Number of insts issued each cycle |
| 384system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 385system.cpu.iq.fu_full::IntAlu 965215 38.57% 38.57% # attempts to use FU when none available 386system.cpu.iq.fu_full::IntMult 5593 0.22% 38.79% # attempts to use FU when none available 387system.cpu.iq.fu_full::IntDiv 0 0.00% 38.79% # attempts to use FU when none available 388system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.79% # attempts to use FU when none available 389system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.79% # attempts to use FU when none available 390system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.79% # attempts to use FU when none available 391system.cpu.iq.fu_full::FloatMult 0 0.00% 38.79% # attempts to use FU when none available --- 19 unchanged lines hidden (view full) --- 411system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.80% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.80% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.80% # attempts to use FU when none available 414system.cpu.iq.fu_full::MemRead 1158967 46.31% 85.11% # attempts to use FU when none available 415system.cpu.iq.fu_full::MemWrite 372730 14.89% 100.00% # attempts to use FU when none available 416system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 417system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 418system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 384system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 385system.cpu.iq.fu_full::IntAlu 965215 38.57% 38.57% # attempts to use FU when none available 386system.cpu.iq.fu_full::IntMult 5593 0.22% 38.79% # attempts to use FU when none available 387system.cpu.iq.fu_full::IntDiv 0 0.00% 38.79% # attempts to use FU when none available 388system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.79% # attempts to use FU when none available 389system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.79% # attempts to use FU when none available 390system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.79% # attempts to use FU when none available 391system.cpu.iq.fu_full::FloatMult 0 0.00% 38.79% # attempts to use FU when none available --- 19 unchanged lines hidden (view full) --- 411system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.80% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.80% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.80% # attempts to use FU when none available 414system.cpu.iq.fu_full::MemRead 1158967 46.31% 85.11% # attempts to use FU when none available 415system.cpu.iq.fu_full::MemWrite 372730 14.89% 100.00% # attempts to use FU when none available 416system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 417system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 418system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 419system.cpu.iq.FU_type_0::IntAlu 194899965 78.13% 78.13% # Type of FU issued | 419system.cpu.iq.FU_type_0::IntAlu 194899963 78.13% 78.13% # Type of FU issued |
| 420system.cpu.iq.FU_type_0::IntMult 979613 0.39% 78.52% # Type of FU issued 421system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued 422system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued 423system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued 424system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.52% # Type of FU issued 425system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.52% # Type of FU issued 426system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.52% # Type of FU issued 427system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.52% # Type of FU issued --- 16 unchanged lines hidden (view full) --- 444system.cpu.iq.FU_type_0::SimdFloatMisc 466123 0.19% 78.92% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdFloatMult 206380 0.08% 79.00% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdFloatMultAcc 71866 0.03% 79.03% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued 448system.cpu.iq.FU_type_0::MemRead 38355278 15.38% 94.41% # Type of FU issued 449system.cpu.iq.FU_type_0::MemWrite 13948063 5.59% 100.00% # Type of FU issued 450system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 451system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 420system.cpu.iq.FU_type_0::IntMult 979613 0.39% 78.52% # Type of FU issued 421system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued 422system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued 423system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued 424system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.52% # Type of FU issued 425system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.52% # Type of FU issued 426system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.52% # Type of FU issued 427system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.52% # Type of FU issued --- 16 unchanged lines hidden (view full) --- 444system.cpu.iq.FU_type_0::SimdFloatMisc 466123 0.19% 78.92% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdFloatMult 206380 0.08% 79.00% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdFloatMultAcc 71866 0.03% 79.03% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued 448system.cpu.iq.FU_type_0::MemRead 38355278 15.38% 94.41% # Type of FU issued 449system.cpu.iq.FU_type_0::MemWrite 13948063 5.59% 100.00% # Type of FU issued 450system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 451system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 452system.cpu.iq.FU_type_0::total 249456619 # Type of FU issued | 452system.cpu.iq.FU_type_0::total 249456617 # Type of FU issued |
| 453system.cpu.iq.rate 1.680523 # Inst issue rate 454system.cpu.iq.fu_busy_cnt 2502654 # FU busy when requested 455system.cpu.iq.fu_busy_rate 0.010032 # FU busy rate (busy events/executed inst) | 453system.cpu.iq.rate 1.680523 # Inst issue rate 454system.cpu.iq.fu_busy_cnt 2502654 # FU busy when requested 455system.cpu.iq.fu_busy_rate 0.010032 # FU busy rate (busy events/executed inst) |
| 456system.cpu.iq.int_inst_queue_reads 646705831 # Number of integer instruction queue reads 457system.cpu.iq.int_inst_queue_writes 466563436 # Number of integer instruction queue writes | 456system.cpu.iq.int_inst_queue_reads 646705826 # Number of integer instruction queue reads 457system.cpu.iq.int_inst_queue_writes 466563414 # Number of integer instruction queue writes |
| 458system.cpu.iq.int_inst_queue_wakeup_accesses 237885445 # Number of integer instruction queue wakeup accesses 459system.cpu.iq.fp_inst_queue_reads 3740007 # Number of floating instruction queue reads 460system.cpu.iq.fp_inst_queue_writes 2195697 # Number of floating instruction queue writes 461system.cpu.iq.fp_inst_queue_wakeup_accesses 1842613 # Number of floating instruction queue wakeup accesses | 458system.cpu.iq.int_inst_queue_wakeup_accesses 237885445 # Number of integer instruction queue wakeup accesses 459system.cpu.iq.fp_inst_queue_reads 3740007 # Number of floating instruction queue reads 460system.cpu.iq.fp_inst_queue_writes 2195697 # Number of floating instruction queue writes 461system.cpu.iq.fp_inst_queue_wakeup_accesses 1842613 # Number of floating instruction queue wakeup accesses |
| 462system.cpu.iq.int_alu_accesses 250082854 # Number of integer alu accesses | 462system.cpu.iq.int_alu_accesses 250082852 # Number of integer alu accesses |
| 463system.cpu.iq.fp_alu_accesses 1876419 # Number of floating point alu accesses 464system.cpu.iew.lsq.thread0.forwLoads 2013198 # Number of loads that had data forwarded from stores 465system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 463system.cpu.iq.fp_alu_accesses 1876419 # Number of floating point alu accesses 464system.cpu.iew.lsq.thread0.forwLoads 2013198 # Number of loads that had data forwarded from stores 465system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 466system.cpu.iew.lsq.thread0.squashedLoads 13163201 # Number of loads squashed | 466system.cpu.iew.lsq.thread0.squashedLoads 13163198 # Number of loads squashed |
| 467system.cpu.iew.lsq.thread0.ignoredResponses 11604 # Number of memory responses ignored because the instruction is squashed 468system.cpu.iew.lsq.thread0.memOrderViolation 18881 # Number of memory ordering violations 469system.cpu.iew.lsq.thread0.squashedStores 3771771 # Number of stores squashed 470system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 471system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 472system.cpu.iew.lsq.thread0.rescheduledLoads 18 # Number of loads that were rescheduled 473system.cpu.iew.lsq.thread0.cacheBlocked 107 # Number of times an access to memory failed due to the cache being blocked 474system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 467system.cpu.iew.lsq.thread0.ignoredResponses 11604 # Number of memory responses ignored because the instruction is squashed 468system.cpu.iew.lsq.thread0.memOrderViolation 18881 # Number of memory ordering violations 469system.cpu.iew.lsq.thread0.squashedStores 3771771 # Number of stores squashed 470system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 471system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 472system.cpu.iew.lsq.thread0.rescheduledLoads 18 # Number of loads that were rescheduled 473system.cpu.iew.lsq.thread0.cacheBlocked 107 # Number of times an access to memory failed due to the cache being blocked 474system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 475system.cpu.iew.iewSquashCycles 20832415 # Number of cycles IEW is squashing | 475system.cpu.iew.iewSquashCycles 20832413 # Number of cycles IEW is squashing |
| 476system.cpu.iew.iewBlockCycles 18550 # Number of cycles IEW is blocking 477system.cpu.iew.iewUnblockCycles 893 # Number of cycles IEW is unblocking | 476system.cpu.iew.iewBlockCycles 18550 # Number of cycles IEW is blocking 477system.cpu.iew.iewUnblockCycles 893 # Number of cycles IEW is unblocking |
| 478system.cpu.iew.iewDispatchedInsts 329254508 # Number of instructions dispatched to IQ | 478system.cpu.iew.iewDispatchedInsts 329254497 # Number of instructions dispatched to IQ |
| 479system.cpu.iew.iewDispSquashedInsts 785294 # Number of squashed instructions skipped by dispatch | 479system.cpu.iew.iewDispSquashedInsts 785294 # Number of squashed instructions skipped by dispatch |
| 480system.cpu.iew.iewDispLoadInsts 43012685 # Number of dispatched load instructions | 480system.cpu.iew.iewDispLoadInsts 43012682 # Number of dispatched load instructions |
| 481system.cpu.iew.iewDispStoreInsts 16416405 # Number of dispatched store instructions 482system.cpu.iew.iewDispNonSpecInsts 24746 # Number of dispatched non-speculative instructions 483system.cpu.iew.iewIQFullEvents 188 # Number of times the IQ has become full, causing a stall 484system.cpu.iew.iewLSQFullEvents 276 # Number of times the LSQ has become full, causing a stall 485system.cpu.iew.memOrderViolationEvents 18881 # Number of memory order violations 486system.cpu.iew.predictedTakenIncorrect 3889958 # Number of branches that were predicted taken incorrectly 487system.cpu.iew.predictedNotTakenIncorrect 3760086 # Number of branches that were predicted not taken incorrectly 488system.cpu.iew.branchMispredicts 7650044 # Number of branch mispredicts detected at execute 489system.cpu.iew.iewExecutedInsts 242960519 # Number of executed instructions 490system.cpu.iew.iewExecLoadInsts 36851938 # Number of load instructions executed | 481system.cpu.iew.iewDispStoreInsts 16416405 # Number of dispatched store instructions 482system.cpu.iew.iewDispNonSpecInsts 24746 # Number of dispatched non-speculative instructions 483system.cpu.iew.iewIQFullEvents 188 # Number of times the IQ has become full, causing a stall 484system.cpu.iew.iewLSQFullEvents 276 # Number of times the LSQ has become full, causing a stall 485system.cpu.iew.memOrderViolationEvents 18881 # Number of memory order violations 486system.cpu.iew.predictedTakenIncorrect 3889958 # Number of branches that were predicted taken incorrectly 487system.cpu.iew.predictedNotTakenIncorrect 3760086 # Number of branches that were predicted not taken incorrectly 488system.cpu.iew.branchMispredicts 7650044 # Number of branch mispredicts detected at execute 489system.cpu.iew.iewExecutedInsts 242960519 # Number of executed instructions 490system.cpu.iew.iewExecLoadInsts 36851938 # Number of load instructions executed |
| 491system.cpu.iew.iewExecSquashedInsts 6496100 # Number of squashed instructions skipped in execute | 491system.cpu.iew.iewExecSquashedInsts 6496098 # Number of squashed instructions skipped in execute |
| 492system.cpu.iew.exec_swp 0 # number of swp insts executed 493system.cpu.iew.exec_nop 17196 # number of nop insts executed 494system.cpu.iew.exec_refs 50500394 # number of memory reference insts executed 495system.cpu.iew.exec_branches 53426072 # Number of branches executed 496system.cpu.iew.exec_stores 13648456 # Number of stores executed 497system.cpu.iew.exec_rate 1.636760 # Inst execution rate 498system.cpu.iew.wb_sent 240785663 # cumulative count of insts sent to commit 499system.cpu.iew.wb_count 239728058 # cumulative count of insts written-back | 492system.cpu.iew.exec_swp 0 # number of swp insts executed 493system.cpu.iew.exec_nop 17196 # number of nop insts executed 494system.cpu.iew.exec_refs 50500394 # number of memory reference insts executed 495system.cpu.iew.exec_branches 53426072 # Number of branches executed 496system.cpu.iew.exec_stores 13648456 # Number of stores executed 497system.cpu.iew.exec_rate 1.636760 # Inst execution rate 498system.cpu.iew.wb_sent 240785663 # cumulative count of insts sent to commit 499system.cpu.iew.wb_count 239728058 # cumulative count of insts written-back |
| 500system.cpu.iew.wb_producers 148474079 # num instructions producing a value 501system.cpu.iew.wb_consumers 267261472 # num instructions consuming a value | 500system.cpu.iew.wb_producers 148474078 # num instructions producing a value 501system.cpu.iew.wb_consumers 267261470 # num instructions consuming a value |
| 502system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 503system.cpu.iew.wb_rate 1.614984 # insts written-back per cycle 504system.cpu.iew.wb_fanout 0.555539 # average fanout of values written-back 505system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 502system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 503system.cpu.iew.wb_rate 1.614984 # insts written-back per cycle 504system.cpu.iew.wb_fanout 0.555539 # average fanout of values written-back 505system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 506system.cpu.commit.commitSquashedInsts 140583620 # The number of squashed insts skipped by commit | 506system.cpu.commit.commitSquashedInsts 140583609 # The number of squashed insts skipped by commit |
| 507system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards 508system.cpu.commit.branchMispredicts 6128235 # The number of times a branch was mispredicted | 507system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards 508system.cpu.commit.branchMispredicts 6128235 # The number of times a branch was mispredicted |
| 509system.cpu.commit.committed_per_cycle::samples 127408160 # Number of insts commited each cycle | 509system.cpu.commit.committed_per_cycle::samples 127408164 # Number of insts commited each cycle |
| 510system.cpu.commit.committed_per_cycle::mean 1.480838 # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::stdev 2.185451 # Number of insts commited each cycle 512system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 510system.cpu.commit.committed_per_cycle::mean 1.480838 # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::stdev 2.185451 # Number of insts commited each cycle 512system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 513system.cpu.commit.committed_per_cycle::0 57701826 45.29% 45.29% # Number of insts commited each cycle 514system.cpu.commit.committed_per_cycle::1 31696936 24.88% 70.17% # Number of insts commited each cycle 515system.cpu.commit.committed_per_cycle::2 13777779 10.81% 80.98% # Number of insts commited each cycle 516system.cpu.commit.committed_per_cycle::3 7640619 6.00% 86.98% # Number of insts commited each cycle | 513system.cpu.commit.committed_per_cycle::0 57701829 45.29% 45.29% # Number of insts commited each cycle 514system.cpu.commit.committed_per_cycle::1 31696937 24.88% 70.17% # Number of insts commited each cycle 515system.cpu.commit.committed_per_cycle::2 13777780 10.81% 80.98% # Number of insts commited each cycle 516system.cpu.commit.committed_per_cycle::3 7640618 6.00% 86.98% # Number of insts commited each cycle |
| 517system.cpu.commit.committed_per_cycle::4 4387787 3.44% 90.42% # Number of insts commited each cycle 518system.cpu.commit.committed_per_cycle::5 1321958 1.04% 91.46% # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::6 1703212 1.34% 92.80% # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::7 1308014 1.03% 93.82% # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::8 7870029 6.18% 100.00% # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 517system.cpu.commit.committed_per_cycle::4 4387787 3.44% 90.42% # Number of insts commited each cycle 518system.cpu.commit.committed_per_cycle::5 1321958 1.04% 91.46% # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::6 1703212 1.34% 92.80% # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::7 1308014 1.03% 93.82% # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::8 7870029 6.18% 100.00% # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 525system.cpu.commit.committed_per_cycle::total 127408160 # Number of insts commited each cycle | 525system.cpu.commit.committed_per_cycle::total 127408164 # Number of insts commited each cycle |
| 526system.cpu.commit.committedInsts 172317409 # Number of instructions committed 527system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed 528system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 529system.cpu.commit.refs 42494118 # Number of memory references committed 530system.cpu.commit.loads 29849484 # Number of loads committed 531system.cpu.commit.membars 22408 # Number of memory barriers committed 532system.cpu.commit.branches 40300311 # Number of branches committed 533system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. 534system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. 535system.cpu.commit.function_calls 1848934 # Number of function calls committed. 536system.cpu.commit.bw_lim_events 7870029 # number cycles where commit BW limit reached 537system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 526system.cpu.commit.committedInsts 172317409 # Number of instructions committed 527system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed 528system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 529system.cpu.commit.refs 42494118 # Number of memory references committed 530system.cpu.commit.loads 29849484 # Number of loads committed 531system.cpu.commit.membars 22408 # Number of memory barriers committed 532system.cpu.commit.branches 40300311 # Number of branches committed 533system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. 534system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. 535system.cpu.commit.function_calls 1848934 # Number of function calls committed. 536system.cpu.commit.bw_lim_events 7870029 # number cycles where commit BW limit reached 537system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 538system.cpu.rob.rob_reads 448787441 # The number of ROB reads 539system.cpu.rob.rob_writes 679451137 # The number of ROB writes | 538system.cpu.rob.rob_reads 448787434 # The number of ROB reads 539system.cpu.rob.rob_writes 679451113 # The number of ROB writes |
| 540system.cpu.timesIdled 2805 # Number of times that the entire CPU went into an idle state and unscheduled itself | 540system.cpu.timesIdled 2805 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 541system.cpu.idleCycles 199323 # Total number of cycles that the CPU has spent unscheduled due to idling | 541system.cpu.idleCycles 199321 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 542system.cpu.committedInsts 172303021 # Number of Instructions Simulated 543system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated 544system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated 545system.cpu.cpi 0.861505 # CPI: Cycles Per Instruction 546system.cpu.cpi_total 0.861505 # CPI: Total CPI of All Threads 547system.cpu.ipc 1.160759 # IPC: Instructions Per Cycle 548system.cpu.ipc_total 1.160759 # IPC: Total IPC of All Threads 549system.cpu.int_regfile_reads 1079417004 # number of integer regfile reads --- 19 unchanged lines hidden (view full) --- 569system.cpu.toL2Bus.reqLayer0.occupancy 3016000 # Layer occupancy (ticks) 570system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 571system.cpu.toL2Bus.respLayer0.occupancy 6552496 # Layer occupancy (ticks) 572system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 573system.cpu.toL2Bus.respLayer1.occupancy 3047739 # Layer occupancy (ticks) 574system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 575system.cpu.icache.tags.replacements 2394 # number of replacements 576system.cpu.icache.tags.tagsinuse 1347.740549 # Cycle average of tags in use | 542system.cpu.committedInsts 172303021 # Number of Instructions Simulated 543system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated 544system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated 545system.cpu.cpi 0.861505 # CPI: Cycles Per Instruction 546system.cpu.cpi_total 0.861505 # CPI: Total CPI of All Threads 547system.cpu.ipc 1.160759 # IPC: Instructions Per Cycle 548system.cpu.ipc_total 1.160759 # IPC: Total IPC of All Threads 549system.cpu.int_regfile_reads 1079417004 # number of integer regfile reads --- 19 unchanged lines hidden (view full) --- 569system.cpu.toL2Bus.reqLayer0.occupancy 3016000 # Layer occupancy (ticks) 570system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 571system.cpu.toL2Bus.respLayer0.occupancy 6552496 # Layer occupancy (ticks) 572system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 573system.cpu.toL2Bus.respLayer1.occupancy 3047739 # Layer occupancy (ticks) 574system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 575system.cpu.icache.tags.replacements 2394 # number of replacements 576system.cpu.icache.tags.tagsinuse 1347.740549 # Cycle average of tags in use |
| 577system.cpu.icache.tags.total_refs 36845555 # Total number of references to valid blocks. | 577system.cpu.icache.tags.total_refs 36845557 # Total number of references to valid blocks. |
| 578system.cpu.icache.tags.sampled_refs 4125 # Sample count of references to valid blocks. | 578system.cpu.icache.tags.sampled_refs 4125 # Sample count of references to valid blocks. |
| 579system.cpu.icache.tags.avg_refs 8932.255758 # Average number of references to valid blocks. | 579system.cpu.icache.tags.avg_refs 8932.256242 # Average number of references to valid blocks. |
| 580system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 581system.cpu.icache.tags.occ_blocks::cpu.inst 1347.740549 # Average occupied blocks per requestor 582system.cpu.icache.tags.occ_percent::cpu.inst 0.658076 # Average percentage of cache occupancy 583system.cpu.icache.tags.occ_percent::total 0.658076 # Average percentage of cache occupancy | 580system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 581system.cpu.icache.tags.occ_blocks::cpu.inst 1347.740549 # Average occupied blocks per requestor 582system.cpu.icache.tags.occ_percent::cpu.inst 0.658076 # Average percentage of cache occupancy 583system.cpu.icache.tags.occ_percent::total 0.658076 # Average percentage of cache occupancy |
| 584system.cpu.icache.ReadReq_hits::cpu.inst 36845555 # number of ReadReq hits 585system.cpu.icache.ReadReq_hits::total 36845555 # number of ReadReq hits 586system.cpu.icache.demand_hits::cpu.inst 36845555 # number of demand (read+write) hits 587system.cpu.icache.demand_hits::total 36845555 # number of demand (read+write) hits 588system.cpu.icache.overall_hits::cpu.inst 36845555 # number of overall hits 589system.cpu.icache.overall_hits::total 36845555 # number of overall hits | 584system.cpu.icache.ReadReq_hits::cpu.inst 36845557 # number of ReadReq hits 585system.cpu.icache.ReadReq_hits::total 36845557 # number of ReadReq hits 586system.cpu.icache.demand_hits::cpu.inst 36845557 # number of demand (read+write) hits 587system.cpu.icache.demand_hits::total 36845557 # number of demand (read+write) hits 588system.cpu.icache.overall_hits::cpu.inst 36845557 # number of overall hits 589system.cpu.icache.overall_hits::total 36845557 # number of overall hits |
| 590system.cpu.icache.ReadReq_misses::cpu.inst 5337 # number of ReadReq misses 591system.cpu.icache.ReadReq_misses::total 5337 # number of ReadReq misses 592system.cpu.icache.demand_misses::cpu.inst 5337 # number of demand (read+write) misses 593system.cpu.icache.demand_misses::total 5337 # number of demand (read+write) misses 594system.cpu.icache.overall_misses::cpu.inst 5337 # number of overall misses 595system.cpu.icache.overall_misses::total 5337 # number of overall misses | 590system.cpu.icache.ReadReq_misses::cpu.inst 5337 # number of ReadReq misses 591system.cpu.icache.ReadReq_misses::total 5337 # number of ReadReq misses 592system.cpu.icache.demand_misses::cpu.inst 5337 # number of demand (read+write) misses 593system.cpu.icache.demand_misses::total 5337 # number of demand (read+write) misses 594system.cpu.icache.overall_misses::cpu.inst 5337 # number of overall misses 595system.cpu.icache.overall_misses::total 5337 # number of overall misses |
| 596system.cpu.icache.ReadReq_miss_latency::cpu.inst 225944745 # number of ReadReq miss cycles 597system.cpu.icache.ReadReq_miss_latency::total 225944745 # number of ReadReq miss cycles 598system.cpu.icache.demand_miss_latency::cpu.inst 225944745 # number of demand (read+write) miss cycles 599system.cpu.icache.demand_miss_latency::total 225944745 # number of demand (read+write) miss cycles 600system.cpu.icache.overall_miss_latency::cpu.inst 225944745 # number of overall miss cycles 601system.cpu.icache.overall_miss_latency::total 225944745 # number of overall miss cycles 602system.cpu.icache.ReadReq_accesses::cpu.inst 36850892 # number of ReadReq accesses(hits+misses) 603system.cpu.icache.ReadReq_accesses::total 36850892 # number of ReadReq accesses(hits+misses) 604system.cpu.icache.demand_accesses::cpu.inst 36850892 # number of demand (read+write) accesses 605system.cpu.icache.demand_accesses::total 36850892 # number of demand (read+write) accesses 606system.cpu.icache.overall_accesses::cpu.inst 36850892 # number of overall (read+write) accesses 607system.cpu.icache.overall_accesses::total 36850892 # number of overall (read+write) accesses | 596system.cpu.icache.ReadReq_miss_latency::cpu.inst 225938245 # number of ReadReq miss cycles 597system.cpu.icache.ReadReq_miss_latency::total 225938245 # number of ReadReq miss cycles 598system.cpu.icache.demand_miss_latency::cpu.inst 225938245 # number of demand (read+write) miss cycles 599system.cpu.icache.demand_miss_latency::total 225938245 # number of demand (read+write) miss cycles 600system.cpu.icache.overall_miss_latency::cpu.inst 225938245 # number of overall miss cycles 601system.cpu.icache.overall_miss_latency::total 225938245 # number of overall miss cycles 602system.cpu.icache.ReadReq_accesses::cpu.inst 36850894 # number of ReadReq accesses(hits+misses) 603system.cpu.icache.ReadReq_accesses::total 36850894 # number of ReadReq accesses(hits+misses) 604system.cpu.icache.demand_accesses::cpu.inst 36850894 # number of demand (read+write) accesses 605system.cpu.icache.demand_accesses::total 36850894 # number of demand (read+write) accesses 606system.cpu.icache.overall_accesses::cpu.inst 36850894 # number of overall (read+write) accesses 607system.cpu.icache.overall_accesses::total 36850894 # number of overall (read+write) accesses |
| 608system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000145 # miss rate for ReadReq accesses 609system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses 610system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses 611system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses 612system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses 613system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses | 608system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000145 # miss rate for ReadReq accesses 609system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses 610system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses 611system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses 612system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses 613system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses |
| 614system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42335.534008 # average ReadReq miss latency 615system.cpu.icache.ReadReq_avg_miss_latency::total 42335.534008 # average ReadReq miss latency 616system.cpu.icache.demand_avg_miss_latency::cpu.inst 42335.534008 # average overall miss latency 617system.cpu.icache.demand_avg_miss_latency::total 42335.534008 # average overall miss latency 618system.cpu.icache.overall_avg_miss_latency::cpu.inst 42335.534008 # average overall miss latency 619system.cpu.icache.overall_avg_miss_latency::total 42335.534008 # average overall miss latency | 614system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42334.316095 # average ReadReq miss latency 615system.cpu.icache.ReadReq_avg_miss_latency::total 42334.316095 # average ReadReq miss latency 616system.cpu.icache.demand_avg_miss_latency::cpu.inst 42334.316095 # average overall miss latency 617system.cpu.icache.demand_avg_miss_latency::total 42334.316095 # average overall miss latency 618system.cpu.icache.overall_avg_miss_latency::cpu.inst 42334.316095 # average overall miss latency 619system.cpu.icache.overall_avg_miss_latency::total 42334.316095 # average overall miss latency |
| 620system.cpu.icache.blocked_cycles::no_mshrs 1128 # number of cycles access was blocked 621system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 622system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked 623system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 624system.cpu.icache.avg_blocked_cycles::no_mshrs 59.368421 # average number of cycles each access was blocked 625system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 626system.cpu.icache.fast_writes 0 # number of fast writes performed 627system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 632system.cpu.icache.overall_mshr_hits::cpu.inst 1211 # number of overall MSHR hits 633system.cpu.icache.overall_mshr_hits::total 1211 # number of overall MSHR hits 634system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4126 # number of ReadReq MSHR misses 635system.cpu.icache.ReadReq_mshr_misses::total 4126 # number of ReadReq MSHR misses 636system.cpu.icache.demand_mshr_misses::cpu.inst 4126 # number of demand (read+write) MSHR misses 637system.cpu.icache.demand_mshr_misses::total 4126 # number of demand (read+write) MSHR misses 638system.cpu.icache.overall_mshr_misses::cpu.inst 4126 # number of overall MSHR misses 639system.cpu.icache.overall_mshr_misses::total 4126 # number of overall MSHR misses | 620system.cpu.icache.blocked_cycles::no_mshrs 1128 # number of cycles access was blocked 621system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 622system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked 623system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 624system.cpu.icache.avg_blocked_cycles::no_mshrs 59.368421 # average number of cycles each access was blocked 625system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 626system.cpu.icache.fast_writes 0 # number of fast writes performed 627system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 632system.cpu.icache.overall_mshr_hits::cpu.inst 1211 # number of overall MSHR hits 633system.cpu.icache.overall_mshr_hits::total 1211 # number of overall MSHR hits 634system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4126 # number of ReadReq MSHR misses 635system.cpu.icache.ReadReq_mshr_misses::total 4126 # number of ReadReq MSHR misses 636system.cpu.icache.demand_mshr_misses::cpu.inst 4126 # number of demand (read+write) MSHR misses 637system.cpu.icache.demand_mshr_misses::total 4126 # number of demand (read+write) MSHR misses 638system.cpu.icache.overall_mshr_misses::cpu.inst 4126 # number of overall MSHR misses 639system.cpu.icache.overall_mshr_misses::total 4126 # number of overall MSHR misses |
| 640system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168091004 # number of ReadReq MSHR miss cycles 641system.cpu.icache.ReadReq_mshr_miss_latency::total 168091004 # number of ReadReq MSHR miss cycles 642system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168091004 # number of demand (read+write) MSHR miss cycles 643system.cpu.icache.demand_mshr_miss_latency::total 168091004 # number of demand (read+write) MSHR miss cycles 644system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168091004 # number of overall MSHR miss cycles 645system.cpu.icache.overall_mshr_miss_latency::total 168091004 # number of overall MSHR miss cycles | 640system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168088504 # number of ReadReq MSHR miss cycles 641system.cpu.icache.ReadReq_mshr_miss_latency::total 168088504 # number of ReadReq MSHR miss cycles 642system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168088504 # number of demand (read+write) MSHR miss cycles 643system.cpu.icache.demand_mshr_miss_latency::total 168088504 # number of demand (read+write) MSHR miss cycles 644system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168088504 # number of overall MSHR miss cycles 645system.cpu.icache.overall_mshr_miss_latency::total 168088504 # number of overall MSHR miss cycles |
| 646system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses 647system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses 648system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses 649system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses 650system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for overall accesses 651system.cpu.icache.overall_mshr_miss_rate::total 0.000112 # mshr miss rate for overall accesses | 646system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses 647system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses 648system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses 649system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses 650system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for overall accesses 651system.cpu.icache.overall_mshr_miss_rate::total 0.000112 # mshr miss rate for overall accesses |
| 652system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40739.458071 # average ReadReq mshr miss latency 653system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40739.458071 # average ReadReq mshr miss latency 654system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40739.458071 # average overall mshr miss latency 655system.cpu.icache.demand_avg_mshr_miss_latency::total 40739.458071 # average overall mshr miss latency 656system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40739.458071 # average overall mshr miss latency 657system.cpu.icache.overall_avg_mshr_miss_latency::total 40739.458071 # average overall mshr miss latency | 652system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40738.852157 # average ReadReq mshr miss latency 653system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40738.852157 # average ReadReq mshr miss latency 654system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40738.852157 # average overall mshr miss latency 655system.cpu.icache.demand_avg_mshr_miss_latency::total 40738.852157 # average overall mshr miss latency 656system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40738.852157 # average overall mshr miss latency 657system.cpu.icache.overall_avg_mshr_miss_latency::total 40738.852157 # average overall mshr miss latency |
| 658system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 659system.cpu.l2cache.tags.replacements 0 # number of replacements | 658system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 659system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 660system.cpu.l2cache.tags.tagsinuse 1967.449765 # Cycle average of tags in use | 660system.cpu.l2cache.tags.tagsinuse 1967.449764 # Cycle average of tags in use |
| 661system.cpu.l2cache.tags.total_refs 2162 # Total number of references to valid blocks. 662system.cpu.l2cache.tags.sampled_refs 2732 # Sample count of references to valid blocks. 663system.cpu.l2cache.tags.avg_refs 0.791362 # Average number of references to valid blocks. 664system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 665system.cpu.l2cache.tags.occ_blocks::writebacks 4.994098 # Average occupied blocks per requestor | 661system.cpu.l2cache.tags.total_refs 2162 # Total number of references to valid blocks. 662system.cpu.l2cache.tags.sampled_refs 2732 # Sample count of references to valid blocks. 663system.cpu.l2cache.tags.avg_refs 0.791362 # Average number of references to valid blocks. 664system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 665system.cpu.l2cache.tags.occ_blocks::writebacks 4.994098 # Average occupied blocks per requestor |
| 666system.cpu.l2cache.tags.occ_blocks::cpu.inst 1425.569688 # Average occupied blocks per requestor | 666system.cpu.l2cache.tags.occ_blocks::cpu.inst 1425.569687 # Average occupied blocks per requestor |
| 667system.cpu.l2cache.tags.occ_blocks::cpu.data 536.885979 # Average occupied blocks per requestor 668system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy 669system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043505 # Average percentage of cache occupancy 670system.cpu.l2cache.tags.occ_percent::cpu.data 0.016384 # Average percentage of cache occupancy 671system.cpu.l2cache.tags.occ_percent::total 0.060042 # Average percentage of cache occupancy 672system.cpu.l2cache.ReadReq_hits::cpu.inst 2073 # number of ReadReq hits 673system.cpu.l2cache.ReadReq_hits::cpu.data 88 # number of ReadReq hits 674system.cpu.l2cache.ReadReq_hits::total 2161 # number of ReadReq hits --- 13 unchanged lines hidden (view full) --- 688system.cpu.l2cache.ReadExReq_misses::cpu.data 1071 # number of ReadExReq misses 689system.cpu.l2cache.ReadExReq_misses::total 1071 # number of ReadExReq misses 690system.cpu.l2cache.demand_misses::cpu.inst 2053 # number of demand (read+write) misses 691system.cpu.l2cache.demand_misses::cpu.data 1756 # number of demand (read+write) misses 692system.cpu.l2cache.demand_misses::total 3809 # number of demand (read+write) misses 693system.cpu.l2cache.overall_misses::cpu.inst 2053 # number of overall misses 694system.cpu.l2cache.overall_misses::cpu.data 1756 # number of overall misses 695system.cpu.l2cache.overall_misses::total 3809 # number of overall misses | 667system.cpu.l2cache.tags.occ_blocks::cpu.data 536.885979 # Average occupied blocks per requestor 668system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy 669system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043505 # Average percentage of cache occupancy 670system.cpu.l2cache.tags.occ_percent::cpu.data 0.016384 # Average percentage of cache occupancy 671system.cpu.l2cache.tags.occ_percent::total 0.060042 # Average percentage of cache occupancy 672system.cpu.l2cache.ReadReq_hits::cpu.inst 2073 # number of ReadReq hits 673system.cpu.l2cache.ReadReq_hits::cpu.data 88 # number of ReadReq hits 674system.cpu.l2cache.ReadReq_hits::total 2161 # number of ReadReq hits --- 13 unchanged lines hidden (view full) --- 688system.cpu.l2cache.ReadExReq_misses::cpu.data 1071 # number of ReadExReq misses 689system.cpu.l2cache.ReadExReq_misses::total 1071 # number of ReadExReq misses 690system.cpu.l2cache.demand_misses::cpu.inst 2053 # number of demand (read+write) misses 691system.cpu.l2cache.demand_misses::cpu.data 1756 # number of demand (read+write) misses 692system.cpu.l2cache.demand_misses::total 3809 # number of demand (read+write) misses 693system.cpu.l2cache.overall_misses::cpu.inst 2053 # number of overall misses 694system.cpu.l2cache.overall_misses::cpu.data 1756 # number of overall misses 695system.cpu.l2cache.overall_misses::total 3809 # number of overall misses |
| 696system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143228000 # number of ReadReq miss cycles 697system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51384000 # number of ReadReq miss cycles 698system.cpu.l2cache.ReadReq_miss_latency::total 194612000 # number of ReadReq miss cycles 699system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 72291750 # number of ReadExReq miss cycles 700system.cpu.l2cache.ReadExReq_miss_latency::total 72291750 # number of ReadExReq miss cycles 701system.cpu.l2cache.demand_miss_latency::cpu.inst 143228000 # number of demand (read+write) miss cycles 702system.cpu.l2cache.demand_miss_latency::cpu.data 123675750 # number of demand (read+write) miss cycles 703system.cpu.l2cache.demand_miss_latency::total 266903750 # number of demand (read+write) miss cycles 704system.cpu.l2cache.overall_miss_latency::cpu.inst 143228000 # number of overall miss cycles 705system.cpu.l2cache.overall_miss_latency::cpu.data 123675750 # number of overall miss cycles 706system.cpu.l2cache.overall_miss_latency::total 266903750 # number of overall miss cycles | 696system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143225500 # number of ReadReq miss cycles 697system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51383000 # number of ReadReq miss cycles 698system.cpu.l2cache.ReadReq_miss_latency::total 194608500 # number of ReadReq miss cycles 699system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 72292250 # number of ReadExReq miss cycles 700system.cpu.l2cache.ReadExReq_miss_latency::total 72292250 # number of ReadExReq miss cycles 701system.cpu.l2cache.demand_miss_latency::cpu.inst 143225500 # number of demand (read+write) miss cycles 702system.cpu.l2cache.demand_miss_latency::cpu.data 123675250 # number of demand (read+write) miss cycles 703system.cpu.l2cache.demand_miss_latency::total 266900750 # number of demand (read+write) miss cycles 704system.cpu.l2cache.overall_miss_latency::cpu.inst 143225500 # number of overall miss cycles 705system.cpu.l2cache.overall_miss_latency::cpu.data 123675250 # number of overall miss cycles 706system.cpu.l2cache.overall_miss_latency::total 266900750 # number of overall miss cycles |
| 707system.cpu.l2cache.ReadReq_accesses::cpu.inst 4126 # number of ReadReq accesses(hits+misses) 708system.cpu.l2cache.ReadReq_accesses::cpu.data 773 # number of ReadReq accesses(hits+misses) 709system.cpu.l2cache.ReadReq_accesses::total 4899 # number of ReadReq accesses(hits+misses) 710system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) 711system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) 712system.cpu.l2cache.ReadExReq_accesses::cpu.data 1079 # number of ReadExReq accesses(hits+misses) 713system.cpu.l2cache.ReadExReq_accesses::total 1079 # number of ReadExReq accesses(hits+misses) 714system.cpu.l2cache.demand_accesses::cpu.inst 4126 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 723system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992586 # miss rate for ReadExReq accesses 724system.cpu.l2cache.ReadExReq_miss_rate::total 0.992586 # miss rate for ReadExReq accesses 725system.cpu.l2cache.demand_miss_rate::cpu.inst 0.497576 # miss rate for demand accesses 726system.cpu.l2cache.demand_miss_rate::cpu.data 0.948164 # miss rate for demand accesses 727system.cpu.l2cache.demand_miss_rate::total 0.637170 # miss rate for demand accesses 728system.cpu.l2cache.overall_miss_rate::cpu.inst 0.497576 # miss rate for overall accesses 729system.cpu.l2cache.overall_miss_rate::cpu.data 0.948164 # miss rate for overall accesses 730system.cpu.l2cache.overall_miss_rate::total 0.637170 # miss rate for overall accesses | 707system.cpu.l2cache.ReadReq_accesses::cpu.inst 4126 # number of ReadReq accesses(hits+misses) 708system.cpu.l2cache.ReadReq_accesses::cpu.data 773 # number of ReadReq accesses(hits+misses) 709system.cpu.l2cache.ReadReq_accesses::total 4899 # number of ReadReq accesses(hits+misses) 710system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) 711system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) 712system.cpu.l2cache.ReadExReq_accesses::cpu.data 1079 # number of ReadExReq accesses(hits+misses) 713system.cpu.l2cache.ReadExReq_accesses::total 1079 # number of ReadExReq accesses(hits+misses) 714system.cpu.l2cache.demand_accesses::cpu.inst 4126 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 723system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992586 # miss rate for ReadExReq accesses 724system.cpu.l2cache.ReadExReq_miss_rate::total 0.992586 # miss rate for ReadExReq accesses 725system.cpu.l2cache.demand_miss_rate::cpu.inst 0.497576 # miss rate for demand accesses 726system.cpu.l2cache.demand_miss_rate::cpu.data 0.948164 # miss rate for demand accesses 727system.cpu.l2cache.demand_miss_rate::total 0.637170 # miss rate for demand accesses 728system.cpu.l2cache.overall_miss_rate::cpu.inst 0.497576 # miss rate for overall accesses 729system.cpu.l2cache.overall_miss_rate::cpu.data 0.948164 # miss rate for overall accesses 730system.cpu.l2cache.overall_miss_rate::total 0.637170 # miss rate for overall accesses |
| 731system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69765.221627 # average ReadReq miss latency 732system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75013.138686 # average ReadReq miss latency 733system.cpu.l2cache.ReadReq_avg_miss_latency::total 71078.159240 # average ReadReq miss latency 734system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67499.299720 # average ReadExReq miss latency 735system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67499.299720 # average ReadExReq miss latency 736system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69765.221627 # average overall miss latency 737system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70430.381549 # average overall miss latency 738system.cpu.l2cache.demand_avg_miss_latency::total 70071.869257 # average overall miss latency 739system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69765.221627 # average overall miss latency 740system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70430.381549 # average overall miss latency 741system.cpu.l2cache.overall_avg_miss_latency::total 70071.869257 # average overall miss latency | 731system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69764.003897 # average ReadReq miss latency 732system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75011.678832 # average ReadReq miss latency 733system.cpu.l2cache.ReadReq_avg_miss_latency::total 71076.880935 # average ReadReq miss latency 734system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67499.766573 # average ReadExReq miss latency 735system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67499.766573 # average ReadExReq miss latency 736system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69764.003897 # average overall miss latency 737system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70430.096811 # average overall miss latency 738system.cpu.l2cache.demand_avg_miss_latency::total 70071.081649 # average overall miss latency 739system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69764.003897 # average overall miss latency 740system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70430.096811 # average overall miss latency 741system.cpu.l2cache.overall_avg_miss_latency::total 70071.081649 # average overall miss latency |
| 742system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 743system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 744system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 745system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 746system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 747system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 748system.cpu.l2cache.fast_writes 0 # number of fast writes performed 749system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 12 unchanged lines hidden (view full) --- 762system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1071 # number of ReadExReq MSHR misses 763system.cpu.l2cache.ReadExReq_mshr_misses::total 1071 # number of ReadExReq MSHR misses 764system.cpu.l2cache.demand_mshr_misses::cpu.inst 2049 # number of demand (read+write) MSHR misses 765system.cpu.l2cache.demand_mshr_misses::cpu.data 1745 # number of demand (read+write) MSHR misses 766system.cpu.l2cache.demand_mshr_misses::total 3794 # number of demand (read+write) MSHR misses 767system.cpu.l2cache.overall_mshr_misses::cpu.inst 2049 # number of overall MSHR misses 768system.cpu.l2cache.overall_mshr_misses::cpu.data 1745 # number of overall MSHR misses 769system.cpu.l2cache.overall_mshr_misses::total 3794 # number of overall MSHR misses | 742system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 743system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 744system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 745system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 746system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 747system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 748system.cpu.l2cache.fast_writes 0 # number of fast writes performed 749system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 12 unchanged lines hidden (view full) --- 762system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1071 # number of ReadExReq MSHR misses 763system.cpu.l2cache.ReadExReq_mshr_misses::total 1071 # number of ReadExReq MSHR misses 764system.cpu.l2cache.demand_mshr_misses::cpu.inst 2049 # number of demand (read+write) MSHR misses 765system.cpu.l2cache.demand_mshr_misses::cpu.data 1745 # number of demand (read+write) MSHR misses 766system.cpu.l2cache.demand_mshr_misses::total 3794 # number of demand (read+write) MSHR misses 767system.cpu.l2cache.overall_mshr_misses::cpu.inst 2049 # number of overall MSHR misses 768system.cpu.l2cache.overall_mshr_misses::cpu.data 1745 # number of overall MSHR misses 769system.cpu.l2cache.overall_mshr_misses::total 3794 # number of overall MSHR misses |
| 770system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117254500 # number of ReadReq MSHR miss cycles 771system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42298000 # number of ReadReq MSHR miss cycles 772system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159552500 # number of ReadReq MSHR miss cycles | 770system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117253000 # number of ReadReq MSHR miss cycles 771system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42297000 # number of ReadReq MSHR miss cycles 772system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159550000 # number of ReadReq MSHR miss cycles |
| 773system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 58841750 # number of ReadExReq MSHR miss cycles 774system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 58841750 # number of ReadExReq MSHR miss cycles | 773system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 58841750 # number of ReadExReq MSHR miss cycles 774system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 58841750 # number of ReadExReq MSHR miss cycles |
| 775system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117254500 # number of demand (read+write) MSHR miss cycles 776system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101139750 # number of demand (read+write) MSHR miss cycles 777system.cpu.l2cache.demand_mshr_miss_latency::total 218394250 # number of demand (read+write) MSHR miss cycles 778system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117254500 # number of overall MSHR miss cycles 779system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101139750 # number of overall MSHR miss cycles 780system.cpu.l2cache.overall_mshr_miss_latency::total 218394250 # number of overall MSHR miss cycles | 775system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117253000 # number of demand (read+write) MSHR miss cycles 776system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101138750 # number of demand (read+write) MSHR miss cycles 777system.cpu.l2cache.demand_mshr_miss_latency::total 218391750 # number of demand (read+write) MSHR miss cycles 778system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117253000 # number of overall MSHR miss cycles 779system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101138750 # number of overall MSHR miss cycles 780system.cpu.l2cache.overall_mshr_miss_latency::total 218391750 # number of overall MSHR miss cycles |
| 781system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for ReadReq accesses 782system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871928 # mshr miss rate for ReadReq accesses 783system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.555828 # mshr miss rate for ReadReq accesses 784system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992586 # mshr miss rate for ReadExReq accesses 785system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992586 # mshr miss rate for ReadExReq accesses 786system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for demand accesses 787system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942225 # mshr miss rate for demand accesses 788system.cpu.l2cache.demand_mshr_miss_rate::total 0.634660 # mshr miss rate for demand accesses 789system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for overall accesses 790system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942225 # mshr miss rate for overall accesses 791system.cpu.l2cache.overall_mshr_miss_rate::total 0.634660 # mshr miss rate for overall accesses | 781system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for ReadReq accesses 782system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871928 # mshr miss rate for ReadReq accesses 783system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.555828 # mshr miss rate for ReadReq accesses 784system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992586 # mshr miss rate for ReadExReq accesses 785system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992586 # mshr miss rate for ReadExReq accesses 786system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for demand accesses 787system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942225 # mshr miss rate for demand accesses 788system.cpu.l2cache.demand_mshr_miss_rate::total 0.634660 # mshr miss rate for demand accesses 789system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for overall accesses 790system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942225 # mshr miss rate for overall accesses 791system.cpu.l2cache.overall_mshr_miss_rate::total 0.634660 # mshr miss rate for overall accesses |
| 792system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57225.231820 # average ReadReq mshr miss latency 793system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62756.676558 # average ReadReq mshr miss latency 794system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58594.381197 # average ReadReq mshr miss latency | 792system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57224.499756 # average ReadReq mshr miss latency 793system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62755.192878 # average ReadReq mshr miss latency 794system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58593.463092 # average ReadReq mshr miss latency |
| 795system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54940.943044 # average ReadExReq mshr miss latency 796system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54940.943044 # average ReadExReq mshr miss latency | 795system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54940.943044 # average ReadExReq mshr miss latency 796system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54940.943044 # average ReadExReq mshr miss latency |
| 797system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57225.231820 # average overall mshr miss latency 798system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57959.742120 # average overall mshr miss latency 799system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57563.060095 # average overall mshr miss latency 800system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57225.231820 # average overall mshr miss latency 801system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57959.742120 # average overall mshr miss latency 802system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57563.060095 # average overall mshr miss latency | 797system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57224.499756 # average overall mshr miss latency 798system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57959.169054 # average overall mshr miss latency 799system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57562.401160 # average overall mshr miss latency 800system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57224.499756 # average overall mshr miss latency 801system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57959.169054 # average overall mshr miss latency 802system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57562.401160 # average overall mshr miss latency |
| 803system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 804system.cpu.dcache.tags.replacements 57 # number of replacements 805system.cpu.dcache.tags.tagsinuse 1406.103135 # Cycle average of tags in use 806system.cpu.dcache.tags.total_refs 46786156 # Total number of references to valid blocks. 807system.cpu.dcache.tags.sampled_refs 1852 # Sample count of references to valid blocks. 808system.cpu.dcache.tags.avg_refs 25262.503240 # Average number of references to valid blocks. 809system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 810system.cpu.dcache.tags.occ_blocks::cpu.data 1406.103135 # Average occupied blocks per requestor --- 16 unchanged lines hidden (view full) --- 827system.cpu.dcache.WriteReq_misses::cpu.data 7723 # number of WriteReq misses 828system.cpu.dcache.WriteReq_misses::total 7723 # number of WriteReq misses 829system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 830system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 831system.cpu.dcache.demand_misses::cpu.data 9625 # number of demand (read+write) misses 832system.cpu.dcache.demand_misses::total 9625 # number of demand (read+write) misses 833system.cpu.dcache.overall_misses::cpu.data 9625 # number of overall misses 834system.cpu.dcache.overall_misses::total 9625 # number of overall misses | 803system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 804system.cpu.dcache.tags.replacements 57 # number of replacements 805system.cpu.dcache.tags.tagsinuse 1406.103135 # Cycle average of tags in use 806system.cpu.dcache.tags.total_refs 46786156 # Total number of references to valid blocks. 807system.cpu.dcache.tags.sampled_refs 1852 # Sample count of references to valid blocks. 808system.cpu.dcache.tags.avg_refs 25262.503240 # Average number of references to valid blocks. 809system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 810system.cpu.dcache.tags.occ_blocks::cpu.data 1406.103135 # Average occupied blocks per requestor --- 16 unchanged lines hidden (view full) --- 827system.cpu.dcache.WriteReq_misses::cpu.data 7723 # number of WriteReq misses 828system.cpu.dcache.WriteReq_misses::total 7723 # number of WriteReq misses 829system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 830system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 831system.cpu.dcache.demand_misses::cpu.data 9625 # number of demand (read+write) misses 832system.cpu.dcache.demand_misses::total 9625 # number of demand (read+write) misses 833system.cpu.dcache.overall_misses::cpu.data 9625 # number of overall misses 834system.cpu.dcache.overall_misses::total 9625 # number of overall misses |
| 835system.cpu.dcache.ReadReq_miss_latency::cpu.data 121870727 # number of ReadReq miss cycles 836system.cpu.dcache.ReadReq_miss_latency::total 121870727 # number of ReadReq miss cycles 837system.cpu.dcache.WriteReq_miss_latency::cpu.data 465623246 # number of WriteReq miss cycles 838system.cpu.dcache.WriteReq_miss_latency::total 465623246 # number of WriteReq miss cycles | 835system.cpu.dcache.ReadReq_miss_latency::cpu.data 121862727 # number of ReadReq miss cycles 836system.cpu.dcache.ReadReq_miss_latency::total 121862727 # number of ReadReq miss cycles 837system.cpu.dcache.WriteReq_miss_latency::cpu.data 465623746 # number of WriteReq miss cycles 838system.cpu.dcache.WriteReq_miss_latency::total 465623746 # number of WriteReq miss cycles |
| 839system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles 840system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles | 839system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles 840system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles |
| 841system.cpu.dcache.demand_miss_latency::cpu.data 587493973 # number of demand (read+write) miss cycles 842system.cpu.dcache.demand_miss_latency::total 587493973 # number of demand (read+write) miss cycles 843system.cpu.dcache.overall_miss_latency::cpu.data 587493973 # number of overall miss cycles 844system.cpu.dcache.overall_miss_latency::total 587493973 # number of overall miss cycles | 841system.cpu.dcache.demand_miss_latency::cpu.data 587486473 # number of demand (read+write) miss cycles 842system.cpu.dcache.demand_miss_latency::total 587486473 # number of demand (read+write) miss cycles 843system.cpu.dcache.overall_miss_latency::cpu.data 587486473 # number of overall miss cycles 844system.cpu.dcache.overall_miss_latency::total 587486473 # number of overall miss cycles |
| 845system.cpu.dcache.ReadReq_accesses::cpu.data 34386613 # number of ReadReq accesses(hits+misses) 846system.cpu.dcache.ReadReq_accesses::total 34386613 # number of ReadReq accesses(hits+misses) 847system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 848system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) 849system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22476 # number of LoadLockedReq accesses(hits+misses) 850system.cpu.dcache.LoadLockedReq_accesses::total 22476 # number of LoadLockedReq accesses(hits+misses) 851system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) 852system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) --- 6 unchanged lines hidden (view full) --- 859system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses 860system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses 861system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses 862system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses 863system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses 864system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses 865system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses 866system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses | 845system.cpu.dcache.ReadReq_accesses::cpu.data 34386613 # number of ReadReq accesses(hits+misses) 846system.cpu.dcache.ReadReq_accesses::total 34386613 # number of ReadReq accesses(hits+misses) 847system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 848system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) 849system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22476 # number of LoadLockedReq accesses(hits+misses) 850system.cpu.dcache.LoadLockedReq_accesses::total 22476 # number of LoadLockedReq accesses(hits+misses) 851system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) 852system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) --- 6 unchanged lines hidden (view full) --- 859system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses 860system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses 861system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses 862system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses 863system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses 864system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses 865system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses 866system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses |
| 867system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64075.040484 # average ReadReq miss latency 868system.cpu.dcache.ReadReq_avg_miss_latency::total 64075.040484 # average ReadReq miss latency 869system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60290.463033 # average WriteReq miss latency 870system.cpu.dcache.WriteReq_avg_miss_latency::total 60290.463033 # average WriteReq miss latency | 867system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64070.834385 # average ReadReq miss latency 868system.cpu.dcache.ReadReq_avg_miss_latency::total 64070.834385 # average ReadReq miss latency 869system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60290.527774 # average WriteReq miss latency 870system.cpu.dcache.WriteReq_avg_miss_latency::total 60290.527774 # average WriteReq miss latency |
| 871system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency 872system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency | 871system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency 872system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency |
| 873system.cpu.dcache.demand_avg_miss_latency::cpu.data 61038.334857 # average overall miss latency 874system.cpu.dcache.demand_avg_miss_latency::total 61038.334857 # average overall miss latency 875system.cpu.dcache.overall_avg_miss_latency::cpu.data 61038.334857 # average overall miss latency 876system.cpu.dcache.overall_avg_miss_latency::total 61038.334857 # average overall miss latency | 873system.cpu.dcache.demand_avg_miss_latency::cpu.data 61037.555636 # average overall miss latency 874system.cpu.dcache.demand_avg_miss_latency::total 61037.555636 # average overall miss latency 875system.cpu.dcache.overall_avg_miss_latency::cpu.data 61037.555636 # average overall miss latency 876system.cpu.dcache.overall_avg_miss_latency::total 61037.555636 # average overall miss latency |
| 877system.cpu.dcache.blocked_cycles::no_mshrs 592 # number of cycles access was blocked 878system.cpu.dcache.blocked_cycles::no_targets 314 # number of cycles access was blocked 879system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked 880system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked 881system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.818182 # average number of cycles each access was blocked 882system.cpu.dcache.avg_blocked_cycles::no_targets 78.500000 # average number of cycles each access was blocked 883system.cpu.dcache.fast_writes 0 # number of fast writes performed 884system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 12 unchanged lines hidden (view full) --- 897system.cpu.dcache.ReadReq_mshr_misses::cpu.data 774 # number of ReadReq MSHR misses 898system.cpu.dcache.ReadReq_mshr_misses::total 774 # number of ReadReq MSHR misses 899system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1078 # number of WriteReq MSHR misses 900system.cpu.dcache.WriteReq_mshr_misses::total 1078 # number of WriteReq MSHR misses 901system.cpu.dcache.demand_mshr_misses::cpu.data 1852 # number of demand (read+write) MSHR misses 902system.cpu.dcache.demand_mshr_misses::total 1852 # number of demand (read+write) MSHR misses 903system.cpu.dcache.overall_mshr_misses::cpu.data 1852 # number of overall MSHR misses 904system.cpu.dcache.overall_mshr_misses::total 1852 # number of overall MSHR misses | 877system.cpu.dcache.blocked_cycles::no_mshrs 592 # number of cycles access was blocked 878system.cpu.dcache.blocked_cycles::no_targets 314 # number of cycles access was blocked 879system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked 880system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked 881system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.818182 # average number of cycles each access was blocked 882system.cpu.dcache.avg_blocked_cycles::no_targets 78.500000 # average number of cycles each access was blocked 883system.cpu.dcache.fast_writes 0 # number of fast writes performed 884system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 12 unchanged lines hidden (view full) --- 897system.cpu.dcache.ReadReq_mshr_misses::cpu.data 774 # number of ReadReq MSHR misses 898system.cpu.dcache.ReadReq_mshr_misses::total 774 # number of ReadReq MSHR misses 899system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1078 # number of WriteReq MSHR misses 900system.cpu.dcache.WriteReq_mshr_misses::total 1078 # number of WriteReq MSHR misses 901system.cpu.dcache.demand_mshr_misses::cpu.data 1852 # number of demand (read+write) MSHR misses 902system.cpu.dcache.demand_mshr_misses::total 1852 # number of demand (read+write) MSHR misses 903system.cpu.dcache.overall_mshr_misses::cpu.data 1852 # number of overall MSHR misses 904system.cpu.dcache.overall_mshr_misses::total 1852 # number of overall MSHR misses |
| 905system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53114761 # number of ReadReq MSHR miss cycles 906system.cpu.dcache.ReadReq_mshr_miss_latency::total 53114761 # number of ReadReq MSHR miss cycles 907system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73392998 # number of WriteReq MSHR miss cycles 908system.cpu.dcache.WriteReq_mshr_miss_latency::total 73392998 # number of WriteReq MSHR miss cycles 909system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126507759 # number of demand (read+write) MSHR miss cycles 910system.cpu.dcache.demand_mshr_miss_latency::total 126507759 # number of demand (read+write) MSHR miss cycles 911system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126507759 # number of overall MSHR miss cycles 912system.cpu.dcache.overall_mshr_miss_latency::total 126507759 # number of overall MSHR miss cycles | 905system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53113761 # number of ReadReq MSHR miss cycles 906system.cpu.dcache.ReadReq_mshr_miss_latency::total 53113761 # number of ReadReq MSHR miss cycles 907system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73393498 # number of WriteReq MSHR miss cycles 908system.cpu.dcache.WriteReq_mshr_miss_latency::total 73393498 # number of WriteReq MSHR miss cycles 909system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126507259 # number of demand (read+write) MSHR miss cycles 910system.cpu.dcache.demand_mshr_miss_latency::total 126507259 # number of demand (read+write) MSHR miss cycles 911system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126507259 # number of overall MSHR miss cycles 912system.cpu.dcache.overall_mshr_miss_latency::total 126507259 # number of overall MSHR miss cycles |
| 913system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses 914system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses 915system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses 916system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses 917system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses 918system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 919system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses 920system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses | 913system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses 914system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses 915system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses 916system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses 917system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses 918system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 919system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses 920system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses |
| 921system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68623.722222 # average ReadReq mshr miss latency 922system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68623.722222 # average ReadReq mshr miss latency 923system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68082.558442 # average WriteReq mshr miss latency 924system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68082.558442 # average WriteReq mshr miss latency 925system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68308.725162 # average overall mshr miss latency 926system.cpu.dcache.demand_avg_mshr_miss_latency::total 68308.725162 # average overall mshr miss latency 927system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68308.725162 # average overall mshr miss latency 928system.cpu.dcache.overall_avg_mshr_miss_latency::total 68308.725162 # average overall mshr miss latency | 921system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68622.430233 # average ReadReq mshr miss latency 922system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68622.430233 # average ReadReq mshr miss latency 923system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68083.022263 # average WriteReq mshr miss latency 924system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68083.022263 # average WriteReq mshr miss latency 925system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68308.455184 # average overall mshr miss latency 926system.cpu.dcache.demand_avg_mshr_miss_latency::total 68308.455184 # average overall mshr miss latency 927system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68308.455184 # average overall mshr miss latency 928system.cpu.dcache.overall_avg_mshr_miss_latency::total 68308.455184 # average overall mshr miss latency |
| 929system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 930 931---------- End Simulation Statistics ---------- | 929system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 930 931---------- End Simulation Statistics ---------- |