| stats.txt (9924:31ef410b6843) | stats.txt (9978:81d7551dd3be) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.074201 # Number of seconds simulated 4sim_ticks 74201024500 # Number of ticks simulated 5final_tick 74201024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.074220 # Number of seconds simulated 4sim_ticks 74219948500 # Number of ticks simulated 5final_tick 74219948500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 115322 # Simulator instruction rate (inst/s) 8host_op_rate 126267 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 49662501 # Simulator tick rate (ticks/s) 10host_mem_usage 251448 # Number of bytes of host memory used 11host_seconds 1494.11 # Real time elapsed on the host | 7host_inst_rate 110839 # Simulator instruction rate (inst/s) 8host_op_rate 121359 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 47744278 # Simulator tick rate (ticks/s) 10host_mem_usage 278976 # Number of bytes of host memory used 11host_seconds 1554.53 # Real time elapsed on the host |
| 12sim_insts 172303021 # Number of instructions simulated 13sim_ops 188656503 # Number of ops (including micro ops) simulated | 12sim_insts 172303021 # Number of instructions simulated 13sim_ops 188656503 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 131328 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 111872 # Number of bytes read from this memory 16system.physmem.bytes_read::total 243200 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 131328 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 131328 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 2052 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 1748 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 3800 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1769895 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 1507688 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 3277583 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1769895 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1769895 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1769895 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 1507688 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 3277583 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 3801 # Total number of read requests accepted by DRAM controller 31system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller 32system.physmem.readBursts 3801 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 33system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts 34system.physmem.bytesRead 243200 # Total number of bytes read from memory 35system.physmem.bytesWritten 0 # Total number of bytes written to memory 36system.physmem.bytesConsumedRd 243200 # bytesRead derated as per pkt->getSize() 37system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 38system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q 39system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed 40system.physmem.perBankRdReqs::0 308 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::1 215 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::2 134 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::3 308 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::4 298 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::5 300 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::6 261 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::7 216 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::8 246 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::9 215 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::10 289 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::11 194 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::12 191 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::13 208 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::14 218 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::15 200 # Track reads on a per bank basis 56system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 72system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 73system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 74system.physmem.totGap 74201006000 # Total gap between requests 75system.physmem.readPktSize::0 0 # Categorize read packet sizes 76system.physmem.readPktSize::1 0 # Categorize read packet sizes 77system.physmem.readPktSize::2 0 # Categorize read packet sizes 78system.physmem.readPktSize::3 0 # Categorize read packet sizes 79system.physmem.readPktSize::4 0 # Categorize read packet sizes 80system.physmem.readPktSize::5 0 # Categorize read packet sizes 81system.physmem.readPktSize::6 3801 # Categorize read packet sizes 82system.physmem.writePktSize::0 0 # Categorize write packet sizes 83system.physmem.writePktSize::1 0 # Categorize write packet sizes 84system.physmem.writePktSize::2 0 # Categorize write packet sizes 85system.physmem.writePktSize::3 0 # Categorize write packet sizes 86system.physmem.writePktSize::4 0 # Categorize write packet sizes 87system.physmem.writePktSize::5 0 # Categorize write packet sizes 88system.physmem.writePktSize::6 0 # Categorize write packet sizes 89system.physmem.rdQLenPdf::0 2829 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::1 792 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::2 136 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see | 14system.physmem.bytes_read::cpu.inst 131072 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 111680 # Number of bytes read from this memory 16system.physmem.bytes_read::total 242752 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 131072 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 131072 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 2048 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 1745 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 3793 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1765994 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 1504717 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 3270711 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1765994 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1765994 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1765994 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 1504717 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 3270711 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 3794 # Number of read requests accepted 31system.physmem.writeReqs 0 # Number of write requests accepted 32system.physmem.readBursts 3794 # Number of DRAM read bursts, including those serviced by the write queue 33system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 34system.physmem.bytesReadDRAM 242816 # Total number of bytes read from DRAM 35system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 36system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 37system.physmem.bytesReadSys 242816 # Total read bytes from the system interface side 38system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 39system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 40system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 41system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 42system.physmem.perBankRdBursts::0 306 # Per bank write bursts 43system.physmem.perBankRdBursts::1 215 # Per bank write bursts 44system.physmem.perBankRdBursts::2 133 # Per bank write bursts 45system.physmem.perBankRdBursts::3 308 # Per bank write bursts 46system.physmem.perBankRdBursts::4 298 # Per bank write bursts 47system.physmem.perBankRdBursts::5 299 # Per bank write bursts 48system.physmem.perBankRdBursts::6 264 # Per bank write bursts 49system.physmem.perBankRdBursts::7 216 # Per bank write bursts 50system.physmem.perBankRdBursts::8 246 # Per bank write bursts 51system.physmem.perBankRdBursts::9 215 # Per bank write bursts 52system.physmem.perBankRdBursts::10 289 # Per bank write bursts 53system.physmem.perBankRdBursts::11 193 # Per bank write bursts 54system.physmem.perBankRdBursts::12 189 # Per bank write bursts 55system.physmem.perBankRdBursts::13 206 # Per bank write bursts 56system.physmem.perBankRdBursts::14 217 # Per bank write bursts 57system.physmem.perBankRdBursts::15 200 # Per bank write bursts 58system.physmem.perBankWrBursts::0 0 # Per bank write bursts 59system.physmem.perBankWrBursts::1 0 # Per bank write bursts 60system.physmem.perBankWrBursts::2 0 # Per bank write bursts 61system.physmem.perBankWrBursts::3 0 # Per bank write bursts 62system.physmem.perBankWrBursts::4 0 # Per bank write bursts 63system.physmem.perBankWrBursts::5 0 # Per bank write bursts 64system.physmem.perBankWrBursts::6 0 # Per bank write bursts 65system.physmem.perBankWrBursts::7 0 # Per bank write bursts 66system.physmem.perBankWrBursts::8 0 # Per bank write bursts 67system.physmem.perBankWrBursts::9 0 # Per bank write bursts 68system.physmem.perBankWrBursts::10 0 # Per bank write bursts 69system.physmem.perBankWrBursts::11 0 # Per bank write bursts 70system.physmem.perBankWrBursts::12 0 # Per bank write bursts 71system.physmem.perBankWrBursts::13 0 # Per bank write bursts 72system.physmem.perBankWrBursts::14 0 # Per bank write bursts 73system.physmem.perBankWrBursts::15 0 # Per bank write bursts 74system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 75system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 76system.physmem.totGap 74219930000 # Total gap between requests 77system.physmem.readPktSize::0 0 # Read request sizes (log2) 78system.physmem.readPktSize::1 0 # Read request sizes (log2) 79system.physmem.readPktSize::2 0 # Read request sizes (log2) 80system.physmem.readPktSize::3 0 # Read request sizes (log2) 81system.physmem.readPktSize::4 0 # Read request sizes (log2) 82system.physmem.readPktSize::5 0 # Read request sizes (log2) 83system.physmem.readPktSize::6 3794 # Read request sizes (log2) 84system.physmem.writePktSize::0 0 # Write request sizes (log2) 85system.physmem.writePktSize::1 0 # Write request sizes (log2) 86system.physmem.writePktSize::2 0 # Write request sizes (log2) 87system.physmem.writePktSize::3 0 # Write request sizes (log2) 88system.physmem.writePktSize::4 0 # Write request sizes (log2) 89system.physmem.writePktSize::5 0 # Write request sizes (log2) 90system.physmem.writePktSize::6 0 # Write request sizes (log2) 91system.physmem.rdQLenPdf::0 2825 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::1 784 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::2 142 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see |
| 94system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 43 unchanged lines hidden (view full) --- 145system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see | 96system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 43 unchanged lines hidden (view full) --- 147system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| 153system.physmem.bytesPerActivate::samples 389 # Bytes accessed per row activation 154system.physmem.bytesPerActivate::mean 616.966581 # Bytes accessed per row activation 155system.physmem.bytesPerActivate::gmean 221.267348 # Bytes accessed per row activation 156system.physmem.bytesPerActivate::stdev 1216.553816 # Bytes accessed per row activation 157system.physmem.bytesPerActivate::64-65 139 35.73% 35.73% # Bytes accessed per row activation 158system.physmem.bytesPerActivate::128-129 59 15.17% 50.90% # Bytes accessed per row activation 159system.physmem.bytesPerActivate::192-193 33 8.48% 59.38% # Bytes accessed per row activation 160system.physmem.bytesPerActivate::256-257 24 6.17% 65.55% # Bytes accessed per row activation 161system.physmem.bytesPerActivate::320-321 15 3.86% 69.41% # Bytes accessed per row activation 162system.physmem.bytesPerActivate::384-385 13 3.34% 72.75% # Bytes accessed per row activation 163system.physmem.bytesPerActivate::448-449 4 1.03% 73.78% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::512-513 7 1.80% 75.58% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::576-577 5 1.29% 76.86% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::640-641 8 2.06% 78.92% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::704-705 4 1.03% 79.95% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::768-769 4 1.03% 80.98% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::832-833 3 0.77% 81.75% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::896-897 3 0.77% 82.52% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::960-961 5 1.29% 83.80% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::1024-1025 4 1.03% 84.83% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::1088-1089 4 1.03% 85.86% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::1152-1153 1 0.26% 86.12% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::1216-1217 1 0.26% 86.38% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::1280-1281 3 0.77% 87.15% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::1344-1345 3 0.77% 87.92% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::1408-1409 3 0.77% 88.69% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::1472-1473 2 0.51% 89.20% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::1536-1537 1 0.26% 89.46% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::1600-1601 3 0.77% 90.23% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::1664-1665 3 0.77% 91.00% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1728-1729 1 0.26% 91.26% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1792-1793 1 0.26% 91.52% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1920-1921 1 0.26% 91.77% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::2048-2049 1 0.26% 92.03% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::2112-2113 2 0.51% 92.54% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::2176-2177 1 0.26% 92.80% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::2304-2305 1 0.26% 93.06% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::2368-2369 1 0.26% 93.32% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::2432-2433 1 0.26% 93.57% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::2624-2625 1 0.26% 93.83% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::2688-2689 1 0.26% 94.09% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::2816-2817 1 0.26% 94.34% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::2944-2945 1 0.26% 94.60% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::3008-3009 1 0.26% 94.86% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::3072-3073 1 0.26% 95.12% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::3200-3201 1 0.26% 95.37% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::3264-3265 4 1.03% 96.40% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::3712-3713 1 0.26% 96.66% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::4032-4033 1 0.26% 96.92% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::4352-4353 1 0.26% 97.17% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::4416-4417 1 0.26% 97.43% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::4480-4481 1 0.26% 97.69% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::4800-4801 1 0.26% 97.94% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::5120-5121 1 0.26% 98.20% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::5248-5249 1 0.26% 98.46% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::6208-6209 1 0.26% 98.71% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::6720-6721 1 0.26% 98.97% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::6848-6849 1 0.26% 99.23% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::8128-8129 1 0.26% 99.49% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::8192-8193 2 0.51% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 389 # Bytes accessed per row activation 214system.physmem.totQLat 12962000 # Total cycles spent in queuing delays 215system.physmem.totMemAccLat 86183250 # Sum of mem lat for all requests 216system.physmem.totBusLat 19005000 # Total cycles spent in databus access 217system.physmem.totBankLat 54216250 # Total cycles spent in bank access 218system.physmem.avgQLat 3410.16 # Average queueing delay per request 219system.physmem.avgBankLat 14263.68 # Average bank access latency per request 220system.physmem.avgBusLat 5000.00 # Average bus latency per request 221system.physmem.avgMemAccLat 22673.84 # Average memory access latency 222system.physmem.avgRdBW 3.28 # Average achieved read bandwidth in MB/s 223system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 224system.physmem.avgConsumedRdBW 3.28 # Average consumed read bandwidth in MB/s 225system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 226system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s | 155system.physmem.bytesPerActivate::samples 717 # Bytes accessed per row activation 156system.physmem.bytesPerActivate::mean 334.192469 # Bytes accessed per row activation 157system.physmem.bytesPerActivate::gmean 180.652659 # Bytes accessed per row activation 158system.physmem.bytesPerActivate::stdev 576.534776 # Bytes accessed per row activation 159system.physmem.bytesPerActivate::64-65 257 35.84% 35.84% # Bytes accessed per row activation 160system.physmem.bytesPerActivate::128-129 120 16.74% 52.58% # Bytes accessed per row activation 161system.physmem.bytesPerActivate::192-193 71 9.90% 62.48% # Bytes accessed per row activation 162system.physmem.bytesPerActivate::256-257 49 6.83% 69.32% # Bytes accessed per row activation 163system.physmem.bytesPerActivate::320-321 19 2.65% 71.97% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::384-385 26 3.63% 75.59% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::448-449 20 2.79% 78.38% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::512-513 17 2.37% 80.75% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::576-577 17 2.37% 83.12% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::640-641 40 5.58% 88.70% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::704-705 17 2.37% 91.07% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::768-769 6 0.84% 91.91% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::832-833 6 0.84% 92.75% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::896-897 8 1.12% 93.86% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::960-961 6 0.84% 94.70% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::1024-1025 5 0.70% 95.40% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::1088-1089 4 0.56% 95.96% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::1152-1153 1 0.14% 96.09% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::1216-1217 2 0.28% 96.37% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::1280-1281 2 0.28% 96.65% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::1344-1345 2 0.28% 96.93% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::1408-1409 2 0.28% 97.21% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::1472-1473 1 0.14% 97.35% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::1536-1537 1 0.14% 97.49% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1600-1601 1 0.14% 97.63% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1664-1665 1 0.14% 97.77% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1728-1729 1 0.14% 97.91% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1792-1793 2 0.28% 98.19% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1856-1857 1 0.14% 98.33% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::1984-1985 2 0.28% 98.61% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::2176-2177 1 0.14% 98.74% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::2688-2689 1 0.14% 98.88% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::2816-2817 1 0.14% 99.02% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::3008-3009 1 0.14% 99.16% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::3200-3201 1 0.14% 99.30% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::3392-3393 1 0.14% 99.44% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::3648-3649 1 0.14% 99.58% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::3712-3713 1 0.14% 99.72% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::6656-6657 1 0.14% 99.86% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::8192-8193 1 0.14% 100.00% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::total 717 # Bytes accessed per row activation 200system.physmem.totQLat 25205500 # Total ticks spent queuing 201system.physmem.totMemAccLat 100715500 # Total ticks spent from burst creation until serviced by the DRAM 202system.physmem.totBusLat 18970000 # Total ticks spent in databus transfers 203system.physmem.totBankLat 56540000 # Total ticks spent accessing banks 204system.physmem.avgQLat 6643.52 # Average queueing delay per DRAM burst 205system.physmem.avgBankLat 14902.48 # Average bank access latency per DRAM burst 206system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 207system.physmem.avgMemAccLat 26545.99 # Average memory access latency per DRAM burst 208system.physmem.avgRdBW 3.27 # Average DRAM read bandwidth in MiByte/s 209system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 210system.physmem.avgRdBWSys 3.27 # Average system read bandwidth in MiByte/s 211system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 212system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 227system.physmem.busUtil 0.03 # Data bus utilization in percentage | 213system.physmem.busUtil 0.03 # Data bus utilization in percentage |
| 228system.physmem.avgRdQLen 0.00 # Average read queue length over time 229system.physmem.avgWrQLen 0.00 # Average write queue length over time 230system.physmem.readRowHits 3412 # Number of row buffer hits during reads | 214system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 215system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 216system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing 217system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 218system.physmem.readRowHits 3077 # Number of row buffer hits during reads |
| 231system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 219system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 232system.physmem.readRowHitRate 89.77 # Row buffer hit rate for reads | 220system.physmem.readRowHitRate 81.10 # Row buffer hit rate for reads |
| 233system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 221system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 234system.physmem.avgGap 19521443.30 # Average gap between requests 235system.membus.throughput 3277583 # Throughput (bytes/s) 236system.membus.trans_dist::ReadReq 2726 # Transaction distribution 237system.membus.trans_dist::ReadResp 2725 # Transaction distribution 238system.membus.trans_dist::UpgradeReq 2 # Transaction distribution 239system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 240system.membus.trans_dist::ReadExReq 1075 # Transaction distribution 241system.membus.trans_dist::ReadExResp 1075 # Transaction distribution 242system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7605 # Packet count per connected master and slave (bytes) 243system.membus.pkt_count::total 7605 # Packet count per connected master and slave (bytes) 244system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 243200 # Cumulative packet size per connected master and slave (bytes) 245system.membus.tot_pkt_size::total 243200 # Cumulative packet size per connected master and slave (bytes) 246system.membus.data_through_bus 243200 # Total data (bytes) | 222system.physmem.avgGap 19562448.60 # Average gap between requests 223system.physmem.pageHitRate 81.10 # Row buffer hit rate, read and write combined 224system.physmem.prechargeAllPercent 0.24 # Percentage of time for which DRAM has all the banks in precharge state 225system.membus.throughput 3270711 # Throughput (bytes/s) 226system.membus.trans_dist::ReadReq 2723 # Transaction distribution 227system.membus.trans_dist::ReadResp 2722 # Transaction distribution 228system.membus.trans_dist::ReadExReq 1071 # Transaction distribution 229system.membus.trans_dist::ReadExResp 1071 # Transaction distribution 230system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7587 # Packet count per connected master and slave (bytes) 231system.membus.pkt_count::total 7587 # Packet count per connected master and slave (bytes) 232system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 242752 # Cumulative packet size per connected master and slave (bytes) 233system.membus.tot_pkt_size::total 242752 # Cumulative packet size per connected master and slave (bytes) 234system.membus.data_through_bus 242752 # Total data (bytes) |
| 247system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 235system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 248system.membus.reqLayer0.occupancy 4684500 # Layer occupancy (ticks) | 236system.membus.reqLayer0.occupancy 4683500 # Layer occupancy (ticks) |
| 249system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 237system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 250system.membus.respLayer1.occupancy 35707998 # Layer occupancy (ticks) | 238system.membus.respLayer1.occupancy 35533250 # Layer occupancy (ticks) |
| 251system.membus.respLayer1.utilization 0.0 # Layer utilization (%) | 239system.membus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 252system.cpu.branchPred.lookups 94803777 # Number of BP lookups 253system.cpu.branchPred.condPredicted 74793629 # Number of conditional branches predicted 254system.cpu.branchPred.condIncorrect 6279390 # Number of conditional branches incorrect 255system.cpu.branchPred.BTBLookups 44652033 # Number of BTB lookups 256system.cpu.branchPred.BTBHits 43049215 # Number of BTB hits | 240system.cpu.branchPred.lookups 94784279 # Number of BP lookups 241system.cpu.branchPred.condPredicted 74784012 # Number of conditional branches predicted 242system.cpu.branchPred.condIncorrect 6281562 # Number of conditional branches incorrect 243system.cpu.branchPred.BTBLookups 44678427 # Number of BTB lookups 244system.cpu.branchPred.BTBHits 43050018 # Number of BTB hits |
| 257system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 245system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 258system.cpu.branchPred.BTBHitPct 96.410425 # BTB Hit Percentage 259system.cpu.branchPred.usedRAS 4355984 # Number of times the RAS was used to get a target. 260system.cpu.branchPred.RASInCorrect 88442 # Number of incorrect RAS predictions. | 246system.cpu.branchPred.BTBHitPct 96.355268 # BTB Hit Percentage 247system.cpu.branchPred.usedRAS 4356637 # Number of times the RAS was used to get a target. 248system.cpu.branchPred.RASInCorrect 88400 # Number of incorrect RAS predictions. |
| 261system.cpu.dtb.inst_hits 0 # ITB inst hits 262system.cpu.dtb.inst_misses 0 # ITB inst misses 263system.cpu.dtb.read_hits 0 # DTB read hits 264system.cpu.dtb.read_misses 0 # DTB read misses 265system.cpu.dtb.write_hits 0 # DTB write hits 266system.cpu.dtb.write_misses 0 # DTB write misses 267system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 268system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 296system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 297system.cpu.itb.read_accesses 0 # DTB read accesses 298system.cpu.itb.write_accesses 0 # DTB write accesses 299system.cpu.itb.inst_accesses 0 # ITB inst accesses 300system.cpu.itb.hits 0 # DTB hits 301system.cpu.itb.misses 0 # DTB misses 302system.cpu.itb.accesses 0 # DTB accesses 303system.cpu.workload.num_syscalls 400 # Number of system calls | 249system.cpu.dtb.inst_hits 0 # ITB inst hits 250system.cpu.dtb.inst_misses 0 # ITB inst misses 251system.cpu.dtb.read_hits 0 # DTB read hits 252system.cpu.dtb.read_misses 0 # DTB read misses 253system.cpu.dtb.write_hits 0 # DTB write hits 254system.cpu.dtb.write_misses 0 # DTB write misses 255system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 256system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 284system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 285system.cpu.itb.read_accesses 0 # DTB read accesses 286system.cpu.itb.write_accesses 0 # DTB write accesses 287system.cpu.itb.inst_accesses 0 # ITB inst accesses 288system.cpu.itb.hits 0 # DTB hits 289system.cpu.itb.misses 0 # DTB misses 290system.cpu.itb.accesses 0 # DTB accesses 291system.cpu.workload.num_syscalls 400 # Number of system calls |
| 304system.cpu.numCycles 148402050 # number of cpu cycles simulated | 292system.cpu.numCycles 148439898 # number of cpu cycles simulated |
| 305system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 306system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 293system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 294system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 307system.cpu.fetch.icacheStallCycles 39645282 # Number of cycles fetch is stalled on an Icache miss 308system.cpu.fetch.Insts 380210735 # Number of instructions fetch has processed 309system.cpu.fetch.Branches 94803777 # Number of branches that fetch encountered 310system.cpu.fetch.predictedBranches 47405199 # Number of branches that fetch has predicted taken 311system.cpu.fetch.Cycles 80366135 # Number of cycles fetch has run and was not squashing or blocked 312system.cpu.fetch.SquashCycles 27283939 # Number of cycles fetch has spent squashing 313system.cpu.fetch.BlockedCycles 7211893 # Number of cycles fetch has spent blocked 314system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 315system.cpu.fetch.PendingTrapStallCycles 5835 # Number of stall cycles due to pending traps | 295system.cpu.fetch.icacheStallCycles 39656913 # Number of cycles fetch is stalled on an Icache miss 296system.cpu.fetch.Insts 380179952 # Number of instructions fetch has processed 297system.cpu.fetch.Branches 94784279 # Number of branches that fetch encountered 298system.cpu.fetch.predictedBranches 47406655 # Number of branches that fetch has predicted taken 299system.cpu.fetch.Cycles 80370667 # Number of cycles fetch has run and was not squashing or blocked 300system.cpu.fetch.SquashCycles 27283129 # Number of cycles fetch has spent squashing 301system.cpu.fetch.BlockedCycles 7220970 # Number of cycles fetch has spent blocked 302system.cpu.fetch.MiscStallCycles 44 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 303system.cpu.fetch.PendingTrapStallCycles 6188 # Number of stall cycles due to pending traps |
| 316system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions | 304system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions |
| 317system.cpu.fetch.IcacheWaitRetryStallCycles 74 # Number of stall cycles due to full MSHR 318system.cpu.fetch.CacheLines 36839707 # Number of cache lines fetched 319system.cpu.fetch.IcacheSquashes 1829204 # Number of outstanding Icache misses that were squashed 320system.cpu.fetch.rateDist::samples 148218142 # Number of instructions fetched each cycle (Total) 321system.cpu.fetch.rateDist::mean 2.802317 # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::stdev 3.153165 # Number of instructions fetched each cycle (Total) | 305system.cpu.fetch.IcacheWaitRetryStallCycles 50 # Number of stall cycles due to full MSHR 306system.cpu.fetch.CacheLines 36850892 # Number of cache lines fetched 307system.cpu.fetch.IcacheSquashes 1831983 # Number of outstanding Icache misses that were squashed 308system.cpu.fetch.rateDist::samples 148240575 # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::mean 2.801601 # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::stdev 3.152871 # Number of instructions fetched each cycle (Total) |
| 323system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 311system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 324system.cpu.fetch.rateDist::0 68020669 45.89% 45.89% # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::1 5263809 3.55% 49.44% # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.rateDist::2 10529342 7.10% 56.55% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::3 10284383 6.94% 63.49% # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::4 8663442 5.85% 69.33% # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::5 6544357 4.42% 73.75% # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::6 6237651 4.21% 77.96% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::7 8018779 5.41% 83.37% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::8 24655710 16.63% 100.00% # Number of instructions fetched each cycle (Total) | 312system.cpu.fetch.rateDist::0 68038754 45.90% 45.90% # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::1 5265463 3.55% 49.45% # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::2 10540667 7.11% 56.56% # Number of instructions fetched each cycle (Total) 315system.cpu.fetch.rateDist::3 10285704 6.94% 63.50% # Number of instructions fetched each cycle (Total) 316system.cpu.fetch.rateDist::4 8660470 5.84% 69.34% # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.rateDist::5 6545128 4.42% 73.76% # Number of instructions fetched each cycle (Total) 318system.cpu.fetch.rateDist::6 6246382 4.21% 77.97% # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.rateDist::7 8002829 5.40% 83.37% # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.rateDist::8 24655178 16.63% 100.00% # Number of instructions fetched each cycle (Total) |
| 333system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 321system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 336system.cpu.fetch.rateDist::total 148218142 # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.branchRate 0.638831 # Number of branch fetches per cycle 338system.cpu.fetch.rate 2.562032 # Number of inst fetches per cycle 339system.cpu.decode.IdleCycles 45496346 # Number of cycles decode is idle 340system.cpu.decode.BlockedCycles 5881053 # Number of cycles decode is blocked 341system.cpu.decode.RunCycles 74801402 # Number of cycles decode is running 342system.cpu.decode.UnblockCycles 1203851 # Number of cycles decode is unblocking 343system.cpu.decode.SquashCycles 20835490 # Number of cycles decode is squashing 344system.cpu.decode.BranchResolved 14335605 # Number of times decode resolved a branch 345system.cpu.decode.BranchMispred 164633 # Number of times decode detected a branch misprediction 346system.cpu.decode.DecodedInsts 392823460 # Number of instructions handled by decode 347system.cpu.decode.SquashedInsts 736203 # Number of squashed instructions handled by decode 348system.cpu.rename.SquashCycles 20835490 # Number of cycles rename is squashing 349system.cpu.rename.IdleCycles 50883815 # Number of cycles rename is idle 350system.cpu.rename.BlockCycles 724795 # Number of cycles rename is blocking 351system.cpu.rename.serializeStallCycles 600466 # count of cycles rename stalled for serializing inst 352system.cpu.rename.RunCycles 70555670 # Number of cycles rename is running 353system.cpu.rename.UnblockCycles 4617906 # Number of cycles rename is unblocking 354system.cpu.rename.RenamedInsts 371356593 # Number of instructions processed by rename 355system.cpu.rename.ROBFullEvents 28 # Number of times rename has blocked due to ROB full 356system.cpu.rename.IQFullEvents 342994 # Number of times rename has blocked due to IQ full 357system.cpu.rename.LSQFullEvents 3662384 # Number of times rename has blocked due to LSQ full 358system.cpu.rename.FullRegisterEvents 29 # Number of times there has been no free registers 359system.cpu.rename.RenamedOperands 631760398 # Number of destination operands rename has renamed 360system.cpu.rename.RenameLookups 1581883462 # Number of register rename lookups that rename has made 361system.cpu.rename.int_rename_lookups 1507069248 # Number of integer rename lookups 362system.cpu.rename.fp_rename_lookups 3196133 # Number of floating rename lookups | 324system.cpu.fetch.rateDist::total 148240575 # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.branchRate 0.638536 # Number of branch fetches per cycle 326system.cpu.fetch.rate 2.561171 # Number of inst fetches per cycle 327system.cpu.decode.IdleCycles 45513789 # Number of cycles decode is idle 328system.cpu.decode.BlockedCycles 5886753 # Number of cycles decode is blocked 329system.cpu.decode.RunCycles 74804125 # Number of cycles decode is running 330system.cpu.decode.UnblockCycles 1203493 # Number of cycles decode is unblocking 331system.cpu.decode.SquashCycles 20832415 # Number of cycles decode is squashing 332system.cpu.decode.BranchResolved 14327913 # Number of times decode resolved a branch 333system.cpu.decode.BranchMispred 164349 # Number of times decode detected a branch misprediction 334system.cpu.decode.DecodedInsts 392779898 # Number of instructions handled by decode 335system.cpu.decode.SquashedInsts 733794 # Number of squashed instructions handled by decode 336system.cpu.rename.SquashCycles 20832415 # Number of cycles rename is squashing 337system.cpu.rename.IdleCycles 50900742 # Number of cycles rename is idle 338system.cpu.rename.BlockCycles 730699 # Number of cycles rename is blocking 339system.cpu.rename.serializeStallCycles 603190 # count of cycles rename stalled for serializing inst 340system.cpu.rename.RunCycles 70558310 # Number of cycles rename is running 341system.cpu.rename.UnblockCycles 4615219 # Number of cycles rename is unblocking 342system.cpu.rename.RenamedInsts 371308094 # Number of instructions processed by rename 343system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full 344system.cpu.rename.IQFullEvents 339277 # Number of times rename has blocked due to IQ full 345system.cpu.rename.LSQFullEvents 3661219 # Number of times rename has blocked due to LSQ full 346system.cpu.rename.FullRegisterEvents 233 # Number of times there has been no free registers 347system.cpu.rename.RenamedOperands 631703486 # Number of destination operands rename has renamed 348system.cpu.rename.RenameLookups 1581699955 # Number of register rename lookups that rename has made 349system.cpu.rename.int_rename_lookups 1506871299 # Number of integer rename lookups 350system.cpu.rename.fp_rename_lookups 3203425 # Number of floating rename lookups |
| 363system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed | 351system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed |
| 364system.cpu.rename.UndoneMaps 333716259 # Number of HB maps that are undone due to squashing 365system.cpu.rename.serializingInsts 25188 # count of serializing insts renamed 366system.cpu.rename.tempSerializingInsts 25185 # count of temporary serializing insts renamed 367system.cpu.rename.skidInsts 13032916 # count of insts added to the skid buffer 368system.cpu.memDep0.insertedLoads 43019038 # Number of loads inserted to the mem dependence unit. 369system.cpu.memDep0.insertedStores 16425001 # Number of stores inserted to the mem dependence unit. 370system.cpu.memDep0.conflictingLoads 5693552 # Number of conflicting loads. 371system.cpu.memDep0.conflictingStores 3686945 # Number of conflicting stores. 372system.cpu.iq.iqInstsAdded 329243417 # Number of instructions added to the IQ (excludes non-spec) 373system.cpu.iq.iqNonSpecInstsAdded 47203 # Number of non-speculative instructions added to the IQ 374system.cpu.iq.iqInstsIssued 249464214 # Number of instructions issued 375system.cpu.iq.iqSquashedInstsIssued 795417 # Number of squashed instructions issued 376system.cpu.iq.iqSquashedInstsExamined 139561180 # Number of squashed instructions iterated over during squash; mainly for profiling 377system.cpu.iq.iqSquashedOperandsExamined 362246737 # Number of squashed operands that are examined and possibly removed from graph 378system.cpu.iq.iqSquashedNonSpecRemoved 1987 # Number of squashed non-spec instructions that were removed 379system.cpu.iq.issued_per_cycle::samples 148218142 # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::mean 1.683088 # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::stdev 1.761802 # Number of insts issued each cycle | 352system.cpu.rename.UndoneMaps 333659347 # Number of HB maps that are undone due to squashing 353system.cpu.rename.serializingInsts 25072 # count of serializing insts renamed 354system.cpu.rename.tempSerializingInsts 25068 # count of temporary serializing insts renamed 355system.cpu.rename.skidInsts 13010245 # count of insts added to the skid buffer 356system.cpu.memDep0.insertedLoads 43012685 # Number of loads inserted to the mem dependence unit. 357system.cpu.memDep0.insertedStores 16416405 # Number of stores inserted to the mem dependence unit. 358system.cpu.memDep0.conflictingLoads 5733542 # Number of conflicting loads. 359system.cpu.memDep0.conflictingStores 3666500 # Number of conflicting stores. 360system.cpu.iq.iqInstsAdded 329190158 # Number of instructions added to the IQ (excludes non-spec) 361system.cpu.iq.iqNonSpecInstsAdded 47154 # Number of non-speculative instructions added to the IQ 362system.cpu.iq.iqInstsIssued 249456619 # Number of instructions issued 363system.cpu.iq.iqSquashedInstsIssued 789371 # Number of squashed instructions issued 364system.cpu.iq.iqSquashedInstsExamined 139503403 # Number of squashed instructions iterated over during squash; mainly for profiling 365system.cpu.iq.iqSquashedOperandsExamined 362002811 # Number of squashed operands that are examined and possibly removed from graph 366system.cpu.iq.iqSquashedNonSpecRemoved 1938 # Number of squashed non-spec instructions that were removed 367system.cpu.iq.issued_per_cycle::samples 148240575 # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::mean 1.682782 # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::stdev 1.761427 # Number of insts issued each cycle |
| 382system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 370system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 383system.cpu.iq.issued_per_cycle::0 56048230 37.81% 37.81% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::1 22642926 15.28% 53.09% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::2 24814212 16.74% 69.83% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::3 20312337 13.70% 83.54% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::4 12552656 8.47% 92.01% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::5 6518158 4.40% 96.40% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::6 4033272 2.72% 99.13% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::7 1116001 0.75% 99.88% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::8 180350 0.12% 100.00% # Number of insts issued each cycle | 371system.cpu.iq.issued_per_cycle::0 56059831 37.82% 37.82% # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::1 22638796 15.27% 53.09% # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::2 24824163 16.75% 69.83% # Number of insts issued each cycle 374system.cpu.iq.issued_per_cycle::3 20343400 13.72% 83.56% # Number of insts issued each cycle 375system.cpu.iq.issued_per_cycle::4 12534795 8.46% 92.01% # Number of insts issued each cycle 376system.cpu.iq.issued_per_cycle::5 6516114 4.40% 96.41% # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::6 4026097 2.72% 99.12% # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::7 1116067 0.75% 99.88% # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::8 181312 0.12% 100.00% # Number of insts issued each cycle |
| 392system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 380system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 395system.cpu.iq.issued_per_cycle::total 148218142 # Number of insts issued each cycle | 383system.cpu.iq.issued_per_cycle::total 148240575 # Number of insts issued each cycle |
| 396system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 384system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 397system.cpu.iq.fu_full::IntAlu 965237 38.47% 38.47% # attempts to use FU when none available 398system.cpu.iq.fu_full::IntMult 5595 0.22% 38.69% # attempts to use FU when none available 399system.cpu.iq.fu_full::IntDiv 0 0.00% 38.69% # attempts to use FU when none available 400system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.69% # attempts to use FU when none available 401system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.69% # attempts to use FU when none available 402system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.69% # attempts to use FU when none available 403system.cpu.iq.fu_full::FloatMult 0 0.00% 38.69% # attempts to use FU when none available 404system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.69% # attempts to use FU when none available 405system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.69% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.69% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.69% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.69% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.69% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.69% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.69% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdMult 0 0.00% 38.69% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.69% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdShift 0 0.00% 38.69% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.69% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.69% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatAdd 98 0.00% 38.70% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.70% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.70% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.70% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.70% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdFloatMisc 50 0.00% 38.70% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.70% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.70% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.70% # attempts to use FU when none available 426system.cpu.iq.fu_full::MemRead 1168121 46.56% 85.25% # attempts to use FU when none available 427system.cpu.iq.fu_full::MemWrite 370007 14.75% 100.00% # attempts to use FU when none available | 385system.cpu.iq.fu_full::IntAlu 965215 38.57% 38.57% # attempts to use FU when none available 386system.cpu.iq.fu_full::IntMult 5593 0.22% 38.79% # attempts to use FU when none available 387system.cpu.iq.fu_full::IntDiv 0 0.00% 38.79% # attempts to use FU when none available 388system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.79% # attempts to use FU when none available 389system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.79% # attempts to use FU when none available 390system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.79% # attempts to use FU when none available 391system.cpu.iq.fu_full::FloatMult 0 0.00% 38.79% # attempts to use FU when none available 392system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.79% # attempts to use FU when none available 393system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.79% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.79% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.79% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.79% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.79% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.79% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.79% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdMult 0 0.00% 38.79% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.79% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdShift 0 0.00% 38.79% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.79% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.79% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdFloatAdd 101 0.00% 38.80% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.80% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.80% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.80% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.80% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.80% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.80% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.80% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.80% # attempts to use FU when none available 414system.cpu.iq.fu_full::MemRead 1158967 46.31% 85.11% # attempts to use FU when none available 415system.cpu.iq.fu_full::MemWrite 372730 14.89% 100.00% # attempts to use FU when none available |
| 428system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 429system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 430system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 416system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 417system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 418system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 431system.cpu.iq.FU_type_0::IntAlu 194903493 78.13% 78.13% # Type of FU issued 432system.cpu.iq.FU_type_0::IntMult 979289 0.39% 78.52% # Type of FU issued | 419system.cpu.iq.FU_type_0::IntAlu 194899965 78.13% 78.13% # Type of FU issued 420system.cpu.iq.FU_type_0::IntMult 979613 0.39% 78.52% # Type of FU issued |
| 433system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued 434system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued 435system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued 436system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.52% # Type of FU issued 437system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.52% # Type of FU issued 438system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.52% # Type of FU issued 439system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.52% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.52% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.52% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.52% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.52% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.52% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.52% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.52% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued | 421system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued 422system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued 423system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued 424system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.52% # Type of FU issued 425system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.52% # Type of FU issued 426system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.52% # Type of FU issued 427system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.52% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.52% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.52% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.52% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.52% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.52% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.52% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.52% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued |
| 451system.cpu.iq.FU_type_0::SimdFloatAdd 33083 0.01% 78.53% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.53% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatCmp 164442 0.07% 78.60% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatCvt 254821 0.10% 78.70% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatDiv 76413 0.03% 78.73% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdFloatMisc 465720 0.19% 78.92% # Type of FU issued | 439system.cpu.iq.FU_type_0::SimdFloatAdd 33082 0.01% 78.54% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.54% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdFloatCmp 164367 0.07% 78.60% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdFloatCvt 255141 0.10% 78.70% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdFloatDiv 76420 0.03% 78.73% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdFloatMisc 466123 0.19% 78.92% # Type of FU issued |
| 457system.cpu.iq.FU_type_0::SimdFloatMult 206380 0.08% 79.00% # Type of FU issued | 445system.cpu.iq.FU_type_0::SimdFloatMult 206380 0.08% 79.00% # Type of FU issued |
| 458system.cpu.iq.FU_type_0::SimdFloatMultAcc 71858 0.03% 79.03% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 79.03% # Type of FU issued 460system.cpu.iq.FU_type_0::MemRead 38359883 15.38% 94.41% # Type of FU issued 461system.cpu.iq.FU_type_0::MemWrite 13948512 5.59% 100.00% # Type of FU issued | 446system.cpu.iq.FU_type_0::SimdFloatMultAcc 71866 0.03% 79.03% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued 448system.cpu.iq.FU_type_0::MemRead 38355278 15.38% 94.41% # Type of FU issued 449system.cpu.iq.FU_type_0::MemWrite 13948063 5.59% 100.00% # Type of FU issued |
| 462system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 463system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 450system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 451system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 464system.cpu.iq.FU_type_0::total 249464214 # Type of FU issued 465system.cpu.iq.rate 1.681002 # Inst issue rate 466system.cpu.iq.fu_busy_cnt 2509108 # FU busy when requested 467system.cpu.iq.fu_busy_rate 0.010058 # FU busy rate (busy events/executed inst) 468system.cpu.iq.int_inst_queue_reads 646714008 # Number of integer instruction queue reads 469system.cpu.iq.int_inst_queue_writes 466681926 # Number of integer instruction queue writes 470system.cpu.iq.int_inst_queue_wakeup_accesses 237887502 # Number of integer instruction queue wakeup accesses 471system.cpu.iq.fp_inst_queue_reads 3737087 # Number of floating instruction queue reads 472system.cpu.iq.fp_inst_queue_writes 2188015 # Number of floating instruction queue writes 473system.cpu.iq.fp_inst_queue_wakeup_accesses 1841410 # Number of floating instruction queue wakeup accesses 474system.cpu.iq.int_alu_accesses 250098110 # Number of integer alu accesses 475system.cpu.iq.fp_alu_accesses 1875212 # Number of floating point alu accesses 476system.cpu.iew.lsq.thread0.forwLoads 2005238 # Number of loads that had data forwarded from stores | 452system.cpu.iq.FU_type_0::total 249456619 # Type of FU issued 453system.cpu.iq.rate 1.680523 # Inst issue rate 454system.cpu.iq.fu_busy_cnt 2502654 # FU busy when requested 455system.cpu.iq.fu_busy_rate 0.010032 # FU busy rate (busy events/executed inst) 456system.cpu.iq.int_inst_queue_reads 646705831 # Number of integer instruction queue reads 457system.cpu.iq.int_inst_queue_writes 466563436 # Number of integer instruction queue writes 458system.cpu.iq.int_inst_queue_wakeup_accesses 237885445 # Number of integer instruction queue wakeup accesses 459system.cpu.iq.fp_inst_queue_reads 3740007 # Number of floating instruction queue reads 460system.cpu.iq.fp_inst_queue_writes 2195697 # Number of floating instruction queue writes 461system.cpu.iq.fp_inst_queue_wakeup_accesses 1842613 # Number of floating instruction queue wakeup accesses 462system.cpu.iq.int_alu_accesses 250082854 # Number of integer alu accesses 463system.cpu.iq.fp_alu_accesses 1876419 # Number of floating point alu accesses 464system.cpu.iew.lsq.thread0.forwLoads 2013198 # Number of loads that had data forwarded from stores |
| 477system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 465system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 478system.cpu.iew.lsq.thread0.squashedLoads 13169554 # Number of loads squashed 479system.cpu.iew.lsq.thread0.ignoredResponses 11470 # Number of memory responses ignored because the instruction is squashed 480system.cpu.iew.lsq.thread0.memOrderViolation 18663 # Number of memory ordering violations 481system.cpu.iew.lsq.thread0.squashedStores 3780367 # Number of stores squashed | 466system.cpu.iew.lsq.thread0.squashedLoads 13163201 # Number of loads squashed 467system.cpu.iew.lsq.thread0.ignoredResponses 11604 # Number of memory responses ignored because the instruction is squashed 468system.cpu.iew.lsq.thread0.memOrderViolation 18881 # Number of memory ordering violations 469system.cpu.iew.lsq.thread0.squashedStores 3771771 # Number of stores squashed |
| 482system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 483system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 470system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 471system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 484system.cpu.iew.lsq.thread0.rescheduledLoads 11 # Number of loads that were rescheduled 485system.cpu.iew.lsq.thread0.cacheBlocked 113 # Number of times an access to memory failed due to the cache being blocked | 472system.cpu.iew.lsq.thread0.rescheduledLoads 18 # Number of loads that were rescheduled 473system.cpu.iew.lsq.thread0.cacheBlocked 107 # Number of times an access to memory failed due to the cache being blocked |
| 486system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 474system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 487system.cpu.iew.iewSquashCycles 20835490 # Number of cycles IEW is squashing 488system.cpu.iew.iewBlockCycles 18710 # Number of cycles IEW is blocking 489system.cpu.iew.iewUnblockCycles 879 # Number of cycles IEW is unblocking 490system.cpu.iew.iewDispatchedInsts 329307607 # Number of instructions dispatched to IQ 491system.cpu.iew.iewDispSquashedInsts 785363 # Number of squashed instructions skipped by dispatch 492system.cpu.iew.iewDispLoadInsts 43019038 # Number of dispatched load instructions 493system.cpu.iew.iewDispStoreInsts 16425001 # Number of dispatched store instructions 494system.cpu.iew.iewDispNonSpecInsts 24795 # Number of dispatched non-speculative instructions 495system.cpu.iew.iewIQFullEvents 182 # Number of times the IQ has become full, causing a stall 496system.cpu.iew.iewLSQFullEvents 275 # Number of times the LSQ has become full, causing a stall 497system.cpu.iew.memOrderViolationEvents 18663 # Number of memory order violations 498system.cpu.iew.predictedTakenIncorrect 3889158 # Number of branches that were predicted taken incorrectly 499system.cpu.iew.predictedNotTakenIncorrect 3759638 # Number of branches that were predicted not taken incorrectly 500system.cpu.iew.branchMispredicts 7648796 # Number of branch mispredicts detected at execute 501system.cpu.iew.iewExecutedInsts 242968769 # Number of executed instructions 502system.cpu.iew.iewExecLoadInsts 36856935 # Number of load instructions executed 503system.cpu.iew.iewExecSquashedInsts 6495445 # Number of squashed instructions skipped in execute | 475system.cpu.iew.iewSquashCycles 20832415 # Number of cycles IEW is squashing 476system.cpu.iew.iewBlockCycles 18550 # Number of cycles IEW is blocking 477system.cpu.iew.iewUnblockCycles 893 # Number of cycles IEW is unblocking 478system.cpu.iew.iewDispatchedInsts 329254508 # Number of instructions dispatched to IQ 479system.cpu.iew.iewDispSquashedInsts 785294 # Number of squashed instructions skipped by dispatch 480system.cpu.iew.iewDispLoadInsts 43012685 # Number of dispatched load instructions 481system.cpu.iew.iewDispStoreInsts 16416405 # Number of dispatched store instructions 482system.cpu.iew.iewDispNonSpecInsts 24746 # Number of dispatched non-speculative instructions 483system.cpu.iew.iewIQFullEvents 188 # Number of times the IQ has become full, causing a stall 484system.cpu.iew.iewLSQFullEvents 276 # Number of times the LSQ has become full, causing a stall 485system.cpu.iew.memOrderViolationEvents 18881 # Number of memory order violations 486system.cpu.iew.predictedTakenIncorrect 3889958 # Number of branches that were predicted taken incorrectly 487system.cpu.iew.predictedNotTakenIncorrect 3760086 # Number of branches that were predicted not taken incorrectly 488system.cpu.iew.branchMispredicts 7650044 # Number of branch mispredicts detected at execute 489system.cpu.iew.iewExecutedInsts 242960519 # Number of executed instructions 490system.cpu.iew.iewExecLoadInsts 36851938 # Number of load instructions executed 491system.cpu.iew.iewExecSquashedInsts 6496100 # Number of squashed instructions skipped in execute |
| 504system.cpu.iew.exec_swp 0 # number of swp insts executed | 492system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 505system.cpu.iew.exec_nop 16987 # number of nop insts executed 506system.cpu.iew.exec_refs 50502724 # number of memory reference insts executed 507system.cpu.iew.exec_branches 53433142 # Number of branches executed 508system.cpu.iew.exec_stores 13645789 # Number of stores executed 509system.cpu.iew.exec_rate 1.637233 # Inst execution rate 510system.cpu.iew.wb_sent 240789077 # cumulative count of insts sent to commit 511system.cpu.iew.wb_count 239728912 # cumulative count of insts written-back 512system.cpu.iew.wb_producers 148477198 # num instructions producing a value 513system.cpu.iew.wb_consumers 267296630 # num instructions consuming a value | 493system.cpu.iew.exec_nop 17196 # number of nop insts executed 494system.cpu.iew.exec_refs 50500394 # number of memory reference insts executed 495system.cpu.iew.exec_branches 53426072 # Number of branches executed 496system.cpu.iew.exec_stores 13648456 # Number of stores executed 497system.cpu.iew.exec_rate 1.636760 # Inst execution rate 498system.cpu.iew.wb_sent 240785663 # cumulative count of insts sent to commit 499system.cpu.iew.wb_count 239728058 # cumulative count of insts written-back 500system.cpu.iew.wb_producers 148474079 # num instructions producing a value 501system.cpu.iew.wb_consumers 267261472 # num instructions consuming a value |
| 514system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 502system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 515system.cpu.iew.wb_rate 1.615402 # insts written-back per cycle 516system.cpu.iew.wb_fanout 0.555477 # average fanout of values written-back | 503system.cpu.iew.wb_rate 1.614984 # insts written-back per cycle 504system.cpu.iew.wb_fanout 0.555539 # average fanout of values written-back |
| 517system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 505system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 518system.cpu.commit.commitSquashedInsts 140636703 # The number of squashed insts skipped by commit | 506system.cpu.commit.commitSquashedInsts 140583620 # The number of squashed insts skipped by commit |
| 519system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards | 507system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards |
| 520system.cpu.commit.branchMispredicts 6125970 # The number of times a branch was mispredicted 521system.cpu.commit.committed_per_cycle::samples 127382652 # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::mean 1.481135 # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::stdev 2.185870 # Number of insts commited each cycle | 508system.cpu.commit.branchMispredicts 6128235 # The number of times a branch was mispredicted 509system.cpu.commit.committed_per_cycle::samples 127408160 # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::mean 1.480838 # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::stdev 2.185451 # Number of insts commited each cycle |
| 524system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 512system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 525system.cpu.commit.committed_per_cycle::0 57681624 45.28% 45.28% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::1 31696418 24.88% 70.17% # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::2 13781439 10.82% 80.98% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::3 7634613 5.99% 86.98% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::4 4380226 3.44% 90.42% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::5 1319827 1.04% 91.45% # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::6 1706186 1.34% 92.79% # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::7 1307951 1.03% 93.82% # Number of insts commited each cycle 533system.cpu.commit.committed_per_cycle::8 7874368 6.18% 100.00% # Number of insts commited each cycle | 513system.cpu.commit.committed_per_cycle::0 57701826 45.29% 45.29% # Number of insts commited each cycle 514system.cpu.commit.committed_per_cycle::1 31696936 24.88% 70.17% # Number of insts commited each cycle 515system.cpu.commit.committed_per_cycle::2 13777779 10.81% 80.98% # Number of insts commited each cycle 516system.cpu.commit.committed_per_cycle::3 7640619 6.00% 86.98% # Number of insts commited each cycle 517system.cpu.commit.committed_per_cycle::4 4387787 3.44% 90.42% # Number of insts commited each cycle 518system.cpu.commit.committed_per_cycle::5 1321958 1.04% 91.46% # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::6 1703212 1.34% 92.80% # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::7 1308014 1.03% 93.82% # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::8 7870029 6.18% 100.00% # Number of insts commited each cycle |
| 534system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 536system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 522system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 537system.cpu.commit.committed_per_cycle::total 127382652 # Number of insts commited each cycle | 525system.cpu.commit.committed_per_cycle::total 127408160 # Number of insts commited each cycle |
| 538system.cpu.commit.committedInsts 172317409 # Number of instructions committed 539system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed 540system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 541system.cpu.commit.refs 42494118 # Number of memory references committed 542system.cpu.commit.loads 29849484 # Number of loads committed 543system.cpu.commit.membars 22408 # Number of memory barriers committed 544system.cpu.commit.branches 40300311 # Number of branches committed 545system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. 546system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. 547system.cpu.commit.function_calls 1848934 # Number of function calls committed. | 526system.cpu.commit.committedInsts 172317409 # Number of instructions committed 527system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed 528system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 529system.cpu.commit.refs 42494118 # Number of memory references committed 530system.cpu.commit.loads 29849484 # Number of loads committed 531system.cpu.commit.membars 22408 # Number of memory barriers committed 532system.cpu.commit.branches 40300311 # Number of branches committed 533system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. 534system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. 535system.cpu.commit.function_calls 1848934 # Number of function calls committed. |
| 548system.cpu.commit.bw_lim_events 7874368 # number cycles where commit BW limit reached | 536system.cpu.commit.bw_lim_events 7870029 # number cycles where commit BW limit reached |
| 549system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 537system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 550system.cpu.rob.rob_reads 448810677 # The number of ROB reads 551system.cpu.rob.rob_writes 679560182 # The number of ROB writes 552system.cpu.timesIdled 2800 # Number of times that the entire CPU went into an idle state and unscheduled itself 553system.cpu.idleCycles 183908 # Total number of cycles that the CPU has spent unscheduled due to idling | 538system.cpu.rob.rob_reads 448787441 # The number of ROB reads 539system.cpu.rob.rob_writes 679451137 # The number of ROB writes 540system.cpu.timesIdled 2805 # Number of times that the entire CPU went into an idle state and unscheduled itself 541system.cpu.idleCycles 199323 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 554system.cpu.committedInsts 172303021 # Number of Instructions Simulated 555system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated 556system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated | 542system.cpu.committedInsts 172303021 # Number of Instructions Simulated 543system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated 544system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated |
| 557system.cpu.cpi 0.861285 # CPI: Cycles Per Instruction 558system.cpu.cpi_total 0.861285 # CPI: Total CPI of All Threads 559system.cpu.ipc 1.161056 # IPC: Instructions Per Cycle 560system.cpu.ipc_total 1.161056 # IPC: Total IPC of All Threads 561system.cpu.int_regfile_reads 1079439367 # number of integer regfile reads 562system.cpu.int_regfile_writes 384873719 # number of integer regfile writes 563system.cpu.fp_regfile_reads 2913212 # number of floating regfile reads 564system.cpu.fp_regfile_writes 2497494 # number of floating regfile writes 565system.cpu.misc_regfile_reads 54494427 # number of misc regfile reads | 545system.cpu.cpi 0.861505 # CPI: Cycles Per Instruction 546system.cpu.cpi_total 0.861505 # CPI: Total CPI of All Threads 547system.cpu.ipc 1.160759 # IPC: Instructions Per Cycle 548system.cpu.ipc_total 1.160759 # IPC: Total IPC of All Threads 549system.cpu.int_regfile_reads 1079417004 # number of integer regfile reads 550system.cpu.int_regfile_writes 384871783 # number of integer regfile writes 551system.cpu.fp_regfile_reads 2913086 # number of floating regfile reads 552system.cpu.fp_regfile_writes 2499105 # number of floating regfile writes 553system.cpu.misc_regfile_reads 54501288 # number of misc regfile reads |
| 566system.cpu.misc_regfile_writes 820036 # number of misc regfile writes | 554system.cpu.misc_regfile_writes 820036 # number of misc regfile writes |
| 567system.cpu.toL2Bus.throughput 5172543 # Throughput (bytes/s) 568system.cpu.toL2Bus.trans_dist::ReadReq 4897 # Transaction distribution 569system.cpu.toL2Bus.trans_dist::ReadResp 4896 # Transaction distribution | 555system.cpu.toL2Bus.throughput 5169500 # Throughput (bytes/s) 556system.cpu.toL2Bus.trans_dist::ReadReq 4899 # Transaction distribution 557system.cpu.toL2Bus.trans_dist::ReadResp 4898 # Transaction distribution |
| 570system.cpu.toL2Bus.trans_dist::Writeback 18 # Transaction distribution | 558system.cpu.toL2Bus.trans_dist::Writeback 18 # Transaction distribution |
| 571system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution 572system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution 573system.cpu.toL2Bus.trans_dist::ReadExReq 1083 # Transaction distribution 574system.cpu.toL2Bus.trans_dist::ReadExResp 1083 # Transaction distribution 575system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8247 # Packet count per connected master and slave (bytes) 576system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3732 # Packet count per connected master and slave (bytes) 577system.cpu.toL2Bus.pkt_count::total 11979 # Packet count per connected master and slave (bytes) 578system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 263808 # Cumulative packet size per connected master and slave (bytes) 579system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119872 # Cumulative packet size per connected master and slave (bytes) | 559system.cpu.toL2Bus.trans_dist::ReadExReq 1079 # Transaction distribution 560system.cpu.toL2Bus.trans_dist::ReadExResp 1079 # Transaction distribution 561system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8251 # Packet count per connected master and slave (bytes) 562system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3722 # Packet count per connected master and slave (bytes) 563system.cpu.toL2Bus.pkt_count::total 11973 # Packet count per connected master and slave (bytes) 564system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 264000 # Cumulative packet size per connected master and slave (bytes) 565system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119680 # Cumulative packet size per connected master and slave (bytes) |
| 580system.cpu.toL2Bus.tot_pkt_size::total 383680 # Cumulative packet size per connected master and slave (bytes) 581system.cpu.toL2Bus.data_through_bus 383680 # Total data (bytes) | 566system.cpu.toL2Bus.tot_pkt_size::total 383680 # Cumulative packet size per connected master and slave (bytes) 567system.cpu.toL2Bus.data_through_bus 383680 # Total data (bytes) |
| 582system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes) 583system.cpu.toL2Bus.reqLayer0.occupancy 3018000 # Layer occupancy (ticks) | 568system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 569system.cpu.toL2Bus.reqLayer0.occupancy 3016000 # Layer occupancy (ticks) |
| 584system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 570system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 585system.cpu.toL2Bus.respLayer0.occupancy 6609745 # Layer occupancy (ticks) | 571system.cpu.toL2Bus.respLayer0.occupancy 6552496 # Layer occupancy (ticks) |
| 586system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 572system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 587system.cpu.toL2Bus.respLayer1.occupancy 3106490 # Layer occupancy (ticks) | 573system.cpu.toL2Bus.respLayer1.occupancy 3047739 # Layer occupancy (ticks) |
| 588system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 574system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 589system.cpu.icache.tags.replacements 2391 # number of replacements 590system.cpu.icache.tags.tagsinuse 1346.456608 # Cycle average of tags in use 591system.cpu.icache.tags.total_refs 36834377 # Total number of references to valid blocks. 592system.cpu.icache.tags.sampled_refs 4122 # Sample count of references to valid blocks. 593system.cpu.icache.tags.avg_refs 8936.044881 # Average number of references to valid blocks. | 575system.cpu.icache.tags.replacements 2394 # number of replacements 576system.cpu.icache.tags.tagsinuse 1347.740549 # Cycle average of tags in use 577system.cpu.icache.tags.total_refs 36845555 # Total number of references to valid blocks. 578system.cpu.icache.tags.sampled_refs 4125 # Sample count of references to valid blocks. 579system.cpu.icache.tags.avg_refs 8932.255758 # Average number of references to valid blocks. |
| 594system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 580system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 595system.cpu.icache.tags.occ_blocks::cpu.inst 1346.456608 # Average occupied blocks per requestor 596system.cpu.icache.tags.occ_percent::cpu.inst 0.657450 # Average percentage of cache occupancy 597system.cpu.icache.tags.occ_percent::total 0.657450 # Average percentage of cache occupancy 598system.cpu.icache.ReadReq_hits::cpu.inst 36834377 # number of ReadReq hits 599system.cpu.icache.ReadReq_hits::total 36834377 # number of ReadReq hits 600system.cpu.icache.demand_hits::cpu.inst 36834377 # number of demand (read+write) hits 601system.cpu.icache.demand_hits::total 36834377 # number of demand (read+write) hits 602system.cpu.icache.overall_hits::cpu.inst 36834377 # number of overall hits 603system.cpu.icache.overall_hits::total 36834377 # number of overall hits 604system.cpu.icache.ReadReq_misses::cpu.inst 5330 # number of ReadReq misses 605system.cpu.icache.ReadReq_misses::total 5330 # number of ReadReq misses 606system.cpu.icache.demand_misses::cpu.inst 5330 # number of demand (read+write) misses 607system.cpu.icache.demand_misses::total 5330 # number of demand (read+write) misses 608system.cpu.icache.overall_misses::cpu.inst 5330 # number of overall misses 609system.cpu.icache.overall_misses::total 5330 # number of overall misses 610system.cpu.icache.ReadReq_miss_latency::cpu.inst 215954243 # number of ReadReq miss cycles 611system.cpu.icache.ReadReq_miss_latency::total 215954243 # number of ReadReq miss cycles 612system.cpu.icache.demand_miss_latency::cpu.inst 215954243 # number of demand (read+write) miss cycles 613system.cpu.icache.demand_miss_latency::total 215954243 # number of demand (read+write) miss cycles 614system.cpu.icache.overall_miss_latency::cpu.inst 215954243 # number of overall miss cycles 615system.cpu.icache.overall_miss_latency::total 215954243 # number of overall miss cycles 616system.cpu.icache.ReadReq_accesses::cpu.inst 36839707 # number of ReadReq accesses(hits+misses) 617system.cpu.icache.ReadReq_accesses::total 36839707 # number of ReadReq accesses(hits+misses) 618system.cpu.icache.demand_accesses::cpu.inst 36839707 # number of demand (read+write) accesses 619system.cpu.icache.demand_accesses::total 36839707 # number of demand (read+write) accesses 620system.cpu.icache.overall_accesses::cpu.inst 36839707 # number of overall (read+write) accesses 621system.cpu.icache.overall_accesses::total 36839707 # number of overall (read+write) accesses | 581system.cpu.icache.tags.occ_blocks::cpu.inst 1347.740549 # Average occupied blocks per requestor 582system.cpu.icache.tags.occ_percent::cpu.inst 0.658076 # Average percentage of cache occupancy 583system.cpu.icache.tags.occ_percent::total 0.658076 # Average percentage of cache occupancy 584system.cpu.icache.ReadReq_hits::cpu.inst 36845555 # number of ReadReq hits 585system.cpu.icache.ReadReq_hits::total 36845555 # number of ReadReq hits 586system.cpu.icache.demand_hits::cpu.inst 36845555 # number of demand (read+write) hits 587system.cpu.icache.demand_hits::total 36845555 # number of demand (read+write) hits 588system.cpu.icache.overall_hits::cpu.inst 36845555 # number of overall hits 589system.cpu.icache.overall_hits::total 36845555 # number of overall hits 590system.cpu.icache.ReadReq_misses::cpu.inst 5337 # number of ReadReq misses 591system.cpu.icache.ReadReq_misses::total 5337 # number of ReadReq misses 592system.cpu.icache.demand_misses::cpu.inst 5337 # number of demand (read+write) misses 593system.cpu.icache.demand_misses::total 5337 # number of demand (read+write) misses 594system.cpu.icache.overall_misses::cpu.inst 5337 # number of overall misses 595system.cpu.icache.overall_misses::total 5337 # number of overall misses 596system.cpu.icache.ReadReq_miss_latency::cpu.inst 225944745 # number of ReadReq miss cycles 597system.cpu.icache.ReadReq_miss_latency::total 225944745 # number of ReadReq miss cycles 598system.cpu.icache.demand_miss_latency::cpu.inst 225944745 # number of demand (read+write) miss cycles 599system.cpu.icache.demand_miss_latency::total 225944745 # number of demand (read+write) miss cycles 600system.cpu.icache.overall_miss_latency::cpu.inst 225944745 # number of overall miss cycles 601system.cpu.icache.overall_miss_latency::total 225944745 # number of overall miss cycles 602system.cpu.icache.ReadReq_accesses::cpu.inst 36850892 # number of ReadReq accesses(hits+misses) 603system.cpu.icache.ReadReq_accesses::total 36850892 # number of ReadReq accesses(hits+misses) 604system.cpu.icache.demand_accesses::cpu.inst 36850892 # number of demand (read+write) accesses 605system.cpu.icache.demand_accesses::total 36850892 # number of demand (read+write) accesses 606system.cpu.icache.overall_accesses::cpu.inst 36850892 # number of overall (read+write) accesses 607system.cpu.icache.overall_accesses::total 36850892 # number of overall (read+write) accesses |
| 622system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000145 # miss rate for ReadReq accesses 623system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses 624system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses 625system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses 626system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses 627system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses | 608system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000145 # miss rate for ReadReq accesses 609system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses 610system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses 611system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses 612system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses 613system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses |
| 628system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40516.743527 # average ReadReq miss latency 629system.cpu.icache.ReadReq_avg_miss_latency::total 40516.743527 # average ReadReq miss latency 630system.cpu.icache.demand_avg_miss_latency::cpu.inst 40516.743527 # average overall miss latency 631system.cpu.icache.demand_avg_miss_latency::total 40516.743527 # average overall miss latency 632system.cpu.icache.overall_avg_miss_latency::cpu.inst 40516.743527 # average overall miss latency 633system.cpu.icache.overall_avg_miss_latency::total 40516.743527 # average overall miss latency 634system.cpu.icache.blocked_cycles::no_mshrs 1739 # number of cycles access was blocked | 614system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42335.534008 # average ReadReq miss latency 615system.cpu.icache.ReadReq_avg_miss_latency::total 42335.534008 # average ReadReq miss latency 616system.cpu.icache.demand_avg_miss_latency::cpu.inst 42335.534008 # average overall miss latency 617system.cpu.icache.demand_avg_miss_latency::total 42335.534008 # average overall miss latency 618system.cpu.icache.overall_avg_miss_latency::cpu.inst 42335.534008 # average overall miss latency 619system.cpu.icache.overall_avg_miss_latency::total 42335.534008 # average overall miss latency 620system.cpu.icache.blocked_cycles::no_mshrs 1128 # number of cycles access was blocked |
| 635system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 621system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 636system.cpu.icache.blocked::no_mshrs 21 # number of cycles access was blocked | 622system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked |
| 637system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 623system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 638system.cpu.icache.avg_blocked_cycles::no_mshrs 82.809524 # average number of cycles each access was blocked | 624system.cpu.icache.avg_blocked_cycles::no_mshrs 59.368421 # average number of cycles each access was blocked |
| 639system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 640system.cpu.icache.fast_writes 0 # number of fast writes performed 641system.cpu.icache.cache_copies 0 # number of cache copies performed | 625system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 626system.cpu.icache.fast_writes 0 # number of fast writes performed 627system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 642system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1205 # number of ReadReq MSHR hits 643system.cpu.icache.ReadReq_mshr_hits::total 1205 # number of ReadReq MSHR hits 644system.cpu.icache.demand_mshr_hits::cpu.inst 1205 # number of demand (read+write) MSHR hits 645system.cpu.icache.demand_mshr_hits::total 1205 # number of demand (read+write) MSHR hits 646system.cpu.icache.overall_mshr_hits::cpu.inst 1205 # number of overall MSHR hits 647system.cpu.icache.overall_mshr_hits::total 1205 # number of overall MSHR hits 648system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4125 # number of ReadReq MSHR misses 649system.cpu.icache.ReadReq_mshr_misses::total 4125 # number of ReadReq MSHR misses 650system.cpu.icache.demand_mshr_misses::cpu.inst 4125 # number of demand (read+write) MSHR misses 651system.cpu.icache.demand_mshr_misses::total 4125 # number of demand (read+write) MSHR misses 652system.cpu.icache.overall_mshr_misses::cpu.inst 4125 # number of overall MSHR misses 653system.cpu.icache.overall_mshr_misses::total 4125 # number of overall MSHR misses 654system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 162387254 # number of ReadReq MSHR miss cycles 655system.cpu.icache.ReadReq_mshr_miss_latency::total 162387254 # number of ReadReq MSHR miss cycles 656system.cpu.icache.demand_mshr_miss_latency::cpu.inst 162387254 # number of demand (read+write) MSHR miss cycles 657system.cpu.icache.demand_mshr_miss_latency::total 162387254 # number of demand (read+write) MSHR miss cycles 658system.cpu.icache.overall_mshr_miss_latency::cpu.inst 162387254 # number of overall MSHR miss cycles 659system.cpu.icache.overall_mshr_miss_latency::total 162387254 # number of overall MSHR miss cycles | 628system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1211 # number of ReadReq MSHR hits 629system.cpu.icache.ReadReq_mshr_hits::total 1211 # number of ReadReq MSHR hits 630system.cpu.icache.demand_mshr_hits::cpu.inst 1211 # number of demand (read+write) MSHR hits 631system.cpu.icache.demand_mshr_hits::total 1211 # number of demand (read+write) MSHR hits 632system.cpu.icache.overall_mshr_hits::cpu.inst 1211 # number of overall MSHR hits 633system.cpu.icache.overall_mshr_hits::total 1211 # number of overall MSHR hits 634system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4126 # number of ReadReq MSHR misses 635system.cpu.icache.ReadReq_mshr_misses::total 4126 # number of ReadReq MSHR misses 636system.cpu.icache.demand_mshr_misses::cpu.inst 4126 # number of demand (read+write) MSHR misses 637system.cpu.icache.demand_mshr_misses::total 4126 # number of demand (read+write) MSHR misses 638system.cpu.icache.overall_mshr_misses::cpu.inst 4126 # number of overall MSHR misses 639system.cpu.icache.overall_mshr_misses::total 4126 # number of overall MSHR misses 640system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168091004 # number of ReadReq MSHR miss cycles 641system.cpu.icache.ReadReq_mshr_miss_latency::total 168091004 # number of ReadReq MSHR miss cycles 642system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168091004 # number of demand (read+write) MSHR miss cycles 643system.cpu.icache.demand_mshr_miss_latency::total 168091004 # number of demand (read+write) MSHR miss cycles 644system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168091004 # number of overall MSHR miss cycles 645system.cpu.icache.overall_mshr_miss_latency::total 168091004 # number of overall MSHR miss cycles |
| 660system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses 661system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses 662system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses 663system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses 664system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for overall accesses 665system.cpu.icache.overall_mshr_miss_rate::total 0.000112 # mshr miss rate for overall accesses | 646system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses 647system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses 648system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses 649system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses 650system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for overall accesses 651system.cpu.icache.overall_mshr_miss_rate::total 0.000112 # mshr miss rate for overall accesses |
| 666system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39366.607030 # average ReadReq mshr miss latency 667system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39366.607030 # average ReadReq mshr miss latency 668system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39366.607030 # average overall mshr miss latency 669system.cpu.icache.demand_avg_mshr_miss_latency::total 39366.607030 # average overall mshr miss latency 670system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39366.607030 # average overall mshr miss latency 671system.cpu.icache.overall_avg_mshr_miss_latency::total 39366.607030 # average overall mshr miss latency | 652system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40739.458071 # average ReadReq mshr miss latency 653system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40739.458071 # average ReadReq mshr miss latency 654system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40739.458071 # average overall mshr miss latency 655system.cpu.icache.demand_avg_mshr_miss_latency::total 40739.458071 # average overall mshr miss latency 656system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40739.458071 # average overall mshr miss latency 657system.cpu.icache.overall_avg_mshr_miss_latency::total 40739.458071 # average overall mshr miss latency |
| 672system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 673system.cpu.l2cache.tags.replacements 0 # number of replacements | 658system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 659system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 674system.cpu.l2cache.tags.tagsinuse 1961.044100 # Cycle average of tags in use 675system.cpu.l2cache.tags.total_refs 2153 # Total number of references to valid blocks. 676system.cpu.l2cache.tags.sampled_refs 2735 # Sample count of references to valid blocks. 677system.cpu.l2cache.tags.avg_refs 0.787203 # Average number of references to valid blocks. | 660system.cpu.l2cache.tags.tagsinuse 1967.449765 # Cycle average of tags in use 661system.cpu.l2cache.tags.total_refs 2162 # Total number of references to valid blocks. 662system.cpu.l2cache.tags.sampled_refs 2732 # Sample count of references to valid blocks. 663system.cpu.l2cache.tags.avg_refs 0.791362 # Average number of references to valid blocks. |
| 678system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 664system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 679system.cpu.l2cache.tags.occ_blocks::writebacks 4.994051 # Average occupied blocks per requestor 680system.cpu.l2cache.tags.occ_blocks::cpu.inst 1423.034105 # Average occupied blocks per requestor 681system.cpu.l2cache.tags.occ_blocks::cpu.data 533.015945 # Average occupied blocks per requestor | 665system.cpu.l2cache.tags.occ_blocks::writebacks 4.994098 # Average occupied blocks per requestor 666system.cpu.l2cache.tags.occ_blocks::cpu.inst 1425.569688 # Average occupied blocks per requestor 667system.cpu.l2cache.tags.occ_blocks::cpu.data 536.885979 # Average occupied blocks per requestor |
| 682system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy | 668system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy |
| 683system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043428 # Average percentage of cache occupancy 684system.cpu.l2cache.tags.occ_percent::cpu.data 0.016266 # Average percentage of cache occupancy 685system.cpu.l2cache.tags.occ_percent::total 0.059846 # Average percentage of cache occupancy 686system.cpu.l2cache.ReadReq_hits::cpu.inst 2065 # number of ReadReq hits 687system.cpu.l2cache.ReadReq_hits::cpu.data 87 # number of ReadReq hits 688system.cpu.l2cache.ReadReq_hits::total 2152 # number of ReadReq hits | 669system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043505 # Average percentage of cache occupancy 670system.cpu.l2cache.tags.occ_percent::cpu.data 0.016384 # Average percentage of cache occupancy 671system.cpu.l2cache.tags.occ_percent::total 0.060042 # Average percentage of cache occupancy 672system.cpu.l2cache.ReadReq_hits::cpu.inst 2073 # number of ReadReq hits 673system.cpu.l2cache.ReadReq_hits::cpu.data 88 # number of ReadReq hits 674system.cpu.l2cache.ReadReq_hits::total 2161 # number of ReadReq hits |
| 689system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits 690system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits 691system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits 692system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits | 675system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits 676system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits 677system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits 678system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits |
| 693system.cpu.l2cache.demand_hits::cpu.inst 2065 # number of demand (read+write) hits 694system.cpu.l2cache.demand_hits::cpu.data 95 # number of demand (read+write) hits 695system.cpu.l2cache.demand_hits::total 2160 # number of demand (read+write) hits 696system.cpu.l2cache.overall_hits::cpu.inst 2065 # number of overall hits 697system.cpu.l2cache.overall_hits::cpu.data 95 # number of overall hits 698system.cpu.l2cache.overall_hits::total 2160 # number of overall hits 699system.cpu.l2cache.ReadReq_misses::cpu.inst 2058 # number of ReadReq misses | 679system.cpu.l2cache.demand_hits::cpu.inst 2073 # number of demand (read+write) hits 680system.cpu.l2cache.demand_hits::cpu.data 96 # number of demand (read+write) hits 681system.cpu.l2cache.demand_hits::total 2169 # number of demand (read+write) hits 682system.cpu.l2cache.overall_hits::cpu.inst 2073 # number of overall hits 683system.cpu.l2cache.overall_hits::cpu.data 96 # number of overall hits 684system.cpu.l2cache.overall_hits::total 2169 # number of overall hits 685system.cpu.l2cache.ReadReq_misses::cpu.inst 2053 # number of ReadReq misses |
| 700system.cpu.l2cache.ReadReq_misses::cpu.data 685 # number of ReadReq misses | 686system.cpu.l2cache.ReadReq_misses::cpu.data 685 # number of ReadReq misses |
| 701system.cpu.l2cache.ReadReq_misses::total 2743 # number of ReadReq misses 702system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses 703system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses 704system.cpu.l2cache.ReadExReq_misses::cpu.data 1075 # number of ReadExReq misses 705system.cpu.l2cache.ReadExReq_misses::total 1075 # number of ReadExReq misses 706system.cpu.l2cache.demand_misses::cpu.inst 2058 # number of demand (read+write) misses 707system.cpu.l2cache.demand_misses::cpu.data 1760 # number of demand (read+write) misses 708system.cpu.l2cache.demand_misses::total 3818 # number of demand (read+write) misses 709system.cpu.l2cache.overall_misses::cpu.inst 2058 # number of overall misses 710system.cpu.l2cache.overall_misses::cpu.data 1760 # number of overall misses 711system.cpu.l2cache.overall_misses::total 3818 # number of overall misses 712system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 137602750 # number of ReadReq miss cycles 713system.cpu.l2cache.ReadReq_miss_latency::cpu.data 47264250 # number of ReadReq miss cycles 714system.cpu.l2cache.ReadReq_miss_latency::total 184867000 # number of ReadReq miss cycles 715system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 68147750 # number of ReadExReq miss cycles 716system.cpu.l2cache.ReadExReq_miss_latency::total 68147750 # number of ReadExReq miss cycles 717system.cpu.l2cache.demand_miss_latency::cpu.inst 137602750 # number of demand (read+write) miss cycles 718system.cpu.l2cache.demand_miss_latency::cpu.data 115412000 # number of demand (read+write) miss cycles 719system.cpu.l2cache.demand_miss_latency::total 253014750 # number of demand (read+write) miss cycles 720system.cpu.l2cache.overall_miss_latency::cpu.inst 137602750 # number of overall miss cycles 721system.cpu.l2cache.overall_miss_latency::cpu.data 115412000 # number of overall miss cycles 722system.cpu.l2cache.overall_miss_latency::total 253014750 # number of overall miss cycles 723system.cpu.l2cache.ReadReq_accesses::cpu.inst 4123 # number of ReadReq accesses(hits+misses) 724system.cpu.l2cache.ReadReq_accesses::cpu.data 772 # number of ReadReq accesses(hits+misses) 725system.cpu.l2cache.ReadReq_accesses::total 4895 # number of ReadReq accesses(hits+misses) | 687system.cpu.l2cache.ReadReq_misses::total 2738 # number of ReadReq misses 688system.cpu.l2cache.ReadExReq_misses::cpu.data 1071 # number of ReadExReq misses 689system.cpu.l2cache.ReadExReq_misses::total 1071 # number of ReadExReq misses 690system.cpu.l2cache.demand_misses::cpu.inst 2053 # number of demand (read+write) misses 691system.cpu.l2cache.demand_misses::cpu.data 1756 # number of demand (read+write) misses 692system.cpu.l2cache.demand_misses::total 3809 # number of demand (read+write) misses 693system.cpu.l2cache.overall_misses::cpu.inst 2053 # number of overall misses 694system.cpu.l2cache.overall_misses::cpu.data 1756 # number of overall misses 695system.cpu.l2cache.overall_misses::total 3809 # number of overall misses 696system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143228000 # number of ReadReq miss cycles 697system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51384000 # number of ReadReq miss cycles 698system.cpu.l2cache.ReadReq_miss_latency::total 194612000 # number of ReadReq miss cycles 699system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 72291750 # number of ReadExReq miss cycles 700system.cpu.l2cache.ReadExReq_miss_latency::total 72291750 # number of ReadExReq miss cycles 701system.cpu.l2cache.demand_miss_latency::cpu.inst 143228000 # number of demand (read+write) miss cycles 702system.cpu.l2cache.demand_miss_latency::cpu.data 123675750 # number of demand (read+write) miss cycles 703system.cpu.l2cache.demand_miss_latency::total 266903750 # number of demand (read+write) miss cycles 704system.cpu.l2cache.overall_miss_latency::cpu.inst 143228000 # number of overall miss cycles 705system.cpu.l2cache.overall_miss_latency::cpu.data 123675750 # number of overall miss cycles 706system.cpu.l2cache.overall_miss_latency::total 266903750 # number of overall miss cycles 707system.cpu.l2cache.ReadReq_accesses::cpu.inst 4126 # number of ReadReq accesses(hits+misses) 708system.cpu.l2cache.ReadReq_accesses::cpu.data 773 # number of ReadReq accesses(hits+misses) 709system.cpu.l2cache.ReadReq_accesses::total 4899 # number of ReadReq accesses(hits+misses) |
| 726system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) 727system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) | 710system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) 711system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) |
| 728system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) 729system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) 730system.cpu.l2cache.ReadExReq_accesses::cpu.data 1083 # number of ReadExReq accesses(hits+misses) 731system.cpu.l2cache.ReadExReq_accesses::total 1083 # number of ReadExReq accesses(hits+misses) 732system.cpu.l2cache.demand_accesses::cpu.inst 4123 # number of demand (read+write) accesses 733system.cpu.l2cache.demand_accesses::cpu.data 1855 # number of demand (read+write) accesses | 712system.cpu.l2cache.ReadExReq_accesses::cpu.data 1079 # number of ReadExReq accesses(hits+misses) 713system.cpu.l2cache.ReadExReq_accesses::total 1079 # number of ReadExReq accesses(hits+misses) 714system.cpu.l2cache.demand_accesses::cpu.inst 4126 # number of demand (read+write) accesses 715system.cpu.l2cache.demand_accesses::cpu.data 1852 # number of demand (read+write) accesses |
| 734system.cpu.l2cache.demand_accesses::total 5978 # number of demand (read+write) accesses | 716system.cpu.l2cache.demand_accesses::total 5978 # number of demand (read+write) accesses |
| 735system.cpu.l2cache.overall_accesses::cpu.inst 4123 # number of overall (read+write) accesses 736system.cpu.l2cache.overall_accesses::cpu.data 1855 # number of overall (read+write) accesses | 717system.cpu.l2cache.overall_accesses::cpu.inst 4126 # number of overall (read+write) accesses 718system.cpu.l2cache.overall_accesses::cpu.data 1852 # number of overall (read+write) accesses |
| 737system.cpu.l2cache.overall_accesses::total 5978 # number of overall (read+write) accesses | 719system.cpu.l2cache.overall_accesses::total 5978 # number of overall (read+write) accesses |
| 738system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.499151 # miss rate for ReadReq accesses 739system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.887306 # miss rate for ReadReq accesses 740system.cpu.l2cache.ReadReq_miss_rate::total 0.560368 # miss rate for ReadReq accesses 741system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 742system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 743system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992613 # miss rate for ReadExReq accesses 744system.cpu.l2cache.ReadExReq_miss_rate::total 0.992613 # miss rate for ReadExReq accesses 745system.cpu.l2cache.demand_miss_rate::cpu.inst 0.499151 # miss rate for demand accesses 746system.cpu.l2cache.demand_miss_rate::cpu.data 0.948787 # miss rate for demand accesses 747system.cpu.l2cache.demand_miss_rate::total 0.638675 # miss rate for demand accesses 748system.cpu.l2cache.overall_miss_rate::cpu.inst 0.499151 # miss rate for overall accesses 749system.cpu.l2cache.overall_miss_rate::cpu.data 0.948787 # miss rate for overall accesses 750system.cpu.l2cache.overall_miss_rate::total 0.638675 # miss rate for overall accesses 751system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66862.366375 # average ReadReq miss latency 752system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68998.905109 # average ReadReq miss latency 753system.cpu.l2cache.ReadReq_avg_miss_latency::total 67395.916879 # average ReadReq miss latency 754system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 63393.255814 # average ReadExReq miss latency 755system.cpu.l2cache.ReadExReq_avg_miss_latency::total 63393.255814 # average ReadExReq miss latency 756system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66862.366375 # average overall miss latency 757system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65575 # average overall miss latency 758system.cpu.l2cache.demand_avg_miss_latency::total 66268.923520 # average overall miss latency 759system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66862.366375 # average overall miss latency 760system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65575 # average overall miss latency 761system.cpu.l2cache.overall_avg_miss_latency::total 66268.923520 # average overall miss latency | 720system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.497576 # miss rate for ReadReq accesses 721system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.886158 # miss rate for ReadReq accesses 722system.cpu.l2cache.ReadReq_miss_rate::total 0.558890 # miss rate for ReadReq accesses 723system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992586 # miss rate for ReadExReq accesses 724system.cpu.l2cache.ReadExReq_miss_rate::total 0.992586 # miss rate for ReadExReq accesses 725system.cpu.l2cache.demand_miss_rate::cpu.inst 0.497576 # miss rate for demand accesses 726system.cpu.l2cache.demand_miss_rate::cpu.data 0.948164 # miss rate for demand accesses 727system.cpu.l2cache.demand_miss_rate::total 0.637170 # miss rate for demand accesses 728system.cpu.l2cache.overall_miss_rate::cpu.inst 0.497576 # miss rate for overall accesses 729system.cpu.l2cache.overall_miss_rate::cpu.data 0.948164 # miss rate for overall accesses 730system.cpu.l2cache.overall_miss_rate::total 0.637170 # miss rate for overall accesses 731system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69765.221627 # average ReadReq miss latency 732system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75013.138686 # average ReadReq miss latency 733system.cpu.l2cache.ReadReq_avg_miss_latency::total 71078.159240 # average ReadReq miss latency 734system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67499.299720 # average ReadExReq miss latency 735system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67499.299720 # average ReadExReq miss latency 736system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69765.221627 # average overall miss latency 737system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70430.381549 # average overall miss latency 738system.cpu.l2cache.demand_avg_miss_latency::total 70071.869257 # average overall miss latency 739system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69765.221627 # average overall miss latency 740system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70430.381549 # average overall miss latency 741system.cpu.l2cache.overall_avg_miss_latency::total 70071.869257 # average overall miss latency |
| 762system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 763system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 764system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 765system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 766system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 767system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 768system.cpu.l2cache.fast_writes 0 # number of fast writes performed 769system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 742system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 743system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 744system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 745system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 746system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 747system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 748system.cpu.l2cache.fast_writes 0 # number of fast writes performed 749system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 770system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits 771system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits 772system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits 773system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits 774system.cpu.l2cache.demand_mshr_hits::cpu.data 12 # number of demand (read+write) MSHR hits 775system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits 776system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits 777system.cpu.l2cache.overall_mshr_hits::cpu.data 12 # number of overall MSHR hits 778system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits 779system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2053 # number of ReadReq MSHR misses 780system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 673 # number of ReadReq MSHR misses 781system.cpu.l2cache.ReadReq_mshr_misses::total 2726 # number of ReadReq MSHR misses 782system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses 783system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses 784system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1075 # number of ReadExReq MSHR misses 785system.cpu.l2cache.ReadExReq_mshr_misses::total 1075 # number of ReadExReq MSHR misses 786system.cpu.l2cache.demand_mshr_misses::cpu.inst 2053 # number of demand (read+write) MSHR misses 787system.cpu.l2cache.demand_mshr_misses::cpu.data 1748 # number of demand (read+write) MSHR misses 788system.cpu.l2cache.demand_mshr_misses::total 3801 # number of demand (read+write) MSHR misses 789system.cpu.l2cache.overall_mshr_misses::cpu.inst 2053 # number of overall MSHR misses 790system.cpu.l2cache.overall_mshr_misses::cpu.data 1748 # number of overall MSHR misses 791system.cpu.l2cache.overall_mshr_misses::total 3801 # number of overall MSHR misses 792system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111409500 # number of ReadReq MSHR miss cycles 793system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 38132750 # number of ReadReq MSHR miss cycles 794system.cpu.l2cache.ReadReq_mshr_miss_latency::total 149542250 # number of ReadReq MSHR miss cycles 795system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles 796system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles 797system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54590750 # number of ReadExReq MSHR miss cycles 798system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54590750 # number of ReadExReq MSHR miss cycles 799system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111409500 # number of demand (read+write) MSHR miss cycles 800system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 92723500 # number of demand (read+write) MSHR miss cycles 801system.cpu.l2cache.demand_mshr_miss_latency::total 204133000 # number of demand (read+write) MSHR miss cycles 802system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111409500 # number of overall MSHR miss cycles 803system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92723500 # number of overall MSHR miss cycles 804system.cpu.l2cache.overall_mshr_miss_latency::total 204133000 # number of overall MSHR miss cycles 805system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.497938 # mshr miss rate for ReadReq accesses 806system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871762 # mshr miss rate for ReadReq accesses 807system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.556895 # mshr miss rate for ReadReq accesses 808system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 809system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 810system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992613 # mshr miss rate for ReadExReq accesses 811system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992613 # mshr miss rate for ReadExReq accesses 812system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.497938 # mshr miss rate for demand accesses 813system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942318 # mshr miss rate for demand accesses 814system.cpu.l2cache.demand_mshr_miss_rate::total 0.635831 # mshr miss rate for demand accesses 815system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.497938 # mshr miss rate for overall accesses 816system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942318 # mshr miss rate for overall accesses 817system.cpu.l2cache.overall_mshr_miss_rate::total 0.635831 # mshr miss rate for overall accesses 818system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54266.682903 # average ReadReq mshr miss latency 819system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56660.846954 # average ReadReq mshr miss latency 820system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54857.758621 # average ReadReq mshr miss latency 821system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 822system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 823system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50782.093023 # average ReadExReq mshr miss latency 824system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50782.093023 # average ReadExReq mshr miss latency 825system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54266.682903 # average overall mshr miss latency 826system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53045.480549 # average overall mshr miss latency 827system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53705.077611 # average overall mshr miss latency 828system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54266.682903 # average overall mshr miss latency 829system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53045.480549 # average overall mshr miss latency 830system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53705.077611 # average overall mshr miss latency | 750system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits 751system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 11 # number of ReadReq MSHR hits 752system.cpu.l2cache.ReadReq_mshr_hits::total 15 # number of ReadReq MSHR hits 753system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits 754system.cpu.l2cache.demand_mshr_hits::cpu.data 11 # number of demand (read+write) MSHR hits 755system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits 756system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits 757system.cpu.l2cache.overall_mshr_hits::cpu.data 11 # number of overall MSHR hits 758system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits 759system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2049 # number of ReadReq MSHR misses 760system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 674 # number of ReadReq MSHR misses 761system.cpu.l2cache.ReadReq_mshr_misses::total 2723 # number of ReadReq MSHR misses 762system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1071 # number of ReadExReq MSHR misses 763system.cpu.l2cache.ReadExReq_mshr_misses::total 1071 # number of ReadExReq MSHR misses 764system.cpu.l2cache.demand_mshr_misses::cpu.inst 2049 # number of demand (read+write) MSHR misses 765system.cpu.l2cache.demand_mshr_misses::cpu.data 1745 # number of demand (read+write) MSHR misses 766system.cpu.l2cache.demand_mshr_misses::total 3794 # number of demand (read+write) MSHR misses 767system.cpu.l2cache.overall_mshr_misses::cpu.inst 2049 # number of overall MSHR misses 768system.cpu.l2cache.overall_mshr_misses::cpu.data 1745 # number of overall MSHR misses 769system.cpu.l2cache.overall_mshr_misses::total 3794 # number of overall MSHR misses 770system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117254500 # number of ReadReq MSHR miss cycles 771system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42298000 # number of ReadReq MSHR miss cycles 772system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159552500 # number of ReadReq MSHR miss cycles 773system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 58841750 # number of ReadExReq MSHR miss cycles 774system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 58841750 # number of ReadExReq MSHR miss cycles 775system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117254500 # number of demand (read+write) MSHR miss cycles 776system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101139750 # number of demand (read+write) MSHR miss cycles 777system.cpu.l2cache.demand_mshr_miss_latency::total 218394250 # number of demand (read+write) MSHR miss cycles 778system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117254500 # number of overall MSHR miss cycles 779system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101139750 # number of overall MSHR miss cycles 780system.cpu.l2cache.overall_mshr_miss_latency::total 218394250 # number of overall MSHR miss cycles 781system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for ReadReq accesses 782system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871928 # mshr miss rate for ReadReq accesses 783system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.555828 # mshr miss rate for ReadReq accesses 784system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992586 # mshr miss rate for ReadExReq accesses 785system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992586 # mshr miss rate for ReadExReq accesses 786system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for demand accesses 787system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942225 # mshr miss rate for demand accesses 788system.cpu.l2cache.demand_mshr_miss_rate::total 0.634660 # mshr miss rate for demand accesses 789system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for overall accesses 790system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942225 # mshr miss rate for overall accesses 791system.cpu.l2cache.overall_mshr_miss_rate::total 0.634660 # mshr miss rate for overall accesses 792system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57225.231820 # average ReadReq mshr miss latency 793system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62756.676558 # average ReadReq mshr miss latency 794system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58594.381197 # average ReadReq mshr miss latency 795system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54940.943044 # average ReadExReq mshr miss latency 796system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54940.943044 # average ReadExReq mshr miss latency 797system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57225.231820 # average overall mshr miss latency 798system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57959.742120 # average overall mshr miss latency 799system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57563.060095 # average overall mshr miss latency 800system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57225.231820 # average overall mshr miss latency 801system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57959.742120 # average overall mshr miss latency 802system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57563.060095 # average overall mshr miss latency |
| 831system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 832system.cpu.dcache.tags.replacements 57 # number of replacements | 803system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 804system.cpu.dcache.tags.replacements 57 # number of replacements |
| 833system.cpu.dcache.tags.tagsinuse 1404.261851 # Cycle average of tags in use 834system.cpu.dcache.tags.total_refs 46798452 # Total number of references to valid blocks. 835system.cpu.dcache.tags.sampled_refs 1855 # Sample count of references to valid blocks. 836system.cpu.dcache.tags.avg_refs 25228.276011 # Average number of references to valid blocks. | 805system.cpu.dcache.tags.tagsinuse 1406.103135 # Cycle average of tags in use 806system.cpu.dcache.tags.total_refs 46786156 # Total number of references to valid blocks. 807system.cpu.dcache.tags.sampled_refs 1852 # Sample count of references to valid blocks. 808system.cpu.dcache.tags.avg_refs 25262.503240 # Average number of references to valid blocks. |
| 837system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 809system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 838system.cpu.dcache.tags.occ_blocks::cpu.data 1404.261851 # Average occupied blocks per requestor 839system.cpu.dcache.tags.occ_percent::cpu.data 0.342837 # Average percentage of cache occupancy 840system.cpu.dcache.tags.occ_percent::total 0.342837 # Average percentage of cache occupancy 841system.cpu.dcache.ReadReq_hits::cpu.data 34397014 # number of ReadReq hits 842system.cpu.dcache.ReadReq_hits::total 34397014 # number of ReadReq hits 843system.cpu.dcache.WriteReq_hits::cpu.data 12356557 # number of WriteReq hits 844system.cpu.dcache.WriteReq_hits::total 12356557 # number of WriteReq hits 845system.cpu.dcache.LoadLockedReq_hits::cpu.data 22472 # number of LoadLockedReq hits 846system.cpu.dcache.LoadLockedReq_hits::total 22472 # number of LoadLockedReq hits | 810system.cpu.dcache.tags.occ_blocks::cpu.data 1406.103135 # Average occupied blocks per requestor 811system.cpu.dcache.tags.occ_percent::cpu.data 0.343287 # Average percentage of cache occupancy 812system.cpu.dcache.tags.occ_percent::total 0.343287 # Average percentage of cache occupancy 813system.cpu.dcache.ReadReq_hits::cpu.data 34384711 # number of ReadReq hits 814system.cpu.dcache.ReadReq_hits::total 34384711 # number of ReadReq hits 815system.cpu.dcache.WriteReq_hits::cpu.data 12356564 # number of WriteReq hits 816system.cpu.dcache.WriteReq_hits::total 12356564 # number of WriteReq hits 817system.cpu.dcache.LoadLockedReq_hits::cpu.data 22474 # number of LoadLockedReq hits 818system.cpu.dcache.LoadLockedReq_hits::total 22474 # number of LoadLockedReq hits |
| 847system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits 848system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits | 819system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits 820system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits |
| 849system.cpu.dcache.demand_hits::cpu.data 46753571 # number of demand (read+write) hits 850system.cpu.dcache.demand_hits::total 46753571 # number of demand (read+write) hits 851system.cpu.dcache.overall_hits::cpu.data 46753571 # number of overall hits 852system.cpu.dcache.overall_hits::total 46753571 # number of overall hits 853system.cpu.dcache.ReadReq_misses::cpu.data 1913 # number of ReadReq misses 854system.cpu.dcache.ReadReq_misses::total 1913 # number of ReadReq misses 855system.cpu.dcache.WriteReq_misses::cpu.data 7730 # number of WriteReq misses 856system.cpu.dcache.WriteReq_misses::total 7730 # number of WriteReq misses | 821system.cpu.dcache.demand_hits::cpu.data 46741275 # number of demand (read+write) hits 822system.cpu.dcache.demand_hits::total 46741275 # number of demand (read+write) hits 823system.cpu.dcache.overall_hits::cpu.data 46741275 # number of overall hits 824system.cpu.dcache.overall_hits::total 46741275 # number of overall hits 825system.cpu.dcache.ReadReq_misses::cpu.data 1902 # number of ReadReq misses 826system.cpu.dcache.ReadReq_misses::total 1902 # number of ReadReq misses 827system.cpu.dcache.WriteReq_misses::cpu.data 7723 # number of WriteReq misses 828system.cpu.dcache.WriteReq_misses::total 7723 # number of WriteReq misses |
| 857system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 858system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses | 829system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 830system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses |
| 859system.cpu.dcache.demand_misses::cpu.data 9643 # number of demand (read+write) misses 860system.cpu.dcache.demand_misses::total 9643 # number of demand (read+write) misses 861system.cpu.dcache.overall_misses::cpu.data 9643 # number of overall misses 862system.cpu.dcache.overall_misses::total 9643 # number of overall misses 863system.cpu.dcache.ReadReq_miss_latency::cpu.data 114314976 # number of ReadReq miss cycles 864system.cpu.dcache.ReadReq_miss_latency::total 114314976 # number of ReadReq miss cycles 865system.cpu.dcache.WriteReq_miss_latency::cpu.data 447415748 # number of WriteReq miss cycles 866system.cpu.dcache.WriteReq_miss_latency::total 447415748 # number of WriteReq miss cycles | 831system.cpu.dcache.demand_misses::cpu.data 9625 # number of demand (read+write) misses 832system.cpu.dcache.demand_misses::total 9625 # number of demand (read+write) misses 833system.cpu.dcache.overall_misses::cpu.data 9625 # number of overall misses 834system.cpu.dcache.overall_misses::total 9625 # number of overall misses 835system.cpu.dcache.ReadReq_miss_latency::cpu.data 121870727 # number of ReadReq miss cycles 836system.cpu.dcache.ReadReq_miss_latency::total 121870727 # number of ReadReq miss cycles 837system.cpu.dcache.WriteReq_miss_latency::cpu.data 465623246 # number of WriteReq miss cycles 838system.cpu.dcache.WriteReq_miss_latency::total 465623246 # number of WriteReq miss cycles |
| 867system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles 868system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles | 839system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles 840system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles |
| 869system.cpu.dcache.demand_miss_latency::cpu.data 561730724 # number of demand (read+write) miss cycles 870system.cpu.dcache.demand_miss_latency::total 561730724 # number of demand (read+write) miss cycles 871system.cpu.dcache.overall_miss_latency::cpu.data 561730724 # number of overall miss cycles 872system.cpu.dcache.overall_miss_latency::total 561730724 # number of overall miss cycles 873system.cpu.dcache.ReadReq_accesses::cpu.data 34398927 # number of ReadReq accesses(hits+misses) 874system.cpu.dcache.ReadReq_accesses::total 34398927 # number of ReadReq accesses(hits+misses) | 841system.cpu.dcache.demand_miss_latency::cpu.data 587493973 # number of demand (read+write) miss cycles 842system.cpu.dcache.demand_miss_latency::total 587493973 # number of demand (read+write) miss cycles 843system.cpu.dcache.overall_miss_latency::cpu.data 587493973 # number of overall miss cycles 844system.cpu.dcache.overall_miss_latency::total 587493973 # number of overall miss cycles 845system.cpu.dcache.ReadReq_accesses::cpu.data 34386613 # number of ReadReq accesses(hits+misses) 846system.cpu.dcache.ReadReq_accesses::total 34386613 # number of ReadReq accesses(hits+misses) |
| 875system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 876system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) | 847system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 848system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) |
| 877system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22474 # number of LoadLockedReq accesses(hits+misses) 878system.cpu.dcache.LoadLockedReq_accesses::total 22474 # number of LoadLockedReq accesses(hits+misses) | 849system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22476 # number of LoadLockedReq accesses(hits+misses) 850system.cpu.dcache.LoadLockedReq_accesses::total 22476 # number of LoadLockedReq accesses(hits+misses) |
| 879system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) 880system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) | 851system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) 852system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) |
| 881system.cpu.dcache.demand_accesses::cpu.data 46763214 # number of demand (read+write) accesses 882system.cpu.dcache.demand_accesses::total 46763214 # number of demand (read+write) accesses 883system.cpu.dcache.overall_accesses::cpu.data 46763214 # number of overall (read+write) accesses 884system.cpu.dcache.overall_accesses::total 46763214 # number of overall (read+write) accesses 885system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000056 # miss rate for ReadReq accesses 886system.cpu.dcache.ReadReq_miss_rate::total 0.000056 # miss rate for ReadReq accesses | 853system.cpu.dcache.demand_accesses::cpu.data 46750900 # number of demand (read+write) accesses 854system.cpu.dcache.demand_accesses::total 46750900 # number of demand (read+write) accesses 855system.cpu.dcache.overall_accesses::cpu.data 46750900 # number of overall (read+write) accesses 856system.cpu.dcache.overall_accesses::total 46750900 # number of overall (read+write) accesses 857system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses 858system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses |
| 887system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses 888system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses 889system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses 890system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses 891system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses 892system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses 893system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses 894system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses | 859system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses 860system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses 861system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses 862system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses 863system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses 864system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses 865system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses 866system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses |
| 895system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59756.913748 # average ReadReq miss latency 896system.cpu.dcache.ReadReq_avg_miss_latency::total 59756.913748 # average ReadReq miss latency 897system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57880.433118 # average WriteReq miss latency 898system.cpu.dcache.WriteReq_avg_miss_latency::total 57880.433118 # average WriteReq miss latency | 867system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64075.040484 # average ReadReq miss latency 868system.cpu.dcache.ReadReq_avg_miss_latency::total 64075.040484 # average ReadReq miss latency 869system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60290.463033 # average WriteReq miss latency 870system.cpu.dcache.WriteReq_avg_miss_latency::total 60290.463033 # average WriteReq miss latency |
| 899system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency 900system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency | 871system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency 872system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency |
| 901system.cpu.dcache.demand_avg_miss_latency::cpu.data 58252.693560 # average overall miss latency 902system.cpu.dcache.demand_avg_miss_latency::total 58252.693560 # average overall miss latency 903system.cpu.dcache.overall_avg_miss_latency::cpu.data 58252.693560 # average overall miss latency 904system.cpu.dcache.overall_avg_miss_latency::total 58252.693560 # average overall miss latency 905system.cpu.dcache.blocked_cycles::no_mshrs 597 # number of cycles access was blocked 906system.cpu.dcache.blocked_cycles::no_targets 154 # number of cycles access was blocked | 873system.cpu.dcache.demand_avg_miss_latency::cpu.data 61038.334857 # average overall miss latency 874system.cpu.dcache.demand_avg_miss_latency::total 61038.334857 # average overall miss latency 875system.cpu.dcache.overall_avg_miss_latency::cpu.data 61038.334857 # average overall miss latency 876system.cpu.dcache.overall_avg_miss_latency::total 61038.334857 # average overall miss latency 877system.cpu.dcache.blocked_cycles::no_mshrs 592 # number of cycles access was blocked 878system.cpu.dcache.blocked_cycles::no_targets 314 # number of cycles access was blocked |
| 907system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked | 879system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked |
| 908system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked 909system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.272727 # average number of cycles each access was blocked 910system.cpu.dcache.avg_blocked_cycles::no_targets 77 # average number of cycles each access was blocked | 880system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked 881system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.818182 # average number of cycles each access was blocked 882system.cpu.dcache.avg_blocked_cycles::no_targets 78.500000 # average number of cycles each access was blocked |
| 911system.cpu.dcache.fast_writes 0 # number of fast writes performed 912system.cpu.dcache.cache_copies 0 # number of cache copies performed 913system.cpu.dcache.writebacks::writebacks 18 # number of writebacks 914system.cpu.dcache.writebacks::total 18 # number of writebacks | 883system.cpu.dcache.fast_writes 0 # number of fast writes performed 884system.cpu.dcache.cache_copies 0 # number of cache copies performed 885system.cpu.dcache.writebacks::writebacks 18 # number of writebacks 886system.cpu.dcache.writebacks::total 18 # number of writebacks |
| 915system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1140 # number of ReadReq MSHR hits 916system.cpu.dcache.ReadReq_mshr_hits::total 1140 # number of ReadReq MSHR hits 917system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6646 # number of WriteReq MSHR hits 918system.cpu.dcache.WriteReq_mshr_hits::total 6646 # number of WriteReq MSHR hits | 887system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1128 # number of ReadReq MSHR hits 888system.cpu.dcache.ReadReq_mshr_hits::total 1128 # number of ReadReq MSHR hits 889system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6645 # number of WriteReq MSHR hits 890system.cpu.dcache.WriteReq_mshr_hits::total 6645 # number of WriteReq MSHR hits |
| 919system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 920system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits | 891system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 892system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits |
| 921system.cpu.dcache.demand_mshr_hits::cpu.data 7786 # number of demand (read+write) MSHR hits 922system.cpu.dcache.demand_mshr_hits::total 7786 # number of demand (read+write) MSHR hits 923system.cpu.dcache.overall_mshr_hits::cpu.data 7786 # number of overall MSHR hits 924system.cpu.dcache.overall_mshr_hits::total 7786 # number of overall MSHR hits 925system.cpu.dcache.ReadReq_mshr_misses::cpu.data 773 # number of ReadReq MSHR misses 926system.cpu.dcache.ReadReq_mshr_misses::total 773 # number of ReadReq MSHR misses 927system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1084 # number of WriteReq MSHR misses 928system.cpu.dcache.WriteReq_mshr_misses::total 1084 # number of WriteReq MSHR misses 929system.cpu.dcache.demand_mshr_misses::cpu.data 1857 # number of demand (read+write) MSHR misses 930system.cpu.dcache.demand_mshr_misses::total 1857 # number of demand (read+write) MSHR misses 931system.cpu.dcache.overall_mshr_misses::cpu.data 1857 # number of overall MSHR misses 932system.cpu.dcache.overall_mshr_misses::total 1857 # number of overall MSHR misses 933system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48960262 # number of ReadReq MSHR miss cycles 934system.cpu.dcache.ReadReq_mshr_miss_latency::total 48960262 # number of ReadReq MSHR miss cycles 935system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 69313496 # number of WriteReq MSHR miss cycles 936system.cpu.dcache.WriteReq_mshr_miss_latency::total 69313496 # number of WriteReq MSHR miss cycles 937system.cpu.dcache.demand_mshr_miss_latency::cpu.data 118273758 # number of demand (read+write) MSHR miss cycles 938system.cpu.dcache.demand_mshr_miss_latency::total 118273758 # number of demand (read+write) MSHR miss cycles 939system.cpu.dcache.overall_mshr_miss_latency::cpu.data 118273758 # number of overall MSHR miss cycles 940system.cpu.dcache.overall_mshr_miss_latency::total 118273758 # number of overall MSHR miss cycles 941system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses 942system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses 943system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses 944system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses | 893system.cpu.dcache.demand_mshr_hits::cpu.data 7773 # number of demand (read+write) MSHR hits 894system.cpu.dcache.demand_mshr_hits::total 7773 # number of demand (read+write) MSHR hits 895system.cpu.dcache.overall_mshr_hits::cpu.data 7773 # number of overall MSHR hits 896system.cpu.dcache.overall_mshr_hits::total 7773 # number of overall MSHR hits 897system.cpu.dcache.ReadReq_mshr_misses::cpu.data 774 # number of ReadReq MSHR misses 898system.cpu.dcache.ReadReq_mshr_misses::total 774 # number of ReadReq MSHR misses 899system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1078 # number of WriteReq MSHR misses 900system.cpu.dcache.WriteReq_mshr_misses::total 1078 # number of WriteReq MSHR misses 901system.cpu.dcache.demand_mshr_misses::cpu.data 1852 # number of demand (read+write) MSHR misses 902system.cpu.dcache.demand_mshr_misses::total 1852 # number of demand (read+write) MSHR misses 903system.cpu.dcache.overall_mshr_misses::cpu.data 1852 # number of overall MSHR misses 904system.cpu.dcache.overall_mshr_misses::total 1852 # number of overall MSHR misses 905system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53114761 # number of ReadReq MSHR miss cycles 906system.cpu.dcache.ReadReq_mshr_miss_latency::total 53114761 # number of ReadReq MSHR miss cycles 907system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73392998 # number of WriteReq MSHR miss cycles 908system.cpu.dcache.WriteReq_mshr_miss_latency::total 73392998 # number of WriteReq MSHR miss cycles 909system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126507759 # number of demand (read+write) MSHR miss cycles 910system.cpu.dcache.demand_mshr_miss_latency::total 126507759 # number of demand (read+write) MSHR miss cycles 911system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126507759 # number of overall MSHR miss cycles 912system.cpu.dcache.overall_mshr_miss_latency::total 126507759 # number of overall MSHR miss cycles 913system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses 914system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses 915system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses 916system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses |
| 945system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses 946system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 947system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses 948system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses | 917system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses 918system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 919system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses 920system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses |
| 949system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63337.984476 # average ReadReq mshr miss latency 950system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63337.984476 # average ReadReq mshr miss latency 951system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63942.339483 # average WriteReq mshr miss latency 952system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63942.339483 # average WriteReq mshr miss latency 953system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63690.768982 # average overall mshr miss latency 954system.cpu.dcache.demand_avg_mshr_miss_latency::total 63690.768982 # average overall mshr miss latency 955system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63690.768982 # average overall mshr miss latency 956system.cpu.dcache.overall_avg_mshr_miss_latency::total 63690.768982 # average overall mshr miss latency | 921system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68623.722222 # average ReadReq mshr miss latency 922system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68623.722222 # average ReadReq mshr miss latency 923system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68082.558442 # average WriteReq mshr miss latency 924system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68082.558442 # average WriteReq mshr miss latency 925system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68308.725162 # average overall mshr miss latency 926system.cpu.dcache.demand_avg_mshr_miss_latency::total 68308.725162 # average overall mshr miss latency 927system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68308.725162 # average overall mshr miss latency 928system.cpu.dcache.overall_avg_mshr_miss_latency::total 68308.725162 # average overall mshr miss latency |
| 957system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 958 959---------- End Simulation Statistics ---------- | 929system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 930 931---------- End Simulation Statistics ---------- |