| stats.txt (9620:89aa34e10625) | stats.txt (9729:e2fafd224f43) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.074157 # Number of seconds simulated 4sim_ticks 74157495500 # Number of ticks simulated 5final_tick 74157495500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.074184 # Number of seconds simulated 4sim_ticks 74184344000 # Number of ticks simulated 5final_tick 74184344000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 51189 # Simulator instruction rate (inst/s) 8host_op_rate 56047 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 22031117 # Simulator tick rate (ticks/s) 10host_mem_usage 291420 # Number of bytes of host memory used 11host_seconds 3366.03 # Real time elapsed on the host | 7host_inst_rate 120810 # Simulator instruction rate (inst/s) 8host_op_rate 132276 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 52014122 # Simulator tick rate (ticks/s) 10host_mem_usage 249648 # Number of bytes of host memory used 11host_seconds 1426.23 # Real time elapsed on the host |
| 12sim_insts 172303021 # Number of instructions simulated 13sim_ops 188656503 # Number of ops (including micro ops) simulated | 12sim_insts 172303021 # Number of instructions simulated 13sim_ops 188656503 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 131776 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 111936 # Number of bytes read from this memory 16system.physmem.bytes_read::total 243712 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 131776 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 131776 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 2059 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 1749 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 3808 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1776975 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 1509436 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 3286411 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1776975 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1776975 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1776975 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 1509436 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 3286411 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 3809 # Total number of read requests seen | 14system.physmem.bytes_read::cpu.inst 131136 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 111808 # Number of bytes read from this memory 16system.physmem.bytes_read::total 242944 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 131136 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 131136 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 2049 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 1747 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 3796 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1767705 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 1507164 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 3274869 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1767705 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1767705 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1767705 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 1507164 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 3274869 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 3796 # Total number of read requests seen |
| 31system.physmem.writeReqs 0 # Total number of write requests seen | 31system.physmem.writeReqs 0 # Total number of write requests seen |
| 32system.physmem.cpureqs 3811 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 243712 # Total number of bytes read from memory | 32system.physmem.cpureqs 3798 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 242944 # Total number of bytes read from memory |
| 34system.physmem.bytesWritten 0 # Total number of bytes written to memory | 34system.physmem.bytesWritten 0 # Total number of bytes written to memory |
| 35system.physmem.bytesConsumedRd 243712 # bytesRead derated as per pkt->getSize() | 35system.physmem.bytesConsumedRd 242944 # bytesRead derated as per pkt->getSize() |
| 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed | 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed |
| 39system.physmem.perBankRdReqs::0 323 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 239 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 208 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 272 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 244 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 197 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 247 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 252 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 233 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 244 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 235 # Track reads on a per bank basis | 39system.physmem.perBankRdReqs::0 309 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 215 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 134 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 309 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 297 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 300 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 262 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 217 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 246 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 213 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 288 # Track reads on a per bank basis |
| 50system.physmem.perBankRdReqs::11 193 # Track reads on a per bank basis | 50system.physmem.perBankRdReqs::11 193 # Track reads on a per bank basis |
| 51system.physmem.perBankRdReqs::12 201 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 199 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 248 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 274 # Track reads on a per bank basis | 51system.physmem.perBankRdReqs::12 189 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 206 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 219 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 199 # Track reads on a per bank basis |
| 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 73system.physmem.totGap 74157477000 # Total gap between requests | 73system.physmem.totGap 74184191000 # Total gap between requests |
| 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes | 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 80system.physmem.readPktSize::6 3809 # Categorize read packet sizes | 80system.physmem.readPktSize::6 3796 # Categorize read packet sizes |
| 81system.physmem.writePktSize::0 0 # Categorize write packet sizes 82system.physmem.writePktSize::1 0 # Categorize write packet sizes 83system.physmem.writePktSize::2 0 # Categorize write packet sizes 84system.physmem.writePktSize::3 0 # Categorize write packet sizes 85system.physmem.writePktSize::4 0 # Categorize write packet sizes 86system.physmem.writePktSize::5 0 # Categorize write packet sizes 87system.physmem.writePktSize::6 0 # Categorize write packet sizes | 81system.physmem.writePktSize::0 0 # Categorize write packet sizes 82system.physmem.writePktSize::1 0 # Categorize write packet sizes 83system.physmem.writePktSize::2 0 # Categorize write packet sizes 84system.physmem.writePktSize::3 0 # Categorize write packet sizes 85system.physmem.writePktSize::4 0 # Categorize write packet sizes 86system.physmem.writePktSize::5 0 # Categorize write packet sizes 87system.physmem.writePktSize::6 0 # Categorize write packet sizes |
| 88system.physmem.rdQLenPdf::0 2784 # What read queue length does an incoming req see 89system.physmem.rdQLenPdf::1 808 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::2 160 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::3 48 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see | 88system.physmem.rdQLenPdf::0 2837 # What read queue length does an incoming req see 89system.physmem.rdQLenPdf::1 786 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::2 131 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see |
| 93system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 43 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see | 93system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 43 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| 152system.physmem.totQLat 17510750 # Total cycles spent in queuing delays 153system.physmem.totMemAccLat 103435750 # Sum of mem lat for all requests 154system.physmem.totBusLat 19045000 # Total cycles spent in databus access 155system.physmem.totBankLat 66880000 # Total cycles spent in bank access 156system.physmem.avgQLat 4597.20 # Average queueing delay per request 157system.physmem.avgBankLat 17558.41 # Average bank access latency per request | 152system.physmem.bytesPerActivate::samples 376 # Bytes accessed per row activation 153system.physmem.bytesPerActivate::mean 621.446809 # Bytes accessed per row activation 154system.physmem.bytesPerActivate::gmean 226.720612 # Bytes accessed per row activation 155system.physmem.bytesPerActivate::stdev 1211.628472 # Bytes accessed per row activation 156system.physmem.bytesPerActivate::64-65 135 35.90% 35.90% # Bytes accessed per row activation 157system.physmem.bytesPerActivate::128-129 51 13.56% 49.47% # Bytes accessed per row activation 158system.physmem.bytesPerActivate::192-193 26 6.91% 56.38% # Bytes accessed per row activation 159system.physmem.bytesPerActivate::256-257 29 7.71% 64.10% # Bytes accessed per row activation 160system.physmem.bytesPerActivate::320-321 14 3.72% 67.82% # Bytes accessed per row activation 161system.physmem.bytesPerActivate::384-385 14 3.72% 71.54% # Bytes accessed per row activation 162system.physmem.bytesPerActivate::448-449 6 1.60% 73.14% # Bytes accessed per row activation 163system.physmem.bytesPerActivate::512-513 5 1.33% 74.47% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::576-577 7 1.86% 76.33% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::640-641 7 1.86% 78.19% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::704-705 5 1.33% 79.52% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::768-769 6 1.60% 81.12% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::832-833 1 0.27% 81.38% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::896-897 5 1.33% 82.71% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::960-961 3 0.80% 83.51% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::1024-1025 4 1.06% 84.57% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::1088-1089 2 0.53% 85.11% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::1152-1153 3 0.80% 85.90% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::1216-1217 3 0.80% 86.70% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::1280-1281 1 0.27% 86.97% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::1344-1345 1 0.27% 87.23% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::1408-1409 5 1.33% 88.56% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::1472-1473 2 0.53% 89.10% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::1536-1537 1 0.27% 89.36% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::1600-1601 3 0.80% 90.16% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::1664-1665 3 0.80% 90.96% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::1728-1729 1 0.27% 91.22% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1792-1793 1 0.27% 91.49% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1856-1857 1 0.27% 91.76% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1920-1921 1 0.27% 92.02% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::2112-2113 2 0.53% 92.55% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::2176-2177 1 0.27% 92.82% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::2240-2241 1 0.27% 93.09% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::2304-2305 1 0.27% 93.35% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::2368-2369 1 0.27% 93.62% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::2432-2433 1 0.27% 93.88% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::2496-2497 1 0.27% 94.15% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::2624-2625 1 0.27% 94.41% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::2688-2689 1 0.27% 94.68% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::2816-2817 1 0.27% 94.95% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::2944-2945 1 0.27% 95.21% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::3008-3009 1 0.27% 95.48% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::3200-3201 1 0.27% 95.74% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::3264-3265 3 0.80% 96.54% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::3712-3713 1 0.27% 96.81% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::4032-4033 1 0.27% 97.07% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::4416-4417 1 0.27% 97.34% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::4480-4481 1 0.27% 97.61% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::4800-4801 1 0.27% 97.87% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::5120-5121 1 0.27% 98.14% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::5312-5313 1 0.27% 98.40% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::6272-6273 1 0.27% 98.67% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::6720-6721 1 0.27% 98.94% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::6848-6849 1 0.27% 99.20% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::8128-8129 1 0.27% 99.47% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::8192-8193 2 0.53% 100.00% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::total 376 # Bytes accessed per row activation 213system.physmem.totQLat 13471250 # Total cycles spent in queuing delays 214system.physmem.totMemAccLat 86310000 # Sum of mem lat for all requests 215system.physmem.totBusLat 18980000 # Total cycles spent in databus access 216system.physmem.totBankLat 53858750 # Total cycles spent in bank access 217system.physmem.avgQLat 3548.80 # Average queueing delay per request 218system.physmem.avgBankLat 14188.29 # Average bank access latency per request |
| 158system.physmem.avgBusLat 5000.00 # Average bus latency per request | 219system.physmem.avgBusLat 5000.00 # Average bus latency per request |
| 159system.physmem.avgMemAccLat 27155.62 # Average memory access latency 160system.physmem.avgRdBW 3.29 # Average achieved read bandwidth in MB/s | 220system.physmem.avgMemAccLat 22737.09 # Average memory access latency 221system.physmem.avgRdBW 3.27 # Average achieved read bandwidth in MB/s |
| 161system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s | 222system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s |
| 162system.physmem.avgConsumedRdBW 3.29 # Average consumed read bandwidth in MB/s | 223system.physmem.avgConsumedRdBW 3.27 # Average consumed read bandwidth in MB/s |
| 163system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 164system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 165system.physmem.busUtil 0.03 # Data bus utilization in percentage 166system.physmem.avgRdQLen 0.00 # Average read queue length over time 167system.physmem.avgWrQLen 0.00 # Average write queue length over time | 224system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 225system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 226system.physmem.busUtil 0.03 # Data bus utilization in percentage 227system.physmem.avgRdQLen 0.00 # Average read queue length over time 228system.physmem.avgWrQLen 0.00 # Average write queue length over time |
| 168system.physmem.readRowHits 3021 # Number of row buffer hits during reads | 229system.physmem.readRowHits 3420 # Number of row buffer hits during reads |
| 169system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 230system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 170system.physmem.readRowHitRate 79.31 # Row buffer hit rate for reads | 231system.physmem.readRowHitRate 90.09 # Row buffer hit rate for reads |
| 171system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 232system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 172system.physmem.avgGap 19469014.70 # Average gap between requests 173system.cpu.branchPred.lookups 94703867 # Number of BP lookups 174system.cpu.branchPred.condPredicted 74722053 # Number of conditional branches predicted 175system.cpu.branchPred.condIncorrect 6280216 # Number of conditional branches incorrect 176system.cpu.branchPred.BTBLookups 44664544 # Number of BTB lookups 177system.cpu.branchPred.BTBHits 43035053 # Number of BTB hits | 233system.physmem.avgGap 19542726.82 # Average gap between requests 234system.membus.throughput 3274869 # Throughput (bytes/s) 235system.membus.trans_dist::ReadReq 2721 # Transaction distribution 236system.membus.trans_dist::ReadResp 2721 # Transaction distribution 237system.membus.trans_dist::UpgradeReq 2 # Transaction distribution 238system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 239system.membus.trans_dist::ReadExReq 1075 # Transaction distribution 240system.membus.trans_dist::ReadExResp 1075 # Transaction distribution 241system.membus.pkt_count_system.cpu.l2cache.mem_side 7596 # Packet count per connected master and slave (bytes) 242system.membus.pkt_count 7596 # Packet count per connected master and slave (bytes) 243system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 242944 # Cumulative packet size per connected master and slave (bytes) 244system.membus.tot_pkt_size 242944 # Cumulative packet size per connected master and slave (bytes) 245system.membus.data_through_bus 242944 # Total data (bytes) 246system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 247system.membus.reqLayer0.occupancy 4823500 # Layer occupancy (ticks) 248system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 249system.membus.respLayer1.occupancy 35740248 # Layer occupancy (ticks) 250system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 251system.cpu.branchPred.lookups 94757540 # Number of BP lookups 252system.cpu.branchPred.condPredicted 74764818 # Number of conditional branches predicted 253system.cpu.branchPred.condIncorrect 6278340 # Number of conditional branches incorrect 254system.cpu.branchPred.BTBLookups 44654246 # Number of BTB lookups 255system.cpu.branchPred.BTBHits 43033777 # Number of BTB hits |
| 178system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 256system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 179system.cpu.branchPred.BTBHitPct 96.351712 # BTB Hit Percentage 180system.cpu.branchPred.usedRAS 4359745 # Number of times the RAS was used to get a target. 181system.cpu.branchPred.RASInCorrect 88611 # Number of incorrect RAS predictions. | 257system.cpu.branchPred.BTBHitPct 96.371075 # BTB Hit Percentage 258system.cpu.branchPred.usedRAS 4354951 # Number of times the RAS was used to get a target. 259system.cpu.branchPred.RASInCorrect 88346 # Number of incorrect RAS predictions. |
| 182system.cpu.dtb.inst_hits 0 # ITB inst hits 183system.cpu.dtb.inst_misses 0 # ITB inst misses 184system.cpu.dtb.read_hits 0 # DTB read hits 185system.cpu.dtb.read_misses 0 # DTB read misses 186system.cpu.dtb.write_hits 0 # DTB write hits 187system.cpu.dtb.write_misses 0 # DTB write misses 188system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 189system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 217system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 218system.cpu.itb.read_accesses 0 # DTB read accesses 219system.cpu.itb.write_accesses 0 # DTB write accesses 220system.cpu.itb.inst_accesses 0 # ITB inst accesses 221system.cpu.itb.hits 0 # DTB hits 222system.cpu.itb.misses 0 # DTB misses 223system.cpu.itb.accesses 0 # DTB accesses 224system.cpu.workload.num_syscalls 400 # Number of system calls | 260system.cpu.dtb.inst_hits 0 # ITB inst hits 261system.cpu.dtb.inst_misses 0 # ITB inst misses 262system.cpu.dtb.read_hits 0 # DTB read hits 263system.cpu.dtb.read_misses 0 # DTB read misses 264system.cpu.dtb.write_hits 0 # DTB write hits 265system.cpu.dtb.write_misses 0 # DTB write misses 266system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 267system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 295system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 296system.cpu.itb.read_accesses 0 # DTB read accesses 297system.cpu.itb.write_accesses 0 # DTB write accesses 298system.cpu.itb.inst_accesses 0 # ITB inst accesses 299system.cpu.itb.hits 0 # DTB hits 300system.cpu.itb.misses 0 # DTB misses 301system.cpu.itb.accesses 0 # DTB accesses 302system.cpu.workload.num_syscalls 400 # Number of system calls |
| 225system.cpu.numCycles 148314992 # number of cpu cycles simulated | 303system.cpu.numCycles 148368689 # number of cpu cycles simulated |
| 226system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 227system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 304system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 305system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 228system.cpu.fetch.icacheStallCycles 39662414 # Number of cycles fetch is stalled on an Icache miss 229system.cpu.fetch.Insts 380030694 # Number of instructions fetch has processed 230system.cpu.fetch.Branches 94703867 # Number of branches that fetch encountered 231system.cpu.fetch.predictedBranches 47394798 # Number of branches that fetch has predicted taken 232system.cpu.fetch.Cycles 80357293 # Number of cycles fetch has run and was not squashing or blocked 233system.cpu.fetch.SquashCycles 27270600 # Number of cycles fetch has spent squashing 234system.cpu.fetch.BlockedCycles 7200009 # Number of cycles fetch has spent blocked 235system.cpu.fetch.MiscStallCycles 7 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 236system.cpu.fetch.PendingTrapStallCycles 5243 # Number of stall cycles due to pending traps | 306system.cpu.fetch.icacheStallCycles 39647823 # Number of cycles fetch is stalled on an Icache miss 307system.cpu.fetch.Insts 380146219 # Number of instructions fetch has processed 308system.cpu.fetch.Branches 94757540 # Number of branches that fetch encountered 309system.cpu.fetch.predictedBranches 47388728 # Number of branches that fetch has predicted taken 310system.cpu.fetch.Cycles 80358140 # Number of cycles fetch has run and was not squashing or blocked 311system.cpu.fetch.SquashCycles 27268312 # Number of cycles fetch has spent squashing 312system.cpu.fetch.BlockedCycles 7203967 # Number of cycles fetch has spent blocked 313system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 314system.cpu.fetch.PendingTrapStallCycles 5523 # Number of stall cycles due to pending traps |
| 237system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions | 315system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions |
| 238system.cpu.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR 239system.cpu.fetch.CacheLines 36857358 # Number of cache lines fetched 240system.cpu.fetch.IcacheSquashes 1832427 # Number of outstanding Icache misses that were squashed 241system.cpu.fetch.rateDist::samples 148199476 # Number of instructions fetched each cycle (Total) 242system.cpu.fetch.rateDist::mean 2.801422 # Number of instructions fetched each cycle (Total) 243system.cpu.fetch.rateDist::stdev 3.152732 # Number of instructions fetched each cycle (Total) | 316system.cpu.fetch.IcacheWaitRetryStallCycles 69 # Number of stall cycles due to full MSHR 317system.cpu.fetch.CacheLines 36843987 # Number of cache lines fetched 318system.cpu.fetch.IcacheSquashes 1833209 # Number of outstanding Icache misses that were squashed 319system.cpu.fetch.rateDist::samples 148189615 # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.rateDist::mean 2.802214 # Number of instructions fetched each cycle (Total) 321system.cpu.fetch.rateDist::stdev 3.153150 # Number of instructions fetched each cycle (Total) |
| 244system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 322system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 245system.cpu.fetch.rateDist::0 68011684 45.89% 45.89% # Number of instructions fetched each cycle (Total) 246system.cpu.fetch.rateDist::1 5276203 3.56% 49.45% # Number of instructions fetched each cycle (Total) 247system.cpu.fetch.rateDist::2 10540688 7.11% 56.56% # Number of instructions fetched each cycle (Total) 248system.cpu.fetch.rateDist::3 10280783 6.94% 63.50% # Number of instructions fetched each cycle (Total) 249system.cpu.fetch.rateDist::4 8654302 5.84% 69.34% # Number of instructions fetched each cycle (Total) 250system.cpu.fetch.rateDist::5 6554085 4.42% 73.76% # Number of instructions fetched each cycle (Total) 251system.cpu.fetch.rateDist::6 6244651 4.21% 77.98% # Number of instructions fetched each cycle (Total) 252system.cpu.fetch.rateDist::7 7982798 5.39% 83.36% # Number of instructions fetched each cycle (Total) 253system.cpu.fetch.rateDist::8 24654282 16.64% 100.00% # Number of instructions fetched each cycle (Total) | 323system.cpu.fetch.rateDist::0 68000764 45.89% 45.89% # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::1 5268021 3.55% 49.44% # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::2 10540392 7.11% 56.56% # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.rateDist::3 10285161 6.94% 63.50% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::4 8646262 5.83% 69.33% # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::5 6545573 4.42% 73.75% # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::6 6244018 4.21% 77.96% # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::7 7997629 5.40% 83.36% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::8 24661795 16.64% 100.00% # Number of instructions fetched each cycle (Total) |
| 254system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 255system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 256system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 332system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 257system.cpu.fetch.rateDist::total 148199476 # Number of instructions fetched each cycle (Total) 258system.cpu.fetch.branchRate 0.638532 # Number of branch fetches per cycle 259system.cpu.fetch.rate 2.562322 # Number of inst fetches per cycle 260system.cpu.decode.IdleCycles 45512613 # Number of cycles decode is idle 261system.cpu.decode.BlockedCycles 5867522 # Number of cycles decode is blocked 262system.cpu.decode.RunCycles 74797201 # Number of cycles decode is running 263system.cpu.decode.UnblockCycles 1201275 # Number of cycles decode is unblocking 264system.cpu.decode.SquashCycles 20820865 # Number of cycles decode is squashing 265system.cpu.decode.BranchResolved 14305085 # Number of times decode resolved a branch 266system.cpu.decode.BranchMispred 164111 # Number of times decode detected a branch misprediction 267system.cpu.decode.DecodedInsts 392663870 # Number of instructions handled by decode 268system.cpu.decode.SquashedInsts 738369 # Number of squashed instructions handled by decode 269system.cpu.rename.SquashCycles 20820865 # Number of cycles rename is squashing 270system.cpu.rename.IdleCycles 50901215 # Number of cycles rename is idle 271system.cpu.rename.BlockCycles 722150 # Number of cycles rename is blocking 272system.cpu.rename.serializeStallCycles 593982 # count of cycles rename stalled for serializing inst 273system.cpu.rename.RunCycles 70547488 # Number of cycles rename is running 274system.cpu.rename.UnblockCycles 4613776 # Number of cycles rename is unblocking 275system.cpu.rename.RenamedInsts 371203156 # Number of instructions processed by rename 276system.cpu.rename.ROBFullEvents 33 # Number of times rename has blocked due to ROB full 277system.cpu.rename.IQFullEvents 343152 # Number of times rename has blocked due to IQ full 278system.cpu.rename.LSQFullEvents 3655877 # Number of times rename has blocked due to LSQ full 279system.cpu.rename.FullRegisterEvents 29 # Number of times there has been no free registers 280system.cpu.rename.RenamedOperands 631482556 # Number of destination operands rename has renamed 281system.cpu.rename.RenameLookups 1581281661 # Number of register rename lookups that rename has made 282system.cpu.rename.int_rename_lookups 1563963855 # Number of integer rename lookups 283system.cpu.rename.fp_rename_lookups 17317806 # Number of floating rename lookups | 335system.cpu.fetch.rateDist::total 148189615 # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.branchRate 0.638663 # Number of branch fetches per cycle 337system.cpu.fetch.rate 2.562173 # Number of inst fetches per cycle 338system.cpu.decode.IdleCycles 45498061 # Number of cycles decode is idle 339system.cpu.decode.BlockedCycles 5874830 # Number of cycles decode is blocked 340system.cpu.decode.RunCycles 74793705 # Number of cycles decode is running 341system.cpu.decode.UnblockCycles 1202536 # Number of cycles decode is unblocking 342system.cpu.decode.SquashCycles 20820483 # Number of cycles decode is squashing 343system.cpu.decode.BranchResolved 14321847 # Number of times decode resolved a branch 344system.cpu.decode.BranchMispred 164416 # Number of times decode detected a branch misprediction 345system.cpu.decode.DecodedInsts 392715815 # Number of instructions handled by decode 346system.cpu.decode.SquashedInsts 749819 # Number of squashed instructions handled by decode 347system.cpu.rename.SquashCycles 20820483 # Number of cycles rename is squashing 348system.cpu.rename.IdleCycles 50886064 # Number of cycles rename is idle 349system.cpu.rename.BlockCycles 722985 # Number of cycles rename is blocking 350system.cpu.rename.serializeStallCycles 600307 # count of cycles rename stalled for serializing inst 351system.cpu.rename.RunCycles 70546117 # Number of cycles rename is running 352system.cpu.rename.UnblockCycles 4613659 # Number of cycles rename is unblocking 353system.cpu.rename.RenamedInsts 371260855 # Number of instructions processed by rename 354system.cpu.rename.ROBFullEvents 69 # Number of times rename has blocked due to ROB full 355system.cpu.rename.IQFullEvents 344235 # Number of times rename has blocked due to IQ full 356system.cpu.rename.LSQFullEvents 3657023 # Number of times rename has blocked due to LSQ full 357system.cpu.rename.FullRegisterEvents 27 # Number of times there has been no free registers 358system.cpu.rename.RenamedOperands 631666093 # Number of destination operands rename has renamed 359system.cpu.rename.RenameLookups 1581493948 # Number of register rename lookups that rename has made 360system.cpu.rename.int_rename_lookups 1564155420 # Number of integer rename lookups 361system.cpu.rename.fp_rename_lookups 17338528 # Number of floating rename lookups |
| 284system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed | 362system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed |
| 285system.cpu.rename.UndoneMaps 333438417 # Number of HB maps that are undone due to squashing 286system.cpu.rename.serializingInsts 25133 # count of serializing insts renamed 287system.cpu.rename.tempSerializingInsts 25129 # count of temporary serializing insts renamed 288system.cpu.rename.skidInsts 13026907 # count of insts added to the skid buffer 289system.cpu.memDep0.insertedLoads 42996111 # Number of loads inserted to the mem dependence unit. 290system.cpu.memDep0.insertedStores 16422667 # Number of stores inserted to the mem dependence unit. 291system.cpu.memDep0.conflictingLoads 5676383 # Number of conflicting loads. 292system.cpu.memDep0.conflictingStores 3667621 # Number of conflicting stores. 293system.cpu.iq.iqInstsAdded 329112708 # Number of instructions added to the IQ (excludes non-spec) 294system.cpu.iq.iqNonSpecInstsAdded 47143 # Number of non-speculative instructions added to the IQ 295system.cpu.iq.iqInstsIssued 249432965 # Number of instructions issued 296system.cpu.iq.iqSquashedInstsIssued 790911 # Number of squashed instructions issued 297system.cpu.iq.iqSquashedInstsExamined 139431014 # Number of squashed instructions iterated over during squash; mainly for profiling 298system.cpu.iq.iqSquashedOperandsExamined 361763997 # Number of squashed operands that are examined and possibly removed from graph 299system.cpu.iq.iqSquashedNonSpecRemoved 1927 # Number of squashed non-spec instructions that were removed 300system.cpu.iq.issued_per_cycle::samples 148199476 # Number of insts issued each cycle 301system.cpu.iq.issued_per_cycle::mean 1.683089 # Number of insts issued each cycle 302system.cpu.iq.issued_per_cycle::stdev 1.761808 # Number of insts issued each cycle | 363system.cpu.rename.UndoneMaps 333621954 # Number of HB maps that are undone due to squashing 364system.cpu.rename.serializingInsts 25182 # count of serializing insts renamed 365system.cpu.rename.tempSerializingInsts 25179 # count of temporary serializing insts renamed 366system.cpu.rename.skidInsts 13028807 # count of insts added to the skid buffer 367system.cpu.memDep0.insertedLoads 42981884 # Number of loads inserted to the mem dependence unit. 368system.cpu.memDep0.insertedStores 16417977 # Number of stores inserted to the mem dependence unit. 369system.cpu.memDep0.conflictingLoads 5680787 # Number of conflicting loads. 370system.cpu.memDep0.conflictingStores 3667947 # Number of conflicting stores. 371system.cpu.iq.iqInstsAdded 329134626 # Number of instructions added to the IQ (excludes non-spec) 372system.cpu.iq.iqNonSpecInstsAdded 47203 # Number of non-speculative instructions added to the IQ 373system.cpu.iq.iqInstsIssued 249422621 # Number of instructions issued 374system.cpu.iq.iqSquashedInstsIssued 787073 # Number of squashed instructions issued 375system.cpu.iq.iqSquashedInstsExamined 139456652 # Number of squashed instructions iterated over during squash; mainly for profiling 376system.cpu.iq.iqSquashedOperandsExamined 361881130 # Number of squashed operands that are examined and possibly removed from graph 377system.cpu.iq.iqSquashedNonSpecRemoved 1987 # Number of squashed non-spec instructions that were removed 378system.cpu.iq.issued_per_cycle::samples 148189615 # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::mean 1.683132 # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::stdev 1.761818 # Number of insts issued each cycle |
| 303system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 381system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 304system.cpu.iq.issued_per_cycle::0 56042939 37.82% 37.82% # Number of insts issued each cycle 305system.cpu.iq.issued_per_cycle::1 22629719 15.27% 53.09% # Number of insts issued each cycle 306system.cpu.iq.issued_per_cycle::2 24820832 16.75% 69.83% # Number of insts issued each cycle 307system.cpu.iq.issued_per_cycle::3 20320046 13.71% 83.55% # Number of insts issued each cycle 308system.cpu.iq.issued_per_cycle::4 12535804 8.46% 92.00% # Number of insts issued each cycle 309system.cpu.iq.issued_per_cycle::5 6521757 4.40% 96.40% # Number of insts issued each cycle 310system.cpu.iq.issued_per_cycle::6 4030887 2.72% 99.12% # Number of insts issued each cycle 311system.cpu.iq.issued_per_cycle::7 1115815 0.75% 99.88% # Number of insts issued each cycle 312system.cpu.iq.issued_per_cycle::8 181677 0.12% 100.00% # Number of insts issued each cycle | 382system.cpu.iq.issued_per_cycle::0 56042296 37.82% 37.82% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::1 22626121 15.27% 53.09% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::2 24808060 16.74% 69.83% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::3 20320875 13.71% 83.54% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::4 12548887 8.47% 92.01% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::5 6516147 4.40% 96.41% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::6 4031410 2.72% 99.13% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::7 1113540 0.75% 99.88% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::8 182279 0.12% 100.00% # Number of insts issued each cycle |
| 313system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 314system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 315system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 391system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 316system.cpu.iq.issued_per_cycle::total 148199476 # Number of insts issued each cycle | 394system.cpu.iq.issued_per_cycle::total 148189615 # Number of insts issued each cycle |
| 317system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 395system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 318system.cpu.iq.fu_full::IntAlu 963057 38.38% 38.38% # attempts to use FU when none available 319system.cpu.iq.fu_full::IntMult 5596 0.22% 38.60% # attempts to use FU when none available 320system.cpu.iq.fu_full::IntDiv 0 0.00% 38.60% # attempts to use FU when none available 321system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.60% # attempts to use FU when none available 322system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.60% # attempts to use FU when none available 323system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.60% # attempts to use FU when none available 324system.cpu.iq.fu_full::FloatMult 0 0.00% 38.60% # attempts to use FU when none available 325system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.60% # attempts to use FU when none available 326system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.60% # attempts to use FU when none available 327system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.60% # attempts to use FU when none available 328system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.60% # attempts to use FU when none available 329system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.60% # attempts to use FU when none available 330system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.60% # attempts to use FU when none available 331system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.60% # attempts to use FU when none available 332system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.60% # attempts to use FU when none available 333system.cpu.iq.fu_full::SimdMult 0 0.00% 38.60% # attempts to use FU when none available 334system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.60% # attempts to use FU when none available 335system.cpu.iq.fu_full::SimdShift 0 0.00% 38.60% # attempts to use FU when none available 336system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.60% # attempts to use FU when none available 337system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.60% # attempts to use FU when none available 338system.cpu.iq.fu_full::SimdFloatAdd 101 0.00% 38.60% # attempts to use FU when none available 339system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.60% # attempts to use FU when none available 340system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.60% # attempts to use FU when none available 341system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.60% # attempts to use FU when none available 342system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.60% # attempts to use FU when none available 343system.cpu.iq.fu_full::SimdFloatMisc 51 0.00% 38.61% # attempts to use FU when none available 344system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.61% # attempts to use FU when none available 345system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.61% # attempts to use FU when none available 346system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.61% # attempts to use FU when none available 347system.cpu.iq.fu_full::MemRead 1167699 46.53% 85.14% # attempts to use FU when none available 348system.cpu.iq.fu_full::MemWrite 372909 14.86% 100.00% # attempts to use FU when none available | 396system.cpu.iq.fu_full::IntAlu 962595 38.42% 38.42% # attempts to use FU when none available 397system.cpu.iq.fu_full::IntMult 5594 0.22% 38.65% # attempts to use FU when none available 398system.cpu.iq.fu_full::IntDiv 0 0.00% 38.65% # attempts to use FU when none available 399system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.65% # attempts to use FU when none available 400system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.65% # attempts to use FU when none available 401system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.65% # attempts to use FU when none available 402system.cpu.iq.fu_full::FloatMult 0 0.00% 38.65% # attempts to use FU when none available 403system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.65% # attempts to use FU when none available 404system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.65% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.65% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.65% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.65% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.65% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.65% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.65% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdMult 0 0.00% 38.65% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.65% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdShift 0 0.00% 38.65% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.65% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.65% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdFloatAdd 107 0.00% 38.65% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.65% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.65% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.65% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.65% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.65% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.65% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.65% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.65% # attempts to use FU when none available 425system.cpu.iq.fu_full::MemRead 1164588 46.49% 85.14% # attempts to use FU when none available 426system.cpu.iq.fu_full::MemWrite 372359 14.86% 100.00% # attempts to use FU when none available |
| 349system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 350system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 351system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 427system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 428system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 429system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 352system.cpu.iq.FU_type_0::IntAlu 194880762 78.13% 78.13% # Type of FU issued 353system.cpu.iq.FU_type_0::IntMult 980286 0.39% 78.52% # Type of FU issued 354system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued 355system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued 356system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued 357system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.52% # Type of FU issued 358system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.52% # Type of FU issued 359system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.52% # Type of FU issued 360system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.52% # Type of FU issued 361system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.52% # Type of FU issued 362system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.52% # Type of FU issued 363system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.52% # Type of FU issued 364system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.52% # Type of FU issued 365system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.52% # Type of FU issued 366system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.52% # Type of FU issued 367system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.52% # Type of FU issued 368system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Type of FU issued 369system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued 370system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued 371system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued 372system.cpu.iq.FU_type_0::SimdFloatAdd 33071 0.01% 78.54% # Type of FU issued | 430system.cpu.iq.FU_type_0::IntAlu 194884583 78.13% 78.13% # Type of FU issued 431system.cpu.iq.FU_type_0::IntMult 979638 0.39% 78.53% # Type of FU issued 432system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.53% # Type of FU issued 433system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.53% # Type of FU issued 434system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.53% # Type of FU issued 435system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.53% # Type of FU issued 436system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.53% # Type of FU issued 437system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.53% # Type of FU issued 438system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.53% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.53% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.53% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.53% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.53% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.53% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.53% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.53% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.53% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.53% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.53% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.53% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdFloatAdd 33073 0.01% 78.54% # Type of FU issued |
| 373system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.54% # Type of FU issued | 451system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.54% # Type of FU issued |
| 374system.cpu.iq.FU_type_0::SimdFloatCmp 164429 0.07% 78.60% # Type of FU issued 375system.cpu.iq.FU_type_0::SimdFloatCvt 254305 0.10% 78.70% # Type of FU issued 376system.cpu.iq.FU_type_0::SimdFloatDiv 76429 0.03% 78.73% # Type of FU issued 377system.cpu.iq.FU_type_0::SimdFloatMisc 465674 0.19% 78.92% # Type of FU issued 378system.cpu.iq.FU_type_0::SimdFloatMult 206396 0.08% 79.00% # Type of FU issued 379system.cpu.iq.FU_type_0::SimdFloatMultAcc 71854 0.03% 79.03% # Type of FU issued 380system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued 381system.cpu.iq.FU_type_0::MemRead 38348799 15.37% 94.41% # Type of FU issued 382system.cpu.iq.FU_type_0::MemWrite 13950639 5.59% 100.00% # Type of FU issued | 452system.cpu.iq.FU_type_0::SimdFloatCmp 164452 0.07% 78.61% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatCvt 254844 0.10% 78.71% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatDiv 76427 0.03% 78.74% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatMisc 465912 0.19% 78.93% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdFloatMult 206449 0.08% 79.01% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdFloatMultAcc 71875 0.03% 79.04% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdFloatSqrt 323 0.00% 79.04% # Type of FU issued 459system.cpu.iq.FU_type_0::MemRead 38337954 15.37% 94.41% # Type of FU issued 460system.cpu.iq.FU_type_0::MemWrite 13947091 5.59% 100.00% # Type of FU issued |
| 383system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 384system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 461system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 462system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 385system.cpu.iq.FU_type_0::total 249432965 # Type of FU issued 386system.cpu.iq.rate 1.681779 # Inst issue rate 387system.cpu.iq.fu_busy_cnt 2509413 # FU busy when requested 388system.cpu.iq.fu_busy_rate 0.010060 # FU busy rate (busy events/executed inst) 389system.cpu.iq.int_inst_queue_reads 646629225 # Number of integer instruction queue reads 390system.cpu.iq.int_inst_queue_writes 466421271 # Number of integer instruction queue writes 391system.cpu.iq.int_inst_queue_wakeup_accesses 237868779 # Number of integer instruction queue wakeup accesses 392system.cpu.iq.fp_inst_queue_reads 3736505 # Number of floating instruction queue reads 393system.cpu.iq.fp_inst_queue_writes 2188097 # Number of floating instruction queue writes 394system.cpu.iq.fp_inst_queue_wakeup_accesses 1840763 # Number of floating instruction queue wakeup accesses 395system.cpu.iq.int_alu_accesses 250067463 # Number of integer alu accesses 396system.cpu.iq.fp_alu_accesses 1874915 # Number of floating point alu accesses 397system.cpu.iew.lsq.thread0.forwLoads 2006857 # Number of loads that had data forwarded from stores | 463system.cpu.iq.FU_type_0::total 249422621 # Type of FU issued 464system.cpu.iq.rate 1.681100 # Inst issue rate 465system.cpu.iq.fu_busy_cnt 2505291 # FU busy when requested 466system.cpu.iq.fu_busy_rate 0.010044 # FU busy rate (busy events/executed inst) 467system.cpu.iq.int_inst_queue_reads 646588556 # Number of integer instruction queue reads 468system.cpu.iq.int_inst_queue_writes 466464832 # Number of integer instruction queue writes 469system.cpu.iq.int_inst_queue_wakeup_accesses 237860517 # Number of integer instruction queue wakeup accesses 470system.cpu.iq.fp_inst_queue_reads 3738665 # Number of floating instruction queue reads 471system.cpu.iq.fp_inst_queue_writes 2192143 # Number of floating instruction queue writes 472system.cpu.iq.fp_inst_queue_wakeup_accesses 1842020 # Number of floating instruction queue wakeup accesses 473system.cpu.iq.int_alu_accesses 250052019 # Number of integer alu accesses 474system.cpu.iq.fp_alu_accesses 1875893 # Number of floating point alu accesses 475system.cpu.iew.lsq.thread0.forwLoads 2007355 # Number of loads that had data forwarded from stores |
| 398system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 476system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 399system.cpu.iew.lsq.thread0.squashedLoads 13146627 # Number of loads squashed 400system.cpu.iew.lsq.thread0.ignoredResponses 11917 # Number of memory responses ignored because the instruction is squashed 401system.cpu.iew.lsq.thread0.memOrderViolation 18980 # Number of memory ordering violations 402system.cpu.iew.lsq.thread0.squashedStores 3778033 # Number of stores squashed | 477system.cpu.iew.lsq.thread0.squashedLoads 13132400 # Number of loads squashed 478system.cpu.iew.lsq.thread0.ignoredResponses 11727 # Number of memory responses ignored because the instruction is squashed 479system.cpu.iew.lsq.thread0.memOrderViolation 18993 # Number of memory ordering violations 480system.cpu.iew.lsq.thread0.squashedStores 3773343 # Number of stores squashed |
| 403system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 404system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 481system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 482system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 405system.cpu.iew.lsq.thread0.rescheduledLoads 10 # Number of loads that were rescheduled | 483system.cpu.iew.lsq.thread0.rescheduledLoads 13 # Number of loads that were rescheduled |
| 406system.cpu.iew.lsq.thread0.cacheBlocked 104 # Number of times an access to memory failed due to the cache being blocked 407system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 484system.cpu.iew.lsq.thread0.cacheBlocked 104 # Number of times an access to memory failed due to the cache being blocked 485system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 408system.cpu.iew.iewSquashCycles 20820865 # Number of cycles IEW is squashing 409system.cpu.iew.iewBlockCycles 17088 # Number of cycles IEW is blocking 410system.cpu.iew.iewUnblockCycles 846 # Number of cycles IEW is unblocking 411system.cpu.iew.iewDispatchedInsts 329176829 # Number of instructions dispatched to IQ 412system.cpu.iew.iewDispSquashedInsts 784787 # Number of squashed instructions skipped by dispatch 413system.cpu.iew.iewDispLoadInsts 42996111 # Number of dispatched load instructions 414system.cpu.iew.iewDispStoreInsts 16422667 # Number of dispatched store instructions 415system.cpu.iew.iewDispNonSpecInsts 24735 # Number of dispatched non-speculative instructions 416system.cpu.iew.iewIQFullEvents 188 # Number of times the IQ has become full, causing a stall 417system.cpu.iew.iewLSQFullEvents 265 # Number of times the LSQ has become full, causing a stall 418system.cpu.iew.memOrderViolationEvents 18980 # Number of memory order violations 419system.cpu.iew.predictedTakenIncorrect 3891833 # Number of branches that were predicted taken incorrectly 420system.cpu.iew.predictedNotTakenIncorrect 3757719 # Number of branches that were predicted not taken incorrectly 421system.cpu.iew.branchMispredicts 7649552 # Number of branch mispredicts detected at execute 422system.cpu.iew.iewExecutedInsts 242934999 # Number of executed instructions 423system.cpu.iew.iewExecLoadInsts 36843669 # Number of load instructions executed 424system.cpu.iew.iewExecSquashedInsts 6497966 # Number of squashed instructions skipped in execute | 486system.cpu.iew.iewSquashCycles 20820483 # Number of cycles IEW is squashing 487system.cpu.iew.iewBlockCycles 18849 # Number of cycles IEW is blocking 488system.cpu.iew.iewUnblockCycles 902 # Number of cycles IEW is unblocking 489system.cpu.iew.iewDispatchedInsts 329198829 # Number of instructions dispatched to IQ 490system.cpu.iew.iewDispSquashedInsts 786805 # Number of squashed instructions skipped by dispatch 491system.cpu.iew.iewDispLoadInsts 42981884 # Number of dispatched load instructions 492system.cpu.iew.iewDispStoreInsts 16417977 # Number of dispatched store instructions 493system.cpu.iew.iewDispNonSpecInsts 24795 # Number of dispatched non-speculative instructions 494system.cpu.iew.iewIQFullEvents 191 # Number of times the IQ has become full, causing a stall 495system.cpu.iew.iewLSQFullEvents 274 # Number of times the LSQ has become full, causing a stall 496system.cpu.iew.memOrderViolationEvents 18993 # Number of memory order violations 497system.cpu.iew.predictedTakenIncorrect 3888167 # Number of branches that were predicted taken incorrectly 498system.cpu.iew.predictedNotTakenIncorrect 3760327 # Number of branches that were predicted not taken incorrectly 499system.cpu.iew.branchMispredicts 7648494 # Number of branch mispredicts detected at execute 500system.cpu.iew.iewExecutedInsts 242926605 # Number of executed instructions 501system.cpu.iew.iewExecLoadInsts 36835264 # Number of load instructions executed 502system.cpu.iew.iewExecSquashedInsts 6496016 # Number of squashed instructions skipped in execute |
| 425system.cpu.iew.exec_swp 0 # number of swp insts executed | 503system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 426system.cpu.iew.exec_nop 16978 # number of nop insts executed 427system.cpu.iew.exec_refs 50492106 # number of memory reference insts executed 428system.cpu.iew.exec_branches 53412943 # Number of branches executed 429system.cpu.iew.exec_stores 13648437 # Number of stores executed 430system.cpu.iew.exec_rate 1.637967 # Inst execution rate 431system.cpu.iew.wb_sent 240767037 # cumulative count of insts sent to commit 432system.cpu.iew.wb_count 239709542 # cumulative count of insts written-back 433system.cpu.iew.wb_producers 148457899 # num instructions producing a value 434system.cpu.iew.wb_consumers 267241195 # num instructions consuming a value | 504system.cpu.iew.exec_nop 17000 # number of nop insts executed 505system.cpu.iew.exec_refs 50481074 # number of memory reference insts executed 506system.cpu.iew.exec_branches 53424163 # Number of branches executed 507system.cpu.iew.exec_stores 13645810 # Number of stores executed 508system.cpu.iew.exec_rate 1.637317 # Inst execution rate 509system.cpu.iew.wb_sent 240758455 # cumulative count of insts sent to commit 510system.cpu.iew.wb_count 239702537 # cumulative count of insts written-back 511system.cpu.iew.wb_producers 148455856 # num instructions producing a value 512system.cpu.iew.wb_consumers 267256641 # num instructions consuming a value |
| 435system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 513system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 436system.cpu.iew.wb_rate 1.616219 # insts written-back per cycle 437system.cpu.iew.wb_fanout 0.555520 # average fanout of values written-back | 514system.cpu.iew.wb_rate 1.615587 # insts written-back per cycle 515system.cpu.iew.wb_fanout 0.555481 # average fanout of values written-back |
| 438system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 516system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 439system.cpu.commit.commitSquashedInsts 140505920 # The number of squashed insts skipped by commit | 517system.cpu.commit.commitSquashedInsts 140527929 # The number of squashed insts skipped by commit |
| 440system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards | 518system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards |
| 441system.cpu.commit.branchMispredicts 6126595 # The number of times a branch was mispredicted 442system.cpu.commit.committed_per_cycle::samples 127378611 # Number of insts commited each cycle 443system.cpu.commit.committed_per_cycle::mean 1.481182 # Number of insts commited each cycle 444system.cpu.commit.committed_per_cycle::stdev 2.186353 # Number of insts commited each cycle | 519system.cpu.commit.branchMispredicts 6124743 # The number of times a branch was mispredicted 520system.cpu.commit.committed_per_cycle::samples 127369132 # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::mean 1.481292 # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::stdev 2.186316 # Number of insts commited each cycle |
| 445system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 523system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 446system.cpu.commit.committed_per_cycle::0 57698651 45.30% 45.30% # Number of insts commited each cycle 447system.cpu.commit.committed_per_cycle::1 31675595 24.87% 70.16% # Number of insts commited each cycle 448system.cpu.commit.committed_per_cycle::2 13783953 10.82% 80.99% # Number of insts commited each cycle 449system.cpu.commit.committed_per_cycle::3 7631475 5.99% 86.98% # Number of insts commited each cycle 450system.cpu.commit.committed_per_cycle::4 4374952 3.43% 90.41% # Number of insts commited each cycle 451system.cpu.commit.committed_per_cycle::5 1321227 1.04% 91.45% # Number of insts commited each cycle 452system.cpu.commit.committed_per_cycle::6 1703973 1.34% 92.79% # Number of insts commited each cycle 453system.cpu.commit.committed_per_cycle::7 1307096 1.03% 93.81% # Number of insts commited each cycle 454system.cpu.commit.committed_per_cycle::8 7881689 6.19% 100.00% # Number of insts commited each cycle | 524system.cpu.commit.committed_per_cycle::0 57689921 45.29% 45.29% # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::1 31670367 24.87% 70.16% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::2 13785643 10.82% 80.98% # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::3 7636266 6.00% 86.98% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::4 4374586 3.43% 90.41% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::5 1321093 1.04% 91.45% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::6 1699680 1.33% 92.78% # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::7 1314057 1.03% 93.82% # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::8 7877519 6.18% 100.00% # Number of insts commited each cycle |
| 455system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 456system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 457system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 533system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 534system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 458system.cpu.commit.committed_per_cycle::total 127378611 # Number of insts commited each cycle | 536system.cpu.commit.committed_per_cycle::total 127369132 # Number of insts commited each cycle |
| 459system.cpu.commit.committedInsts 172317409 # Number of instructions committed 460system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed 461system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 462system.cpu.commit.refs 42494118 # Number of memory references committed 463system.cpu.commit.loads 29849484 # Number of loads committed 464system.cpu.commit.membars 22408 # Number of memory barriers committed 465system.cpu.commit.branches 40300311 # Number of branches committed 466system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. 467system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. 468system.cpu.commit.function_calls 1848934 # Number of function calls committed. | 537system.cpu.commit.committedInsts 172317409 # Number of instructions committed 538system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed 539system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 540system.cpu.commit.refs 42494118 # Number of memory references committed 541system.cpu.commit.loads 29849484 # Number of loads committed 542system.cpu.commit.membars 22408 # Number of memory barriers committed 543system.cpu.commit.branches 40300311 # Number of branches committed 544system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. 545system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. 546system.cpu.commit.function_calls 1848934 # Number of function calls committed. |
| 469system.cpu.commit.bw_lim_events 7881689 # number cycles where commit BW limit reached | 547system.cpu.commit.bw_lim_events 7877519 # number cycles where commit BW limit reached |
| 470system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 548system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 471system.cpu.rob.rob_reads 448668532 # The number of ROB reads 472system.cpu.rob.rob_writes 679284219 # The number of ROB writes 473system.cpu.timesIdled 2567 # Number of times that the entire CPU went into an idle state and unscheduled itself 474system.cpu.idleCycles 115516 # Total number of cycles that the CPU has spent unscheduled due to idling | 549system.cpu.rob.rob_reads 448685232 # The number of ROB reads 550system.cpu.rob.rob_writes 679327064 # The number of ROB writes 551system.cpu.timesIdled 2810 # Number of times that the entire CPU went into an idle state and unscheduled itself 552system.cpu.idleCycles 179074 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 475system.cpu.committedInsts 172303021 # Number of Instructions Simulated 476system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated 477system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated | 553system.cpu.committedInsts 172303021 # Number of Instructions Simulated 554system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated 555system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated |
| 478system.cpu.cpi 0.860780 # CPI: Cycles Per Instruction 479system.cpu.cpi_total 0.860780 # CPI: Total CPI of All Threads 480system.cpu.ipc 1.161737 # IPC: Instructions Per Cycle 481system.cpu.ipc_total 1.161737 # IPC: Total IPC of All Threads 482system.cpu.int_regfile_reads 1079304778 # number of integer regfile reads 483system.cpu.int_regfile_writes 384845307 # number of integer regfile writes 484system.cpu.fp_regfile_reads 2912671 # number of floating regfile reads 485system.cpu.fp_regfile_writes 2496150 # number of floating regfile writes 486system.cpu.misc_regfile_reads 54492663 # number of misc regfile reads | 556system.cpu.cpi 0.861092 # CPI: Cycles Per Instruction 557system.cpu.cpi_total 0.861092 # CPI: Total CPI of All Threads 558system.cpu.ipc 1.161317 # IPC: Instructions Per Cycle 559system.cpu.ipc_total 1.161317 # IPC: Total IPC of All Threads 560system.cpu.int_regfile_reads 1079239284 # number of integer regfile reads 561system.cpu.int_regfile_writes 384835773 # number of integer regfile writes 562system.cpu.fp_regfile_reads 2913699 # number of floating regfile reads 563system.cpu.fp_regfile_writes 2498274 # number of floating regfile writes 564system.cpu.misc_regfile_reads 54487026 # number of misc regfile reads |
| 487system.cpu.misc_regfile_writes 820036 # number of misc regfile writes | 565system.cpu.misc_regfile_writes 820036 # number of misc regfile writes |
| 488system.cpu.icache.replacements 2376 # number of replacements 489system.cpu.icache.tagsinuse 1350.566241 # Cycle average of tags in use 490system.cpu.icache.total_refs 36852122 # Total number of references to valid blocks. 491system.cpu.icache.sampled_refs 4106 # Sample count of references to valid blocks. 492system.cpu.icache.avg_refs 8975.188018 # Average number of references to valid blocks. | 566system.cpu.toL2Bus.throughput 5142648 # Throughput (bytes/s) 567system.cpu.toL2Bus.trans_dist::ReadReq 4861 # Transaction distribution 568system.cpu.toL2Bus.trans_dist::ReadResp 4861 # Transaction distribution 569system.cpu.toL2Bus.trans_dist::Writeback 17 # Transaction distribution 570system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution 571system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution 572system.cpu.toL2Bus.trans_dist::ReadExReq 1083 # Transaction distribution 573system.cpu.toL2Bus.trans_dist::ReadExResp 1083 # Transaction distribution 574system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 8180 # Packet count per connected master and slave (bytes) 575system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3727 # Packet count per connected master and slave (bytes) 576system.cpu.toL2Bus.pkt_count 11907 # Packet count per connected master and slave (bytes) 577system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 261696 # Cumulative packet size per connected master and slave (bytes) 578system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 119680 # Cumulative packet size per connected master and slave (bytes) 579system.cpu.toL2Bus.tot_pkt_size 381376 # Cumulative packet size per connected master and slave (bytes) 580system.cpu.toL2Bus.data_through_bus 381376 # Total data (bytes) 581system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes) 582system.cpu.toL2Bus.reqLayer0.occupancy 2998500 # Layer occupancy (ticks) 583system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 584system.cpu.toL2Bus.respLayer0.occupancy 6138496 # Layer occupancy (ticks) 585system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 586system.cpu.toL2Bus.respLayer1.occupancy 2786987 # Layer occupancy (ticks) 587system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 588system.cpu.icache.replacements 2359 # number of replacements 589system.cpu.icache.tagsinuse 1350.344535 # Cycle average of tags in use 590system.cpu.icache.total_refs 36838706 # Total number of references to valid blocks. 591system.cpu.icache.sampled_refs 4089 # Sample count of references to valid blocks. 592system.cpu.icache.avg_refs 9009.221326 # Average number of references to valid blocks. |
| 493system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 593system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 494system.cpu.icache.occ_blocks::cpu.inst 1350.566241 # Average occupied blocks per requestor 495system.cpu.icache.occ_percent::cpu.inst 0.659456 # Average percentage of cache occupancy 496system.cpu.icache.occ_percent::total 0.659456 # Average percentage of cache occupancy 497system.cpu.icache.ReadReq_hits::cpu.inst 36852123 # number of ReadReq hits 498system.cpu.icache.ReadReq_hits::total 36852123 # number of ReadReq hits 499system.cpu.icache.demand_hits::cpu.inst 36852123 # number of demand (read+write) hits 500system.cpu.icache.demand_hits::total 36852123 # number of demand (read+write) hits 501system.cpu.icache.overall_hits::cpu.inst 36852123 # number of overall hits 502system.cpu.icache.overall_hits::total 36852123 # number of overall hits 503system.cpu.icache.ReadReq_misses::cpu.inst 5235 # number of ReadReq misses 504system.cpu.icache.ReadReq_misses::total 5235 # number of ReadReq misses 505system.cpu.icache.demand_misses::cpu.inst 5235 # number of demand (read+write) misses 506system.cpu.icache.demand_misses::total 5235 # number of demand (read+write) misses 507system.cpu.icache.overall_misses::cpu.inst 5235 # number of overall misses 508system.cpu.icache.overall_misses::total 5235 # number of overall misses 509system.cpu.icache.ReadReq_miss_latency::cpu.inst 167149000 # number of ReadReq miss cycles 510system.cpu.icache.ReadReq_miss_latency::total 167149000 # number of ReadReq miss cycles 511system.cpu.icache.demand_miss_latency::cpu.inst 167149000 # number of demand (read+write) miss cycles 512system.cpu.icache.demand_miss_latency::total 167149000 # number of demand (read+write) miss cycles 513system.cpu.icache.overall_miss_latency::cpu.inst 167149000 # number of overall miss cycles 514system.cpu.icache.overall_miss_latency::total 167149000 # number of overall miss cycles 515system.cpu.icache.ReadReq_accesses::cpu.inst 36857358 # number of ReadReq accesses(hits+misses) 516system.cpu.icache.ReadReq_accesses::total 36857358 # number of ReadReq accesses(hits+misses) 517system.cpu.icache.demand_accesses::cpu.inst 36857358 # number of demand (read+write) accesses 518system.cpu.icache.demand_accesses::total 36857358 # number of demand (read+write) accesses 519system.cpu.icache.overall_accesses::cpu.inst 36857358 # number of overall (read+write) accesses 520system.cpu.icache.overall_accesses::total 36857358 # number of overall (read+write) accesses 521system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000142 # miss rate for ReadReq accesses 522system.cpu.icache.ReadReq_miss_rate::total 0.000142 # miss rate for ReadReq accesses 523system.cpu.icache.demand_miss_rate::cpu.inst 0.000142 # miss rate for demand accesses 524system.cpu.icache.demand_miss_rate::total 0.000142 # miss rate for demand accesses 525system.cpu.icache.overall_miss_rate::cpu.inst 0.000142 # miss rate for overall accesses 526system.cpu.icache.overall_miss_rate::total 0.000142 # miss rate for overall accesses 527system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31929.130850 # average ReadReq miss latency 528system.cpu.icache.ReadReq_avg_miss_latency::total 31929.130850 # average ReadReq miss latency 529system.cpu.icache.demand_avg_miss_latency::cpu.inst 31929.130850 # average overall miss latency 530system.cpu.icache.demand_avg_miss_latency::total 31929.130850 # average overall miss latency 531system.cpu.icache.overall_avg_miss_latency::cpu.inst 31929.130850 # average overall miss latency 532system.cpu.icache.overall_avg_miss_latency::total 31929.130850 # average overall miss latency 533system.cpu.icache.blocked_cycles::no_mshrs 608 # number of cycles access was blocked | 594system.cpu.icache.occ_blocks::cpu.inst 1350.344535 # Average occupied blocks per requestor 595system.cpu.icache.occ_percent::cpu.inst 0.659348 # Average percentage of cache occupancy 596system.cpu.icache.occ_percent::total 0.659348 # Average percentage of cache occupancy 597system.cpu.icache.ReadReq_hits::cpu.inst 36838706 # number of ReadReq hits 598system.cpu.icache.ReadReq_hits::total 36838706 # number of ReadReq hits 599system.cpu.icache.demand_hits::cpu.inst 36838706 # number of demand (read+write) hits 600system.cpu.icache.demand_hits::total 36838706 # number of demand (read+write) hits 601system.cpu.icache.overall_hits::cpu.inst 36838706 # number of overall hits 602system.cpu.icache.overall_hits::total 36838706 # number of overall hits 603system.cpu.icache.ReadReq_misses::cpu.inst 5281 # number of ReadReq misses 604system.cpu.icache.ReadReq_misses::total 5281 # number of ReadReq misses 605system.cpu.icache.demand_misses::cpu.inst 5281 # number of demand (read+write) misses 606system.cpu.icache.demand_misses::total 5281 # number of demand (read+write) misses 607system.cpu.icache.overall_misses::cpu.inst 5281 # number of overall misses 608system.cpu.icache.overall_misses::total 5281 # number of overall misses 609system.cpu.icache.ReadReq_miss_latency::cpu.inst 212968998 # number of ReadReq miss cycles 610system.cpu.icache.ReadReq_miss_latency::total 212968998 # number of ReadReq miss cycles 611system.cpu.icache.demand_miss_latency::cpu.inst 212968998 # number of demand (read+write) miss cycles 612system.cpu.icache.demand_miss_latency::total 212968998 # number of demand (read+write) miss cycles 613system.cpu.icache.overall_miss_latency::cpu.inst 212968998 # number of overall miss cycles 614system.cpu.icache.overall_miss_latency::total 212968998 # number of overall miss cycles 615system.cpu.icache.ReadReq_accesses::cpu.inst 36843987 # number of ReadReq accesses(hits+misses) 616system.cpu.icache.ReadReq_accesses::total 36843987 # number of ReadReq accesses(hits+misses) 617system.cpu.icache.demand_accesses::cpu.inst 36843987 # number of demand (read+write) accesses 618system.cpu.icache.demand_accesses::total 36843987 # number of demand (read+write) accesses 619system.cpu.icache.overall_accesses::cpu.inst 36843987 # number of overall (read+write) accesses 620system.cpu.icache.overall_accesses::total 36843987 # number of overall (read+write) accesses 621system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000143 # miss rate for ReadReq accesses 622system.cpu.icache.ReadReq_miss_rate::total 0.000143 # miss rate for ReadReq accesses 623system.cpu.icache.demand_miss_rate::cpu.inst 0.000143 # miss rate for demand accesses 624system.cpu.icache.demand_miss_rate::total 0.000143 # miss rate for demand accesses 625system.cpu.icache.overall_miss_rate::cpu.inst 0.000143 # miss rate for overall accesses 626system.cpu.icache.overall_miss_rate::total 0.000143 # miss rate for overall accesses 627system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40327.399735 # average ReadReq miss latency 628system.cpu.icache.ReadReq_avg_miss_latency::total 40327.399735 # average ReadReq miss latency 629system.cpu.icache.demand_avg_miss_latency::cpu.inst 40327.399735 # average overall miss latency 630system.cpu.icache.demand_avg_miss_latency::total 40327.399735 # average overall miss latency 631system.cpu.icache.overall_avg_miss_latency::cpu.inst 40327.399735 # average overall miss latency 632system.cpu.icache.overall_avg_miss_latency::total 40327.399735 # average overall miss latency 633system.cpu.icache.blocked_cycles::no_mshrs 1167 # number of cycles access was blocked |
| 534system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 634system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 535system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked | 635system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked |
| 536system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 636system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 537system.cpu.icache.avg_blocked_cycles::no_mshrs 38 # average number of cycles each access was blocked | 637system.cpu.icache.avg_blocked_cycles::no_mshrs 58.350000 # average number of cycles each access was blocked |
| 538system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 539system.cpu.icache.fast_writes 0 # number of fast writes performed 540system.cpu.icache.cache_copies 0 # number of cache copies performed | 638system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 639system.cpu.icache.fast_writes 0 # number of fast writes performed 640system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 541system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1123 # number of ReadReq MSHR hits 542system.cpu.icache.ReadReq_mshr_hits::total 1123 # number of ReadReq MSHR hits 543system.cpu.icache.demand_mshr_hits::cpu.inst 1123 # number of demand (read+write) MSHR hits 544system.cpu.icache.demand_mshr_hits::total 1123 # number of demand (read+write) MSHR hits 545system.cpu.icache.overall_mshr_hits::cpu.inst 1123 # number of overall MSHR hits 546system.cpu.icache.overall_mshr_hits::total 1123 # number of overall MSHR hits 547system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4112 # number of ReadReq MSHR misses 548system.cpu.icache.ReadReq_mshr_misses::total 4112 # number of ReadReq MSHR misses 549system.cpu.icache.demand_mshr_misses::cpu.inst 4112 # number of demand (read+write) MSHR misses 550system.cpu.icache.demand_mshr_misses::total 4112 # number of demand (read+write) MSHR misses 551system.cpu.icache.overall_mshr_misses::cpu.inst 4112 # number of overall MSHR misses 552system.cpu.icache.overall_mshr_misses::total 4112 # number of overall MSHR misses 553system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 128908500 # number of ReadReq MSHR miss cycles 554system.cpu.icache.ReadReq_mshr_miss_latency::total 128908500 # number of ReadReq MSHR miss cycles 555system.cpu.icache.demand_mshr_miss_latency::cpu.inst 128908500 # number of demand (read+write) MSHR miss cycles 556system.cpu.icache.demand_mshr_miss_latency::total 128908500 # number of demand (read+write) MSHR miss cycles 557system.cpu.icache.overall_mshr_miss_latency::cpu.inst 128908500 # number of overall MSHR miss cycles 558system.cpu.icache.overall_mshr_miss_latency::total 128908500 # number of overall MSHR miss cycles 559system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses 560system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses 561system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses 562system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses 563system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for overall accesses 564system.cpu.icache.overall_mshr_miss_rate::total 0.000112 # mshr miss rate for overall accesses 565system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 31349.343385 # average ReadReq mshr miss latency 566system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 31349.343385 # average ReadReq mshr miss latency 567system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 31349.343385 # average overall mshr miss latency 568system.cpu.icache.demand_avg_mshr_miss_latency::total 31349.343385 # average overall mshr miss latency 569system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 31349.343385 # average overall mshr miss latency 570system.cpu.icache.overall_avg_mshr_miss_latency::total 31349.343385 # average overall mshr miss latency | 641system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1190 # number of ReadReq MSHR hits 642system.cpu.icache.ReadReq_mshr_hits::total 1190 # number of ReadReq MSHR hits 643system.cpu.icache.demand_mshr_hits::cpu.inst 1190 # number of demand (read+write) MSHR hits 644system.cpu.icache.demand_mshr_hits::total 1190 # number of demand (read+write) MSHR hits 645system.cpu.icache.overall_mshr_hits::cpu.inst 1190 # number of overall MSHR hits 646system.cpu.icache.overall_mshr_hits::total 1190 # number of overall MSHR hits 647system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4091 # number of ReadReq MSHR misses 648system.cpu.icache.ReadReq_mshr_misses::total 4091 # number of ReadReq MSHR misses 649system.cpu.icache.demand_mshr_misses::cpu.inst 4091 # number of demand (read+write) MSHR misses 650system.cpu.icache.demand_mshr_misses::total 4091 # number of demand (read+write) MSHR misses 651system.cpu.icache.overall_mshr_misses::cpu.inst 4091 # number of overall MSHR misses 652system.cpu.icache.overall_mshr_misses::total 4091 # number of overall MSHR misses 653system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 161081503 # number of ReadReq MSHR miss cycles 654system.cpu.icache.ReadReq_mshr_miss_latency::total 161081503 # number of ReadReq MSHR miss cycles 655system.cpu.icache.demand_mshr_miss_latency::cpu.inst 161081503 # number of demand (read+write) MSHR miss cycles 656system.cpu.icache.demand_mshr_miss_latency::total 161081503 # number of demand (read+write) MSHR miss cycles 657system.cpu.icache.overall_mshr_miss_latency::cpu.inst 161081503 # number of overall MSHR miss cycles 658system.cpu.icache.overall_mshr_miss_latency::total 161081503 # number of overall MSHR miss cycles 659system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for ReadReq accesses 660system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000111 # mshr miss rate for ReadReq accesses 661system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for demand accesses 662system.cpu.icache.demand_mshr_miss_rate::total 0.000111 # mshr miss rate for demand accesses 663system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for overall accesses 664system.cpu.icache.overall_mshr_miss_rate::total 0.000111 # mshr miss rate for overall accesses 665system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39374.603520 # average ReadReq mshr miss latency 666system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39374.603520 # average ReadReq mshr miss latency 667system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39374.603520 # average overall mshr miss latency 668system.cpu.icache.demand_avg_mshr_miss_latency::total 39374.603520 # average overall mshr miss latency 669system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39374.603520 # average overall mshr miss latency 670system.cpu.icache.overall_avg_mshr_miss_latency::total 39374.603520 # average overall mshr miss latency |
| 571system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 572system.cpu.l2cache.replacements 0 # number of replacements | 671system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 672system.cpu.l2cache.replacements 0 # number of replacements |
| 573system.cpu.l2cache.tagsinuse 1970.529288 # Cycle average of tags in use 574system.cpu.l2cache.total_refs 2136 # Total number of references to valid blocks. 575system.cpu.l2cache.sampled_refs 2737 # Sample count of references to valid blocks. 576system.cpu.l2cache.avg_refs 0.780417 # Average number of references to valid blocks. | 673system.cpu.l2cache.tagsinuse 1965.775294 # Cycle average of tags in use 674system.cpu.l2cache.total_refs 2123 # Total number of references to valid blocks. 675system.cpu.l2cache.sampled_refs 2730 # Sample count of references to valid blocks. 676system.cpu.l2cache.avg_refs 0.777656 # Average number of references to valid blocks. |
| 577system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 677system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 578system.cpu.l2cache.occ_blocks::writebacks 4.024044 # Average occupied blocks per requestor 579system.cpu.l2cache.occ_blocks::cpu.inst 1429.621147 # Average occupied blocks per requestor 580system.cpu.l2cache.occ_blocks::cpu.data 536.884097 # Average occupied blocks per requestor 581system.cpu.l2cache.occ_percent::writebacks 0.000123 # Average percentage of cache occupancy 582system.cpu.l2cache.occ_percent::cpu.inst 0.043629 # Average percentage of cache occupancy 583system.cpu.l2cache.occ_percent::cpu.data 0.016384 # Average percentage of cache occupancy 584system.cpu.l2cache.occ_percent::total 0.060136 # Average percentage of cache occupancy 585system.cpu.l2cache.ReadReq_hits::cpu.inst 2045 # number of ReadReq hits 586system.cpu.l2cache.ReadReq_hits::cpu.data 90 # number of ReadReq hits 587system.cpu.l2cache.ReadReq_hits::total 2135 # number of ReadReq hits 588system.cpu.l2cache.Writeback_hits::writebacks 19 # number of Writeback hits 589system.cpu.l2cache.Writeback_hits::total 19 # number of Writeback hits 590system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits 591system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits 592system.cpu.l2cache.ReadExReq_hits::cpu.data 10 # number of ReadExReq hits 593system.cpu.l2cache.ReadExReq_hits::total 10 # number of ReadExReq hits 594system.cpu.l2cache.demand_hits::cpu.inst 2045 # number of demand (read+write) hits 595system.cpu.l2cache.demand_hits::cpu.data 100 # number of demand (read+write) hits 596system.cpu.l2cache.demand_hits::total 2145 # number of demand (read+write) hits 597system.cpu.l2cache.overall_hits::cpu.inst 2045 # number of overall hits 598system.cpu.l2cache.overall_hits::cpu.data 100 # number of overall hits 599system.cpu.l2cache.overall_hits::total 2145 # number of overall hits 600system.cpu.l2cache.ReadReq_misses::cpu.inst 2064 # number of ReadReq misses 601system.cpu.l2cache.ReadReq_misses::cpu.data 683 # number of ReadReq misses 602system.cpu.l2cache.ReadReq_misses::total 2747 # number of ReadReq misses | 678system.cpu.l2cache.occ_blocks::writebacks 4.992159 # Average occupied blocks per requestor 679system.cpu.l2cache.occ_blocks::cpu.inst 1426.906678 # Average occupied blocks per requestor 680system.cpu.l2cache.occ_blocks::cpu.data 533.876457 # Average occupied blocks per requestor 681system.cpu.l2cache.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy 682system.cpu.l2cache.occ_percent::cpu.inst 0.043546 # Average percentage of cache occupancy 683system.cpu.l2cache.occ_percent::cpu.data 0.016293 # Average percentage of cache occupancy 684system.cpu.l2cache.occ_percent::total 0.059991 # Average percentage of cache occupancy 685system.cpu.l2cache.ReadReq_hits::cpu.inst 2037 # number of ReadReq hits 686system.cpu.l2cache.ReadReq_hits::cpu.data 85 # number of ReadReq hits 687system.cpu.l2cache.ReadReq_hits::total 2122 # number of ReadReq hits 688system.cpu.l2cache.Writeback_hits::writebacks 17 # number of Writeback hits 689system.cpu.l2cache.Writeback_hits::total 17 # number of Writeback hits 690system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits 691system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits 692system.cpu.l2cache.demand_hits::cpu.inst 2037 # number of demand (read+write) hits 693system.cpu.l2cache.demand_hits::cpu.data 93 # number of demand (read+write) hits 694system.cpu.l2cache.demand_hits::total 2130 # number of demand (read+write) hits 695system.cpu.l2cache.overall_hits::cpu.inst 2037 # number of overall hits 696system.cpu.l2cache.overall_hits::cpu.data 93 # number of overall hits 697system.cpu.l2cache.overall_hits::total 2130 # number of overall hits 698system.cpu.l2cache.ReadReq_misses::cpu.inst 2052 # number of ReadReq misses 699system.cpu.l2cache.ReadReq_misses::cpu.data 685 # number of ReadReq misses 700system.cpu.l2cache.ReadReq_misses::total 2737 # number of ReadReq misses |
| 603system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses 604system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses | 701system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses 702system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses |
| 605system.cpu.l2cache.ReadExReq_misses::cpu.data 1077 # number of ReadExReq misses 606system.cpu.l2cache.ReadExReq_misses::total 1077 # number of ReadExReq misses 607system.cpu.l2cache.demand_misses::cpu.inst 2064 # number of demand (read+write) misses | 703system.cpu.l2cache.ReadExReq_misses::cpu.data 1075 # number of ReadExReq misses 704system.cpu.l2cache.ReadExReq_misses::total 1075 # number of ReadExReq misses 705system.cpu.l2cache.demand_misses::cpu.inst 2052 # number of demand (read+write) misses |
| 608system.cpu.l2cache.demand_misses::cpu.data 1760 # number of demand (read+write) misses | 706system.cpu.l2cache.demand_misses::cpu.data 1760 # number of demand (read+write) misses |
| 609system.cpu.l2cache.demand_misses::total 3824 # number of demand (read+write) misses 610system.cpu.l2cache.overall_misses::cpu.inst 2064 # number of overall misses | 707system.cpu.l2cache.demand_misses::total 3812 # number of demand (read+write) misses 708system.cpu.l2cache.overall_misses::cpu.inst 2052 # number of overall misses |
| 611system.cpu.l2cache.overall_misses::cpu.data 1760 # number of overall misses | 709system.cpu.l2cache.overall_misses::cpu.data 1760 # number of overall misses |
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number of overall miss cycles 623system.cpu.l2cache.overall_miss_latency::total 193101000 # number of overall miss cycles 624system.cpu.l2cache.ReadReq_accesses::cpu.inst 4109 # number of ReadReq accesses(hits+misses) 625system.cpu.l2cache.ReadReq_accesses::cpu.data 773 # number of ReadReq accesses(hits+misses) 626system.cpu.l2cache.ReadReq_accesses::total 4882 # number of ReadReq accesses(hits+misses) 627system.cpu.l2cache.Writeback_accesses::writebacks 19 # number of Writeback accesses(hits+misses) 628system.cpu.l2cache.Writeback_accesses::total 19 # number of Writeback accesses(hits+misses) 629system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses) 630system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses) 631system.cpu.l2cache.ReadExReq_accesses::cpu.data 1087 # number of ReadExReq accesses(hits+misses) 632system.cpu.l2cache.ReadExReq_accesses::total 1087 # number of ReadExReq accesses(hits+misses) 633system.cpu.l2cache.demand_accesses::cpu.inst 4109 # number of demand (read+write) accesses 634system.cpu.l2cache.demand_accesses::cpu.data 1860 # number of demand (read+write) accesses 635system.cpu.l2cache.demand_accesses::total 5969 # number of demand (read+write) accesses 636system.cpu.l2cache.overall_accesses::cpu.inst 4109 # number of overall (read+write) accesses 637system.cpu.l2cache.overall_accesses::cpu.data 1860 # number of overall (read+write) accesses 638system.cpu.l2cache.overall_accesses::total 5969 # number of overall (read+write) accesses 639system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.502312 # miss rate for ReadReq accesses 640system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.883571 # miss rate for ReadReq accesses 641system.cpu.l2cache.ReadReq_miss_rate::total 0.562679 # miss rate for ReadReq accesses 642system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for UpgradeReq accesses 643system.cpu.l2cache.UpgradeReq_miss_rate::total 0.400000 # miss rate for UpgradeReq accesses 644system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.990800 # miss rate for ReadExReq accesses 645system.cpu.l2cache.ReadExReq_miss_rate::total 0.990800 # miss rate for ReadExReq accesses 646system.cpu.l2cache.demand_miss_rate::cpu.inst 0.502312 # miss rate for demand accesses 647system.cpu.l2cache.demand_miss_rate::cpu.data 0.946237 # miss rate for demand accesses 648system.cpu.l2cache.demand_miss_rate::total 0.640643 # miss rate for demand accesses 649system.cpu.l2cache.overall_miss_rate::cpu.inst 0.502312 # miss rate for overall accesses 650system.cpu.l2cache.overall_miss_rate::cpu.data 0.946237 # miss rate for overall accesses 651system.cpu.l2cache.overall_miss_rate::total 0.640643 # miss rate for overall accesses 652system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50545.542636 # average ReadReq miss latency 653system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57597.364568 # average ReadReq miss latency 654system.cpu.l2cache.ReadReq_avg_miss_latency::total 52298.871496 # average ReadReq miss latency 655system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45901.578459 # average ReadExReq miss latency 656system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45901.578459 # average ReadExReq miss latency 657system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50545.542636 # average overall miss latency 658system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50440.340909 # average overall miss latency 659system.cpu.l2cache.demand_avg_miss_latency::total 50497.123431 # average overall miss latency 660system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50545.542636 # average overall miss latency 661system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50440.340909 # average overall miss latency 662system.cpu.l2cache.overall_avg_miss_latency::total 50497.123431 # average overall miss latency | 710system.cpu.l2cache.overall_misses::total 3812 # number of overall misses 711system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 136608500 # number of ReadReq miss cycles 712system.cpu.l2cache.ReadReq_miss_latency::cpu.data 47553500 # number of ReadReq miss cycles 713system.cpu.l2cache.ReadReq_miss_latency::total 184162000 # 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number of ReadReq accesses(hits+misses) 725system.cpu.l2cache.Writeback_accesses::writebacks 17 # number of Writeback accesses(hits+misses) 726system.cpu.l2cache.Writeback_accesses::total 17 # number of Writeback accesses(hits+misses) 727system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) 728system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) 729system.cpu.l2cache.ReadExReq_accesses::cpu.data 1083 # number of ReadExReq accesses(hits+misses) 730system.cpu.l2cache.ReadExReq_accesses::total 1083 # number of ReadExReq accesses(hits+misses) 731system.cpu.l2cache.demand_accesses::cpu.inst 4089 # number of demand (read+write) accesses 732system.cpu.l2cache.demand_accesses::cpu.data 1853 # number of demand (read+write) accesses 733system.cpu.l2cache.demand_accesses::total 5942 # number of demand (read+write) accesses 734system.cpu.l2cache.overall_accesses::cpu.inst 4089 # number of overall (read+write) accesses 735system.cpu.l2cache.overall_accesses::cpu.data 1853 # number of overall (read+write) accesses 736system.cpu.l2cache.overall_accesses::total 5942 # number of overall (read+write) accesses 737system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.501834 # miss rate for ReadReq accesses 738system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.889610 # miss rate for ReadReq accesses 739system.cpu.l2cache.ReadReq_miss_rate::total 0.563285 # miss rate for ReadReq accesses 740system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 741system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 742system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992613 # miss rate for ReadExReq accesses 743system.cpu.l2cache.ReadExReq_miss_rate::total 0.992613 # miss rate for ReadExReq accesses 744system.cpu.l2cache.demand_miss_rate::cpu.inst 0.501834 # miss rate for demand accesses 745system.cpu.l2cache.demand_miss_rate::cpu.data 0.949811 # miss rate for demand accesses 746system.cpu.l2cache.demand_miss_rate::total 0.641535 # miss rate for demand accesses 747system.cpu.l2cache.overall_miss_rate::cpu.inst 0.501834 # miss rate for overall accesses 748system.cpu.l2cache.overall_miss_rate::cpu.data 0.949811 # miss rate for overall accesses 749system.cpu.l2cache.overall_miss_rate::total 0.641535 # miss rate for overall accesses 750system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66573.343080 # average ReadReq miss latency 751system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69421.167883 # average ReadReq miss latency 752system.cpu.l2cache.ReadReq_avg_miss_latency::total 67286.079649 # average ReadReq miss latency 753system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 63302.790698 # average ReadExReq miss latency 754system.cpu.l2cache.ReadExReq_avg_miss_latency::total 63302.790698 # average ReadExReq miss latency 755system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66573.343080 # average overall miss latency 756system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65684.090909 # average overall miss latency 757system.cpu.l2cache.demand_avg_miss_latency::total 66162.775446 # average overall miss latency 758system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66573.343080 # average overall miss latency 759system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65684.090909 # average overall miss latency 760system.cpu.l2cache.overall_avg_miss_latency::total 66162.775446 # average overall miss latency |
| 663system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 664system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 665system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 666system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 667system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 668system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 669system.cpu.l2cache.fast_writes 0 # number of fast writes performed 670system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 761system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 762system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 763system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 764system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 765system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 766system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 767system.cpu.l2cache.fast_writes 0 # number of fast writes performed 768system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
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| 681system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 672 # number of ReadReq MSHR misses | 779system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 672 # number of ReadReq MSHR misses |
| 682system.cpu.l2cache.ReadReq_mshr_misses::total 2732 # number of ReadReq MSHR misses | 780system.cpu.l2cache.ReadReq_mshr_misses::total 2721 # number of ReadReq MSHR misses |
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| 696system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles 697system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles | 794system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles 795system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles |
| 698system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 36053347 # number of ReadExReq MSHR miss cycles 699system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 36053347 # number of ReadExReq MSHR miss cycles 700system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 78499737 # number of demand (read+write) MSHR miss cycles 701system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 66568603 # number of demand (read+write) MSHR miss cycles 702system.cpu.l2cache.demand_mshr_miss_latency::total 145068340 # number of demand (read+write) MSHR miss cycles 703system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 78499737 # number of overall MSHR miss cycles 704system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 66568603 # number of overall MSHR miss cycles 705system.cpu.l2cache.overall_mshr_miss_latency::total 145068340 # number of overall MSHR miss cycles 706system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.501339 # mshr miss rate for ReadReq accesses 707system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869340 # mshr miss rate for ReadReq accesses 708system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.559607 # mshr miss rate for ReadReq accesses 709system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for UpgradeReq accesses 710system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for UpgradeReq accesses 711system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.990800 # mshr miss rate for ReadExReq accesses 712system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.990800 # mshr miss rate for ReadExReq accesses 713system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.501339 # mshr miss rate for demand accesses 714system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.940323 # mshr miss rate for demand accesses 715system.cpu.l2cache.demand_mshr_miss_rate::total 0.638130 # mshr miss rate for demand accesses 716system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.501339 # mshr miss rate for overall accesses 717system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940323 # mshr miss rate for overall accesses 718system.cpu.l2cache.overall_mshr_miss_rate::total 0.638130 # mshr miss rate for overall accesses 719system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38106.668447 # average ReadReq mshr miss latency 720system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45409.607143 # average ReadReq mshr miss latency 721system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39902.998902 # average ReadReq mshr miss latency | 796system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54679250 # number of ReadExReq MSHR miss cycles 797system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54679250 # number of ReadExReq MSHR miss cycles 798system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110944750 # number of demand (read+write) MSHR miss cycles 799system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 93185500 # number of demand (read+write) MSHR miss cycles 800system.cpu.l2cache.demand_mshr_miss_latency::total 204130250 # number of demand (read+write) MSHR miss cycles 801system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110944750 # number of overall MSHR miss cycles 802system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 93185500 # number of overall MSHR miss cycles 803system.cpu.l2cache.overall_mshr_miss_latency::total 204130250 # number of overall MSHR miss cycles 804system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.501101 # mshr miss rate for ReadReq accesses 805system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.872727 # mshr miss rate for ReadReq accesses 806system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.559992 # mshr miss rate for ReadReq accesses 807system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 808system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 809system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992613 # mshr miss rate for ReadExReq accesses 810system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992613 # mshr miss rate for ReadExReq accesses 811system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.501101 # mshr miss rate for demand accesses 812system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942795 # mshr miss rate for demand accesses 813system.cpu.l2cache.demand_mshr_miss_rate::total 0.638842 # mshr miss rate for demand accesses 814system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.501101 # mshr miss rate for overall accesses 815system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942795 # mshr miss rate for overall accesses 816system.cpu.l2cache.overall_mshr_miss_rate::total 0.638842 # mshr miss rate for overall accesses 817system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54145.802831 # average ReadReq mshr miss latency 818system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57300.967262 # average ReadReq mshr miss latency 819system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54925.027563 # average ReadReq mshr miss latency |
| 722system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 723system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency | 820system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 821system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency |
| 724system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33475.716806 # average ReadExReq mshr miss latency 725system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33475.716806 # average ReadExReq mshr miss latency 726system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38106.668447 # average overall mshr miss latency 727system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38060.950829 # average overall mshr miss latency 728system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38085.676030 # average overall mshr miss latency 729system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38106.668447 # average overall mshr miss latency 730system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38060.950829 # average overall mshr miss latency 731system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38085.676030 # average overall mshr miss latency | 822system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50864.418605 # average ReadExReq mshr miss latency 823system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50864.418605 # average ReadExReq mshr miss latency 824system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54145.802831 # average overall mshr miss latency 825system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53340.297653 # average overall mshr miss latency 826system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53775.092202 # average overall mshr miss latency 827system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54145.802831 # average overall mshr miss latency 828system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53340.297653 # average overall mshr miss latency 829system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53775.092202 # average overall mshr miss latency |
| 732system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 830system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 733system.cpu.dcache.replacements 61 # number of replacements 734system.cpu.dcache.tagsinuse 1409.645291 # Cycle average of tags in use 735system.cpu.dcache.total_refs 46783527 # Total number of references to valid blocks. 736system.cpu.dcache.sampled_refs 1860 # Sample count of references to valid blocks. 737system.cpu.dcache.avg_refs 25152.433871 # Average number of references to valid blocks. | 831system.cpu.dcache.replacements 57 # number of replacements 832system.cpu.dcache.tagsinuse 1407.131551 # Cycle average of tags in use 833system.cpu.dcache.total_refs 46775584 # Total number of references to valid blocks. 834system.cpu.dcache.sampled_refs 1853 # Sample count of references to valid blocks. 835system.cpu.dcache.avg_refs 25243.164598 # Average number of references to valid blocks. |
| 738system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 836system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 739system.cpu.dcache.occ_blocks::cpu.data 1409.645291 # Average occupied blocks per requestor 740system.cpu.dcache.occ_percent::cpu.data 0.344152 # Average percentage of cache occupancy 741system.cpu.dcache.occ_percent::total 0.344152 # Average percentage of cache occupancy 742system.cpu.dcache.ReadReq_hits::cpu.data 34382093 # number of ReadReq hits 743system.cpu.dcache.ReadReq_hits::total 34382093 # number of ReadReq hits 744system.cpu.dcache.WriteReq_hits::cpu.data 12356549 # number of WriteReq hits 745system.cpu.dcache.WriteReq_hits::total 12356549 # number of WriteReq hits 746system.cpu.dcache.LoadLockedReq_hits::cpu.data 22473 # number of LoadLockedReq hits 747system.cpu.dcache.LoadLockedReq_hits::total 22473 # number of LoadLockedReq hits | 837system.cpu.dcache.occ_blocks::cpu.data 1407.131551 # Average occupied blocks per requestor 838system.cpu.dcache.occ_percent::cpu.data 0.343538 # Average percentage of cache occupancy 839system.cpu.dcache.occ_percent::total 0.343538 # Average percentage of cache occupancy 840system.cpu.dcache.ReadReq_hits::cpu.data 34374175 # number of ReadReq hits 841system.cpu.dcache.ReadReq_hits::total 34374175 # number of ReadReq hits 842system.cpu.dcache.WriteReq_hits::cpu.data 12356535 # number of WriteReq hits 843system.cpu.dcache.WriteReq_hits::total 12356535 # number of WriteReq hits 844system.cpu.dcache.LoadLockedReq_hits::cpu.data 22465 # number of LoadLockedReq hits 845system.cpu.dcache.LoadLockedReq_hits::total 22465 # number of LoadLockedReq hits |
| 748system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits 749system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits | 846system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits 847system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits |
| 750system.cpu.dcache.demand_hits::cpu.data 46738642 # number of demand (read+write) hits 751system.cpu.dcache.demand_hits::total 46738642 # number of demand (read+write) hits 752system.cpu.dcache.overall_hits::cpu.data 46738642 # number of overall hits 753system.cpu.dcache.overall_hits::total 46738642 # number of overall hits 754system.cpu.dcache.ReadReq_misses::cpu.data 1903 # number of ReadReq misses 755system.cpu.dcache.ReadReq_misses::total 1903 # number of ReadReq misses 756system.cpu.dcache.WriteReq_misses::cpu.data 7738 # number of WriteReq misses 757system.cpu.dcache.WriteReq_misses::total 7738 # number of WriteReq misses | 848system.cpu.dcache.demand_hits::cpu.data 46730710 # number of demand (read+write) hits 849system.cpu.dcache.demand_hits::total 46730710 # number of demand (read+write) hits 850system.cpu.dcache.overall_hits::cpu.data 46730710 # number of overall hits 851system.cpu.dcache.overall_hits::total 46730710 # number of overall hits 852system.cpu.dcache.ReadReq_misses::cpu.data 1909 # number of ReadReq misses 853system.cpu.dcache.ReadReq_misses::total 1909 # number of ReadReq misses 854system.cpu.dcache.WriteReq_misses::cpu.data 7752 # number of WriteReq misses 855system.cpu.dcache.WriteReq_misses::total 7752 # number of WriteReq misses |
| 758system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 759system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses | 856system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 857system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses |
| 760system.cpu.dcache.demand_misses::cpu.data 9641 # number of demand (read+write) misses 761system.cpu.dcache.demand_misses::total 9641 # number of demand (read+write) misses 762system.cpu.dcache.overall_misses::cpu.data 9641 # number of overall misses 763system.cpu.dcache.overall_misses::total 9641 # number of overall misses 764system.cpu.dcache.ReadReq_miss_latency::cpu.data 93214000 # number of ReadReq miss cycles 765system.cpu.dcache.ReadReq_miss_latency::total 93214000 # number of ReadReq miss cycles 766system.cpu.dcache.WriteReq_miss_latency::cpu.data 305598496 # number of WriteReq miss cycles 767system.cpu.dcache.WriteReq_miss_latency::total 305598496 # number of WriteReq miss cycles 768system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles 769system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles 770system.cpu.dcache.demand_miss_latency::cpu.data 398812496 # number of demand (read+write) miss cycles 771system.cpu.dcache.demand_miss_latency::total 398812496 # number of demand (read+write) miss cycles 772system.cpu.dcache.overall_miss_latency::cpu.data 398812496 # number of overall miss cycles 773system.cpu.dcache.overall_miss_latency::total 398812496 # number of overall miss cycles 774system.cpu.dcache.ReadReq_accesses::cpu.data 34383996 # number of ReadReq accesses(hits+misses) 775system.cpu.dcache.ReadReq_accesses::total 34383996 # number of ReadReq accesses(hits+misses) | 858system.cpu.dcache.demand_misses::cpu.data 9661 # number of demand (read+write) misses 859system.cpu.dcache.demand_misses::total 9661 # number of demand (read+write) misses 860system.cpu.dcache.overall_misses::cpu.data 9661 # number of overall misses 861system.cpu.dcache.overall_misses::total 9661 # number of overall misses 862system.cpu.dcache.ReadReq_miss_latency::cpu.data 115578500 # number of ReadReq miss cycles 863system.cpu.dcache.ReadReq_miss_latency::total 115578500 # number of ReadReq miss cycles 864system.cpu.dcache.WriteReq_miss_latency::cpu.data 443691996 # number of WriteReq miss cycles 865system.cpu.dcache.WriteReq_miss_latency::total 443691996 # number of WriteReq miss cycles 866system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 141000 # number of LoadLockedReq miss cycles 867system.cpu.dcache.LoadLockedReq_miss_latency::total 141000 # number of LoadLockedReq miss cycles 868system.cpu.dcache.demand_miss_latency::cpu.data 559270496 # number of demand (read+write) miss cycles 869system.cpu.dcache.demand_miss_latency::total 559270496 # number of demand (read+write) miss cycles 870system.cpu.dcache.overall_miss_latency::cpu.data 559270496 # number of overall miss cycles 871system.cpu.dcache.overall_miss_latency::total 559270496 # number of overall miss cycles 872system.cpu.dcache.ReadReq_accesses::cpu.data 34376084 # number of ReadReq accesses(hits+misses) 873system.cpu.dcache.ReadReq_accesses::total 34376084 # number of ReadReq accesses(hits+misses) |
| 776system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 777system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) | 874system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 875system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) |
| 778system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22475 # number of LoadLockedReq accesses(hits+misses) 779system.cpu.dcache.LoadLockedReq_accesses::total 22475 # number of LoadLockedReq accesses(hits+misses) | 876system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22467 # number of LoadLockedReq accesses(hits+misses) 877system.cpu.dcache.LoadLockedReq_accesses::total 22467 # number of LoadLockedReq accesses(hits+misses) |
| 780system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) 781system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) | 878system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) 879system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) |
| 782system.cpu.dcache.demand_accesses::cpu.data 46748283 # number of demand (read+write) accesses 783system.cpu.dcache.demand_accesses::total 46748283 # number of demand (read+write) accesses 784system.cpu.dcache.overall_accesses::cpu.data 46748283 # number of overall (read+write) accesses 785system.cpu.dcache.overall_accesses::total 46748283 # number of overall (read+write) accesses 786system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses 787system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses 788system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000626 # miss rate for WriteReq accesses 789system.cpu.dcache.WriteReq_miss_rate::total 0.000626 # miss rate for WriteReq accesses | 880system.cpu.dcache.demand_accesses::cpu.data 46740371 # number of demand (read+write) accesses 881system.cpu.dcache.demand_accesses::total 46740371 # number of demand (read+write) accesses 882system.cpu.dcache.overall_accesses::cpu.data 46740371 # number of overall (read+write) accesses 883system.cpu.dcache.overall_accesses::total 46740371 # number of overall (read+write) accesses 884system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000056 # miss rate for ReadReq accesses 885system.cpu.dcache.ReadReq_miss_rate::total 0.000056 # miss rate for ReadReq accesses 886system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000627 # miss rate for WriteReq accesses 887system.cpu.dcache.WriteReq_miss_rate::total 0.000627 # miss rate for WriteReq accesses |
| 790system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses 791system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses | 888system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses 889system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses |
| 792system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses 793system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses 794system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses 795system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses 796system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48982.658960 # average ReadReq miss latency 797system.cpu.dcache.ReadReq_avg_miss_latency::total 48982.658960 # average ReadReq miss latency 798system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39493.214784 # average WriteReq miss latency 799system.cpu.dcache.WriteReq_avg_miss_latency::total 39493.214784 # average WriteReq miss latency 800system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency 801system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency 802system.cpu.dcache.demand_avg_miss_latency::cpu.data 41366.299761 # average overall miss latency 803system.cpu.dcache.demand_avg_miss_latency::total 41366.299761 # average overall miss latency 804system.cpu.dcache.overall_avg_miss_latency::cpu.data 41366.299761 # average overall miss latency 805system.cpu.dcache.overall_avg_miss_latency::total 41366.299761 # average overall miss latency 806system.cpu.dcache.blocked_cycles::no_mshrs 527 # number of cycles access was blocked 807system.cpu.dcache.blocked_cycles::no_targets 67 # number of cycles access was blocked 808system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked | 890system.cpu.dcache.demand_miss_rate::cpu.data 0.000207 # miss rate for demand accesses 891system.cpu.dcache.demand_miss_rate::total 0.000207 # miss rate for demand accesses 892system.cpu.dcache.overall_miss_rate::cpu.data 0.000207 # miss rate for overall accesses 893system.cpu.dcache.overall_miss_rate::total 0.000207 # miss rate for overall accesses 894system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60544.002095 # average ReadReq miss latency 895system.cpu.dcache.ReadReq_avg_miss_latency::total 60544.002095 # average ReadReq miss latency 896system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57235.809598 # average WriteReq miss latency 897system.cpu.dcache.WriteReq_avg_miss_latency::total 57235.809598 # average WriteReq miss latency 898system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70500 # average LoadLockedReq miss latency 899system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70500 # average LoadLockedReq miss latency 900system.cpu.dcache.demand_avg_miss_latency::cpu.data 57889.503778 # average overall miss latency 901system.cpu.dcache.demand_avg_miss_latency::total 57889.503778 # average overall miss latency 902system.cpu.dcache.overall_avg_miss_latency::cpu.data 57889.503778 # average overall miss latency 903system.cpu.dcache.overall_avg_miss_latency::total 57889.503778 # average overall miss latency 904system.cpu.dcache.blocked_cycles::no_mshrs 581 # number of cycles access was blocked 905system.cpu.dcache.blocked_cycles::no_targets 112 # number of cycles access was blocked 906system.cpu.dcache.blocked::no_mshrs 12 # number of cycles access was blocked |
| 809system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked | 907system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked |
| 810system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.538462 # average number of cycles each access was blocked 811system.cpu.dcache.avg_blocked_cycles::no_targets 33.500000 # average number of cycles each access was blocked | 908system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.416667 # average number of cycles each access was blocked 909system.cpu.dcache.avg_blocked_cycles::no_targets 56 # average number of cycles each access was blocked |
| 812system.cpu.dcache.fast_writes 0 # number of fast writes performed 813system.cpu.dcache.cache_copies 0 # number of cache copies performed | 910system.cpu.dcache.fast_writes 0 # number of fast writes performed 911system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 814system.cpu.dcache.writebacks::writebacks 19 # number of writebacks 815system.cpu.dcache.writebacks::total 19 # number of writebacks 816system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1128 # number of ReadReq MSHR hits 817system.cpu.dcache.ReadReq_mshr_hits::total 1128 # number of ReadReq MSHR hits 818system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6648 # number of WriteReq MSHR hits 819system.cpu.dcache.WriteReq_mshr_hits::total 6648 # number of WriteReq MSHR hits | 912system.cpu.dcache.writebacks::writebacks 17 # number of writebacks 913system.cpu.dcache.writebacks::total 17 # number of writebacks 914system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1137 # number of ReadReq MSHR hits 915system.cpu.dcache.ReadReq_mshr_hits::total 1137 # number of ReadReq MSHR hits 916system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6669 # number of WriteReq MSHR hits 917system.cpu.dcache.WriteReq_mshr_hits::total 6669 # number of WriteReq MSHR hits |
| 820system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 821system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits | 918system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 919system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits |
| 822system.cpu.dcache.demand_mshr_hits::cpu.data 7776 # number of demand (read+write) MSHR hits 823system.cpu.dcache.demand_mshr_hits::total 7776 # number of demand (read+write) MSHR hits 824system.cpu.dcache.overall_mshr_hits::cpu.data 7776 # number of overall MSHR hits 825system.cpu.dcache.overall_mshr_hits::total 7776 # number of overall MSHR hits 826system.cpu.dcache.ReadReq_mshr_misses::cpu.data 775 # number of ReadReq MSHR misses 827system.cpu.dcache.ReadReq_mshr_misses::total 775 # number of ReadReq MSHR misses 828system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1090 # number of WriteReq MSHR misses 829system.cpu.dcache.WriteReq_mshr_misses::total 1090 # number of WriteReq MSHR misses 830system.cpu.dcache.demand_mshr_misses::cpu.data 1865 # number of demand (read+write) MSHR misses 831system.cpu.dcache.demand_mshr_misses::total 1865 # number of demand (read+write) MSHR misses 832system.cpu.dcache.overall_mshr_misses::cpu.data 1865 # number of overall MSHR misses 833system.cpu.dcache.overall_mshr_misses::total 1865 # number of overall MSHR misses 834system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41130000 # number of ReadReq MSHR miss cycles 835system.cpu.dcache.ReadReq_mshr_miss_latency::total 41130000 # number of ReadReq MSHR miss cycles 836system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 50620998 # number of WriteReq MSHR miss cycles 837system.cpu.dcache.WriteReq_mshr_miss_latency::total 50620998 # number of WriteReq MSHR miss cycles 838system.cpu.dcache.demand_mshr_miss_latency::cpu.data 91750998 # number of demand (read+write) MSHR miss cycles 839system.cpu.dcache.demand_mshr_miss_latency::total 91750998 # number of demand (read+write) MSHR miss cycles 840system.cpu.dcache.overall_mshr_miss_latency::cpu.data 91750998 # number of overall MSHR miss cycles 841system.cpu.dcache.overall_mshr_miss_latency::total 91750998 # number of overall MSHR miss cycles 842system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses 843system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses | 920system.cpu.dcache.demand_mshr_hits::cpu.data 7806 # number of demand (read+write) MSHR hits 921system.cpu.dcache.demand_mshr_hits::total 7806 # number of demand (read+write) MSHR hits 922system.cpu.dcache.overall_mshr_hits::cpu.data 7806 # number of overall MSHR hits 923system.cpu.dcache.overall_mshr_hits::total 7806 # number of overall MSHR hits 924system.cpu.dcache.ReadReq_mshr_misses::cpu.data 772 # number of ReadReq MSHR misses 925system.cpu.dcache.ReadReq_mshr_misses::total 772 # number of ReadReq MSHR misses 926system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1083 # number of WriteReq MSHR misses 927system.cpu.dcache.WriteReq_mshr_misses::total 1083 # number of WriteReq MSHR misses 928system.cpu.dcache.demand_mshr_misses::cpu.data 1855 # number of demand (read+write) MSHR misses 929system.cpu.dcache.demand_mshr_misses::total 1855 # number of demand (read+write) MSHR misses 930system.cpu.dcache.overall_mshr_misses::cpu.data 1855 # number of overall MSHR misses 931system.cpu.dcache.overall_mshr_misses::total 1855 # number of overall MSHR misses 932system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 49331013 # number of ReadReq MSHR miss cycles 933system.cpu.dcache.ReadReq_mshr_miss_latency::total 49331013 # number of ReadReq MSHR miss cycles 934system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 69111498 # number of WriteReq MSHR miss cycles 935system.cpu.dcache.WriteReq_mshr_miss_latency::total 69111498 # number of WriteReq MSHR miss cycles 936system.cpu.dcache.demand_mshr_miss_latency::cpu.data 118442511 # number of demand (read+write) MSHR miss cycles 937system.cpu.dcache.demand_mshr_miss_latency::total 118442511 # number of demand (read+write) MSHR miss cycles 938system.cpu.dcache.overall_mshr_miss_latency::cpu.data 118442511 # number of overall MSHR miss cycles 939system.cpu.dcache.overall_mshr_miss_latency::total 118442511 # number of overall MSHR miss cycles 940system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses 941system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses |
| 844system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses 845system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses 846system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses 847system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 848system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses 849system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses | 942system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses 943system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses 944system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses 945system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 946system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses 947system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses |
| 850system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53070.967742 # average ReadReq mshr miss latency 851system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53070.967742 # average ReadReq mshr miss latency 852system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46441.282569 # average WriteReq mshr miss latency 853system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46441.282569 # average WriteReq mshr miss latency 854system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49196.245576 # average overall mshr miss latency 855system.cpu.dcache.demand_avg_mshr_miss_latency::total 49196.245576 # average overall mshr miss latency 856system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49196.245576 # average overall mshr miss latency 857system.cpu.dcache.overall_avg_mshr_miss_latency::total 49196.245576 # average overall mshr miss latency | 948system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63900.275907 # average ReadReq mshr miss latency 949system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63900.275907 # average ReadReq mshr miss latency 950system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63814.864266 # average WriteReq mshr miss latency 951system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63814.864266 # average WriteReq mshr miss latency 952system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63850.410243 # average overall mshr miss latency 953system.cpu.dcache.demand_avg_mshr_miss_latency::total 63850.410243 # average overall mshr miss latency 954system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63850.410243 # average overall mshr miss latency 955system.cpu.dcache.overall_avg_mshr_miss_latency::total 63850.410243 # average overall mshr miss latency |
| 858system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 859 860---------- End Simulation Statistics ---------- | 956system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 957 958---------- End Simulation Statistics ---------- |