| stats.txt (9481:b0fa6b872f40) | stats.txt (9490:e6a09d97bdc9) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.074149 # Number of seconds simulated 4sim_ticks 74148853000 # Number of ticks simulated 5final_tick 74148853000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.074156 # Number of seconds simulated 4sim_ticks 74155951500 # Number of ticks simulated 5final_tick 74155951500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 87257 # Simulator instruction rate (inst/s) 8host_op_rate 95539 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 37550131 # Simulator tick rate (ticks/s) 10host_mem_usage 292636 # Number of bytes of host memory used 11host_seconds 1974.66 # Real time elapsed on the host | 7host_inst_rate 108940 # Simulator instruction rate (inst/s) 8host_op_rate 119280 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 46885764 # Simulator tick rate (ticks/s) 10host_mem_usage 245224 # Number of bytes of host memory used 11host_seconds 1581.63 # Real time elapsed on the host |
| 12sim_insts 172303021 # Number of instructions simulated 13sim_ops 188656503 # Number of ops (including micro ops) simulated | 12sim_insts 172303021 # Number of instructions simulated 13sim_ops 188656503 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 131648 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 111744 # Number of bytes read from this memory 16system.physmem.bytes_read::total 243392 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 131648 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 131648 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 2057 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 1746 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 3803 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1775456 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 1507023 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 3282478 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1775456 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1775456 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1775456 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 1507023 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 3282478 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 3804 # Total number of read requests seen | 14system.physmem.bytes_read::cpu.inst 131776 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 112064 # Number of bytes read from this memory 16system.physmem.bytes_read::total 243840 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 131776 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 131776 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 2059 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 1751 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 3810 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1777012 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 1511194 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 3288205 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1777012 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1777012 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1777012 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 1511194 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 3288205 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 3811 # Total number of read requests seen |
| 31system.physmem.writeReqs 0 # Total number of write requests seen | 31system.physmem.writeReqs 0 # Total number of write requests seen |
| 32system.physmem.cpureqs 3804 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 243392 # Total number of bytes read from memory | 32system.physmem.cpureqs 3811 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 243840 # Total number of bytes read from memory |
| 34system.physmem.bytesWritten 0 # Total number of bytes written to memory | 34system.physmem.bytesWritten 0 # Total number of bytes written to memory |
| 35system.physmem.bytesConsumedRd 243392 # bytesRead derated as per pkt->getSize() | 35system.physmem.bytesConsumedRd 243840 # bytesRead derated as per pkt->getSize() |
| 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed | 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed |
| 39system.physmem.perBankRdReqs::0 319 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 234 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 190 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 235 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 227 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 193 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 221 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 282 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 243 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 247 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 249 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 261 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 249 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 234 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 181 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 239 # Track reads on a per bank basis | 39system.physmem.perBankRdReqs::0 322 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 240 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 207 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 272 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 246 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 197 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 248 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 252 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 233 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 244 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 235 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 194 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 203 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 197 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 247 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 274 # Track reads on a per bank basis |
| 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 73system.physmem.totGap 74148834500 # Total gap between requests | 73system.physmem.totGap 74155933000 # Total gap between requests |
| 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes | 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 80system.physmem.readPktSize::6 3804 # Categorize read packet sizes | 80system.physmem.readPktSize::6 3811 # Categorize read packet sizes |
| 81system.physmem.readPktSize::7 0 # Categorize read packet sizes 82system.physmem.readPktSize::8 0 # Categorize read packet sizes 83system.physmem.writePktSize::0 0 # categorize write packet sizes 84system.physmem.writePktSize::1 0 # categorize write packet sizes 85system.physmem.writePktSize::2 0 # categorize write packet sizes 86system.physmem.writePktSize::3 0 # categorize write packet sizes 87system.physmem.writePktSize::4 0 # categorize write packet sizes 88system.physmem.writePktSize::5 0 # categorize write packet sizes --- 4 unchanged lines hidden (view full) --- 93system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 94system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 95system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 96system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 97system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 98system.physmem.neitherpktsize::6 0 # categorize neither packet sizes 99system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::8 0 # categorize neither packet sizes | 81system.physmem.readPktSize::7 0 # Categorize read packet sizes 82system.physmem.readPktSize::8 0 # Categorize read packet sizes 83system.physmem.writePktSize::0 0 # categorize write packet sizes 84system.physmem.writePktSize::1 0 # categorize write packet sizes 85system.physmem.writePktSize::2 0 # categorize write packet sizes 86system.physmem.writePktSize::3 0 # categorize write packet sizes 87system.physmem.writePktSize::4 0 # categorize write packet sizes 88system.physmem.writePktSize::5 0 # categorize write packet sizes --- 4 unchanged lines hidden (view full) --- 93system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 94system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 95system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 96system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 97system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 98system.physmem.neitherpktsize::6 0 # categorize neither packet sizes 99system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::8 0 # categorize neither packet sizes |
| 101system.physmem.rdQLenPdf::0 2808 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 800 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 151 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see | 101system.physmem.rdQLenPdf::0 2809 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 787 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 160 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 46 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see |
| 106system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 45 unchanged lines hidden (view full) --- 159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see | 106system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 45 unchanged lines hidden (view full) --- 159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see |
| 167system.physmem.totQLat 11954297 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 86040297 # Sum of mem lat for all requests 169system.physmem.totBusLat 15216000 # Total cycles spent in databus access 170system.physmem.totBankLat 58870000 # Total cycles spent in bank access 171system.physmem.avgQLat 3142.56 # Average queueing delay per request 172system.physmem.avgBankLat 15475.81 # Average bank access latency per request 173system.physmem.avgBusLat 4000.00 # Average bus latency per request 174system.physmem.avgMemAccLat 22618.37 # Average memory access latency 175system.physmem.avgRdBW 3.28 # Average achieved read bandwidth in MB/s | 167system.physmem.totQLat 17813284 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 103885784 # Sum of mem lat for all requests 169system.physmem.totBusLat 19055000 # Total cycles spent in databus access 170system.physmem.totBankLat 67017500 # Total cycles spent in bank access 171system.physmem.avgQLat 4674.18 # Average queueing delay per request 172system.physmem.avgBankLat 17585.28 # Average bank access latency per request 173system.physmem.avgBusLat 5000.00 # Average bus latency per request 174system.physmem.avgMemAccLat 27259.46 # Average memory access latency 175system.physmem.avgRdBW 3.29 # Average achieved read bandwidth in MB/s |
| 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s | 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s |
| 177system.physmem.avgConsumedRdBW 3.28 # Average consumed read bandwidth in MB/s | 177system.physmem.avgConsumedRdBW 3.29 # Average consumed read bandwidth in MB/s |
| 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s | 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s |
| 179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 180system.physmem.busUtil 0.02 # Data bus utilization in percentage | 179system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 180system.physmem.busUtil 0.03 # Data bus utilization in percentage |
| 181system.physmem.avgRdQLen 0.00 # Average read queue length over time 182system.physmem.avgWrQLen 0.00 # Average write queue length over time | 181system.physmem.avgRdQLen 0.00 # Average read queue length over time 182system.physmem.avgWrQLen 0.00 # Average write queue length over time |
| 183system.physmem.readRowHits 3306 # Number of row buffer hits during reads | 183system.physmem.readRowHits 3029 # Number of row buffer hits during reads |
| 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 185system.physmem.readRowHitRate 86.91 # Row buffer hit rate for reads | 185system.physmem.readRowHitRate 79.48 # Row buffer hit rate for reads |
| 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 187system.physmem.avgGap 19492332.94 # Average gap between requests 188system.cpu.branchPred.lookups 94799058 # Number of BP lookups 189system.cpu.branchPred.condPredicted 74801869 # Number of conditional branches predicted 190system.cpu.branchPred.condIncorrect 6279291 # Number of conditional branches incorrect 191system.cpu.branchPred.BTBLookups 44724397 # Number of BTB lookups 192system.cpu.branchPred.BTBHits 43048437 # Number of BTB hits | 187system.physmem.avgGap 19458392.29 # Average gap between requests 188system.cpu.branchPred.lookups 94769609 # Number of BP lookups 189system.cpu.branchPred.condPredicted 74778233 # Number of conditional branches predicted 190system.cpu.branchPred.condIncorrect 6277605 # Number of conditional branches incorrect 191system.cpu.branchPred.BTBLookups 44694278 # Number of BTB lookups 192system.cpu.branchPred.BTBHits 43050555 # Number of BTB hits |
| 193system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 193system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 194system.cpu.branchPred.BTBHitPct 96.252694 # BTB Hit Percentage 195system.cpu.branchPred.usedRAS 4355507 # Number of times the RAS was used to get a target. 196system.cpu.branchPred.RASInCorrect 88338 # Number of incorrect RAS predictions. | 194system.cpu.branchPred.BTBHitPct 96.322297 # BTB Hit Percentage 195system.cpu.branchPred.usedRAS 4352672 # Number of times the RAS was used to get a target. 196system.cpu.branchPred.RASInCorrect 88403 # Number of incorrect RAS predictions. |
| 197system.cpu.dtb.inst_hits 0 # ITB inst hits 198system.cpu.dtb.inst_misses 0 # ITB inst misses 199system.cpu.dtb.read_hits 0 # DTB read hits 200system.cpu.dtb.read_misses 0 # DTB read misses 201system.cpu.dtb.write_hits 0 # DTB write hits 202system.cpu.dtb.write_misses 0 # DTB write misses 203system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 204system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 232system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 233system.cpu.itb.read_accesses 0 # DTB read accesses 234system.cpu.itb.write_accesses 0 # DTB write accesses 235system.cpu.itb.inst_accesses 0 # ITB inst accesses 236system.cpu.itb.hits 0 # DTB hits 237system.cpu.itb.misses 0 # DTB misses 238system.cpu.itb.accesses 0 # DTB accesses 239system.cpu.workload.num_syscalls 400 # Number of system calls | 197system.cpu.dtb.inst_hits 0 # ITB inst hits 198system.cpu.dtb.inst_misses 0 # ITB inst misses 199system.cpu.dtb.read_hits 0 # DTB read hits 200system.cpu.dtb.read_misses 0 # DTB read misses 201system.cpu.dtb.write_hits 0 # DTB write hits 202system.cpu.dtb.write_misses 0 # DTB write misses 203system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 204system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 232system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 233system.cpu.itb.read_accesses 0 # DTB read accesses 234system.cpu.itb.write_accesses 0 # DTB write accesses 235system.cpu.itb.inst_accesses 0 # ITB inst accesses 236system.cpu.itb.hits 0 # DTB hits 237system.cpu.itb.misses 0 # DTB misses 238system.cpu.itb.accesses 0 # DTB accesses 239system.cpu.workload.num_syscalls 400 # Number of system calls |
| 240system.cpu.numCycles 148297707 # number of cpu cycles simulated | 240system.cpu.numCycles 148311904 # number of cpu cycles simulated |
| 241system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 242system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 241system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 242system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 243system.cpu.fetch.icacheStallCycles 39650853 # Number of cycles fetch is stalled on an Icache miss 244system.cpu.fetch.Insts 380235632 # Number of instructions fetch has processed 245system.cpu.fetch.Branches 94799058 # Number of branches that fetch encountered 246system.cpu.fetch.predictedBranches 47403944 # Number of branches that fetch has predicted taken 247system.cpu.fetch.Cycles 80363745 # Number of cycles fetch has run and was not squashing or blocked 248system.cpu.fetch.SquashCycles 27281096 # Number of cycles fetch has spent squashing 249system.cpu.fetch.BlockedCycles 7190522 # Number of cycles fetch has spent blocked 250system.cpu.fetch.MiscStallCycles 43 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 251system.cpu.fetch.PendingTrapStallCycles 5914 # Number of stall cycles due to pending traps | 243system.cpu.fetch.icacheStallCycles 39646309 # Number of cycles fetch is stalled on an Icache miss 244system.cpu.fetch.Insts 380172339 # Number of instructions fetch has processed 245system.cpu.fetch.Branches 94769609 # Number of branches that fetch encountered 246system.cpu.fetch.predictedBranches 47403227 # Number of branches that fetch has predicted taken 247system.cpu.fetch.Cycles 80367500 # Number of cycles fetch has run and was not squashing or blocked 248system.cpu.fetch.SquashCycles 27273234 # Number of cycles fetch has spent squashing 249system.cpu.fetch.BlockedCycles 7195566 # Number of cycles fetch has spent blocked 250system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 251system.cpu.fetch.PendingTrapStallCycles 5621 # Number of stall cycles due to pending traps |
| 252system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions | 252system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions |
| 253system.cpu.fetch.IcacheWaitRetryStallCycles 51 # Number of stall cycles due to full MSHR 254system.cpu.fetch.CacheLines 36846162 # Number of cache lines fetched 255system.cpu.fetch.IcacheSquashes 1830987 # Number of outstanding Icache misses that were squashed 256system.cpu.fetch.rateDist::samples 148197153 # Number of instructions fetched each cycle (Total) 257system.cpu.fetch.rateDist::mean 2.802808 # Number of instructions fetched each cycle (Total) 258system.cpu.fetch.rateDist::stdev 3.153253 # Number of instructions fetched each cycle (Total) | 253system.cpu.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR 254system.cpu.fetch.CacheLines 36841499 # Number of cache lines fetched 255system.cpu.fetch.IcacheSquashes 1830160 # Number of outstanding Icache misses that were squashed 256system.cpu.fetch.rateDist::samples 148194878 # Number of instructions fetched each cycle (Total) 257system.cpu.fetch.rateDist::mean 2.802185 # Number of instructions fetched each cycle (Total) 258system.cpu.fetch.rateDist::stdev 3.152973 # Number of instructions fetched each cycle (Total) |
| 259system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 259system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 260system.cpu.fetch.rateDist::0 68002614 45.89% 45.89% # Number of instructions fetched each cycle (Total) 261system.cpu.fetch.rateDist::1 5258973 3.55% 49.44% # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::2 10529156 7.10% 56.54% # Number of instructions fetched each cycle (Total) 263system.cpu.fetch.rateDist::3 10279296 6.94% 63.48% # Number of instructions fetched each cycle (Total) 264system.cpu.fetch.rateDist::4 8665155 5.85% 69.32% # Number of instructions fetched each cycle (Total) 265system.cpu.fetch.rateDist::5 6547882 4.42% 73.74% # Number of instructions fetched each cycle (Total) 266system.cpu.fetch.rateDist::6 6243481 4.21% 77.95% # Number of instructions fetched each cycle (Total) 267system.cpu.fetch.rateDist::7 8012637 5.41% 83.36% # Number of instructions fetched each cycle (Total) 268system.cpu.fetch.rateDist::8 24657959 16.64% 100.00% # Number of instructions fetched each cycle (Total) | 260system.cpu.fetch.rateDist::0 67997083 45.88% 45.88% # Number of instructions fetched each cycle (Total) 261system.cpu.fetch.rateDist::1 5272996 3.56% 49.44% # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::2 10535975 7.11% 56.55% # Number of instructions fetched each cycle (Total) 263system.cpu.fetch.rateDist::3 10290073 6.94% 63.49% # Number of instructions fetched each cycle (Total) 264system.cpu.fetch.rateDist::4 8651484 5.84% 69.33% # Number of instructions fetched each cycle (Total) 265system.cpu.fetch.rateDist::5 6547502 4.42% 73.75% # Number of instructions fetched each cycle (Total) 266system.cpu.fetch.rateDist::6 6243559 4.21% 77.96% # Number of instructions fetched each cycle (Total) 267system.cpu.fetch.rateDist::7 8000119 5.40% 83.36% # Number of instructions fetched each cycle (Total) 268system.cpu.fetch.rateDist::8 24656087 16.64% 100.00% # Number of instructions fetched each cycle (Total) |
| 269system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 270system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 271system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 269system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 270system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 271system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 272system.cpu.fetch.rateDist::total 148197153 # Number of instructions fetched each cycle (Total) 273system.cpu.fetch.branchRate 0.639248 # Number of branch fetches per cycle 274system.cpu.fetch.rate 2.564002 # Number of inst fetches per cycle 275system.cpu.decode.IdleCycles 45504222 # Number of cycles decode is idle 276system.cpu.decode.BlockedCycles 5859124 # Number of cycles decode is blocked 277system.cpu.decode.RunCycles 74799977 # Number of cycles decode is running 278system.cpu.decode.UnblockCycles 1201103 # Number of cycles decode is unblocking 279system.cpu.decode.SquashCycles 20832727 # Number of cycles decode is squashing 280system.cpu.decode.BranchResolved 14326960 # Number of times decode resolved a branch 281system.cpu.decode.BranchMispred 164415 # Number of times decode detected a branch misprediction 282system.cpu.decode.DecodedInsts 392837219 # Number of instructions handled by decode 283system.cpu.decode.SquashedInsts 734618 # Number of squashed instructions handled by decode 284system.cpu.rename.SquashCycles 20832727 # Number of cycles rename is squashing 285system.cpu.rename.IdleCycles 50888432 # Number of cycles rename is idle 286system.cpu.rename.BlockCycles 722612 # Number of cycles rename is blocking 287system.cpu.rename.serializeStallCycles 592441 # count of cycles rename stalled for serializing inst 288system.cpu.rename.RunCycles 70554465 # Number of cycles rename is running 289system.cpu.rename.UnblockCycles 4606476 # Number of cycles rename is unblocking 290system.cpu.rename.RenamedInsts 371355589 # Number of instructions processed by rename 291system.cpu.rename.ROBFullEvents 30 # Number of times rename has blocked due to ROB full 292system.cpu.rename.IQFullEvents 339881 # Number of times rename has blocked due to IQ full 293system.cpu.rename.LSQFullEvents 3653545 # Number of times rename has blocked due to LSQ full 294system.cpu.rename.FullRegisterEvents 8 # Number of times there has been no free registers 295system.cpu.rename.RenamedOperands 631848996 # Number of destination operands rename has renamed 296system.cpu.rename.RenameLookups 1581867929 # Number of register rename lookups that rename has made 297system.cpu.rename.int_rename_lookups 1564559444 # Number of integer rename lookups 298system.cpu.rename.fp_rename_lookups 17308485 # Number of floating rename lookups | 272system.cpu.fetch.rateDist::total 148194878 # Number of instructions fetched each cycle (Total) 273system.cpu.fetch.branchRate 0.638989 # Number of branch fetches per cycle 274system.cpu.fetch.rate 2.563330 # Number of inst fetches per cycle 275system.cpu.decode.IdleCycles 45496007 # Number of cycles decode is idle 276system.cpu.decode.BlockedCycles 5866375 # Number of cycles decode is blocked 277system.cpu.decode.RunCycles 74802564 # Number of cycles decode is running 278system.cpu.decode.UnblockCycles 1203257 # Number of cycles decode is unblocking 279system.cpu.decode.SquashCycles 20826675 # Number of cycles decode is squashing 280system.cpu.decode.BranchResolved 14321536 # Number of times decode resolved a branch 281system.cpu.decode.BranchMispred 164034 # Number of times decode detected a branch misprediction 282system.cpu.decode.DecodedInsts 392763604 # Number of instructions handled by decode 283system.cpu.decode.SquashedInsts 730055 # Number of squashed instructions handled by decode 284system.cpu.rename.SquashCycles 20826675 # Number of cycles rename is squashing 285system.cpu.rename.IdleCycles 50882111 # Number of cycles rename is idle 286system.cpu.rename.BlockCycles 721217 # Number of cycles rename is blocking 287system.cpu.rename.serializeStallCycles 592672 # count of cycles rename stalled for serializing inst 288system.cpu.rename.RunCycles 70557397 # Number of cycles rename is running 289system.cpu.rename.UnblockCycles 4614806 # Number of cycles rename is unblocking 290system.cpu.rename.RenamedInsts 371296733 # Number of instructions processed by rename 291system.cpu.rename.ROBFullEvents 36 # Number of times rename has blocked due to ROB full 292system.cpu.rename.IQFullEvents 341377 # Number of times rename has blocked due to IQ full 293system.cpu.rename.LSQFullEvents 3661217 # Number of times rename has blocked due to LSQ full 294system.cpu.rename.FullRegisterEvents 37 # Number of times there has been no free registers 295system.cpu.rename.RenamedOperands 631671723 # Number of destination operands rename has renamed 296system.cpu.rename.RenameLookups 1581648558 # Number of register rename lookups that rename has made 297system.cpu.rename.int_rename_lookups 1564322118 # Number of integer rename lookups 298system.cpu.rename.fp_rename_lookups 17326440 # Number of floating rename lookups |
| 299system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed | 299system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed |
| 300system.cpu.rename.UndoneMaps 333804857 # Number of HB maps that are undone due to squashing 301system.cpu.rename.serializingInsts 25175 # count of serializing insts renamed 302system.cpu.rename.tempSerializingInsts 25171 # count of temporary serializing insts renamed 303system.cpu.rename.skidInsts 13001756 # count of insts added to the skid buffer 304system.cpu.memDep0.insertedLoads 43004891 # Number of loads inserted to the mem dependence unit. 305system.cpu.memDep0.insertedStores 16418786 # Number of stores inserted to the mem dependence unit. 306system.cpu.memDep0.conflictingLoads 5685881 # Number of conflicting loads. 307system.cpu.memDep0.conflictingStores 3634471 # Number of conflicting stores. 308system.cpu.iq.iqInstsAdded 329217927 # Number of instructions added to the IQ (excludes non-spec) 309system.cpu.iq.iqNonSpecInstsAdded 47188 # Number of non-speculative instructions added to the IQ 310system.cpu.iq.iqInstsIssued 249444233 # Number of instructions issued 311system.cpu.iq.iqSquashedInstsIssued 790071 # Number of squashed instructions issued 312system.cpu.iq.iqSquashedInstsExamined 139538270 # Number of squashed instructions iterated over during squash; mainly for profiling 313system.cpu.iq.iqSquashedOperandsExamined 362161071 # Number of squashed operands that are examined and possibly removed from graph 314system.cpu.iq.iqSquashedNonSpecRemoved 1972 # Number of squashed non-spec instructions that were removed 315system.cpu.iq.issued_per_cycle::samples 148197153 # Number of insts issued each cycle 316system.cpu.iq.issued_per_cycle::mean 1.683192 # Number of insts issued each cycle 317system.cpu.iq.issued_per_cycle::stdev 1.761683 # Number of insts issued each cycle | 300system.cpu.rename.UndoneMaps 333627584 # Number of HB maps that are undone due to squashing 301system.cpu.rename.serializingInsts 25019 # count of serializing insts renamed 302system.cpu.rename.tempSerializingInsts 25015 # count of temporary serializing insts renamed 303system.cpu.rename.skidInsts 13027360 # count of insts added to the skid buffer 304system.cpu.memDep0.insertedLoads 43001248 # Number of loads inserted to the mem dependence unit. 305system.cpu.memDep0.insertedStores 16425649 # Number of stores inserted to the mem dependence unit. 306system.cpu.memDep0.conflictingLoads 5676819 # Number of conflicting loads. 307system.cpu.memDep0.conflictingStores 3663476 # Number of conflicting stores. 308system.cpu.iq.iqInstsAdded 329185491 # Number of instructions added to the IQ (excludes non-spec) 309system.cpu.iq.iqNonSpecInstsAdded 47072 # Number of non-speculative instructions added to the IQ 310system.cpu.iq.iqInstsIssued 249459953 # Number of instructions issued 311system.cpu.iq.iqSquashedInstsIssued 787409 # Number of squashed instructions issued 312system.cpu.iq.iqSquashedInstsExamined 139507738 # Number of squashed instructions iterated over during squash; mainly for profiling 313system.cpu.iq.iqSquashedOperandsExamined 361963164 # Number of squashed operands that are examined and possibly removed from graph 314system.cpu.iq.iqSquashedNonSpecRemoved 1856 # Number of squashed non-spec instructions that were removed 315system.cpu.iq.issued_per_cycle::samples 148194878 # Number of insts issued each cycle 316system.cpu.iq.issued_per_cycle::mean 1.683324 # Number of insts issued each cycle 317system.cpu.iq.issued_per_cycle::stdev 1.761955 # Number of insts issued each cycle |
| 318system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 318system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 319system.cpu.iq.issued_per_cycle::0 56041941 37.82% 37.82% # Number of insts issued each cycle 320system.cpu.iq.issued_per_cycle::1 22617532 15.26% 53.08% # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::2 24819018 16.75% 69.82% # Number of insts issued each cycle 322system.cpu.iq.issued_per_cycle::3 20330052 13.72% 83.54% # Number of insts issued each cycle 323system.cpu.iq.issued_per_cycle::4 12543560 8.46% 92.01% # Number of insts issued each cycle 324system.cpu.iq.issued_per_cycle::5 6522981 4.40% 96.41% # Number of insts issued each cycle 325system.cpu.iq.issued_per_cycle::6 4027974 2.72% 99.13% # Number of insts issued each cycle 326system.cpu.iq.issued_per_cycle::7 1111240 0.75% 99.88% # Number of insts issued each cycle 327system.cpu.iq.issued_per_cycle::8 182855 0.12% 100.00% # Number of insts issued each cycle | 319system.cpu.iq.issued_per_cycle::0 56034848 37.81% 37.81% # Number of insts issued each cycle 320system.cpu.iq.issued_per_cycle::1 22634456 15.27% 53.09% # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::2 24811776 16.74% 69.83% # Number of insts issued each cycle 322system.cpu.iq.issued_per_cycle::3 20313354 13.71% 83.53% # Number of insts issued each cycle 323system.cpu.iq.issued_per_cycle::4 12551343 8.47% 92.00% # Number of insts issued each cycle 324system.cpu.iq.issued_per_cycle::5 6515797 4.40% 96.40% # Number of insts issued each cycle 325system.cpu.iq.issued_per_cycle::6 4037298 2.72% 99.13% # Number of insts issued each cycle 326system.cpu.iq.issued_per_cycle::7 1114310 0.75% 99.88% # Number of insts issued each cycle 327system.cpu.iq.issued_per_cycle::8 181696 0.12% 100.00% # Number of insts issued each cycle |
| 328system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 329system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 330system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 328system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 329system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 330system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 331system.cpu.iq.issued_per_cycle::total 148197153 # Number of insts issued each cycle | 331system.cpu.iq.issued_per_cycle::total 148194878 # Number of insts issued each cycle |
| 332system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 332system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 333system.cpu.iq.fu_full::IntAlu 964308 38.46% 38.46% # attempts to use FU when none available 334system.cpu.iq.fu_full::IntMult 5601 0.22% 38.68% # attempts to use FU when none available 335system.cpu.iq.fu_full::IntDiv 0 0.00% 38.68% # attempts to use FU when none available 336system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.68% # attempts to use FU when none available 337system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.68% # attempts to use FU when none available 338system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.68% # attempts to use FU when none available 339system.cpu.iq.fu_full::FloatMult 0 0.00% 38.68% # attempts to use FU when none available 340system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.68% # attempts to use FU when none available 341system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.68% # attempts to use FU when none available 342system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.68% # attempts to use FU when none available 343system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.68% # attempts to use FU when none available 344system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.68% # attempts to use FU when none available 345system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.68% # attempts to use FU when none available 346system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.68% # attempts to use FU when none available 347system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.68% # attempts to use FU when none available 348system.cpu.iq.fu_full::SimdMult 0 0.00% 38.68% # attempts to use FU when none available 349system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.68% # attempts to use FU when none available 350system.cpu.iq.fu_full::SimdShift 0 0.00% 38.68% # attempts to use FU when none available 351system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.68% # attempts to use FU when none available 352system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.68% # attempts to use FU when none available 353system.cpu.iq.fu_full::SimdFloatAdd 100 0.00% 38.69% # attempts to use FU when none available 354system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.69% # attempts to use FU when none available 355system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.69% # attempts to use FU when none available 356system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.69% # attempts to use FU when none available 357system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.69% # attempts to use FU when none available 358system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.69% # attempts to use FU when none available 359system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.69% # attempts to use FU when none available 360system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.69% # attempts to use FU when none available 361system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.69% # attempts to use FU when none available 362system.cpu.iq.fu_full::MemRead 1163168 46.39% 85.08% # attempts to use FU when none available 363system.cpu.iq.fu_full::MemWrite 374037 14.92% 100.00% # attempts to use FU when none available | 333system.cpu.iq.fu_full::IntAlu 964655 38.37% 38.37% # attempts to use FU when none available 334system.cpu.iq.fu_full::IntMult 5597 0.22% 38.59% # attempts to use FU when none available 335system.cpu.iq.fu_full::IntDiv 0 0.00% 38.59% # attempts to use FU when none available 336system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.59% # attempts to use FU when none available 337system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.59% # attempts to use FU when none available 338system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.59% # attempts to use FU when none available 339system.cpu.iq.fu_full::FloatMult 0 0.00% 38.59% # attempts to use FU when none available 340system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.59% # attempts to use FU when none available 341system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.59% # attempts to use FU when none available 342system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.59% # attempts to use FU when none available 343system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.59% # attempts to use FU when none available 344system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.59% # attempts to use FU when none available 345system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.59% # attempts to use FU when none available 346system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.59% # attempts to use FU when none available 347system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.59% # attempts to use FU when none available 348system.cpu.iq.fu_full::SimdMult 0 0.00% 38.59% # attempts to use FU when none available 349system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.59% # attempts to use FU when none available 350system.cpu.iq.fu_full::SimdShift 0 0.00% 38.59% # attempts to use FU when none available 351system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.59% # attempts to use FU when none available 352system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.59% # attempts to use FU when none available 353system.cpu.iq.fu_full::SimdFloatAdd 98 0.00% 38.60% # attempts to use FU when none available 354system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.60% # attempts to use FU when none available 355system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.60% # attempts to use FU when none available 356system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.60% # attempts to use FU when none available 357system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.60% # attempts to use FU when none available 358system.cpu.iq.fu_full::SimdFloatMisc 47 0.00% 38.60% # attempts to use FU when none available 359system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.60% # attempts to use FU when none available 360system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.60% # attempts to use FU when none available 361system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.60% # attempts to use FU when none available 362system.cpu.iq.fu_full::MemRead 1171629 46.60% 85.20% # attempts to use FU when none available 363system.cpu.iq.fu_full::MemWrite 372002 14.80% 100.00% # attempts to use FU when none available |
| 364system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 365system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 366system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 364system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 365system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 366system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 367system.cpu.iq.FU_type_0::IntAlu 194888705 78.13% 78.13% # Type of FU issued 368system.cpu.iq.FU_type_0::IntMult 979440 0.39% 78.52% # Type of FU issued | 367system.cpu.iq.FU_type_0::IntAlu 194901733 78.13% 78.13% # Type of FU issued 368system.cpu.iq.FU_type_0::IntMult 979970 0.39% 78.52% # Type of FU issued |
| 369system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued 370system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued 371system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued 372system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.52% # Type of FU issued 373system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.52% # Type of FU issued 374system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.52% # Type of FU issued 375system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.52% # Type of FU issued 376system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.52% # Type of FU issued 377system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.52% # Type of FU issued 378system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.52% # Type of FU issued 379system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.52% # Type of FU issued 380system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.52% # Type of FU issued 381system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.52% # Type of FU issued 382system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.52% # Type of FU issued 383system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Type of FU issued 384system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued 385system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued 386system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued | 369system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued 370system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued 371system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued 372system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.52% # Type of FU issued 373system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.52% # Type of FU issued 374system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.52% # Type of FU issued 375system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.52% # Type of FU issued 376system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.52% # Type of FU issued 377system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.52% # Type of FU issued 378system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.52% # Type of FU issued 379system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.52% # Type of FU issued 380system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.52% # Type of FU issued 381system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.52% # Type of FU issued 382system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.52% # Type of FU issued 383system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Type of FU issued 384system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued 385system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued 386system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued |
| 387system.cpu.iq.FU_type_0::SimdFloatAdd 33084 0.01% 78.54% # Type of FU issued | 387system.cpu.iq.FU_type_0::SimdFloatAdd 33123 0.01% 78.54% # Type of FU issued |
| 388system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.54% # Type of FU issued | 388system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.54% # Type of FU issued |
| 389system.cpu.iq.FU_type_0::SimdFloatCmp 164341 0.07% 78.60% # Type of FU issued 390system.cpu.iq.FU_type_0::SimdFloatCvt 254530 0.10% 78.70% # Type of FU issued 391system.cpu.iq.FU_type_0::SimdFloatDiv 76430 0.03% 78.73% # Type of FU issued 392system.cpu.iq.FU_type_0::SimdFloatMisc 465703 0.19% 78.92% # Type of FU issued 393system.cpu.iq.FU_type_0::SimdFloatMult 206396 0.08% 79.00% # Type of FU issued 394system.cpu.iq.FU_type_0::SimdFloatMultAcc 71859 0.03% 79.03% # Type of FU issued 395system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 79.03% # Type of FU issued 396system.cpu.iq.FU_type_0::MemRead 38355599 15.38% 94.41% # Type of FU issued 397system.cpu.iq.FU_type_0::MemWrite 13947826 5.59% 100.00% # Type of FU issued | 389system.cpu.iq.FU_type_0::SimdFloatCmp 164480 0.07% 78.60% # Type of FU issued 390system.cpu.iq.FU_type_0::SimdFloatCvt 254950 0.10% 78.70% # Type of FU issued 391system.cpu.iq.FU_type_0::SimdFloatDiv 76426 0.03% 78.73% # Type of FU issued 392system.cpu.iq.FU_type_0::SimdFloatMisc 465883 0.19% 78.92% # Type of FU issued 393system.cpu.iq.FU_type_0::SimdFloatMult 206474 0.08% 79.00% # Type of FU issued 394system.cpu.iq.FU_type_0::SimdFloatMultAcc 71858 0.03% 79.03% # Type of FU issued 395system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued 396system.cpu.iq.FU_type_0::MemRead 38354449 15.37% 94.41% # Type of FU issued 397system.cpu.iq.FU_type_0::MemWrite 13950286 5.59% 100.00% # Type of FU issued |
| 398system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 399system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 398system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 399system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 400system.cpu.iq.FU_type_0::total 249444233 # Type of FU issued 401system.cpu.iq.rate 1.682051 # Inst issue rate 402system.cpu.iq.fu_busy_cnt 2507262 # FU busy when requested 403system.cpu.iq.fu_busy_rate 0.010051 # FU busy rate (busy events/executed inst) 404system.cpu.iq.int_inst_queue_reads 646645921 # Number of integer instruction queue reads 405system.cpu.iq.int_inst_queue_writes 466634028 # Number of integer instruction queue writes 406system.cpu.iq.int_inst_queue_wakeup_accesses 237875698 # Number of integer instruction queue wakeup accesses 407system.cpu.iq.fp_inst_queue_reads 3737031 # Number of floating instruction queue reads 408system.cpu.iq.fp_inst_queue_writes 2187759 # Number of floating instruction queue writes 409system.cpu.iq.fp_inst_queue_wakeup_accesses 1841461 # Number of floating instruction queue wakeup accesses 410system.cpu.iq.int_alu_accesses 250076224 # Number of integer alu accesses 411system.cpu.iq.fp_alu_accesses 1875271 # Number of floating point alu accesses 412system.cpu.iew.lsq.thread0.forwLoads 2007740 # Number of loads that had data forwarded from stores | 400system.cpu.iq.FU_type_0::total 249459953 # Type of FU issued 401system.cpu.iq.rate 1.681995 # Inst issue rate 402system.cpu.iq.fu_busy_cnt 2514028 # FU busy when requested 403system.cpu.iq.fu_busy_rate 0.010078 # FU busy rate (busy events/executed inst) 404system.cpu.iq.int_inst_queue_reads 646678377 # Number of integer instruction queue reads 405system.cpu.iq.int_inst_queue_writes 466567894 # Number of integer instruction queue writes 406system.cpu.iq.int_inst_queue_wakeup_accesses 237899290 # Number of integer instruction queue wakeup accesses 407system.cpu.iq.fp_inst_queue_reads 3737844 # Number of floating instruction queue reads 408system.cpu.iq.fp_inst_queue_writes 2190776 # Number of floating instruction queue writes 409system.cpu.iq.fp_inst_queue_wakeup_accesses 1842401 # Number of floating instruction queue wakeup accesses 410system.cpu.iq.int_alu_accesses 250099013 # Number of integer alu accesses 411system.cpu.iq.fp_alu_accesses 1874968 # Number of floating point alu accesses 412system.cpu.iew.lsq.thread0.forwLoads 2006458 # Number of loads that had data forwarded from stores |
| 413system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 413system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 414system.cpu.iew.lsq.thread0.squashedLoads 13155407 # Number of loads squashed 415system.cpu.iew.lsq.thread0.ignoredResponses 11336 # Number of memory responses ignored because the instruction is squashed 416system.cpu.iew.lsq.thread0.memOrderViolation 18867 # Number of memory ordering violations 417system.cpu.iew.lsq.thread0.squashedStores 3774152 # Number of stores squashed | 414system.cpu.iew.lsq.thread0.squashedLoads 13151764 # Number of loads squashed 415system.cpu.iew.lsq.thread0.ignoredResponses 11904 # Number of memory responses ignored because the instruction is squashed 416system.cpu.iew.lsq.thread0.memOrderViolation 18813 # Number of memory ordering violations 417system.cpu.iew.lsq.thread0.squashedStores 3781015 # Number of stores squashed |
| 418system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 419system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 418system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 419system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 420system.cpu.iew.lsq.thread0.rescheduledLoads 17 # Number of loads that were rescheduled 421system.cpu.iew.lsq.thread0.cacheBlocked 95 # Number of times an access to memory failed due to the cache being blocked | 420system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled 421system.cpu.iew.lsq.thread0.cacheBlocked 104 # Number of times an access to memory failed due to the cache being blocked |
| 422system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 422system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 423system.cpu.iew.iewSquashCycles 20832727 # Number of cycles IEW is squashing 424system.cpu.iew.iewBlockCycles 16956 # Number of cycles IEW is blocking 425system.cpu.iew.iewUnblockCycles 865 # Number of cycles IEW is unblocking 426system.cpu.iew.iewDispatchedInsts 329282292 # Number of instructions dispatched to IQ 427system.cpu.iew.iewDispSquashedInsts 783571 # Number of squashed instructions skipped by dispatch 428system.cpu.iew.iewDispLoadInsts 43004891 # Number of dispatched load instructions 429system.cpu.iew.iewDispStoreInsts 16418786 # Number of dispatched store instructions 430system.cpu.iew.iewDispNonSpecInsts 24780 # Number of dispatched non-speculative instructions 431system.cpu.iew.iewIQFullEvents 182 # Number of times the IQ has become full, causing a stall 432system.cpu.iew.iewLSQFullEvents 273 # Number of times the LSQ has become full, causing a stall 433system.cpu.iew.memOrderViolationEvents 18867 # Number of memory order violations 434system.cpu.iew.predictedTakenIncorrect 3889474 # Number of branches that were predicted taken incorrectly 435system.cpu.iew.predictedNotTakenIncorrect 3759056 # Number of branches that were predicted not taken incorrectly 436system.cpu.iew.branchMispredicts 7648530 # Number of branch mispredicts detected at execute 437system.cpu.iew.iewExecutedInsts 242951850 # Number of executed instructions 438system.cpu.iew.iewExecLoadInsts 36852953 # Number of load instructions executed 439system.cpu.iew.iewExecSquashedInsts 6492383 # Number of squashed instructions skipped in execute | 423system.cpu.iew.iewSquashCycles 20826675 # Number of cycles IEW is squashing 424system.cpu.iew.iewBlockCycles 16651 # Number of cycles IEW is blocking 425system.cpu.iew.iewUnblockCycles 839 # Number of cycles IEW is unblocking 426system.cpu.iew.iewDispatchedInsts 329249613 # Number of instructions dispatched to IQ 427system.cpu.iew.iewDispSquashedInsts 779131 # Number of squashed instructions skipped by dispatch 428system.cpu.iew.iewDispLoadInsts 43001248 # Number of dispatched load instructions 429system.cpu.iew.iewDispStoreInsts 16425649 # Number of dispatched store instructions 430system.cpu.iew.iewDispNonSpecInsts 24664 # Number of dispatched non-speculative instructions 431system.cpu.iew.iewIQFullEvents 195 # Number of times the IQ has become full, causing a stall 432system.cpu.iew.iewLSQFullEvents 269 # Number of times the LSQ has become full, causing a stall 433system.cpu.iew.memOrderViolationEvents 18813 # Number of memory order violations 434system.cpu.iew.predictedTakenIncorrect 3890202 # Number of branches that were predicted taken incorrectly 435system.cpu.iew.predictedNotTakenIncorrect 3759917 # Number of branches that were predicted not taken incorrectly 436system.cpu.iew.branchMispredicts 7650119 # Number of branch mispredicts detected at execute 437system.cpu.iew.iewExecutedInsts 242971028 # Number of executed instructions 438system.cpu.iew.iewExecLoadInsts 36855113 # Number of load instructions executed 439system.cpu.iew.iewExecSquashedInsts 6488925 # Number of squashed instructions skipped in execute |
| 440system.cpu.iew.exec_swp 0 # number of swp insts executed | 440system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 441system.cpu.iew.exec_nop 17177 # number of nop insts executed 442system.cpu.iew.exec_refs 50499895 # number of memory reference insts executed 443system.cpu.iew.exec_branches 53421871 # Number of branches executed 444system.cpu.iew.exec_stores 13646942 # Number of stores executed 445system.cpu.iew.exec_rate 1.638271 # Inst execution rate 446system.cpu.iew.wb_sent 240774594 # cumulative count of insts sent to commit 447system.cpu.iew.wb_count 239717159 # cumulative count of insts written-back 448system.cpu.iew.wb_producers 148465347 # num instructions producing a value 449system.cpu.iew.wb_consumers 267264848 # num instructions consuming a value | 441system.cpu.iew.exec_nop 17050 # number of nop insts executed 442system.cpu.iew.exec_refs 50502517 # number of memory reference insts executed 443system.cpu.iew.exec_branches 53426440 # Number of branches executed 444system.cpu.iew.exec_stores 13647404 # Number of stores executed 445system.cpu.iew.exec_rate 1.638244 # Inst execution rate 446system.cpu.iew.wb_sent 240798946 # cumulative count of insts sent to commit 447system.cpu.iew.wb_count 239741691 # cumulative count of insts written-back 448system.cpu.iew.wb_producers 148482444 # num instructions producing a value 449system.cpu.iew.wb_consumers 267276214 # num instructions consuming a value |
| 450system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 450system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 451system.cpu.iew.wb_rate 1.616459 # insts written-back per cycle 452system.cpu.iew.wb_fanout 0.555499 # average fanout of values written-back | 451system.cpu.iew.wb_rate 1.616470 # insts written-back per cycle 452system.cpu.iew.wb_fanout 0.555539 # average fanout of values written-back |
| 453system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 453system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 454system.cpu.commit.commitSquashedInsts 140611386 # The number of squashed insts skipped by commit | 454system.cpu.commit.commitSquashedInsts 140578703 # The number of squashed insts skipped by commit |
| 455system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards | 455system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards |
| 456system.cpu.commit.branchMispredicts 6125994 # The number of times a branch was mispredicted 457system.cpu.commit.committed_per_cycle::samples 127364426 # Number of insts commited each cycle 458system.cpu.commit.committed_per_cycle::mean 1.481347 # Number of insts commited each cycle 459system.cpu.commit.committed_per_cycle::stdev 2.186226 # Number of insts commited each cycle | 456system.cpu.commit.branchMispredicts 6124430 # The number of times a branch was mispredicted 457system.cpu.commit.committed_per_cycle::samples 127368203 # Number of insts commited each cycle 458system.cpu.commit.committed_per_cycle::mean 1.481303 # Number of insts commited each cycle 459system.cpu.commit.committed_per_cycle::stdev 2.186211 # Number of insts commited each cycle |
| 460system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 460system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 461system.cpu.commit.committed_per_cycle::0 57685030 45.29% 45.29% # Number of insts commited each cycle 462system.cpu.commit.committed_per_cycle::1 31666758 24.86% 70.15% # Number of insts commited each cycle 463system.cpu.commit.committed_per_cycle::2 13788542 10.83% 80.98% # Number of insts commited each cycle 464system.cpu.commit.committed_per_cycle::3 7634444 5.99% 86.97% # Number of insts commited each cycle 465system.cpu.commit.committed_per_cycle::4 4378206 3.44% 90.41% # Number of insts commited each cycle 466system.cpu.commit.committed_per_cycle::5 1321179 1.04% 91.45% # Number of insts commited each cycle 467system.cpu.commit.committed_per_cycle::6 1702157 1.34% 92.79% # Number of insts commited each cycle 468system.cpu.commit.committed_per_cycle::7 1312824 1.03% 93.82% # Number of insts commited each cycle 469system.cpu.commit.committed_per_cycle::8 7875286 6.18% 100.00% # Number of insts commited each cycle | 461system.cpu.commit.committed_per_cycle::0 57677570 45.28% 45.28% # Number of insts commited each cycle 462system.cpu.commit.committed_per_cycle::1 31688766 24.88% 70.16% # Number of insts commited each cycle 463system.cpu.commit.committed_per_cycle::2 13782136 10.82% 80.98% # Number of insts commited each cycle 464system.cpu.commit.committed_per_cycle::3 7629564 5.99% 86.97% # Number of insts commited each cycle 465system.cpu.commit.committed_per_cycle::4 4377691 3.44% 90.41% # Number of insts commited each cycle 466system.cpu.commit.committed_per_cycle::5 1320690 1.04% 91.45% # Number of insts commited each cycle 467system.cpu.commit.committed_per_cycle::6 1704652 1.34% 92.79% # Number of insts commited each cycle 468system.cpu.commit.committed_per_cycle::7 1310037 1.03% 93.82% # Number of insts commited each cycle 469system.cpu.commit.committed_per_cycle::8 7877097 6.18% 100.00% # Number of insts commited each cycle |
| 470system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 471system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 472system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 470system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 471system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 472system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 473system.cpu.commit.committed_per_cycle::total 127364426 # Number of insts commited each cycle | 473system.cpu.commit.committed_per_cycle::total 127368203 # Number of insts commited each cycle |
| 474system.cpu.commit.committedInsts 172317409 # Number of instructions committed 475system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed 476system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 477system.cpu.commit.refs 42494118 # Number of memory references committed 478system.cpu.commit.loads 29849484 # Number of loads committed 479system.cpu.commit.membars 22408 # Number of memory barriers committed 480system.cpu.commit.branches 40300311 # Number of branches committed 481system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. 482system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. 483system.cpu.commit.function_calls 1848934 # Number of function calls committed. | 474system.cpu.commit.committedInsts 172317409 # Number of instructions committed 475system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed 476system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 477system.cpu.commit.refs 42494118 # Number of memory references committed 478system.cpu.commit.loads 29849484 # Number of loads committed 479system.cpu.commit.membars 22408 # Number of memory barriers committed 480system.cpu.commit.branches 40300311 # Number of branches committed 481system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. 482system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. 483system.cpu.commit.function_calls 1848934 # Number of function calls committed. |
| 484system.cpu.commit.bw_lim_events 7875286 # number cycles where commit BW limit reached | 484system.cpu.commit.bw_lim_events 7877097 # number cycles where commit BW limit reached |
| 485system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 485system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 486system.cpu.rob.rob_reads 448766216 # The number of ROB reads 487system.cpu.rob.rob_writes 679506166 # The number of ROB writes 488system.cpu.timesIdled 2556 # Number of times that the entire CPU went into an idle state and unscheduled itself 489system.cpu.idleCycles 100554 # Total number of cycles that the CPU has spent unscheduled due to idling | 486system.cpu.rob.rob_reads 448735499 # The number of ROB reads 487system.cpu.rob.rob_writes 679435154 # The number of ROB writes 488system.cpu.timesIdled 2602 # Number of times that the entire CPU went into an idle state and unscheduled itself 489system.cpu.idleCycles 117026 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 490system.cpu.committedInsts 172303021 # Number of Instructions Simulated 491system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated 492system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated | 490system.cpu.committedInsts 172303021 # Number of Instructions Simulated 491system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated 492system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated |
| 493system.cpu.cpi 0.860680 # CPI: Cycles Per Instruction 494system.cpu.cpi_total 0.860680 # CPI: Total CPI of All Threads 495system.cpu.ipc 1.161872 # IPC: Instructions Per Cycle 496system.cpu.ipc_total 1.161872 # IPC: Total IPC of All Threads 497system.cpu.int_regfile_reads 1079384127 # number of integer regfile reads 498system.cpu.int_regfile_writes 384869699 # number of integer regfile writes 499system.cpu.fp_regfile_reads 2912697 # number of floating regfile reads 500system.cpu.fp_regfile_writes 2497246 # number of floating regfile writes 501system.cpu.misc_regfile_reads 54493639 # number of misc regfile reads | 493system.cpu.cpi 0.860762 # CPI: Cycles Per Instruction 494system.cpu.cpi_total 0.860762 # CPI: Total CPI of All Threads 495system.cpu.ipc 1.161761 # IPC: Instructions Per Cycle 496system.cpu.ipc_total 1.161761 # IPC: Total IPC of All Threads 497system.cpu.int_regfile_reads 1079459412 # number of integer regfile reads 498system.cpu.int_regfile_writes 384885584 # number of integer regfile writes 499system.cpu.fp_regfile_reads 2914044 # number of floating regfile reads 500system.cpu.fp_regfile_writes 2498648 # number of floating regfile writes 501system.cpu.misc_regfile_reads 54505090 # number of misc regfile reads |
| 502system.cpu.misc_regfile_writes 820036 # number of misc regfile writes | 502system.cpu.misc_regfile_writes 820036 # number of misc regfile writes |
| 503system.cpu.icache.replacements 2375 # number of replacements 504system.cpu.icache.tagsinuse 1350.215949 # Cycle average of tags in use 505system.cpu.icache.total_refs 36840897 # Total number of references to valid blocks. 506system.cpu.icache.sampled_refs 4105 # Sample count of references to valid blocks. 507system.cpu.icache.avg_refs 8974.639951 # Average number of references to valid blocks. | 503system.cpu.icache.replacements 2367 # number of replacements 504system.cpu.icache.tagsinuse 1349.329106 # Cycle average of tags in use 505system.cpu.icache.total_refs 36836268 # Total number of references to valid blocks. 506system.cpu.icache.sampled_refs 4097 # Sample count of references to valid blocks. 507system.cpu.icache.avg_refs 8991.034415 # Average number of references to valid blocks. |
| 508system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 508system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 509system.cpu.icache.occ_blocks::cpu.inst 1350.215949 # Average occupied blocks per requestor 510system.cpu.icache.occ_percent::cpu.inst 0.659285 # Average percentage of cache occupancy 511system.cpu.icache.occ_percent::total 0.659285 # Average percentage of cache occupancy 512system.cpu.icache.ReadReq_hits::cpu.inst 36840897 # number of ReadReq hits 513system.cpu.icache.ReadReq_hits::total 36840897 # number of ReadReq hits 514system.cpu.icache.demand_hits::cpu.inst 36840897 # number of demand (read+write) hits 515system.cpu.icache.demand_hits::total 36840897 # number of demand (read+write) hits 516system.cpu.icache.overall_hits::cpu.inst 36840897 # number of overall hits 517system.cpu.icache.overall_hits::total 36840897 # number of overall hits 518system.cpu.icache.ReadReq_misses::cpu.inst 5265 # number of ReadReq misses 519system.cpu.icache.ReadReq_misses::total 5265 # number of ReadReq misses 520system.cpu.icache.demand_misses::cpu.inst 5265 # number of demand (read+write) misses 521system.cpu.icache.demand_misses::total 5265 # number of demand (read+write) misses 522system.cpu.icache.overall_misses::cpu.inst 5265 # number of overall misses 523system.cpu.icache.overall_misses::total 5265 # number of overall misses 524system.cpu.icache.ReadReq_miss_latency::cpu.inst 158318499 # number of ReadReq miss cycles 525system.cpu.icache.ReadReq_miss_latency::total 158318499 # number of ReadReq miss cycles 526system.cpu.icache.demand_miss_latency::cpu.inst 158318499 # number of demand (read+write) miss cycles 527system.cpu.icache.demand_miss_latency::total 158318499 # number of demand (read+write) miss cycles 528system.cpu.icache.overall_miss_latency::cpu.inst 158318499 # number of overall miss cycles 529system.cpu.icache.overall_miss_latency::total 158318499 # number of overall miss cycles 530system.cpu.icache.ReadReq_accesses::cpu.inst 36846162 # number of ReadReq accesses(hits+misses) 531system.cpu.icache.ReadReq_accesses::total 36846162 # number of ReadReq accesses(hits+misses) 532system.cpu.icache.demand_accesses::cpu.inst 36846162 # number of demand (read+write) accesses 533system.cpu.icache.demand_accesses::total 36846162 # number of demand (read+write) accesses 534system.cpu.icache.overall_accesses::cpu.inst 36846162 # number of overall (read+write) accesses 535system.cpu.icache.overall_accesses::total 36846162 # number of overall (read+write) accesses 536system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000143 # miss rate for ReadReq accesses 537system.cpu.icache.ReadReq_miss_rate::total 0.000143 # miss rate for ReadReq accesses 538system.cpu.icache.demand_miss_rate::cpu.inst 0.000143 # miss rate for demand accesses 539system.cpu.icache.demand_miss_rate::total 0.000143 # miss rate for demand accesses 540system.cpu.icache.overall_miss_rate::cpu.inst 0.000143 # miss rate for overall accesses 541system.cpu.icache.overall_miss_rate::total 0.000143 # miss rate for overall accesses 542system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30069.990313 # average ReadReq miss latency 543system.cpu.icache.ReadReq_avg_miss_latency::total 30069.990313 # average ReadReq miss latency 544system.cpu.icache.demand_avg_miss_latency::cpu.inst 30069.990313 # average overall miss latency 545system.cpu.icache.demand_avg_miss_latency::total 30069.990313 # average overall miss latency 546system.cpu.icache.overall_avg_miss_latency::cpu.inst 30069.990313 # average overall miss latency 547system.cpu.icache.overall_avg_miss_latency::total 30069.990313 # average overall miss latency 548system.cpu.icache.blocked_cycles::no_mshrs 679 # number of cycles access was blocked | 509system.cpu.icache.occ_blocks::cpu.inst 1349.329106 # Average occupied blocks per requestor 510system.cpu.icache.occ_percent::cpu.inst 0.658852 # Average percentage of cache occupancy 511system.cpu.icache.occ_percent::total 0.658852 # Average percentage of cache occupancy 512system.cpu.icache.ReadReq_hits::cpu.inst 36836269 # number of ReadReq hits 513system.cpu.icache.ReadReq_hits::total 36836269 # number of ReadReq hits 514system.cpu.icache.demand_hits::cpu.inst 36836269 # number of demand (read+write) hits 515system.cpu.icache.demand_hits::total 36836269 # number of demand (read+write) hits 516system.cpu.icache.overall_hits::cpu.inst 36836269 # number of overall hits 517system.cpu.icache.overall_hits::total 36836269 # number of overall hits 518system.cpu.icache.ReadReq_misses::cpu.inst 5230 # number of ReadReq misses 519system.cpu.icache.ReadReq_misses::total 5230 # number of ReadReq misses 520system.cpu.icache.demand_misses::cpu.inst 5230 # number of demand (read+write) misses 521system.cpu.icache.demand_misses::total 5230 # number of demand (read+write) misses 522system.cpu.icache.overall_misses::cpu.inst 5230 # number of overall misses 523system.cpu.icache.overall_misses::total 5230 # number of overall misses 524system.cpu.icache.ReadReq_miss_latency::cpu.inst 167188500 # number of ReadReq miss cycles 525system.cpu.icache.ReadReq_miss_latency::total 167188500 # number of ReadReq miss cycles 526system.cpu.icache.demand_miss_latency::cpu.inst 167188500 # number of demand (read+write) miss cycles 527system.cpu.icache.demand_miss_latency::total 167188500 # number of demand (read+write) miss cycles 528system.cpu.icache.overall_miss_latency::cpu.inst 167188500 # number of overall miss cycles 529system.cpu.icache.overall_miss_latency::total 167188500 # number of overall miss cycles 530system.cpu.icache.ReadReq_accesses::cpu.inst 36841499 # number of ReadReq accesses(hits+misses) 531system.cpu.icache.ReadReq_accesses::total 36841499 # number of ReadReq accesses(hits+misses) 532system.cpu.icache.demand_accesses::cpu.inst 36841499 # number of demand (read+write) accesses 533system.cpu.icache.demand_accesses::total 36841499 # number of demand (read+write) accesses 534system.cpu.icache.overall_accesses::cpu.inst 36841499 # number of overall (read+write) accesses 535system.cpu.icache.overall_accesses::total 36841499 # number of overall (read+write) accesses 536system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000142 # miss rate for ReadReq accesses 537system.cpu.icache.ReadReq_miss_rate::total 0.000142 # miss rate for ReadReq accesses 538system.cpu.icache.demand_miss_rate::cpu.inst 0.000142 # miss rate for demand accesses 539system.cpu.icache.demand_miss_rate::total 0.000142 # miss rate for demand accesses 540system.cpu.icache.overall_miss_rate::cpu.inst 0.000142 # miss rate for overall accesses 541system.cpu.icache.overall_miss_rate::total 0.000142 # miss rate for overall accesses 542system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31967.208413 # average ReadReq miss latency 543system.cpu.icache.ReadReq_avg_miss_latency::total 31967.208413 # average ReadReq miss latency 544system.cpu.icache.demand_avg_miss_latency::cpu.inst 31967.208413 # average overall miss latency 545system.cpu.icache.demand_avg_miss_latency::total 31967.208413 # average overall miss latency 546system.cpu.icache.overall_avg_miss_latency::cpu.inst 31967.208413 # average overall miss latency 547system.cpu.icache.overall_avg_miss_latency::total 31967.208413 # average overall miss latency 548system.cpu.icache.blocked_cycles::no_mshrs 552 # number of cycles access was blocked |
| 549system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 549system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 550system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked | 550system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked |
| 551system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 551system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 552system.cpu.icache.avg_blocked_cycles::no_mshrs 37.722222 # average number of cycles each access was blocked | 552system.cpu.icache.avg_blocked_cycles::no_mshrs 34.500000 # average number of cycles each access was blocked |
| 553system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 554system.cpu.icache.fast_writes 0 # number of fast writes performed 555system.cpu.icache.cache_copies 0 # number of cache copies performed | 553system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 554system.cpu.icache.fast_writes 0 # number of fast writes performed 555system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 556system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1159 # number of ReadReq MSHR hits 557system.cpu.icache.ReadReq_mshr_hits::total 1159 # number of ReadReq MSHR hits 558system.cpu.icache.demand_mshr_hits::cpu.inst 1159 # number of demand (read+write) MSHR hits 559system.cpu.icache.demand_mshr_hits::total 1159 # number of demand (read+write) MSHR hits 560system.cpu.icache.overall_mshr_hits::cpu.inst 1159 # number of overall MSHR hits 561system.cpu.icache.overall_mshr_hits::total 1159 # number of overall MSHR hits 562system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4106 # number of ReadReq MSHR misses 563system.cpu.icache.ReadReq_mshr_misses::total 4106 # number of ReadReq MSHR misses 564system.cpu.icache.demand_mshr_misses::cpu.inst 4106 # number of demand (read+write) MSHR misses 565system.cpu.icache.demand_mshr_misses::total 4106 # number of demand (read+write) MSHR misses 566system.cpu.icache.overall_mshr_misses::cpu.inst 4106 # number of overall MSHR misses 567system.cpu.icache.overall_mshr_misses::total 4106 # number of overall MSHR misses 568system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 121527999 # number of ReadReq MSHR miss cycles 569system.cpu.icache.ReadReq_mshr_miss_latency::total 121527999 # number of ReadReq MSHR miss cycles 570system.cpu.icache.demand_mshr_miss_latency::cpu.inst 121527999 # number of demand (read+write) MSHR miss cycles 571system.cpu.icache.demand_mshr_miss_latency::total 121527999 # number of demand (read+write) MSHR miss cycles 572system.cpu.icache.overall_mshr_miss_latency::cpu.inst 121527999 # number of overall MSHR miss cycles 573system.cpu.icache.overall_mshr_miss_latency::total 121527999 # number of overall MSHR miss cycles | 556system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1129 # number of ReadReq MSHR hits 557system.cpu.icache.ReadReq_mshr_hits::total 1129 # number of ReadReq MSHR hits 558system.cpu.icache.demand_mshr_hits::cpu.inst 1129 # number of demand (read+write) MSHR hits 559system.cpu.icache.demand_mshr_hits::total 1129 # number of demand (read+write) MSHR hits 560system.cpu.icache.overall_mshr_hits::cpu.inst 1129 # number of overall MSHR hits 561system.cpu.icache.overall_mshr_hits::total 1129 # number of overall MSHR hits 562system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4101 # number of ReadReq MSHR misses 563system.cpu.icache.ReadReq_mshr_misses::total 4101 # number of ReadReq MSHR misses 564system.cpu.icache.demand_mshr_misses::cpu.inst 4101 # number of demand (read+write) MSHR misses 565system.cpu.icache.demand_mshr_misses::total 4101 # number of demand (read+write) MSHR misses 566system.cpu.icache.overall_mshr_misses::cpu.inst 4101 # number of overall MSHR misses 567system.cpu.icache.overall_mshr_misses::total 4101 # number of overall MSHR misses 568system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 128471500 # number of ReadReq MSHR miss cycles 569system.cpu.icache.ReadReq_mshr_miss_latency::total 128471500 # number of ReadReq MSHR miss cycles 570system.cpu.icache.demand_mshr_miss_latency::cpu.inst 128471500 # number of demand (read+write) MSHR miss cycles 571system.cpu.icache.demand_mshr_miss_latency::total 128471500 # number of demand (read+write) MSHR miss cycles 572system.cpu.icache.overall_mshr_miss_latency::cpu.inst 128471500 # number of overall MSHR miss cycles 573system.cpu.icache.overall_mshr_miss_latency::total 128471500 # number of overall MSHR miss cycles |
| 574system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for ReadReq accesses 575system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000111 # mshr miss rate for ReadReq accesses 576system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for demand accesses 577system.cpu.icache.demand_mshr_miss_rate::total 0.000111 # mshr miss rate for demand accesses 578system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for overall accesses 579system.cpu.icache.overall_mshr_miss_rate::total 0.000111 # mshr miss rate for overall accesses | 574system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for ReadReq accesses 575system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000111 # mshr miss rate for ReadReq accesses 576system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for demand accesses 577system.cpu.icache.demand_mshr_miss_rate::total 0.000111 # mshr miss rate for demand accesses 578system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for overall accesses 579system.cpu.icache.overall_mshr_miss_rate::total 0.000111 # mshr miss rate for overall accesses |
| 580system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29597.661715 # average ReadReq mshr miss latency 581system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29597.661715 # average ReadReq mshr miss latency 582system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29597.661715 # average overall mshr miss latency 583system.cpu.icache.demand_avg_mshr_miss_latency::total 29597.661715 # average overall mshr miss latency 584system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29597.661715 # average overall mshr miss latency 585system.cpu.icache.overall_avg_mshr_miss_latency::total 29597.661715 # average overall mshr miss latency | 580system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 31326.871495 # average ReadReq mshr miss latency 581system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 31326.871495 # average ReadReq mshr miss latency 582system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 31326.871495 # average overall mshr miss latency 583system.cpu.icache.demand_avg_mshr_miss_latency::total 31326.871495 # average overall mshr miss latency 584system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 31326.871495 # average overall mshr miss latency 585system.cpu.icache.overall_avg_mshr_miss_latency::total 31326.871495 # average overall mshr miss latency |
| 586system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 587system.cpu.l2cache.replacements 0 # number of replacements | 586system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 587system.cpu.l2cache.replacements 0 # number of replacements |
| 588system.cpu.l2cache.tagsinuse 1964.083296 # Cycle average of tags in use 589system.cpu.l2cache.total_refs 2132 # Total number of references to valid blocks. 590system.cpu.l2cache.sampled_refs 2732 # Sample count of references to valid blocks. 591system.cpu.l2cache.avg_refs 0.780381 # Average number of references to valid blocks. | 588system.cpu.l2cache.tagsinuse 1970.907280 # Cycle average of tags in use 589system.cpu.l2cache.total_refs 2125 # Total number of references to valid blocks. 590system.cpu.l2cache.sampled_refs 2740 # Sample count of references to valid blocks. 591system.cpu.l2cache.avg_refs 0.775547 # Average number of references to valid blocks. |
| 592system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 592system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 593system.cpu.l2cache.occ_blocks::writebacks 4.995038 # Average occupied blocks per requestor 594system.cpu.l2cache.occ_blocks::cpu.inst 1428.113595 # Average occupied blocks per requestor 595system.cpu.l2cache.occ_blocks::cpu.data 530.974663 # Average occupied blocks per requestor 596system.cpu.l2cache.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy 597system.cpu.l2cache.occ_percent::cpu.inst 0.043583 # Average percentage of cache occupancy 598system.cpu.l2cache.occ_percent::cpu.data 0.016204 # Average percentage of cache occupancy 599system.cpu.l2cache.occ_percent::total 0.059939 # Average percentage of cache occupancy 600system.cpu.l2cache.ReadReq_hits::cpu.inst 2043 # number of ReadReq hits 601system.cpu.l2cache.ReadReq_hits::cpu.data 88 # number of ReadReq hits 602system.cpu.l2cache.ReadReq_hits::total 2131 # number of ReadReq hits | 593system.cpu.l2cache.occ_blocks::writebacks 5.016873 # Average occupied blocks per requestor 594system.cpu.l2cache.occ_blocks::cpu.inst 1429.150441 # Average occupied blocks per requestor 595system.cpu.l2cache.occ_blocks::cpu.data 536.739967 # Average occupied blocks per requestor 596system.cpu.l2cache.occ_percent::writebacks 0.000153 # Average percentage of cache occupancy 597system.cpu.l2cache.occ_percent::cpu.inst 0.043614 # Average percentage of cache occupancy 598system.cpu.l2cache.occ_percent::cpu.data 0.016380 # Average percentage of cache occupancy 599system.cpu.l2cache.occ_percent::total 0.060147 # Average percentage of cache occupancy 600system.cpu.l2cache.ReadReq_hits::cpu.inst 2035 # number of ReadReq hits 601system.cpu.l2cache.ReadReq_hits::cpu.data 89 # number of ReadReq hits 602system.cpu.l2cache.ReadReq_hits::total 2124 # number of ReadReq hits |
| 603system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits 604system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits | 603system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits 604system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits |
| 605system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits 606system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits |
|
| 605system.cpu.l2cache.ReadExReq_hits::cpu.data 9 # number of ReadExReq hits 606system.cpu.l2cache.ReadExReq_hits::total 9 # number of ReadExReq hits | 607system.cpu.l2cache.ReadExReq_hits::cpu.data 9 # number of ReadExReq hits 608system.cpu.l2cache.ReadExReq_hits::total 9 # number of ReadExReq hits |
| 607system.cpu.l2cache.demand_hits::cpu.inst 2043 # number of demand (read+write) hits 608system.cpu.l2cache.demand_hits::cpu.data 97 # number of demand (read+write) hits 609system.cpu.l2cache.demand_hits::total 2140 # number of demand (read+write) hits 610system.cpu.l2cache.overall_hits::cpu.inst 2043 # number of overall hits 611system.cpu.l2cache.overall_hits::cpu.data 97 # number of overall hits 612system.cpu.l2cache.overall_hits::total 2140 # number of overall hits 613system.cpu.l2cache.ReadReq_misses::cpu.inst 2063 # number of ReadReq misses 614system.cpu.l2cache.ReadReq_misses::cpu.data 677 # number of ReadReq misses 615system.cpu.l2cache.ReadReq_misses::total 2740 # number of ReadReq misses 616system.cpu.l2cache.ReadExReq_misses::cpu.data 1080 # number of ReadExReq misses 617system.cpu.l2cache.ReadExReq_misses::total 1080 # number of ReadExReq misses 618system.cpu.l2cache.demand_misses::cpu.inst 2063 # number of demand (read+write) misses 619system.cpu.l2cache.demand_misses::cpu.data 1757 # number of demand (read+write) misses 620system.cpu.l2cache.demand_misses::total 3820 # number of demand (read+write) misses 621system.cpu.l2cache.overall_misses::cpu.inst 2063 # number of overall misses 622system.cpu.l2cache.overall_misses::cpu.data 1757 # number of overall misses 623system.cpu.l2cache.overall_misses::total 3820 # number of overall misses 624system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 96979500 # number of ReadReq miss cycles 625system.cpu.l2cache.ReadReq_miss_latency::cpu.data 34478500 # number of ReadReq miss cycles 626system.cpu.l2cache.ReadReq_miss_latency::total 131458000 # number of ReadReq miss cycles 627system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46382000 # number of ReadExReq miss cycles 628system.cpu.l2cache.ReadExReq_miss_latency::total 46382000 # number of ReadExReq miss cycles 629system.cpu.l2cache.demand_miss_latency::cpu.inst 96979500 # number of demand (read+write) miss cycles 630system.cpu.l2cache.demand_miss_latency::cpu.data 80860500 # number of demand (read+write) miss cycles 631system.cpu.l2cache.demand_miss_latency::total 177840000 # number of demand (read+write) miss cycles 632system.cpu.l2cache.overall_miss_latency::cpu.inst 96979500 # number of overall miss cycles 633system.cpu.l2cache.overall_miss_latency::cpu.data 80860500 # number of overall miss cycles 634system.cpu.l2cache.overall_miss_latency::total 177840000 # number of overall miss cycles 635system.cpu.l2cache.ReadReq_accesses::cpu.inst 4106 # number of ReadReq accesses(hits+misses) 636system.cpu.l2cache.ReadReq_accesses::cpu.data 765 # number of ReadReq accesses(hits+misses) 637system.cpu.l2cache.ReadReq_accesses::total 4871 # number of ReadReq accesses(hits+misses) | 609system.cpu.l2cache.demand_hits::cpu.inst 2035 # number of demand (read+write) hits 610system.cpu.l2cache.demand_hits::cpu.data 98 # number of demand (read+write) hits 611system.cpu.l2cache.demand_hits::total 2133 # number of demand (read+write) hits 612system.cpu.l2cache.overall_hits::cpu.inst 2035 # number of overall hits 613system.cpu.l2cache.overall_hits::cpu.data 98 # number of overall hits 614system.cpu.l2cache.overall_hits::total 2133 # number of overall hits 615system.cpu.l2cache.ReadReq_misses::cpu.inst 2065 # number of ReadReq misses 616system.cpu.l2cache.ReadReq_misses::cpu.data 687 # number of ReadReq misses 617system.cpu.l2cache.ReadReq_misses::total 2752 # number of ReadReq misses 618system.cpu.l2cache.ReadExReq_misses::cpu.data 1076 # number of ReadExReq misses 619system.cpu.l2cache.ReadExReq_misses::total 1076 # number of ReadExReq misses 620system.cpu.l2cache.demand_misses::cpu.inst 2065 # number of demand (read+write) misses 621system.cpu.l2cache.demand_misses::cpu.data 1763 # number of demand (read+write) misses 622system.cpu.l2cache.demand_misses::total 3828 # number of demand (read+write) misses 623system.cpu.l2cache.overall_misses::cpu.inst 2065 # number of overall misses 624system.cpu.l2cache.overall_misses::cpu.data 1763 # number of overall misses 625system.cpu.l2cache.overall_misses::total 3828 # number of overall misses 626system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 104007500 # number of ReadReq miss cycles 627system.cpu.l2cache.ReadReq_miss_latency::cpu.data 39870000 # number of ReadReq miss cycles 628system.cpu.l2cache.ReadReq_miss_latency::total 143877500 # number of ReadReq miss cycles 629system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 49709000 # number of ReadExReq miss cycles 630system.cpu.l2cache.ReadExReq_miss_latency::total 49709000 # number of ReadExReq miss cycles 631system.cpu.l2cache.demand_miss_latency::cpu.inst 104007500 # number of demand (read+write) miss cycles 632system.cpu.l2cache.demand_miss_latency::cpu.data 89579000 # number of demand (read+write) miss cycles 633system.cpu.l2cache.demand_miss_latency::total 193586500 # number of demand (read+write) miss cycles 634system.cpu.l2cache.overall_miss_latency::cpu.inst 104007500 # number of overall miss cycles 635system.cpu.l2cache.overall_miss_latency::cpu.data 89579000 # number of overall miss cycles 636system.cpu.l2cache.overall_miss_latency::total 193586500 # number of overall miss cycles 637system.cpu.l2cache.ReadReq_accesses::cpu.inst 4100 # number of ReadReq accesses(hits+misses) 638system.cpu.l2cache.ReadReq_accesses::cpu.data 776 # number of ReadReq accesses(hits+misses) 639system.cpu.l2cache.ReadReq_accesses::total 4876 # number of ReadReq accesses(hits+misses) |
| 638system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) 639system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) | 640system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) 641system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) |
| 640system.cpu.l2cache.ReadExReq_accesses::cpu.data 1089 # number of ReadExReq accesses(hits+misses) 641system.cpu.l2cache.ReadExReq_accesses::total 1089 # number of ReadExReq accesses(hits+misses) 642system.cpu.l2cache.demand_accesses::cpu.inst 4106 # number of demand (read+write) accesses 643system.cpu.l2cache.demand_accesses::cpu.data 1854 # number of demand (read+write) accesses 644system.cpu.l2cache.demand_accesses::total 5960 # number of demand (read+write) accesses 645system.cpu.l2cache.overall_accesses::cpu.inst 4106 # number of overall (read+write) accesses 646system.cpu.l2cache.overall_accesses::cpu.data 1854 # number of overall (read+write) accesses 647system.cpu.l2cache.overall_accesses::total 5960 # number of overall (read+write) accesses 648system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.502435 # miss rate for ReadReq accesses 649system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.884967 # miss rate for ReadReq accesses 650system.cpu.l2cache.ReadReq_miss_rate::total 0.562513 # miss rate for ReadReq accesses 651system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991736 # miss rate for ReadExReq accesses 652system.cpu.l2cache.ReadExReq_miss_rate::total 0.991736 # miss rate for ReadExReq accesses 653system.cpu.l2cache.demand_miss_rate::cpu.inst 0.502435 # miss rate for demand accesses 654system.cpu.l2cache.demand_miss_rate::cpu.data 0.947681 # miss rate for demand accesses 655system.cpu.l2cache.demand_miss_rate::total 0.640940 # miss rate for demand accesses 656system.cpu.l2cache.overall_miss_rate::cpu.inst 0.502435 # miss rate for overall accesses 657system.cpu.l2cache.overall_miss_rate::cpu.data 0.947681 # miss rate for overall accesses 658system.cpu.l2cache.overall_miss_rate::total 0.640940 # miss rate for overall accesses 659system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47008.967523 # average ReadReq miss latency 660system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50928.360414 # average ReadReq miss latency 661system.cpu.l2cache.ReadReq_avg_miss_latency::total 47977.372263 # average ReadReq miss latency 662system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42946.296296 # average ReadExReq miss latency 663system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42946.296296 # average ReadExReq miss latency 664system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47008.967523 # average overall miss latency 665system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46021.912351 # average overall miss latency 666system.cpu.l2cache.demand_avg_miss_latency::total 46554.973822 # average overall miss latency 667system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47008.967523 # average overall miss latency 668system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46021.912351 # average overall miss latency 669system.cpu.l2cache.overall_avg_miss_latency::total 46554.973822 # average overall miss latency | 642system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses) 643system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses) 644system.cpu.l2cache.ReadExReq_accesses::cpu.data 1085 # number of ReadExReq accesses(hits+misses) 645system.cpu.l2cache.ReadExReq_accesses::total 1085 # number of ReadExReq accesses(hits+misses) 646system.cpu.l2cache.demand_accesses::cpu.inst 4100 # number of demand (read+write) accesses 647system.cpu.l2cache.demand_accesses::cpu.data 1861 # number of demand (read+write) accesses 648system.cpu.l2cache.demand_accesses::total 5961 # number of demand (read+write) accesses 649system.cpu.l2cache.overall_accesses::cpu.inst 4100 # number of overall (read+write) accesses 650system.cpu.l2cache.overall_accesses::cpu.data 1861 # number of overall (read+write) accesses 651system.cpu.l2cache.overall_accesses::total 5961 # number of overall (read+write) accesses 652system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.503659 # miss rate for ReadReq accesses 653system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.885309 # miss rate for ReadReq accesses 654system.cpu.l2cache.ReadReq_miss_rate::total 0.564397 # miss rate for ReadReq accesses 655system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991705 # miss rate for ReadExReq accesses 656system.cpu.l2cache.ReadExReq_miss_rate::total 0.991705 # miss rate for ReadExReq accesses 657system.cpu.l2cache.demand_miss_rate::cpu.inst 0.503659 # miss rate for demand accesses 658system.cpu.l2cache.demand_miss_rate::cpu.data 0.947340 # miss rate for demand accesses 659system.cpu.l2cache.demand_miss_rate::total 0.642174 # miss rate for demand accesses 660system.cpu.l2cache.overall_miss_rate::cpu.inst 0.503659 # miss rate for overall accesses 661system.cpu.l2cache.overall_miss_rate::cpu.data 0.947340 # miss rate for overall accesses 662system.cpu.l2cache.overall_miss_rate::total 0.642174 # miss rate for overall accesses 663system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50366.828087 # average ReadReq miss latency 664system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58034.934498 # average ReadReq miss latency 665system.cpu.l2cache.ReadReq_avg_miss_latency::total 52281.068314 # average ReadReq miss latency 666system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46197.955390 # average ReadExReq miss latency 667system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46197.955390 # average ReadExReq miss latency 668system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50366.828087 # average overall miss latency 669system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50810.550199 # average overall miss latency 670system.cpu.l2cache.demand_avg_miss_latency::total 50571.185998 # average overall miss latency 671system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50366.828087 # average overall miss latency 672system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50810.550199 # average overall miss latency 673system.cpu.l2cache.overall_avg_miss_latency::total 50571.185998 # average overall miss latency |
| 670system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 671system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 672system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 673system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 674system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 675system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 676system.cpu.l2cache.fast_writes 0 # number of fast writes performed 677system.cpu.l2cache.cache_copies 0 # number of cache copies performed 678system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits | 674system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 675system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 676system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 677system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 678system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 679system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 680system.cpu.l2cache.fast_writes 0 # number of fast writes performed 681system.cpu.l2cache.cache_copies 0 # number of cache copies performed 682system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits |
| 679system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 11 # number of ReadReq MSHR hits 680system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits | 683system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits 684system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits |
| 681system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits | 685system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits |
| 682system.cpu.l2cache.demand_mshr_hits::cpu.data 11 # number of demand (read+write) MSHR hits 683system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits | 686system.cpu.l2cache.demand_mshr_hits::cpu.data 12 # number of demand (read+write) MSHR hits 687system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits |
| 684system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits | 688system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits |
| 685system.cpu.l2cache.overall_mshr_hits::cpu.data 11 # number of overall MSHR hits 686system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits 687system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2058 # number of ReadReq MSHR misses 688system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 666 # number of ReadReq MSHR misses 689system.cpu.l2cache.ReadReq_mshr_misses::total 2724 # number of ReadReq MSHR misses 690system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1080 # number of ReadExReq MSHR misses 691system.cpu.l2cache.ReadExReq_mshr_misses::total 1080 # number of ReadExReq MSHR misses 692system.cpu.l2cache.demand_mshr_misses::cpu.inst 2058 # number of demand (read+write) MSHR misses 693system.cpu.l2cache.demand_mshr_misses::cpu.data 1746 # number of demand (read+write) MSHR misses 694system.cpu.l2cache.demand_mshr_misses::total 3804 # number of demand (read+write) MSHR misses 695system.cpu.l2cache.overall_mshr_misses::cpu.inst 2058 # number of overall MSHR misses 696system.cpu.l2cache.overall_mshr_misses::cpu.data 1746 # number of overall MSHR misses 697system.cpu.l2cache.overall_mshr_misses::total 3804 # number of overall MSHR misses 698system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70489427 # number of ReadReq MSHR miss cycles 699system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25721458 # number of ReadReq MSHR miss cycles 700system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96210885 # number of ReadReq MSHR miss cycles 701system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32841183 # number of ReadExReq MSHR miss cycles 702system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32841183 # number of ReadExReq MSHR miss cycles 703system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70489427 # number of demand (read+write) MSHR miss cycles 704system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 58562641 # number of demand (read+write) MSHR miss cycles 705system.cpu.l2cache.demand_mshr_miss_latency::total 129052068 # number of demand (read+write) MSHR miss cycles 706system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70489427 # number of overall MSHR miss cycles 707system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 58562641 # number of overall MSHR miss cycles 708system.cpu.l2cache.overall_mshr_miss_latency::total 129052068 # number of overall MSHR miss cycles 709system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.501218 # mshr miss rate for ReadReq accesses 710system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870588 # mshr miss rate for ReadReq accesses 711system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.559228 # mshr miss rate for ReadReq accesses 712system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991736 # mshr miss rate for ReadExReq accesses 713system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991736 # mshr miss rate for ReadExReq accesses 714system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.501218 # mshr miss rate for demand accesses 715system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941748 # mshr miss rate for demand accesses 716system.cpu.l2cache.demand_mshr_miss_rate::total 0.638255 # mshr miss rate for demand accesses 717system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.501218 # mshr miss rate for overall accesses 718system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941748 # mshr miss rate for overall accesses 719system.cpu.l2cache.overall_mshr_miss_rate::total 0.638255 # mshr miss rate for overall accesses 720system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34251.422255 # average ReadReq mshr miss latency 721system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38620.807808 # average ReadReq mshr miss latency 722system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35319.708150 # average ReadReq mshr miss latency 723system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30408.502778 # average ReadExReq mshr miss latency 724system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30408.502778 # average ReadExReq mshr miss latency 725system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34251.422255 # average overall mshr miss latency 726system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33541.031501 # average overall mshr miss latency 727system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33925.359621 # average overall mshr miss latency 728system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34251.422255 # average overall mshr miss latency 729system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33541.031501 # average overall mshr miss latency 730system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33925.359621 # average overall mshr miss latency | 689system.cpu.l2cache.overall_mshr_hits::cpu.data 12 # number of overall MSHR hits 690system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits 691system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2060 # number of ReadReq MSHR misses 692system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 675 # number of ReadReq MSHR misses 693system.cpu.l2cache.ReadReq_mshr_misses::total 2735 # number of ReadReq MSHR misses 694system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1076 # number of ReadExReq MSHR misses 695system.cpu.l2cache.ReadExReq_mshr_misses::total 1076 # number of ReadExReq MSHR misses 696system.cpu.l2cache.demand_mshr_misses::cpu.inst 2060 # number of demand (read+write) MSHR misses 697system.cpu.l2cache.demand_mshr_misses::cpu.data 1751 # number of demand (read+write) MSHR misses 698system.cpu.l2cache.demand_mshr_misses::total 3811 # number of demand (read+write) MSHR misses 699system.cpu.l2cache.overall_mshr_misses::cpu.inst 2060 # number of overall MSHR misses 700system.cpu.l2cache.overall_mshr_misses::cpu.data 1751 # number of overall MSHR misses 701system.cpu.l2cache.overall_mshr_misses::total 3811 # number of overall MSHR misses 702system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 78131980 # number of ReadReq MSHR miss cycles 703system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30985263 # number of ReadReq MSHR miss cycles 704system.cpu.l2cache.ReadReq_mshr_miss_latency::total 109117243 # number of ReadReq MSHR miss cycles 705system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 36314730 # number of ReadExReq MSHR miss cycles 706system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 36314730 # number of ReadExReq MSHR miss cycles 707system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 78131980 # number of demand (read+write) MSHR miss cycles 708system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67299993 # number of demand (read+write) MSHR miss cycles 709system.cpu.l2cache.demand_mshr_miss_latency::total 145431973 # number of demand (read+write) MSHR miss cycles 710system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 78131980 # number of overall MSHR miss cycles 711system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67299993 # number of overall MSHR miss cycles 712system.cpu.l2cache.overall_mshr_miss_latency::total 145431973 # number of overall MSHR miss cycles 713system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.502439 # mshr miss rate for ReadReq accesses 714system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869845 # mshr miss rate for ReadReq accesses 715system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.560911 # mshr miss rate for ReadReq accesses 716system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991705 # mshr miss rate for ReadExReq accesses 717system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991705 # mshr miss rate for ReadExReq accesses 718system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.502439 # mshr miss rate for demand accesses 719system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.940892 # mshr miss rate for demand accesses 720system.cpu.l2cache.demand_mshr_miss_rate::total 0.639322 # mshr miss rate for demand accesses 721system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.502439 # mshr miss rate for overall accesses 722system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940892 # mshr miss rate for overall accesses 723system.cpu.l2cache.overall_mshr_miss_rate::total 0.639322 # mshr miss rate for overall accesses 724system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37928.145631 # average ReadReq mshr miss latency 725system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45904.093333 # average ReadReq mshr miss latency 726system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39896.615356 # average ReadReq mshr miss latency 727system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33749.749071 # average ReadExReq mshr miss latency 728system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33749.749071 # average ReadExReq mshr miss latency 729system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37928.145631 # average overall mshr miss latency 730system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38435.175899 # average overall mshr miss latency 731system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38161.105484 # average overall mshr miss latency 732system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37928.145631 # average overall mshr miss latency 733system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38435.175899 # average overall mshr miss latency 734system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38161.105484 # average overall mshr miss latency |
| 731system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 735system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 732system.cpu.dcache.replacements 58 # number of replacements 733system.cpu.dcache.tagsinuse 1406.419520 # Cycle average of tags in use 734system.cpu.dcache.total_refs 46792514 # Total number of references to valid blocks. 735system.cpu.dcache.sampled_refs 1854 # Sample count of references to valid blocks. 736system.cpu.dcache.avg_refs 25238.680690 # Average number of references to valid blocks. | 736system.cpu.dcache.replacements 57 # number of replacements 737system.cpu.dcache.tagsinuse 1410.136977 # Cycle average of tags in use 738system.cpu.dcache.total_refs 46795714 # Total number of references to valid blocks. 739system.cpu.dcache.sampled_refs 1861 # Sample count of references to valid blocks. 740system.cpu.dcache.avg_refs 25145.466953 # Average number of references to valid blocks. |
| 737system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 741system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 738system.cpu.dcache.occ_blocks::cpu.data 1406.419520 # Average occupied blocks per requestor 739system.cpu.dcache.occ_percent::cpu.data 0.343364 # Average percentage of cache occupancy 740system.cpu.dcache.occ_percent::total 0.343364 # Average percentage of cache occupancy 741system.cpu.dcache.ReadReq_hits::cpu.data 34391106 # number of ReadReq hits 742system.cpu.dcache.ReadReq_hits::total 34391106 # number of ReadReq hits 743system.cpu.dcache.WriteReq_hits::cpu.data 12356535 # number of WriteReq hits 744system.cpu.dcache.WriteReq_hits::total 12356535 # number of WriteReq hits 745system.cpu.dcache.LoadLockedReq_hits::cpu.data 22466 # number of LoadLockedReq hits 746system.cpu.dcache.LoadLockedReq_hits::total 22466 # number of LoadLockedReq hits | 742system.cpu.dcache.occ_blocks::cpu.data 1410.136977 # Average occupied blocks per requestor 743system.cpu.dcache.occ_percent::cpu.data 0.344272 # Average percentage of cache occupancy 744system.cpu.dcache.occ_percent::total 0.344272 # Average percentage of cache occupancy 745system.cpu.dcache.ReadReq_hits::cpu.data 34394275 # number of ReadReq hits 746system.cpu.dcache.ReadReq_hits::total 34394275 # number of ReadReq hits 747system.cpu.dcache.WriteReq_hits::cpu.data 12356557 # number of WriteReq hits 748system.cpu.dcache.WriteReq_hits::total 12356557 # number of WriteReq hits 749system.cpu.dcache.LoadLockedReq_hits::cpu.data 22472 # number of LoadLockedReq hits 750system.cpu.dcache.LoadLockedReq_hits::total 22472 # number of LoadLockedReq hits |
| 747system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits 748system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits | 751system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits 752system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits |
| 749system.cpu.dcache.demand_hits::cpu.data 46747641 # number of demand (read+write) hits 750system.cpu.dcache.demand_hits::total 46747641 # number of demand (read+write) hits 751system.cpu.dcache.overall_hits::cpu.data 46747641 # number of overall hits 752system.cpu.dcache.overall_hits::total 46747641 # number of overall hits | 753system.cpu.dcache.demand_hits::cpu.data 46750832 # number of demand (read+write) hits 754system.cpu.dcache.demand_hits::total 46750832 # number of demand (read+write) hits 755system.cpu.dcache.overall_hits::cpu.data 46750832 # number of overall hits 756system.cpu.dcache.overall_hits::total 46750832 # number of overall hits |
| 753system.cpu.dcache.ReadReq_misses::cpu.data 1904 # number of ReadReq misses 754system.cpu.dcache.ReadReq_misses::total 1904 # number of ReadReq misses | 757system.cpu.dcache.ReadReq_misses::cpu.data 1904 # number of ReadReq misses 758system.cpu.dcache.ReadReq_misses::total 1904 # number of ReadReq misses |
| 755system.cpu.dcache.WriteReq_misses::cpu.data 7752 # number of WriteReq misses 756system.cpu.dcache.WriteReq_misses::total 7752 # number of WriteReq misses | 759system.cpu.dcache.WriteReq_misses::cpu.data 7730 # number of WriteReq misses 760system.cpu.dcache.WriteReq_misses::total 7730 # number of WriteReq misses |
| 757system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 758system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses | 761system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 762system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses |
| 759system.cpu.dcache.demand_misses::cpu.data 9656 # number of demand (read+write) misses 760system.cpu.dcache.demand_misses::total 9656 # number of demand (read+write) misses 761system.cpu.dcache.overall_misses::cpu.data 9656 # number of overall misses 762system.cpu.dcache.overall_misses::total 9656 # number of overall misses 763system.cpu.dcache.ReadReq_miss_latency::cpu.data 84169500 # number of ReadReq miss cycles 764system.cpu.dcache.ReadReq_miss_latency::total 84169500 # number of ReadReq miss cycles 765system.cpu.dcache.WriteReq_miss_latency::cpu.data 293859496 # number of WriteReq miss cycles 766system.cpu.dcache.WriteReq_miss_latency::total 293859496 # number of WriteReq miss cycles | 763system.cpu.dcache.demand_misses::cpu.data 9634 # number of demand (read+write) misses 764system.cpu.dcache.demand_misses::total 9634 # number of demand (read+write) misses 765system.cpu.dcache.overall_misses::cpu.data 9634 # number of overall misses 766system.cpu.dcache.overall_misses::total 9634 # number of overall misses 767system.cpu.dcache.ReadReq_miss_latency::cpu.data 93402000 # number of ReadReq miss cycles 768system.cpu.dcache.ReadReq_miss_latency::total 93402000 # number of ReadReq miss cycles 769system.cpu.dcache.WriteReq_miss_latency::cpu.data 306706496 # number of WriteReq miss cycles 770system.cpu.dcache.WriteReq_miss_latency::total 306706496 # number of WriteReq miss cycles |
| 767system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles 768system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles | 771system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles 772system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles |
| 769system.cpu.dcache.demand_miss_latency::cpu.data 378028996 # number of demand (read+write) miss cycles 770system.cpu.dcache.demand_miss_latency::total 378028996 # number of demand (read+write) miss cycles 771system.cpu.dcache.overall_miss_latency::cpu.data 378028996 # number of overall miss cycles 772system.cpu.dcache.overall_miss_latency::total 378028996 # number of overall miss cycles 773system.cpu.dcache.ReadReq_accesses::cpu.data 34393010 # number of ReadReq accesses(hits+misses) 774system.cpu.dcache.ReadReq_accesses::total 34393010 # number of ReadReq accesses(hits+misses) | 773system.cpu.dcache.demand_miss_latency::cpu.data 400108496 # number of demand (read+write) miss cycles 774system.cpu.dcache.demand_miss_latency::total 400108496 # number of demand (read+write) miss cycles 775system.cpu.dcache.overall_miss_latency::cpu.data 400108496 # number of overall miss cycles 776system.cpu.dcache.overall_miss_latency::total 400108496 # number of overall miss cycles 777system.cpu.dcache.ReadReq_accesses::cpu.data 34396179 # number of ReadReq accesses(hits+misses) 778system.cpu.dcache.ReadReq_accesses::total 34396179 # number of ReadReq accesses(hits+misses) |
| 775system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 776system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) | 779system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 780system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) |
| 777system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22468 # number of LoadLockedReq accesses(hits+misses) 778system.cpu.dcache.LoadLockedReq_accesses::total 22468 # number of LoadLockedReq accesses(hits+misses) | 781system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22474 # number of LoadLockedReq accesses(hits+misses) 782system.cpu.dcache.LoadLockedReq_accesses::total 22474 # number of LoadLockedReq accesses(hits+misses) |
| 779system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) 780system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) | 783system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) 784system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) |
| 781system.cpu.dcache.demand_accesses::cpu.data 46757297 # number of demand (read+write) accesses 782system.cpu.dcache.demand_accesses::total 46757297 # number of demand (read+write) accesses 783system.cpu.dcache.overall_accesses::cpu.data 46757297 # number of overall (read+write) accesses 784system.cpu.dcache.overall_accesses::total 46757297 # number of overall (read+write) accesses | 785system.cpu.dcache.demand_accesses::cpu.data 46760466 # number of demand (read+write) accesses 786system.cpu.dcache.demand_accesses::total 46760466 # number of demand (read+write) accesses 787system.cpu.dcache.overall_accesses::cpu.data 46760466 # number of overall (read+write) accesses 788system.cpu.dcache.overall_accesses::total 46760466 # number of overall (read+write) accesses |
| 785system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses 786system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses | 789system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses 790system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses |
| 787system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000627 # miss rate for WriteReq accesses 788system.cpu.dcache.WriteReq_miss_rate::total 0.000627 # miss rate for WriteReq accesses | 791system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses 792system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses |
| 789system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses 790system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses | 793system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses 794system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses |
| 791system.cpu.dcache.demand_miss_rate::cpu.data 0.000207 # miss rate for demand accesses 792system.cpu.dcache.demand_miss_rate::total 0.000207 # miss rate for demand accesses 793system.cpu.dcache.overall_miss_rate::cpu.data 0.000207 # miss rate for overall accesses 794system.cpu.dcache.overall_miss_rate::total 0.000207 # miss rate for overall accesses 795system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44206.670168 # average ReadReq miss latency 796system.cpu.dcache.ReadReq_avg_miss_latency::total 44206.670168 # average ReadReq miss latency 797system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37907.571723 # average WriteReq miss latency 798system.cpu.dcache.WriteReq_avg_miss_latency::total 37907.571723 # average WriteReq miss latency | 795system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses 796system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses 797system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses 798system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses 799system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49055.672269 # average ReadReq miss latency 800system.cpu.dcache.ReadReq_avg_miss_latency::total 49055.672269 # average ReadReq miss latency 801system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39677.425097 # average WriteReq miss latency 802system.cpu.dcache.WriteReq_avg_miss_latency::total 39677.425097 # average WriteReq miss latency |
| 799system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency 800system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency | 803system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency 804system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency |
| 801system.cpu.dcache.demand_avg_miss_latency::cpu.data 39149.647473 # average overall miss latency 802system.cpu.dcache.demand_avg_miss_latency::total 39149.647473 # average overall miss latency 803system.cpu.dcache.overall_avg_miss_latency::cpu.data 39149.647473 # average overall miss latency 804system.cpu.dcache.overall_avg_miss_latency::total 39149.647473 # average overall miss latency 805system.cpu.dcache.blocked_cycles::no_mshrs 472 # number of cycles access was blocked 806system.cpu.dcache.blocked_cycles::no_targets 34 # number of cycles access was blocked | 805system.cpu.dcache.demand_avg_miss_latency::cpu.data 41530.879801 # average overall miss latency 806system.cpu.dcache.demand_avg_miss_latency::total 41530.879801 # average overall miss latency 807system.cpu.dcache.overall_avg_miss_latency::cpu.data 41530.879801 # average overall miss latency 808system.cpu.dcache.overall_avg_miss_latency::total 41530.879801 # average overall miss latency 809system.cpu.dcache.blocked_cycles::no_mshrs 527 # number of cycles access was blocked 810system.cpu.dcache.blocked_cycles::no_targets 73 # number of cycles access was blocked |
| 807system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked 808system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked | 811system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked 812system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked |
| 809system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.307692 # average number of cycles each access was blocked 810system.cpu.dcache.avg_blocked_cycles::no_targets 17 # average number of cycles each access was blocked | 813system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.538462 # average number of cycles each access was blocked 814system.cpu.dcache.avg_blocked_cycles::no_targets 36.500000 # average number of cycles each access was blocked |
| 811system.cpu.dcache.fast_writes 0 # number of fast writes performed 812system.cpu.dcache.cache_copies 0 # number of cache copies performed 813system.cpu.dcache.writebacks::writebacks 18 # number of writebacks 814system.cpu.dcache.writebacks::total 18 # number of writebacks | 815system.cpu.dcache.fast_writes 0 # number of fast writes performed 816system.cpu.dcache.cache_copies 0 # number of cache copies performed 817system.cpu.dcache.writebacks::writebacks 18 # number of writebacks 818system.cpu.dcache.writebacks::total 18 # number of writebacks |
| 815system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1138 # number of ReadReq MSHR hits 816system.cpu.dcache.ReadReq_mshr_hits::total 1138 # number of ReadReq MSHR hits 817system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6664 # number of WriteReq MSHR hits 818system.cpu.dcache.WriteReq_mshr_hits::total 6664 # number of WriteReq MSHR hits | 819system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1127 # number of ReadReq MSHR hits 820system.cpu.dcache.ReadReq_mshr_hits::total 1127 # number of ReadReq MSHR hits 821system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6643 # number of WriteReq MSHR hits 822system.cpu.dcache.WriteReq_mshr_hits::total 6643 # number of WriteReq MSHR hits |
| 819system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 820system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits | 823system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 824system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits |
| 821system.cpu.dcache.demand_mshr_hits::cpu.data 7802 # number of demand (read+write) MSHR hits 822system.cpu.dcache.demand_mshr_hits::total 7802 # number of demand (read+write) MSHR hits 823system.cpu.dcache.overall_mshr_hits::cpu.data 7802 # number of overall MSHR hits 824system.cpu.dcache.overall_mshr_hits::total 7802 # number of overall MSHR hits 825system.cpu.dcache.ReadReq_mshr_misses::cpu.data 766 # number of ReadReq MSHR misses 826system.cpu.dcache.ReadReq_mshr_misses::total 766 # number of ReadReq MSHR misses 827system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1088 # number of WriteReq MSHR misses 828system.cpu.dcache.WriteReq_mshr_misses::total 1088 # number of WriteReq MSHR misses 829system.cpu.dcache.demand_mshr_misses::cpu.data 1854 # number of demand (read+write) MSHR misses 830system.cpu.dcache.demand_mshr_misses::total 1854 # number of demand (read+write) MSHR misses 831system.cpu.dcache.overall_mshr_misses::cpu.data 1854 # number of overall MSHR misses 832system.cpu.dcache.overall_mshr_misses::total 1854 # number of overall MSHR misses 833system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36187000 # number of ReadReq MSHR miss cycles 834system.cpu.dcache.ReadReq_mshr_miss_latency::total 36187000 # number of ReadReq MSHR miss cycles 835system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47523998 # number of WriteReq MSHR miss cycles 836system.cpu.dcache.WriteReq_mshr_miss_latency::total 47523998 # number of WriteReq MSHR miss cycles 837system.cpu.dcache.demand_mshr_miss_latency::cpu.data 83710998 # number of demand (read+write) MSHR miss cycles 838system.cpu.dcache.demand_mshr_miss_latency::total 83710998 # number of demand (read+write) MSHR miss cycles 839system.cpu.dcache.overall_mshr_miss_latency::cpu.data 83710998 # number of overall MSHR miss cycles 840system.cpu.dcache.overall_mshr_miss_latency::total 83710998 # number of overall MSHR miss cycles 841system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses 842system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses | 825system.cpu.dcache.demand_mshr_hits::cpu.data 7770 # number of demand (read+write) MSHR hits 826system.cpu.dcache.demand_mshr_hits::total 7770 # number of demand (read+write) MSHR hits 827system.cpu.dcache.overall_mshr_hits::cpu.data 7770 # number of overall MSHR hits 828system.cpu.dcache.overall_mshr_hits::total 7770 # number of overall MSHR hits 829system.cpu.dcache.ReadReq_mshr_misses::cpu.data 777 # number of ReadReq MSHR misses 830system.cpu.dcache.ReadReq_mshr_misses::total 777 # number of ReadReq MSHR misses 831system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1087 # number of WriteReq MSHR misses 832system.cpu.dcache.WriteReq_mshr_misses::total 1087 # number of WriteReq MSHR misses 833system.cpu.dcache.demand_mshr_misses::cpu.data 1864 # number of demand (read+write) MSHR misses 834system.cpu.dcache.demand_mshr_misses::total 1864 # number of demand (read+write) MSHR misses 835system.cpu.dcache.overall_mshr_misses::cpu.data 1864 # number of overall MSHR misses 836system.cpu.dcache.overall_mshr_misses::total 1864 # number of overall MSHR misses 837system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41603000 # number of ReadReq MSHR miss cycles 838system.cpu.dcache.ReadReq_mshr_miss_latency::total 41603000 # number of ReadReq MSHR miss cycles 839system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 50879498 # number of WriteReq MSHR miss cycles 840system.cpu.dcache.WriteReq_mshr_miss_latency::total 50879498 # number of WriteReq MSHR miss cycles 841system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92482498 # number of demand (read+write) MSHR miss cycles 842system.cpu.dcache.demand_mshr_miss_latency::total 92482498 # number of demand (read+write) MSHR miss cycles 843system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92482498 # number of overall MSHR miss cycles 844system.cpu.dcache.overall_mshr_miss_latency::total 92482498 # number of overall MSHR miss cycles 845system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses 846system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses |
| 843system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses 844system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses 845system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses 846system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 847system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses 848system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses | 847system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses 848system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses 849system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses 850system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 851system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses 852system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses |
| 849system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47241.514360 # average ReadReq mshr miss latency 850system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47241.514360 # average ReadReq mshr miss latency 851system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43680.145221 # average WriteReq mshr miss latency 852system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43680.145221 # average WriteReq mshr miss latency 853system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45151.563107 # average overall mshr miss latency 854system.cpu.dcache.demand_avg_mshr_miss_latency::total 45151.563107 # average overall mshr miss latency 855system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45151.563107 # average overall mshr miss latency 856system.cpu.dcache.overall_avg_mshr_miss_latency::total 45151.563107 # average overall mshr miss latency | 853system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53543.114543 # average ReadReq mshr miss latency 854system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53543.114543 # average ReadReq mshr miss latency 855system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46807.265869 # average WriteReq mshr miss latency 856system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46807.265869 # average WriteReq mshr miss latency 857system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49615.074034 # average overall mshr miss latency 858system.cpu.dcache.demand_avg_mshr_miss_latency::total 49615.074034 # average overall mshr miss latency 859system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49615.074034 # average overall mshr miss latency 860system.cpu.dcache.overall_avg_mshr_miss_latency::total 49615.074034 # average overall mshr miss latency |
| 857system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 858 859---------- End Simulation Statistics ---------- | 861system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 862 863---------- End Simulation Statistics ---------- |