| stats.txt (9378:36ed6d4654bb) | stats.txt (9449:56610ab73040) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.074245 # Number of seconds simulated 4sim_ticks 74245032000 # Number of ticks simulated 5final_tick 74245032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.074245 # Number of seconds simulated 4sim_ticks 74245032000 # Number of ticks simulated 5final_tick 74245032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 131550 # Simulator instruction rate (inst/s) 8host_op_rate 144033 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 56674428 # Simulator tick rate (ticks/s) 10host_mem_usage 280244 # Number of bytes of host memory used 11host_seconds 1310.03 # Real time elapsed on the host | 7host_inst_rate 44193 # Simulator instruction rate (inst/s) 8host_op_rate 48386 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 19039219 # Simulator tick rate (ticks/s) 10host_mem_usage 236076 # Number of bytes of host memory used 11host_seconds 3899.58 # Real time elapsed on the host |
| 12sim_insts 172333441 # Number of instructions simulated 13sim_ops 188686923 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 131008 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 111680 # Number of bytes read from this memory 16system.physmem.bytes_read::total 242688 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 131008 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 131008 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 2047 # Number of read requests responded to by this memory --- 45 unchanged lines hidden (view full) --- 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 12sim_insts 172333441 # Number of instructions simulated 13sim_ops 188686923 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 131008 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 111680 # Number of bytes read from this memory 16system.physmem.bytes_read::total 242688 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 131008 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 131008 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 2047 # Number of read requests responded to by this memory --- 45 unchanged lines hidden (view full) --- 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 73system.physmem.totGap 74245012500 # Total gap between requests | 73system.physmem.totGap 74245013500 # Total gap between requests |
| 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 3793 # Categorize read packet sizes 81system.physmem.readPktSize::7 0 # Categorize read packet sizes --- 77 unchanged lines hidden (view full) --- 159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see | 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 3793 # Categorize read packet sizes 81system.physmem.readPktSize::7 0 # Categorize read packet sizes --- 77 unchanged lines hidden (view full) --- 159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see |
| 167system.physmem.totQLat 12366785 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 86366785 # Sum of mem lat for all requests | 167system.physmem.totQLat 12368785 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 86368785 # Sum of mem lat for all requests |
| 169system.physmem.totBusLat 15172000 # Total cycles spent in databus access 170system.physmem.totBankLat 58828000 # Total cycles spent in bank access | 169system.physmem.totBusLat 15172000 # Total cycles spent in databus access 170system.physmem.totBankLat 58828000 # Total cycles spent in bank access |
| 171system.physmem.avgQLat 3260.42 # Average queueing delay per request | 171system.physmem.avgQLat 3260.95 # Average queueing delay per request |
| 172system.physmem.avgBankLat 15509.62 # Average bank access latency per request 173system.physmem.avgBusLat 4000.00 # Average bus latency per request | 172system.physmem.avgBankLat 15509.62 # Average bank access latency per request 173system.physmem.avgBusLat 4000.00 # Average bus latency per request |
| 174system.physmem.avgMemAccLat 22770.05 # Average memory access latency | 174system.physmem.avgMemAccLat 22770.57 # Average memory access latency |
| 175system.physmem.avgRdBW 3.27 # Average achieved read bandwidth in MB/s 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 177system.physmem.avgConsumedRdBW 3.27 # Average consumed read bandwidth in MB/s 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 180system.physmem.busUtil 0.02 # Data bus utilization in percentage 181system.physmem.avgRdQLen 0.00 # Average read queue length over time 182system.physmem.avgWrQLen 0.00 # Average write queue length over time 183system.physmem.readRowHits 3295 # Number of row buffer hits during reads 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes 185system.physmem.readRowHitRate 86.87 # Row buffer hit rate for reads 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 175system.physmem.avgRdBW 3.27 # Average achieved read bandwidth in MB/s 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 177system.physmem.avgConsumedRdBW 3.27 # Average consumed read bandwidth in MB/s 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 180system.physmem.busUtil 0.02 # Data bus utilization in percentage 181system.physmem.avgRdQLen 0.00 # Average read queue length over time 182system.physmem.avgWrQLen 0.00 # Average write queue length over time 183system.physmem.readRowHits 3295 # Number of row buffer hits during reads 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes 185system.physmem.readRowHitRate 86.87 # Row buffer hit rate for reads 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 187system.physmem.avgGap 19574218.96 # Average gap between requests | 187system.physmem.avgGap 19574219.22 # Average gap between requests |
| 188system.cpu.dtb.inst_hits 0 # ITB inst hits 189system.cpu.dtb.inst_misses 0 # ITB inst misses 190system.cpu.dtb.read_hits 0 # DTB read hits 191system.cpu.dtb.read_misses 0 # DTB read misses 192system.cpu.dtb.write_hits 0 # DTB write hits 193system.cpu.dtb.write_misses 0 # DTB write misses 194system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 195system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 38 unchanged lines hidden (view full) --- 234system.cpu.BPredUnit.lookups 94824011 # Number of BP lookups 235system.cpu.BPredUnit.condPredicted 74811084 # Number of conditional branches predicted 236system.cpu.BPredUnit.condIncorrect 6283419 # Number of conditional branches incorrect 237system.cpu.BPredUnit.BTBLookups 44691419 # Number of BTB lookups 238system.cpu.BPredUnit.BTBHits 43068728 # Number of BTB hits 239system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 240system.cpu.BPredUnit.usedRAS 4355687 # Number of times the RAS was used to get a target. 241system.cpu.BPredUnit.RASInCorrect 88461 # Number of incorrect RAS predictions. | 188system.cpu.dtb.inst_hits 0 # ITB inst hits 189system.cpu.dtb.inst_misses 0 # ITB inst misses 190system.cpu.dtb.read_hits 0 # DTB read hits 191system.cpu.dtb.read_misses 0 # DTB read misses 192system.cpu.dtb.write_hits 0 # DTB write hits 193system.cpu.dtb.write_misses 0 # DTB write misses 194system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 195system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 38 unchanged lines hidden (view full) --- 234system.cpu.BPredUnit.lookups 94824011 # Number of BP lookups 235system.cpu.BPredUnit.condPredicted 74811084 # Number of conditional branches predicted 236system.cpu.BPredUnit.condIncorrect 6283419 # Number of conditional branches incorrect 237system.cpu.BPredUnit.BTBLookups 44691419 # Number of BTB lookups 238system.cpu.BPredUnit.BTBHits 43068728 # Number of BTB hits 239system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 240system.cpu.BPredUnit.usedRAS 4355687 # Number of times the RAS was used to get a target. 241system.cpu.BPredUnit.RASInCorrect 88461 # Number of incorrect RAS predictions. |
| 242system.cpu.fetch.icacheStallCycles 39671704 # Number of cycles fetch is stalled on an Icache miss | 242system.cpu.fetch.icacheStallCycles 39671705 # Number of cycles fetch is stalled on an Icache miss |
| 243system.cpu.fetch.Insts 380334125 # Number of instructions fetch has processed 244system.cpu.fetch.Branches 94824011 # Number of branches that fetch encountered 245system.cpu.fetch.predictedBranches 47424415 # Number of branches that fetch has predicted taken 246system.cpu.fetch.Cycles 80393373 # Number of cycles fetch has run and was not squashing or blocked 247system.cpu.fetch.SquashCycles 27296286 # Number of cycles fetch has spent squashing | 243system.cpu.fetch.Insts 380334125 # Number of instructions fetch has processed 244system.cpu.fetch.Branches 94824011 # Number of branches that fetch encountered 245system.cpu.fetch.predictedBranches 47424415 # Number of branches that fetch has predicted taken 246system.cpu.fetch.Cycles 80393373 # Number of cycles fetch has run and was not squashing or blocked 247system.cpu.fetch.SquashCycles 27296286 # Number of cycles fetch has spent squashing |
| 248system.cpu.fetch.BlockedCycles 7321256 # Number of cycles fetch has spent blocked 249system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 248system.cpu.fetch.BlockedCycles 7321257 # Number of cycles fetch has spent blocked 249system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 250system.cpu.fetch.PendingTrapStallCycles 4918 # Number of stall cycles due to pending traps 251system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions 252system.cpu.fetch.IcacheWaitRetryStallCycles 51 # Number of stall cycles due to full MSHR | 250system.cpu.fetch.PendingTrapStallCycles 4918 # Number of stall cycles due to pending traps 251system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions 252system.cpu.fetch.IcacheWaitRetryStallCycles 51 # Number of stall cycles due to full MSHR |
| 253system.cpu.fetch.CacheLines 36859860 # Number of cache lines fetched 254system.cpu.fetch.IcacheSquashes 1828379 # Number of outstanding Icache misses that were squashed 255system.cpu.fetch.rateDist::samples 148388373 # Number of instructions fetched each cycle (Total) | 253system.cpu.fetch.CacheLines 36859861 # Number of cache lines fetched 254system.cpu.fetch.IcacheSquashes 1828380 # Number of outstanding Icache misses that were squashed 255system.cpu.fetch.rateDist::samples 148388374 # Number of instructions fetched each cycle (Total) |
| 256system.cpu.fetch.rateDist::mean 2.800016 # Number of instructions fetched each cycle (Total) 257system.cpu.fetch.rateDist::stdev 3.152801 # Number of instructions fetched each cycle (Total) 258system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 256system.cpu.fetch.rateDist::mean 2.800016 # Number of instructions fetched each cycle (Total) 257system.cpu.fetch.rateDist::stdev 3.152801 # Number of instructions fetched each cycle (Total) 258system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 259system.cpu.fetch.rateDist::0 68164460 45.94% 45.94% # Number of instructions fetched each cycle (Total) | 259system.cpu.fetch.rateDist::0 68164461 45.94% 45.94% # Number of instructions fetched each cycle (Total) |
| 260system.cpu.fetch.rateDist::1 5263921 3.55% 49.48% # Number of instructions fetched each cycle (Total) 261system.cpu.fetch.rateDist::2 10532073 7.10% 56.58% # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::3 10289171 6.93% 63.52% # Number of instructions fetched each cycle (Total) 263system.cpu.fetch.rateDist::4 8658719 5.84% 69.35% # Number of instructions fetched each cycle (Total) 264system.cpu.fetch.rateDist::5 6556174 4.42% 73.77% # Number of instructions fetched each cycle (Total) 265system.cpu.fetch.rateDist::6 6250200 4.21% 77.98% # Number of instructions fetched each cycle (Total) 266system.cpu.fetch.rateDist::7 8011886 5.40% 83.38% # Number of instructions fetched each cycle (Total) 267system.cpu.fetch.rateDist::8 24661769 16.62% 100.00% # Number of instructions fetched each cycle (Total) 268system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 269system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 270system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 260system.cpu.fetch.rateDist::1 5263921 3.55% 49.48% # Number of instructions fetched each cycle (Total) 261system.cpu.fetch.rateDist::2 10532073 7.10% 56.58% # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::3 10289171 6.93% 63.52% # Number of instructions fetched each cycle (Total) 263system.cpu.fetch.rateDist::4 8658719 5.84% 69.35% # Number of instructions fetched each cycle (Total) 264system.cpu.fetch.rateDist::5 6556174 4.42% 73.77% # Number of instructions fetched each cycle (Total) 265system.cpu.fetch.rateDist::6 6250200 4.21% 77.98% # Number of instructions fetched each cycle (Total) 266system.cpu.fetch.rateDist::7 8011886 5.40% 83.38% # Number of instructions fetched each cycle (Total) 267system.cpu.fetch.rateDist::8 24661769 16.62% 100.00% # Number of instructions fetched each cycle (Total) 268system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 269system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 270system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 271system.cpu.fetch.rateDist::total 148388373 # Number of instructions fetched each cycle (Total) | 271system.cpu.fetch.rateDist::total 148388374 # Number of instructions fetched each cycle (Total) |
| 272system.cpu.fetch.branchRate 0.638588 # Number of branch fetches per cycle 273system.cpu.fetch.rate 2.561344 # Number of inst fetches per cycle 274system.cpu.decode.IdleCycles 45525708 # Number of cycles decode is idle | 272system.cpu.fetch.branchRate 0.638588 # Number of branch fetches per cycle 273system.cpu.fetch.rate 2.561344 # Number of inst fetches per cycle 274system.cpu.decode.IdleCycles 45525708 # Number of cycles decode is idle |
| 275system.cpu.decode.BlockedCycles 5988328 # Number of cycles decode is blocked | 275system.cpu.decode.BlockedCycles 5988329 # Number of cycles decode is blocked |
| 276system.cpu.decode.RunCycles 74834240 # Number of cycles decode is running 277system.cpu.decode.UnblockCycles 1196373 # Number of cycles decode is unblocking 278system.cpu.decode.SquashCycles 20843724 # Number of cycles decode is squashing 279system.cpu.decode.BranchResolved 14343881 # Number of times decode resolved a branch 280system.cpu.decode.BranchMispred 164426 # Number of times decode detected a branch misprediction 281system.cpu.decode.DecodedInsts 392938907 # Number of instructions handled by decode 282system.cpu.decode.SquashedInsts 736414 # Number of squashed instructions handled by decode 283system.cpu.rename.SquashCycles 20843724 # Number of cycles rename is squashing 284system.cpu.rename.IdleCycles 50922630 # Number of cycles rename is idle 285system.cpu.rename.BlockCycles 727420 # Number of cycles rename is blocking 286system.cpu.rename.serializeStallCycles 699991 # count of cycles rename stalled for serializing inst | 276system.cpu.decode.RunCycles 74834240 # Number of cycles decode is running 277system.cpu.decode.UnblockCycles 1196373 # Number of cycles decode is unblocking 278system.cpu.decode.SquashCycles 20843724 # Number of cycles decode is squashing 279system.cpu.decode.BranchResolved 14343881 # Number of times decode resolved a branch 280system.cpu.decode.BranchMispred 164426 # Number of times decode detected a branch misprediction 281system.cpu.decode.DecodedInsts 392938907 # Number of instructions handled by decode 282system.cpu.decode.SquashedInsts 736414 # Number of squashed instructions handled by decode 283system.cpu.rename.SquashCycles 20843724 # Number of cycles rename is squashing 284system.cpu.rename.IdleCycles 50922630 # Number of cycles rename is idle 285system.cpu.rename.BlockCycles 727420 # Number of cycles rename is blocking 286system.cpu.rename.serializeStallCycles 699991 # count of cycles rename stalled for serializing inst |
| 287system.cpu.rename.RunCycles 70572280 # Number of cycles rename is running | 287system.cpu.rename.RunCycles 70572281 # Number of cycles rename is running |
| 288system.cpu.rename.UnblockCycles 4622328 # Number of cycles rename is unblocking | 288system.cpu.rename.UnblockCycles 4622328 # Number of cycles rename is unblocking |
| 289system.cpu.rename.RenamedInsts 371457492 # Number of instructions processed by rename | 289system.cpu.rename.RenamedInsts 371457493 # Number of instructions processed by rename |
| 290system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full 291system.cpu.rename.IQFullEvents 340569 # Number of times rename has blocked due to IQ full 292system.cpu.rename.LSQFullEvents 3661423 # Number of times rename has blocked due to LSQ full 293system.cpu.rename.FullRegisterEvents 29 # Number of times there has been no free registers | 290system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full 291system.cpu.rename.IQFullEvents 340569 # Number of times rename has blocked due to IQ full 292system.cpu.rename.LSQFullEvents 3661423 # Number of times rename has blocked due to LSQ full 293system.cpu.rename.FullRegisterEvents 29 # Number of times there has been no free registers |
| 294system.cpu.rename.RenamedOperands 631852668 # Number of destination operands rename has renamed 295system.cpu.rename.RenameLookups 1582346867 # Number of register rename lookups that rename has made 296system.cpu.rename.int_rename_lookups 1565037376 # Number of integer rename lookups | 294system.cpu.rename.RenamedOperands 631852669 # Number of destination operands rename has renamed 295system.cpu.rename.RenameLookups 1582346871 # Number of register rename lookups that rename has made 296system.cpu.rename.int_rename_lookups 1565037380 # Number of integer rename lookups |
| 297system.cpu.rename.fp_rename_lookups 17309491 # Number of floating rename lookups 298system.cpu.rename.CommittedMaps 298092811 # Number of HB maps that are committed | 297system.cpu.rename.fp_rename_lookups 17309491 # Number of floating rename lookups 298system.cpu.rename.CommittedMaps 298092811 # Number of HB maps that are committed |
| 299system.cpu.rename.UndoneMaps 333759857 # Number of HB maps that are undone due to squashing | 299system.cpu.rename.UndoneMaps 333759858 # Number of HB maps that are undone due to squashing |
| 300system.cpu.rename.serializingInsts 32532 # count of serializing insts renamed 301system.cpu.rename.tempSerializingInsts 32528 # count of temporary serializing insts renamed 302system.cpu.rename.skidInsts 13064863 # count of insts added to the skid buffer 303system.cpu.memDep0.insertedLoads 43027461 # Number of loads inserted to the mem dependence unit. 304system.cpu.memDep0.insertedStores 16443523 # Number of stores inserted to the mem dependence unit. 305system.cpu.memDep0.conflictingLoads 5668310 # Number of conflicting loads. 306system.cpu.memDep0.conflictingStores 3691413 # Number of conflicting stores. 307system.cpu.iq.iqInstsAdded 329308816 # Number of instructions added to the IQ (excludes non-spec) 308system.cpu.iq.iqNonSpecInstsAdded 54643 # Number of non-speculative instructions added to the IQ 309system.cpu.iq.iqInstsIssued 249531465 # Number of instructions issued 310system.cpu.iq.iqSquashedInstsIssued 795533 # Number of squashed instructions issued 311system.cpu.iq.iqSquashedInstsExamined 139603170 # Number of squashed instructions iterated over during squash; mainly for profiling 312system.cpu.iq.iqSquashedOperandsExamined 362284552 # Number of squashed operands that are examined and possibly removed from graph 313system.cpu.iq.iqSquashedNonSpecRemoved 3343 # Number of squashed non-spec instructions that were removed | 300system.cpu.rename.serializingInsts 32532 # count of serializing insts renamed 301system.cpu.rename.tempSerializingInsts 32528 # count of temporary serializing insts renamed 302system.cpu.rename.skidInsts 13064863 # count of insts added to the skid buffer 303system.cpu.memDep0.insertedLoads 43027461 # Number of loads inserted to the mem dependence unit. 304system.cpu.memDep0.insertedStores 16443523 # Number of stores inserted to the mem dependence unit. 305system.cpu.memDep0.conflictingLoads 5668310 # Number of conflicting loads. 306system.cpu.memDep0.conflictingStores 3691413 # Number of conflicting stores. 307system.cpu.iq.iqInstsAdded 329308816 # Number of instructions added to the IQ (excludes non-spec) 308system.cpu.iq.iqNonSpecInstsAdded 54643 # Number of non-speculative instructions added to the IQ 309system.cpu.iq.iqInstsIssued 249531465 # Number of instructions issued 310system.cpu.iq.iqSquashedInstsIssued 795533 # Number of squashed instructions issued 311system.cpu.iq.iqSquashedInstsExamined 139603170 # Number of squashed instructions iterated over during squash; mainly for profiling 312system.cpu.iq.iqSquashedOperandsExamined 362284552 # Number of squashed operands that are examined and possibly removed from graph 313system.cpu.iq.iqSquashedNonSpecRemoved 3343 # Number of squashed non-spec instructions that were removed |
| 314system.cpu.iq.issued_per_cycle::samples 148388373 # Number of insts issued each cycle | 314system.cpu.iq.issued_per_cycle::samples 148388374 # Number of insts issued each cycle |
| 315system.cpu.iq.issued_per_cycle::mean 1.681611 # Number of insts issued each cycle 316system.cpu.iq.issued_per_cycle::stdev 1.761108 # Number of insts issued each cycle 317system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 315system.cpu.iq.issued_per_cycle::mean 1.681611 # Number of insts issued each cycle 316system.cpu.iq.issued_per_cycle::stdev 1.761108 # Number of insts issued each cycle 317system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 318system.cpu.iq.issued_per_cycle::0 56153945 37.84% 37.84% # Number of insts issued each cycle | 318system.cpu.iq.issued_per_cycle::0 56153946 37.84% 37.84% # Number of insts issued each cycle |
| 319system.cpu.iq.issued_per_cycle::1 22688522 15.29% 53.13% # Number of insts issued each cycle 320system.cpu.iq.issued_per_cycle::2 24821947 16.73% 69.86% # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::3 20330759 13.70% 83.56% # Number of insts issued each cycle 322system.cpu.iq.issued_per_cycle::4 12554169 8.46% 92.02% # Number of insts issued each cycle 323system.cpu.iq.issued_per_cycle::5 6514357 4.39% 96.41% # Number of insts issued each cycle 324system.cpu.iq.issued_per_cycle::6 4035019 2.72% 99.13% # Number of insts issued each cycle 325system.cpu.iq.issued_per_cycle::7 1109043 0.75% 99.88% # Number of insts issued each cycle 326system.cpu.iq.issued_per_cycle::8 180612 0.12% 100.00% # Number of insts issued each cycle 327system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 328system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 329system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 319system.cpu.iq.issued_per_cycle::1 22688522 15.29% 53.13% # Number of insts issued each cycle 320system.cpu.iq.issued_per_cycle::2 24821947 16.73% 69.86% # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::3 20330759 13.70% 83.56% # Number of insts issued each cycle 322system.cpu.iq.issued_per_cycle::4 12554169 8.46% 92.02% # Number of insts issued each cycle 323system.cpu.iq.issued_per_cycle::5 6514357 4.39% 96.41% # Number of insts issued each cycle 324system.cpu.iq.issued_per_cycle::6 4035019 2.72% 99.13% # Number of insts issued each cycle 325system.cpu.iq.issued_per_cycle::7 1109043 0.75% 99.88% # Number of insts issued each cycle 326system.cpu.iq.issued_per_cycle::8 180612 0.12% 100.00% # Number of insts issued each cycle 327system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 328system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 329system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 330system.cpu.iq.issued_per_cycle::total 148388373 # Number of insts issued each cycle | 330system.cpu.iq.issued_per_cycle::total 148388374 # Number of insts issued each cycle |
| 331system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 332system.cpu.iq.fu_full::IntAlu 962652 38.43% 38.43% # attempts to use FU when none available 333system.cpu.iq.fu_full::IntMult 5596 0.22% 38.65% # attempts to use FU when none available 334system.cpu.iq.fu_full::IntDiv 0 0.00% 38.65% # attempts to use FU when none available 335system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.65% # attempts to use FU when none available 336system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.65% # attempts to use FU when none available 337system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.65% # attempts to use FU when none available 338system.cpu.iq.fu_full::FloatMult 0 0.00% 38.65% # attempts to use FU when none available --- 56 unchanged lines hidden (view full) --- 395system.cpu.iq.FU_type_0::MemRead 38372441 15.38% 94.40% # Type of FU issued 396system.cpu.iq.FU_type_0::MemWrite 13962748 5.60% 100.00% # Type of FU issued 397system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 398system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 399system.cpu.iq.FU_type_0::total 249531465 # Type of FU issued 400system.cpu.iq.rate 1.680459 # Inst issue rate 401system.cpu.iq.fu_busy_cnt 2504922 # FU busy when requested 402system.cpu.iq.fu_busy_rate 0.010039 # FU busy rate (busy events/executed inst) | 331system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 332system.cpu.iq.fu_full::IntAlu 962652 38.43% 38.43% # attempts to use FU when none available 333system.cpu.iq.fu_full::IntMult 5596 0.22% 38.65% # attempts to use FU when none available 334system.cpu.iq.fu_full::IntDiv 0 0.00% 38.65% # attempts to use FU when none available 335system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.65% # attempts to use FU when none available 336system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.65% # attempts to use FU when none available 337system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.65% # attempts to use FU when none available 338system.cpu.iq.fu_full::FloatMult 0 0.00% 38.65% # attempts to use FU when none available --- 56 unchanged lines hidden (view full) --- 395system.cpu.iq.FU_type_0::MemRead 38372441 15.38% 94.40% # Type of FU issued 396system.cpu.iq.FU_type_0::MemWrite 13962748 5.60% 100.00% # Type of FU issued 397system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 398system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 399system.cpu.iq.FU_type_0::total 249531465 # Type of FU issued 400system.cpu.iq.rate 1.680459 # Inst issue rate 401system.cpu.iq.fu_busy_cnt 2504922 # FU busy when requested 402system.cpu.iq.fu_busy_rate 0.010039 # FU busy rate (busy events/executed inst) |
| 403system.cpu.iq.int_inst_queue_reads 647013011 # Number of integer instruction queue reads | 403system.cpu.iq.int_inst_queue_reads 647013012 # Number of integer instruction queue reads |
| 404system.cpu.iq.int_inst_queue_writes 466795184 # Number of integer instruction queue writes 405system.cpu.iq.int_inst_queue_wakeup_accesses 237947786 # Number of integer instruction queue wakeup accesses 406system.cpu.iq.fp_inst_queue_reads 3738747 # Number of floating instruction queue reads 407system.cpu.iq.fp_inst_queue_writes 2189794 # Number of floating instruction queue writes 408system.cpu.iq.fp_inst_queue_wakeup_accesses 1841578 # Number of floating instruction queue wakeup accesses 409system.cpu.iq.int_alu_accesses 250160112 # Number of integer alu accesses 410system.cpu.iq.fp_alu_accesses 1876275 # Number of floating point alu accesses 411system.cpu.iew.lsq.thread0.forwLoads 2013222 # Number of loads that had data forwarded from stores --- 6 unchanged lines hidden (view full) --- 418system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 419system.cpu.iew.lsq.thread0.rescheduledLoads 14 # Number of loads that were rescheduled 420system.cpu.iew.lsq.thread0.cacheBlocked 96 # Number of times an access to memory failed due to the cache being blocked 421system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 422system.cpu.iew.iewSquashCycles 20843724 # Number of cycles IEW is squashing 423system.cpu.iew.iewBlockCycles 17321 # Number of cycles IEW is blocking 424system.cpu.iew.iewUnblockCycles 891 # Number of cycles IEW is unblocking 425system.cpu.iew.iewDispatchedInsts 329380427 # Number of instructions dispatched to IQ | 404system.cpu.iq.int_inst_queue_writes 466795184 # Number of integer instruction queue writes 405system.cpu.iq.int_inst_queue_wakeup_accesses 237947786 # Number of integer instruction queue wakeup accesses 406system.cpu.iq.fp_inst_queue_reads 3738747 # Number of floating instruction queue reads 407system.cpu.iq.fp_inst_queue_writes 2189794 # Number of floating instruction queue writes 408system.cpu.iq.fp_inst_queue_wakeup_accesses 1841578 # Number of floating instruction queue wakeup accesses 409system.cpu.iq.int_alu_accesses 250160112 # Number of integer alu accesses 410system.cpu.iq.fp_alu_accesses 1876275 # Number of floating point alu accesses 411system.cpu.iew.lsq.thread0.forwLoads 2013222 # Number of loads that had data forwarded from stores --- 6 unchanged lines hidden (view full) --- 418system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 419system.cpu.iew.lsq.thread0.rescheduledLoads 14 # Number of loads that were rescheduled 420system.cpu.iew.lsq.thread0.cacheBlocked 96 # Number of times an access to memory failed due to the cache being blocked 421system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 422system.cpu.iew.iewSquashCycles 20843724 # Number of cycles IEW is squashing 423system.cpu.iew.iewBlockCycles 17321 # Number of cycles IEW is blocking 424system.cpu.iew.iewUnblockCycles 891 # Number of cycles IEW is unblocking 425system.cpu.iew.iewDispatchedInsts 329380427 # Number of instructions dispatched to IQ |
| 426system.cpu.iew.iewDispSquashedInsts 786985 # Number of squashed instructions skipped by dispatch | 426system.cpu.iew.iewDispSquashedInsts 786986 # Number of squashed instructions skipped by dispatch |
| 427system.cpu.iew.iewDispLoadInsts 43027461 # Number of dispatched load instructions 428system.cpu.iew.iewDispStoreInsts 16443523 # Number of dispatched store instructions 429system.cpu.iew.iewDispNonSpecInsts 32104 # Number of dispatched non-speculative instructions 430system.cpu.iew.iewIQFullEvents 209 # Number of times the IQ has become full, causing a stall 431system.cpu.iew.iewLSQFullEvents 288 # Number of times the LSQ has become full, causing a stall 432system.cpu.iew.memOrderViolationEvents 18785 # Number of memory order violations 433system.cpu.iew.predictedTakenIncorrect 3890771 # Number of branches that were predicted taken incorrectly 434system.cpu.iew.predictedNotTakenIncorrect 3762289 # Number of branches that were predicted not taken incorrectly --- 45 unchanged lines hidden (view full) --- 480system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. 481system.cpu.commit.int_insts 150130553 # Number of committed integer instructions. 482system.cpu.commit.function_calls 1848934 # Number of function calls committed. 483system.cpu.commit.bw_lim_events 7871050 # number cycles where commit BW limit reached 484system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 485system.cpu.rob.rob_reads 449048801 # The number of ROB reads 486system.cpu.rob.rob_writes 679713725 # The number of ROB writes 487system.cpu.timesIdled 2572 # Number of times that the entire CPU went into an idle state and unscheduled itself | 427system.cpu.iew.iewDispLoadInsts 43027461 # Number of dispatched load instructions 428system.cpu.iew.iewDispStoreInsts 16443523 # Number of dispatched store instructions 429system.cpu.iew.iewDispNonSpecInsts 32104 # Number of dispatched non-speculative instructions 430system.cpu.iew.iewIQFullEvents 209 # Number of times the IQ has become full, causing a stall 431system.cpu.iew.iewLSQFullEvents 288 # Number of times the LSQ has become full, causing a stall 432system.cpu.iew.memOrderViolationEvents 18785 # Number of memory order violations 433system.cpu.iew.predictedTakenIncorrect 3890771 # Number of branches that were predicted taken incorrectly 434system.cpu.iew.predictedNotTakenIncorrect 3762289 # Number of branches that were predicted not taken incorrectly --- 45 unchanged lines hidden (view full) --- 480system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. 481system.cpu.commit.int_insts 150130553 # Number of committed integer instructions. 482system.cpu.commit.function_calls 1848934 # Number of function calls committed. 483system.cpu.commit.bw_lim_events 7871050 # number cycles where commit BW limit reached 484system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 485system.cpu.rob.rob_reads 449048801 # The number of ROB reads 486system.cpu.rob.rob_writes 679713725 # The number of ROB writes 487system.cpu.timesIdled 2572 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 488system.cpu.idleCycles 101692 # Total number of cycles that the CPU has spent unscheduled due to idling | 488system.cpu.idleCycles 101691 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 489system.cpu.committedInsts 172333441 # Number of Instructions Simulated 490system.cpu.committedOps 188686923 # Number of Ops (including micro ops) Simulated 491system.cpu.committedInsts_total 172333441 # Number of Instructions Simulated 492system.cpu.cpi 0.861644 # CPI: Cycles Per Instruction 493system.cpu.cpi_total 0.861644 # CPI: Total CPI of All Threads 494system.cpu.ipc 1.160572 # IPC: Instructions Per Cycle 495system.cpu.ipc_total 1.160572 # IPC: Total IPC of All Threads 496system.cpu.int_regfile_reads 1079711901 # number of integer regfile reads 497system.cpu.int_regfile_writes 384939818 # number of integer regfile writes 498system.cpu.fp_regfile_reads 2913621 # number of floating regfile reads 499system.cpu.fp_regfile_writes 2497505 # number of floating regfile writes 500system.cpu.misc_regfile_reads 54528814 # number of misc regfile reads 501system.cpu.misc_regfile_writes 832204 # number of misc regfile writes 502system.cpu.icache.replacements 2508 # number of replacements | 489system.cpu.committedInsts 172333441 # Number of Instructions Simulated 490system.cpu.committedOps 188686923 # Number of Ops (including micro ops) Simulated 491system.cpu.committedInsts_total 172333441 # Number of Instructions Simulated 492system.cpu.cpi 0.861644 # CPI: Cycles Per Instruction 493system.cpu.cpi_total 0.861644 # CPI: Total CPI of All Threads 494system.cpu.ipc 1.160572 # IPC: Instructions Per Cycle 495system.cpu.ipc_total 1.160572 # IPC: Total IPC of All Threads 496system.cpu.int_regfile_reads 1079711901 # number of integer regfile reads 497system.cpu.int_regfile_writes 384939818 # number of integer regfile writes 498system.cpu.fp_regfile_reads 2913621 # number of floating regfile reads 499system.cpu.fp_regfile_writes 2497505 # number of floating regfile writes 500system.cpu.misc_regfile_reads 54528814 # number of misc regfile reads 501system.cpu.misc_regfile_writes 832204 # number of misc regfile writes 502system.cpu.icache.replacements 2508 # number of replacements |
| 503system.cpu.icache.tagsinuse 1347.136586 # Cycle average of tags in use | 503system.cpu.icache.tagsinuse 1347.136600 # Cycle average of tags in use |
| 504system.cpu.icache.total_refs 36854521 # Total number of references to valid blocks. 505system.cpu.icache.sampled_refs 4234 # Sample count of references to valid blocks. 506system.cpu.icache.avg_refs 8704.421587 # Average number of references to valid blocks. 507system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 504system.cpu.icache.total_refs 36854521 # Total number of references to valid blocks. 505system.cpu.icache.sampled_refs 4234 # Sample count of references to valid blocks. 506system.cpu.icache.avg_refs 8704.421587 # Average number of references to valid blocks. 507system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 508system.cpu.icache.occ_blocks::cpu.inst 1347.136586 # Average occupied blocks per requestor | 508system.cpu.icache.occ_blocks::cpu.inst 1347.136600 # Average occupied blocks per requestor |
| 509system.cpu.icache.occ_percent::cpu.inst 0.657782 # Average percentage of cache occupancy 510system.cpu.icache.occ_percent::total 0.657782 # Average percentage of cache occupancy 511system.cpu.icache.ReadReq_hits::cpu.inst 36854521 # number of ReadReq hits 512system.cpu.icache.ReadReq_hits::total 36854521 # number of ReadReq hits 513system.cpu.icache.demand_hits::cpu.inst 36854521 # number of demand (read+write) hits 514system.cpu.icache.demand_hits::total 36854521 # number of demand (read+write) hits 515system.cpu.icache.overall_hits::cpu.inst 36854521 # number of overall hits 516system.cpu.icache.overall_hits::total 36854521 # number of overall hits | 509system.cpu.icache.occ_percent::cpu.inst 0.657782 # Average percentage of cache occupancy 510system.cpu.icache.occ_percent::total 0.657782 # Average percentage of cache occupancy 511system.cpu.icache.ReadReq_hits::cpu.inst 36854521 # number of ReadReq hits 512system.cpu.icache.ReadReq_hits::total 36854521 # number of ReadReq hits 513system.cpu.icache.demand_hits::cpu.inst 36854521 # number of demand (read+write) hits 514system.cpu.icache.demand_hits::total 36854521 # number of demand (read+write) hits 515system.cpu.icache.overall_hits::cpu.inst 36854521 # number of overall hits 516system.cpu.icache.overall_hits::total 36854521 # number of overall hits |
| 517system.cpu.icache.ReadReq_misses::cpu.inst 5339 # number of ReadReq misses 518system.cpu.icache.ReadReq_misses::total 5339 # number of ReadReq misses 519system.cpu.icache.demand_misses::cpu.inst 5339 # number of demand (read+write) misses 520system.cpu.icache.demand_misses::total 5339 # number of demand (read+write) misses 521system.cpu.icache.overall_misses::cpu.inst 5339 # number of overall misses 522system.cpu.icache.overall_misses::total 5339 # number of overall misses 523system.cpu.icache.ReadReq_miss_latency::cpu.inst 158626499 # number of ReadReq miss cycles 524system.cpu.icache.ReadReq_miss_latency::total 158626499 # number of ReadReq miss cycles 525system.cpu.icache.demand_miss_latency::cpu.inst 158626499 # number of demand (read+write) miss cycles 526system.cpu.icache.demand_miss_latency::total 158626499 # number of demand (read+write) miss cycles 527system.cpu.icache.overall_miss_latency::cpu.inst 158626499 # number of overall miss cycles 528system.cpu.icache.overall_miss_latency::total 158626499 # number of overall miss cycles 529system.cpu.icache.ReadReq_accesses::cpu.inst 36859860 # number of ReadReq accesses(hits+misses) 530system.cpu.icache.ReadReq_accesses::total 36859860 # number of ReadReq accesses(hits+misses) 531system.cpu.icache.demand_accesses::cpu.inst 36859860 # number of demand (read+write) accesses 532system.cpu.icache.demand_accesses::total 36859860 # number of demand (read+write) accesses 533system.cpu.icache.overall_accesses::cpu.inst 36859860 # number of overall (read+write) accesses 534system.cpu.icache.overall_accesses::total 36859860 # number of overall (read+write) accesses | 517system.cpu.icache.ReadReq_misses::cpu.inst 5340 # number of ReadReq misses 518system.cpu.icache.ReadReq_misses::total 5340 # number of ReadReq misses 519system.cpu.icache.demand_misses::cpu.inst 5340 # number of demand (read+write) misses 520system.cpu.icache.demand_misses::total 5340 # number of demand (read+write) misses 521system.cpu.icache.overall_misses::cpu.inst 5340 # number of overall misses 522system.cpu.icache.overall_misses::total 5340 # number of overall misses 523system.cpu.icache.ReadReq_miss_latency::cpu.inst 158697499 # number of ReadReq miss cycles 524system.cpu.icache.ReadReq_miss_latency::total 158697499 # number of ReadReq miss cycles 525system.cpu.icache.demand_miss_latency::cpu.inst 158697499 # number of demand (read+write) miss cycles 526system.cpu.icache.demand_miss_latency::total 158697499 # number of demand (read+write) miss cycles 527system.cpu.icache.overall_miss_latency::cpu.inst 158697499 # number of overall miss cycles 528system.cpu.icache.overall_miss_latency::total 158697499 # number of overall miss cycles 529system.cpu.icache.ReadReq_accesses::cpu.inst 36859861 # number of ReadReq accesses(hits+misses) 530system.cpu.icache.ReadReq_accesses::total 36859861 # number of ReadReq accesses(hits+misses) 531system.cpu.icache.demand_accesses::cpu.inst 36859861 # number of demand (read+write) accesses 532system.cpu.icache.demand_accesses::total 36859861 # number of demand (read+write) accesses 533system.cpu.icache.overall_accesses::cpu.inst 36859861 # number of overall (read+write) accesses 534system.cpu.icache.overall_accesses::total 36859861 # number of overall (read+write) accesses |
| 535system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000145 # miss rate for ReadReq accesses 536system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses 537system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses 538system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses 539system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses 540system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses | 535system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000145 # miss rate for ReadReq accesses 536system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses 537system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses 538system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses 539system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses 540system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses |
| 541system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29710.900730 # average ReadReq miss latency 542system.cpu.icache.ReadReq_avg_miss_latency::total 29710.900730 # average ReadReq miss latency 543system.cpu.icache.demand_avg_miss_latency::cpu.inst 29710.900730 # average overall miss latency 544system.cpu.icache.demand_avg_miss_latency::total 29710.900730 # average overall miss latency 545system.cpu.icache.overall_avg_miss_latency::cpu.inst 29710.900730 # average overall miss latency 546system.cpu.icache.overall_avg_miss_latency::total 29710.900730 # average overall miss latency | 541system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29718.632772 # average ReadReq miss latency 542system.cpu.icache.ReadReq_avg_miss_latency::total 29718.632772 # average ReadReq miss latency 543system.cpu.icache.demand_avg_miss_latency::cpu.inst 29718.632772 # average overall miss latency 544system.cpu.icache.demand_avg_miss_latency::total 29718.632772 # average overall miss latency 545system.cpu.icache.overall_avg_miss_latency::cpu.inst 29718.632772 # average overall miss latency 546system.cpu.icache.overall_avg_miss_latency::total 29718.632772 # average overall miss latency |
| 547system.cpu.icache.blocked_cycles::no_mshrs 604 # number of cycles access was blocked 548system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 549system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked 550system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 551system.cpu.icache.avg_blocked_cycles::no_mshrs 35.529412 # average number of cycles each access was blocked 552system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 553system.cpu.icache.fast_writes 0 # number of fast writes performed 554system.cpu.icache.cache_copies 0 # number of cache copies performed | 547system.cpu.icache.blocked_cycles::no_mshrs 604 # number of cycles access was blocked 548system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 549system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked 550system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 551system.cpu.icache.avg_blocked_cycles::no_mshrs 35.529412 # average number of cycles each access was blocked 552system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 553system.cpu.icache.fast_writes 0 # number of fast writes performed 554system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 555system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1102 # number of ReadReq MSHR hits 556system.cpu.icache.ReadReq_mshr_hits::total 1102 # number of ReadReq MSHR hits 557system.cpu.icache.demand_mshr_hits::cpu.inst 1102 # number of demand (read+write) MSHR hits 558system.cpu.icache.demand_mshr_hits::total 1102 # number of demand (read+write) MSHR hits 559system.cpu.icache.overall_mshr_hits::cpu.inst 1102 # number of overall MSHR hits 560system.cpu.icache.overall_mshr_hits::total 1102 # number of overall MSHR hits | 555system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1103 # number of ReadReq MSHR hits 556system.cpu.icache.ReadReq_mshr_hits::total 1103 # number of ReadReq MSHR hits 557system.cpu.icache.demand_mshr_hits::cpu.inst 1103 # number of demand (read+write) MSHR hits 558system.cpu.icache.demand_mshr_hits::total 1103 # number of demand (read+write) MSHR hits 559system.cpu.icache.overall_mshr_hits::cpu.inst 1103 # number of overall MSHR hits 560system.cpu.icache.overall_mshr_hits::total 1103 # number of overall MSHR hits |
| 561system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4237 # number of ReadReq MSHR misses 562system.cpu.icache.ReadReq_mshr_misses::total 4237 # number of ReadReq MSHR misses 563system.cpu.icache.demand_mshr_misses::cpu.inst 4237 # number of demand (read+write) MSHR misses 564system.cpu.icache.demand_mshr_misses::total 4237 # number of demand (read+write) MSHR misses 565system.cpu.icache.overall_mshr_misses::cpu.inst 4237 # number of overall MSHR misses 566system.cpu.icache.overall_mshr_misses::total 4237 # number of overall MSHR misses 567system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122742499 # number of ReadReq MSHR miss cycles 568system.cpu.icache.ReadReq_mshr_miss_latency::total 122742499 # number of ReadReq MSHR miss cycles --- 9 unchanged lines hidden (view full) --- 578system.cpu.icache.overall_mshr_miss_rate::total 0.000115 # mshr miss rate for overall accesses 579system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28969.199670 # average ReadReq mshr miss latency 580system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28969.199670 # average ReadReq mshr miss latency 581system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28969.199670 # average overall mshr miss latency 582system.cpu.icache.demand_avg_mshr_miss_latency::total 28969.199670 # average overall mshr miss latency 583system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28969.199670 # average overall mshr miss latency 584system.cpu.icache.overall_avg_mshr_miss_latency::total 28969.199670 # average overall mshr miss latency 585system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 561system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4237 # number of ReadReq MSHR misses 562system.cpu.icache.ReadReq_mshr_misses::total 4237 # number of ReadReq MSHR misses 563system.cpu.icache.demand_mshr_misses::cpu.inst 4237 # number of demand (read+write) MSHR misses 564system.cpu.icache.demand_mshr_misses::total 4237 # number of demand (read+write) MSHR misses 565system.cpu.icache.overall_mshr_misses::cpu.inst 4237 # number of overall MSHR misses 566system.cpu.icache.overall_mshr_misses::total 4237 # number of overall MSHR misses 567system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122742499 # number of ReadReq MSHR miss cycles 568system.cpu.icache.ReadReq_mshr_miss_latency::total 122742499 # number of ReadReq MSHR miss cycles --- 9 unchanged lines hidden (view full) --- 578system.cpu.icache.overall_mshr_miss_rate::total 0.000115 # mshr miss rate for overall accesses 579system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28969.199670 # average ReadReq mshr miss latency 580system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28969.199670 # average ReadReq mshr miss latency 581system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28969.199670 # average overall mshr miss latency 582system.cpu.icache.demand_avg_mshr_miss_latency::total 28969.199670 # average overall mshr miss latency 583system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28969.199670 # average overall mshr miss latency 584system.cpu.icache.overall_avg_mshr_miss_latency::total 28969.199670 # average overall mshr miss latency 585system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 586system.cpu.dcache.replacements 57 # number of replacements 587system.cpu.dcache.tagsinuse 1406.445400 # Cycle average of tags in use 588system.cpu.dcache.total_refs 46805125 # Total number of references to valid blocks. 589system.cpu.dcache.sampled_refs 1854 # Sample count of references to valid blocks. 590system.cpu.dcache.avg_refs 25245.482740 # Average number of references to valid blocks. 591system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 592system.cpu.dcache.occ_blocks::cpu.data 1406.445400 # Average occupied blocks per requestor 593system.cpu.dcache.occ_percent::cpu.data 0.343370 # Average percentage of cache occupancy 594system.cpu.dcache.occ_percent::total 0.343370 # Average percentage of cache occupancy 595system.cpu.dcache.ReadReq_hits::cpu.data 34390274 # number of ReadReq hits 596system.cpu.dcache.ReadReq_hits::total 34390274 # number of ReadReq hits 597system.cpu.dcache.WriteReq_hits::cpu.data 12356568 # number of WriteReq hits 598system.cpu.dcache.WriteReq_hits::total 12356568 # number of WriteReq hits 599system.cpu.dcache.LoadLockedReq_hits::cpu.data 29790 # number of LoadLockedReq hits 600system.cpu.dcache.LoadLockedReq_hits::total 29790 # number of LoadLockedReq hits 601system.cpu.dcache.StoreCondReq_hits::cpu.data 28491 # number of StoreCondReq hits 602system.cpu.dcache.StoreCondReq_hits::total 28491 # number of StoreCondReq hits 603system.cpu.dcache.demand_hits::cpu.data 46746842 # number of demand (read+write) hits 604system.cpu.dcache.demand_hits::total 46746842 # number of demand (read+write) hits 605system.cpu.dcache.overall_hits::cpu.data 46746842 # number of overall hits 606system.cpu.dcache.overall_hits::total 46746842 # number of overall hits 607system.cpu.dcache.ReadReq_misses::cpu.data 1833 # number of ReadReq misses 608system.cpu.dcache.ReadReq_misses::total 1833 # number of ReadReq misses 609system.cpu.dcache.WriteReq_misses::cpu.data 7719 # number of WriteReq misses 610system.cpu.dcache.WriteReq_misses::total 7719 # number of WriteReq misses 611system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 612system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 613system.cpu.dcache.demand_misses::cpu.data 9552 # number of demand (read+write) misses 614system.cpu.dcache.demand_misses::total 9552 # number of demand (read+write) misses 615system.cpu.dcache.overall_misses::cpu.data 9552 # number of overall misses 616system.cpu.dcache.overall_misses::total 9552 # number of overall misses 617system.cpu.dcache.ReadReq_miss_latency::cpu.data 82596000 # number of ReadReq miss cycles 618system.cpu.dcache.ReadReq_miss_latency::total 82596000 # number of ReadReq miss cycles 619system.cpu.dcache.WriteReq_miss_latency::cpu.data 292720496 # number of WriteReq miss cycles 620system.cpu.dcache.WriteReq_miss_latency::total 292720496 # number of WriteReq miss cycles 621system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles 622system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles 623system.cpu.dcache.demand_miss_latency::cpu.data 375316496 # number of demand (read+write) miss cycles 624system.cpu.dcache.demand_miss_latency::total 375316496 # number of demand (read+write) miss cycles 625system.cpu.dcache.overall_miss_latency::cpu.data 375316496 # number of overall miss cycles 626system.cpu.dcache.overall_miss_latency::total 375316496 # number of overall miss cycles 627system.cpu.dcache.ReadReq_accesses::cpu.data 34392107 # number of ReadReq accesses(hits+misses) 628system.cpu.dcache.ReadReq_accesses::total 34392107 # number of ReadReq accesses(hits+misses) 629system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 630system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) 631system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29792 # number of LoadLockedReq accesses(hits+misses) 632system.cpu.dcache.LoadLockedReq_accesses::total 29792 # number of LoadLockedReq accesses(hits+misses) 633system.cpu.dcache.StoreCondReq_accesses::cpu.data 28491 # number of StoreCondReq accesses(hits+misses) 634system.cpu.dcache.StoreCondReq_accesses::total 28491 # number of StoreCondReq accesses(hits+misses) 635system.cpu.dcache.demand_accesses::cpu.data 46756394 # number of demand (read+write) accesses 636system.cpu.dcache.demand_accesses::total 46756394 # number of demand (read+write) accesses 637system.cpu.dcache.overall_accesses::cpu.data 46756394 # number of overall (read+write) accesses 638system.cpu.dcache.overall_accesses::total 46756394 # number of overall (read+write) accesses 639system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses 640system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses 641system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses 642system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses 643system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses 644system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses 645system.cpu.dcache.demand_miss_rate::cpu.data 0.000204 # miss rate for demand accesses 646system.cpu.dcache.demand_miss_rate::total 0.000204 # miss rate for demand accesses 647system.cpu.dcache.overall_miss_rate::cpu.data 0.000204 # miss rate for overall accesses 648system.cpu.dcache.overall_miss_rate::total 0.000204 # miss rate for overall accesses 649system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45060.556465 # average ReadReq miss latency 650system.cpu.dcache.ReadReq_avg_miss_latency::total 45060.556465 # average ReadReq miss latency 651system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37922.074880 # average WriteReq miss latency 652system.cpu.dcache.WriteReq_avg_miss_latency::total 37922.074880 # average WriteReq miss latency 653system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency 654system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency 655system.cpu.dcache.demand_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency 656system.cpu.dcache.demand_avg_miss_latency::total 39291.927973 # average overall miss latency 657system.cpu.dcache.overall_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency 658system.cpu.dcache.overall_avg_miss_latency::total 39291.927973 # average overall miss latency 659system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked 660system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked 661system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked 662system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked 663system.cpu.dcache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked 664system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked 665system.cpu.dcache.fast_writes 0 # number of fast writes performed 666system.cpu.dcache.cache_copies 0 # number of cache copies performed 667system.cpu.dcache.writebacks::writebacks 18 # number of writebacks 668system.cpu.dcache.writebacks::total 18 # number of writebacks 669system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1062 # number of ReadReq MSHR hits 670system.cpu.dcache.ReadReq_mshr_hits::total 1062 # number of ReadReq MSHR hits 671system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits 672system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits 673system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 674system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 675system.cpu.dcache.demand_mshr_hits::cpu.data 7696 # number of demand (read+write) MSHR hits 676system.cpu.dcache.demand_mshr_hits::total 7696 # number of demand (read+write) MSHR hits 677system.cpu.dcache.overall_mshr_hits::cpu.data 7696 # number of overall MSHR hits 678system.cpu.dcache.overall_mshr_hits::total 7696 # number of overall MSHR hits 679system.cpu.dcache.ReadReq_mshr_misses::cpu.data 771 # number of ReadReq MSHR misses 680system.cpu.dcache.ReadReq_mshr_misses::total 771 # number of ReadReq MSHR misses 681system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses 682system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses 683system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses 684system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses 685system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses 686system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses 687system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36781000 # number of ReadReq MSHR miss cycles 688system.cpu.dcache.ReadReq_mshr_miss_latency::total 36781000 # number of ReadReq MSHR miss cycles 689system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47410498 # number of WriteReq MSHR miss cycles 690system.cpu.dcache.WriteReq_mshr_miss_latency::total 47410498 # number of WriteReq MSHR miss cycles 691system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84191498 # number of demand (read+write) MSHR miss cycles 692system.cpu.dcache.demand_mshr_miss_latency::total 84191498 # number of demand (read+write) MSHR miss cycles 693system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84191498 # number of overall MSHR miss cycles 694system.cpu.dcache.overall_mshr_miss_latency::total 84191498 # number of overall MSHR miss cycles 695system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses 696system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses 697system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses 698system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses 699system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses 700system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 701system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses 702system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses 703system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47705.577173 # average ReadReq mshr miss latency 704system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47705.577173 # average ReadReq mshr miss latency 705system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43696.311521 # average WriteReq mshr miss latency 706system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43696.311521 # average WriteReq mshr miss latency 707system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency 708system.cpu.dcache.demand_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency 709system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency 710system.cpu.dcache.overall_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency 711system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 712system.cpu.l2cache.replacements 0 # number of replacements | 586system.cpu.l2cache.replacements 0 # number of replacements |
| 713system.cpu.l2cache.tagsinuse 1961.084973 # Cycle average of tags in use | 587system.cpu.l2cache.tagsinuse 1961.084990 # Cycle average of tags in use |
| 714system.cpu.l2cache.total_refs 2275 # Total number of references to valid blocks. 715system.cpu.l2cache.sampled_refs 2727 # Sample count of references to valid blocks. 716system.cpu.l2cache.avg_refs 0.834250 # Average number of references to valid blocks. 717system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 718system.cpu.l2cache.occ_blocks::writebacks 4.022996 # Average occupied blocks per requestor | 588system.cpu.l2cache.total_refs 2275 # Total number of references to valid blocks. 589system.cpu.l2cache.sampled_refs 2727 # Sample count of references to valid blocks. 590system.cpu.l2cache.avg_refs 0.834250 # Average number of references to valid blocks. 591system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 592system.cpu.l2cache.occ_blocks::writebacks 4.022996 # Average occupied blocks per requestor |
| 719system.cpu.l2cache.occ_blocks::cpu.inst 1424.044648 # Average occupied blocks per requestor 720system.cpu.l2cache.occ_blocks::cpu.data 533.017329 # Average occupied blocks per requestor | 593system.cpu.l2cache.occ_blocks::cpu.inst 1424.044661 # Average occupied blocks per requestor 594system.cpu.l2cache.occ_blocks::cpu.data 533.017333 # Average occupied blocks per requestor |
| 721system.cpu.l2cache.occ_percent::writebacks 0.000123 # Average percentage of cache occupancy 722system.cpu.l2cache.occ_percent::cpu.inst 0.043458 # Average percentage of cache occupancy 723system.cpu.l2cache.occ_percent::cpu.data 0.016266 # Average percentage of cache occupancy 724system.cpu.l2cache.occ_percent::total 0.059848 # Average percentage of cache occupancy 725system.cpu.l2cache.ReadReq_hits::cpu.inst 2184 # number of ReadReq hits 726system.cpu.l2cache.ReadReq_hits::cpu.data 90 # number of ReadReq hits 727system.cpu.l2cache.ReadReq_hits::total 2274 # number of ReadReq hits 728system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits --- 15 unchanged lines hidden (view full) --- 744system.cpu.l2cache.ReadExReq_misses::total 1075 # number of ReadExReq misses 745system.cpu.l2cache.demand_misses::cpu.inst 2051 # number of demand (read+write) misses 746system.cpu.l2cache.demand_misses::cpu.data 1756 # number of demand (read+write) misses 747system.cpu.l2cache.demand_misses::total 3807 # number of demand (read+write) misses 748system.cpu.l2cache.overall_misses::cpu.inst 2051 # number of overall misses 749system.cpu.l2cache.overall_misses::cpu.data 1756 # number of overall misses 750system.cpu.l2cache.overall_misses::total 3807 # number of overall misses 751system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 96653500 # number of ReadReq miss cycles | 595system.cpu.l2cache.occ_percent::writebacks 0.000123 # Average percentage of cache occupancy 596system.cpu.l2cache.occ_percent::cpu.inst 0.043458 # Average percentage of cache occupancy 597system.cpu.l2cache.occ_percent::cpu.data 0.016266 # Average percentage of cache occupancy 598system.cpu.l2cache.occ_percent::total 0.059848 # Average percentage of cache occupancy 599system.cpu.l2cache.ReadReq_hits::cpu.inst 2184 # number of ReadReq hits 600system.cpu.l2cache.ReadReq_hits::cpu.data 90 # number of ReadReq hits 601system.cpu.l2cache.ReadReq_hits::total 2274 # number of ReadReq hits 602system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits --- 15 unchanged lines hidden (view full) --- 618system.cpu.l2cache.ReadExReq_misses::total 1075 # number of ReadExReq misses 619system.cpu.l2cache.demand_misses::cpu.inst 2051 # number of demand (read+write) misses 620system.cpu.l2cache.demand_misses::cpu.data 1756 # number of demand (read+write) misses 621system.cpu.l2cache.demand_misses::total 3807 # number of demand (read+write) misses 622system.cpu.l2cache.overall_misses::cpu.inst 2051 # number of overall misses 623system.cpu.l2cache.overall_misses::cpu.data 1756 # number of overall misses 624system.cpu.l2cache.overall_misses::total 3807 # number of overall misses 625system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 96653500 # number of ReadReq miss cycles |
| 752system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35087500 # number of ReadReq miss cycles 753system.cpu.l2cache.ReadReq_miss_latency::total 131741000 # number of ReadReq miss cycles | 626system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35089000 # number of ReadReq miss cycles 627system.cpu.l2cache.ReadReq_miss_latency::total 131742500 # number of ReadReq miss cycles |
| 754system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46197000 # number of ReadExReq miss cycles 755system.cpu.l2cache.ReadExReq_miss_latency::total 46197000 # number of ReadExReq miss cycles 756system.cpu.l2cache.demand_miss_latency::cpu.inst 96653500 # number of demand (read+write) miss cycles | 628system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46197000 # number of ReadExReq miss cycles 629system.cpu.l2cache.ReadExReq_miss_latency::total 46197000 # number of ReadExReq miss cycles 630system.cpu.l2cache.demand_miss_latency::cpu.inst 96653500 # number of demand (read+write) miss cycles |
| 757system.cpu.l2cache.demand_miss_latency::cpu.data 81284500 # number of demand (read+write) miss cycles 758system.cpu.l2cache.demand_miss_latency::total 177938000 # number of demand (read+write) miss cycles | 631system.cpu.l2cache.demand_miss_latency::cpu.data 81286000 # number of demand (read+write) miss cycles 632system.cpu.l2cache.demand_miss_latency::total 177939500 # number of demand (read+write) miss cycles |
| 759system.cpu.l2cache.overall_miss_latency::cpu.inst 96653500 # number of overall miss cycles | 633system.cpu.l2cache.overall_miss_latency::cpu.inst 96653500 # number of overall miss cycles |
| 760system.cpu.l2cache.overall_miss_latency::cpu.data 81284500 # number of overall miss cycles 761system.cpu.l2cache.overall_miss_latency::total 177938000 # number of overall miss cycles | 634system.cpu.l2cache.overall_miss_latency::cpu.data 81286000 # number of overall miss cycles 635system.cpu.l2cache.overall_miss_latency::total 177939500 # number of overall miss cycles |
| 762system.cpu.l2cache.ReadReq_accesses::cpu.inst 4235 # number of ReadReq accesses(hits+misses) 763system.cpu.l2cache.ReadReq_accesses::cpu.data 771 # number of ReadReq accesses(hits+misses) 764system.cpu.l2cache.ReadReq_accesses::total 5006 # number of ReadReq accesses(hits+misses) 765system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) 766system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) 767system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) 768system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) 769system.cpu.l2cache.ReadExReq_accesses::cpu.data 1083 # number of ReadExReq accesses(hits+misses) --- 13 unchanged lines hidden (view full) --- 783system.cpu.l2cache.ReadExReq_miss_rate::total 0.992613 # miss rate for ReadExReq accesses 784system.cpu.l2cache.demand_miss_rate::cpu.inst 0.484298 # miss rate for demand accesses 785system.cpu.l2cache.demand_miss_rate::cpu.data 0.947141 # miss rate for demand accesses 786system.cpu.l2cache.demand_miss_rate::total 0.625226 # miss rate for demand accesses 787system.cpu.l2cache.overall_miss_rate::cpu.inst 0.484298 # miss rate for overall accesses 788system.cpu.l2cache.overall_miss_rate::cpu.data 0.947141 # miss rate for overall accesses 789system.cpu.l2cache.overall_miss_rate::total 0.625226 # miss rate for overall accesses 790system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47125.060946 # average ReadReq miss latency | 636system.cpu.l2cache.ReadReq_accesses::cpu.inst 4235 # number of ReadReq accesses(hits+misses) 637system.cpu.l2cache.ReadReq_accesses::cpu.data 771 # number of ReadReq accesses(hits+misses) 638system.cpu.l2cache.ReadReq_accesses::total 5006 # number of ReadReq accesses(hits+misses) 639system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) 640system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) 641system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) 642system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) 643system.cpu.l2cache.ReadExReq_accesses::cpu.data 1083 # number of ReadExReq accesses(hits+misses) --- 13 unchanged lines hidden (view full) --- 657system.cpu.l2cache.ReadExReq_miss_rate::total 0.992613 # miss rate for ReadExReq accesses 658system.cpu.l2cache.demand_miss_rate::cpu.inst 0.484298 # miss rate for demand accesses 659system.cpu.l2cache.demand_miss_rate::cpu.data 0.947141 # miss rate for demand accesses 660system.cpu.l2cache.demand_miss_rate::total 0.625226 # miss rate for demand accesses 661system.cpu.l2cache.overall_miss_rate::cpu.inst 0.484298 # miss rate for overall accesses 662system.cpu.l2cache.overall_miss_rate::cpu.data 0.947141 # miss rate for overall accesses 663system.cpu.l2cache.overall_miss_rate::total 0.625226 # miss rate for overall accesses 664system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47125.060946 # average ReadReq miss latency |
| 791system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 51523.494860 # average ReadReq miss latency 792system.cpu.l2cache.ReadReq_avg_miss_latency::total 48221.449488 # average ReadReq miss latency | 665system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 51525.697504 # average ReadReq miss latency 666system.cpu.l2cache.ReadReq_avg_miss_latency::total 48221.998536 # average ReadReq miss latency |
| 793system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42973.953488 # average ReadExReq miss latency 794system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42973.953488 # average ReadExReq miss latency 795system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47125.060946 # average overall miss latency | 667system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42973.953488 # average ReadExReq miss latency 668system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42973.953488 # average ReadExReq miss latency 669system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47125.060946 # average overall miss latency |
| 796system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46289.578588 # average overall miss latency 797system.cpu.l2cache.demand_avg_miss_latency::total 46739.690045 # average overall miss latency | 670system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46290.432802 # average overall miss latency 671system.cpu.l2cache.demand_avg_miss_latency::total 46740.084056 # average overall miss latency |
| 798system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47125.060946 # average overall miss latency | 672system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47125.060946 # average overall miss latency |
| 799system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46289.578588 # average overall miss latency 800system.cpu.l2cache.overall_avg_miss_latency::total 46739.690045 # average overall miss latency | 673system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46290.432802 # average overall miss latency 674system.cpu.l2cache.overall_avg_miss_latency::total 46740.084056 # average overall miss latency |
| 801system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 802system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 803system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 804system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 805system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 806system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 807system.cpu.l2cache.fast_writes 0 # number of fast writes performed 808system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 14 unchanged lines hidden (view full) --- 823system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1075 # number of ReadExReq MSHR misses 824system.cpu.l2cache.ReadExReq_mshr_misses::total 1075 # number of ReadExReq MSHR misses 825system.cpu.l2cache.demand_mshr_misses::cpu.inst 2048 # number of demand (read+write) MSHR misses 826system.cpu.l2cache.demand_mshr_misses::cpu.data 1745 # number of demand (read+write) MSHR misses 827system.cpu.l2cache.demand_mshr_misses::total 3793 # number of demand (read+write) MSHR misses 828system.cpu.l2cache.overall_mshr_misses::cpu.inst 2048 # number of overall MSHR misses 829system.cpu.l2cache.overall_mshr_misses::cpu.data 1745 # number of overall MSHR misses 830system.cpu.l2cache.overall_mshr_misses::total 3793 # number of overall MSHR misses | 675system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 676system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 677system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 678system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 679system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 680system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 681system.cpu.l2cache.fast_writes 0 # number of fast writes performed 682system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 14 unchanged lines hidden (view full) --- 697system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1075 # number of ReadExReq MSHR misses 698system.cpu.l2cache.ReadExReq_mshr_misses::total 1075 # number of ReadExReq MSHR misses 699system.cpu.l2cache.demand_mshr_misses::cpu.inst 2048 # number of demand (read+write) MSHR misses 700system.cpu.l2cache.demand_mshr_misses::cpu.data 1745 # number of demand (read+write) MSHR misses 701system.cpu.l2cache.demand_mshr_misses::total 3793 # number of demand (read+write) MSHR misses 702system.cpu.l2cache.overall_mshr_misses::cpu.inst 2048 # number of overall MSHR misses 703system.cpu.l2cache.overall_mshr_misses::cpu.data 1745 # number of overall MSHR misses 704system.cpu.l2cache.overall_mshr_misses::total 3793 # number of overall MSHR misses |
| 831system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70387399 # number of ReadReq MSHR miss cycles 832system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26266459 # number of ReadReq MSHR miss cycles 833system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96653858 # number of ReadReq MSHR miss cycles | 705system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70388399 # number of ReadReq MSHR miss cycles 706system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26267459 # number of ReadReq MSHR miss cycles 707system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96655858 # number of ReadReq MSHR miss cycles |
| 834system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles 835system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles 836system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32716158 # number of ReadExReq MSHR miss cycles 837system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32716158 # number of ReadExReq MSHR miss cycles | 708system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles 709system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles 710system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32716158 # number of ReadExReq MSHR miss cycles 711system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32716158 # number of ReadExReq MSHR miss cycles |
| 838system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70387399 # number of demand (read+write) MSHR miss cycles 839system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 58982617 # number of demand (read+write) MSHR miss cycles 840system.cpu.l2cache.demand_mshr_miss_latency::total 129370016 # number of demand (read+write) MSHR miss cycles 841system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70387399 # number of overall MSHR miss cycles 842system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 58982617 # number of overall MSHR miss cycles 843system.cpu.l2cache.overall_mshr_miss_latency::total 129370016 # number of overall MSHR miss cycles | 712system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70388399 # number of demand (read+write) MSHR miss cycles 713system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 58983617 # number of demand (read+write) MSHR miss cycles 714system.cpu.l2cache.demand_mshr_miss_latency::total 129372016 # number of demand (read+write) MSHR miss cycles 715system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70388399 # number of overall MSHR miss cycles 716system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 58983617 # number of overall MSHR miss cycles 717system.cpu.l2cache.overall_mshr_miss_latency::total 129372016 # number of overall MSHR miss cycles |
| 844system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.483589 # mshr miss rate for ReadReq accesses 845system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869001 # mshr miss rate for ReadReq accesses 846system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.542948 # mshr miss rate for ReadReq accesses 847system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 848system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 849system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992613 # mshr miss rate for ReadExReq accesses 850system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992613 # mshr miss rate for ReadExReq accesses 851system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.483589 # mshr miss rate for demand accesses 852system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941208 # mshr miss rate for demand accesses 853system.cpu.l2cache.demand_mshr_miss_rate::total 0.622927 # mshr miss rate for demand accesses 854system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.483589 # mshr miss rate for overall accesses 855system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941208 # mshr miss rate for overall accesses 856system.cpu.l2cache.overall_mshr_miss_rate::total 0.622927 # mshr miss rate for overall accesses | 718system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.483589 # mshr miss rate for ReadReq accesses 719system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869001 # mshr miss rate for ReadReq accesses 720system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.542948 # mshr miss rate for ReadReq accesses 721system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 722system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 723system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992613 # mshr miss rate for ReadExReq accesses 724system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992613 # mshr miss rate for ReadExReq accesses 725system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.483589 # mshr miss rate for demand accesses 726system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941208 # mshr miss rate for demand accesses 727system.cpu.l2cache.demand_mshr_miss_rate::total 0.622927 # mshr miss rate for demand accesses 728system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.483589 # mshr miss rate for overall accesses 729system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941208 # mshr miss rate for overall accesses 730system.cpu.l2cache.overall_mshr_miss_rate::total 0.622927 # mshr miss rate for overall accesses |
| 857system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34368.847168 # average ReadReq mshr miss latency 858system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39203.670149 # average ReadReq mshr miss latency 859system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35560.654157 # average ReadReq mshr miss latency | 731system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34369.335449 # average ReadReq mshr miss latency 732system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39205.162687 # average ReadReq mshr miss latency 733system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35561.389993 # average ReadReq mshr miss latency |
| 860system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 861system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 862system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30433.635349 # average ReadExReq mshr miss latency 863system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30433.635349 # average ReadExReq mshr miss latency | 734system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 735system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 736system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30433.635349 # average ReadExReq mshr miss latency 737system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30433.635349 # average ReadExReq mshr miss latency |
| 864system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34368.847168 # average overall mshr miss latency 865system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33800.926648 # average overall mshr miss latency 866system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34107.570788 # average overall mshr miss latency 867system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34368.847168 # average overall mshr miss latency 868system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33800.926648 # average overall mshr miss latency 869system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34107.570788 # average overall mshr miss latency | 738system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34369.335449 # average overall mshr miss latency 739system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33801.499713 # average overall mshr miss latency 740system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34108.098075 # average overall mshr miss latency 741system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34369.335449 # average overall mshr miss latency 742system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33801.499713 # average overall mshr miss latency 743system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34108.098075 # average overall mshr miss latency |
| 870system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 744system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 745system.cpu.dcache.replacements 57 # number of replacements 746system.cpu.dcache.tagsinuse 1406.445410 # Cycle average of tags in use 747system.cpu.dcache.total_refs 46805125 # Total number of references to valid blocks. 748system.cpu.dcache.sampled_refs 1854 # Sample count of references to valid blocks. 749system.cpu.dcache.avg_refs 25245.482740 # Average number of references to valid blocks. 750system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 751system.cpu.dcache.occ_blocks::cpu.data 1406.445410 # Average occupied blocks per requestor 752system.cpu.dcache.occ_percent::cpu.data 0.343370 # Average percentage of cache occupancy 753system.cpu.dcache.occ_percent::total 0.343370 # Average percentage of cache occupancy 754system.cpu.dcache.ReadReq_hits::cpu.data 34390274 # number of ReadReq hits 755system.cpu.dcache.ReadReq_hits::total 34390274 # number of ReadReq hits 756system.cpu.dcache.WriteReq_hits::cpu.data 12356568 # number of WriteReq hits 757system.cpu.dcache.WriteReq_hits::total 12356568 # number of WriteReq hits 758system.cpu.dcache.LoadLockedReq_hits::cpu.data 29790 # number of LoadLockedReq hits 759system.cpu.dcache.LoadLockedReq_hits::total 29790 # number of LoadLockedReq hits 760system.cpu.dcache.StoreCondReq_hits::cpu.data 28491 # number of StoreCondReq hits 761system.cpu.dcache.StoreCondReq_hits::total 28491 # number of StoreCondReq hits 762system.cpu.dcache.demand_hits::cpu.data 46746842 # number of demand (read+write) hits 763system.cpu.dcache.demand_hits::total 46746842 # number of demand (read+write) hits 764system.cpu.dcache.overall_hits::cpu.data 46746842 # number of overall hits 765system.cpu.dcache.overall_hits::total 46746842 # number of overall hits 766system.cpu.dcache.ReadReq_misses::cpu.data 1833 # number of ReadReq misses 767system.cpu.dcache.ReadReq_misses::total 1833 # number of ReadReq misses 768system.cpu.dcache.WriteReq_misses::cpu.data 7719 # number of WriteReq misses 769system.cpu.dcache.WriteReq_misses::total 7719 # number of WriteReq misses 770system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 771system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 772system.cpu.dcache.demand_misses::cpu.data 9552 # number of demand (read+write) misses 773system.cpu.dcache.demand_misses::total 9552 # number of demand (read+write) misses 774system.cpu.dcache.overall_misses::cpu.data 9552 # number of overall misses 775system.cpu.dcache.overall_misses::total 9552 # number of overall misses 776system.cpu.dcache.ReadReq_miss_latency::cpu.data 82599500 # number of ReadReq miss cycles 777system.cpu.dcache.ReadReq_miss_latency::total 82599500 # number of ReadReq miss cycles 778system.cpu.dcache.WriteReq_miss_latency::cpu.data 292720496 # number of WriteReq miss cycles 779system.cpu.dcache.WriteReq_miss_latency::total 292720496 # number of WriteReq miss cycles 780system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles 781system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles 782system.cpu.dcache.demand_miss_latency::cpu.data 375319996 # number of demand (read+write) miss cycles 783system.cpu.dcache.demand_miss_latency::total 375319996 # number of demand (read+write) miss cycles 784system.cpu.dcache.overall_miss_latency::cpu.data 375319996 # number of overall miss cycles 785system.cpu.dcache.overall_miss_latency::total 375319996 # number of overall miss cycles 786system.cpu.dcache.ReadReq_accesses::cpu.data 34392107 # number of ReadReq accesses(hits+misses) 787system.cpu.dcache.ReadReq_accesses::total 34392107 # number of ReadReq accesses(hits+misses) 788system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 789system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) 790system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29792 # number of LoadLockedReq accesses(hits+misses) 791system.cpu.dcache.LoadLockedReq_accesses::total 29792 # number of LoadLockedReq accesses(hits+misses) 792system.cpu.dcache.StoreCondReq_accesses::cpu.data 28491 # number of StoreCondReq accesses(hits+misses) 793system.cpu.dcache.StoreCondReq_accesses::total 28491 # number of StoreCondReq accesses(hits+misses) 794system.cpu.dcache.demand_accesses::cpu.data 46756394 # number of demand (read+write) accesses 795system.cpu.dcache.demand_accesses::total 46756394 # number of demand (read+write) accesses 796system.cpu.dcache.overall_accesses::cpu.data 46756394 # number of overall (read+write) accesses 797system.cpu.dcache.overall_accesses::total 46756394 # number of overall (read+write) accesses 798system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses 799system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses 800system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses 801system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses 802system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses 803system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses 804system.cpu.dcache.demand_miss_rate::cpu.data 0.000204 # miss rate for demand accesses 805system.cpu.dcache.demand_miss_rate::total 0.000204 # miss rate for demand accesses 806system.cpu.dcache.overall_miss_rate::cpu.data 0.000204 # miss rate for overall accesses 807system.cpu.dcache.overall_miss_rate::total 0.000204 # miss rate for overall accesses 808system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45062.465903 # average ReadReq miss latency 809system.cpu.dcache.ReadReq_avg_miss_latency::total 45062.465903 # average ReadReq miss latency 810system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37922.074880 # average WriteReq miss latency 811system.cpu.dcache.WriteReq_avg_miss_latency::total 37922.074880 # average WriteReq miss latency 812system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency 813system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency 814system.cpu.dcache.demand_avg_miss_latency::cpu.data 39292.294389 # average overall miss latency 815system.cpu.dcache.demand_avg_miss_latency::total 39292.294389 # average overall miss latency 816system.cpu.dcache.overall_avg_miss_latency::cpu.data 39292.294389 # average overall miss latency 817system.cpu.dcache.overall_avg_miss_latency::total 39292.294389 # average overall miss latency 818system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked 819system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked 820system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked 821system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked 822system.cpu.dcache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked 823system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked 824system.cpu.dcache.fast_writes 0 # number of fast writes performed 825system.cpu.dcache.cache_copies 0 # number of cache copies performed 826system.cpu.dcache.writebacks::writebacks 18 # number of writebacks 827system.cpu.dcache.writebacks::total 18 # number of writebacks 828system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1062 # number of ReadReq MSHR hits 829system.cpu.dcache.ReadReq_mshr_hits::total 1062 # number of ReadReq MSHR hits 830system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits 831system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits 832system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 833system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 834system.cpu.dcache.demand_mshr_hits::cpu.data 7696 # number of demand (read+write) MSHR hits 835system.cpu.dcache.demand_mshr_hits::total 7696 # number of demand (read+write) MSHR hits 836system.cpu.dcache.overall_mshr_hits::cpu.data 7696 # number of overall MSHR hits 837system.cpu.dcache.overall_mshr_hits::total 7696 # number of overall MSHR hits 838system.cpu.dcache.ReadReq_mshr_misses::cpu.data 771 # number of ReadReq MSHR misses 839system.cpu.dcache.ReadReq_mshr_misses::total 771 # number of ReadReq MSHR misses 840system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses 841system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses 842system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses 843system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses 844system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses 845system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses 846system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36782500 # number of ReadReq MSHR miss cycles 847system.cpu.dcache.ReadReq_mshr_miss_latency::total 36782500 # number of ReadReq MSHR miss cycles 848system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47410498 # number of WriteReq MSHR miss cycles 849system.cpu.dcache.WriteReq_mshr_miss_latency::total 47410498 # number of WriteReq MSHR miss cycles 850system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84192998 # number of demand (read+write) MSHR miss cycles 851system.cpu.dcache.demand_mshr_miss_latency::total 84192998 # number of demand (read+write) MSHR miss cycles 852system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84192998 # number of overall MSHR miss cycles 853system.cpu.dcache.overall_mshr_miss_latency::total 84192998 # number of overall MSHR miss cycles 854system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses 855system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses 856system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses 857system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses 858system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses 859system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 860system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses 861system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses 862system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47707.522698 # average ReadReq mshr miss latency 863system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47707.522698 # average ReadReq mshr miss latency 864system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43696.311521 # average WriteReq mshr miss latency 865system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43696.311521 # average WriteReq mshr miss latency 866system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45362.606681 # average overall mshr miss latency 867system.cpu.dcache.demand_avg_mshr_miss_latency::total 45362.606681 # average overall mshr miss latency 868system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45362.606681 # average overall mshr miss latency 869system.cpu.dcache.overall_avg_mshr_miss_latency::total 45362.606681 # average overall mshr miss latency 870system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
|
| 871 872---------- End Simulation Statistics ---------- | 871 872---------- End Simulation Statistics ---------- |