| stats.txt (9322:01c8c5ff2c3b) | stats.txt (9348:44d31345e360) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.075963 # Number of seconds simulated 4sim_ticks 75962996000 # Number of ticks simulated 5final_tick 75962996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.074245 # Number of seconds simulated 4sim_ticks 74245032000 # Number of ticks simulated 5final_tick 74245032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 82470 # Simulator instruction rate (inst/s) 8host_op_rate 90296 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 36352186 # Simulator tick rate (ticks/s) 10host_mem_usage 236740 # Number of bytes of host memory used 11host_seconds 2089.64 # Real time elapsed on the host 12sim_insts 172333241 # Number of instructions simulated 13sim_ops 188686723 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 132736 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 112192 # Number of bytes read from this memory 16system.physmem.bytes_read::total 244928 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 132736 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 132736 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 2074 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 1753 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 3827 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1747377 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 1476930 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 3224307 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1747377 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1747377 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1747377 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 1476930 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 3224307 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 3828 # Total number of read requests seen | 7host_inst_rate 109443 # Simulator instruction rate (inst/s) 8host_op_rate 119829 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 47150577 # Simulator tick rate (ticks/s) 10host_mem_usage 234068 # Number of bytes of host memory used 11host_seconds 1574.64 # Real time elapsed on the host 12sim_insts 172333441 # Number of instructions simulated 13sim_ops 188686923 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 131008 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 111680 # Number of bytes read from this memory 16system.physmem.bytes_read::total 242688 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 131008 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 131008 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 2047 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 1745 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 3792 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1764536 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 1504208 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 3268744 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1764536 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1764536 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1764536 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 1504208 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 3268744 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 3793 # Total number of read requests seen |
| 31system.physmem.writeReqs 0 # Total number of write requests seen | 31system.physmem.writeReqs 0 # Total number of write requests seen |
| 32system.physmem.cpureqs 3829 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 244928 # Total number of bytes read from memory | 32system.physmem.cpureqs 3795 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 242688 # Total number of bytes read from memory |
| 34system.physmem.bytesWritten 0 # Total number of bytes written to memory | 34system.physmem.bytesWritten 0 # Total number of bytes written to memory |
| 35system.physmem.bytesConsumedRd 244928 # bytesRead derated as per pkt->getSize() | 35system.physmem.bytesConsumedRd 242688 # bytesRead derated as per pkt->getSize() |
| 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q | 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q |
| 38system.physmem.neitherReadNorWrite 1 # Reqs where no action is needed 39system.physmem.perBankRdReqs::0 320 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 234 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 192 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 240 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 228 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 194 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 224 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 284 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 247 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 249 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 248 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 263 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 249 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 236 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 182 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 238 # Track reads on a per bank basis | 38system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed 39system.physmem.perBankRdReqs::0 319 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 231 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 191 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 236 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 227 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 193 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 221 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 282 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 242 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 247 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 247 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 259 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 248 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 234 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 179 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 237 # Track reads on a per bank basis |
| 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 73system.physmem.totGap 75962976500 # Total gap between requests | 73system.physmem.totGap 74245012500 # Total gap between requests |
| 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes | 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 80system.physmem.readPktSize::6 3828 # Categorize read packet sizes | 80system.physmem.readPktSize::6 3793 # Categorize read packet sizes |
| 81system.physmem.readPktSize::7 0 # Categorize read packet sizes 82system.physmem.readPktSize::8 0 # Categorize read packet sizes 83system.physmem.writePktSize::0 0 # categorize write packet sizes 84system.physmem.writePktSize::1 0 # categorize write packet sizes 85system.physmem.writePktSize::2 0 # categorize write packet sizes 86system.physmem.writePktSize::3 0 # categorize write packet sizes 87system.physmem.writePktSize::4 0 # categorize write packet sizes 88system.physmem.writePktSize::5 0 # categorize write packet sizes 89system.physmem.writePktSize::6 0 # categorize write packet sizes 90system.physmem.writePktSize::7 0 # categorize write packet sizes 91system.physmem.writePktSize::8 0 # categorize write packet sizes 92system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 93system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 94system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 95system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 96system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 97system.physmem.neitherpktsize::5 0 # categorize neither packet sizes | 81system.physmem.readPktSize::7 0 # Categorize read packet sizes 82system.physmem.readPktSize::8 0 # Categorize read packet sizes 83system.physmem.writePktSize::0 0 # categorize write packet sizes 84system.physmem.writePktSize::1 0 # categorize write packet sizes 85system.physmem.writePktSize::2 0 # categorize write packet sizes 86system.physmem.writePktSize::3 0 # categorize write packet sizes 87system.physmem.writePktSize::4 0 # categorize write packet sizes 88system.physmem.writePktSize::5 0 # categorize write packet sizes 89system.physmem.writePktSize::6 0 # categorize write packet sizes 90system.physmem.writePktSize::7 0 # categorize write packet sizes 91system.physmem.writePktSize::8 0 # categorize write packet sizes 92system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 93system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 94system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 95system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 96system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 97system.physmem.neitherpktsize::5 0 # categorize neither packet sizes |
| 98system.physmem.neitherpktsize::6 1 # categorize neither packet sizes | 98system.physmem.neitherpktsize::6 2 # categorize neither packet sizes |
| 99system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::8 0 # categorize neither packet sizes | 99system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::8 0 # categorize neither packet sizes |
| 101system.physmem.rdQLenPdf::0 2829 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 799 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 151 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 40 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see | 101system.physmem.rdQLenPdf::0 2791 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 811 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 147 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see |
| 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see --- 44 unchanged lines hidden (view full) --- 159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see | 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see --- 44 unchanged lines hidden (view full) --- 159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see |
| 167system.physmem.totQLat 15909310 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 90413310 # Sum of mem lat for all requests 169system.physmem.totBusLat 15312000 # Total cycles spent in databus access 170system.physmem.totBankLat 59192000 # Total cycles spent in bank access 171system.physmem.avgQLat 4156.04 # Average queueing delay per request 172system.physmem.avgBankLat 15462.90 # Average bank access latency per request | 167system.physmem.totQLat 12366785 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 86366785 # Sum of mem lat for all requests 169system.physmem.totBusLat 15172000 # Total cycles spent in databus access 170system.physmem.totBankLat 58828000 # Total cycles spent in bank access 171system.physmem.avgQLat 3260.42 # Average queueing delay per request 172system.physmem.avgBankLat 15509.62 # Average bank access latency per request |
| 173system.physmem.avgBusLat 4000.00 # Average bus latency per request | 173system.physmem.avgBusLat 4000.00 # Average bus latency per request |
| 174system.physmem.avgMemAccLat 23618.94 # Average memory access latency 175system.physmem.avgRdBW 3.22 # Average achieved read bandwidth in MB/s | 174system.physmem.avgMemAccLat 22770.05 # Average memory access latency 175system.physmem.avgRdBW 3.27 # Average achieved read bandwidth in MB/s |
| 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s | 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s |
| 177system.physmem.avgConsumedRdBW 3.22 # Average consumed read bandwidth in MB/s | 177system.physmem.avgConsumedRdBW 3.27 # Average consumed read bandwidth in MB/s |
| 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 180system.physmem.busUtil 0.02 # Data bus utilization in percentage 181system.physmem.avgRdQLen 0.00 # Average read queue length over time 182system.physmem.avgWrQLen 0.00 # Average write queue length over time | 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 180system.physmem.busUtil 0.02 # Data bus utilization in percentage 181system.physmem.avgRdQLen 0.00 # Average read queue length over time 182system.physmem.avgWrQLen 0.00 # Average write queue length over time |
| 183system.physmem.readRowHits 3324 # Number of row buffer hits during reads | 183system.physmem.readRowHits 3295 # Number of row buffer hits during reads |
| 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 185system.physmem.readRowHitRate 86.83 # Row buffer hit rate for reads | 185system.physmem.readRowHitRate 86.87 # Row buffer hit rate for reads |
| 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 187system.physmem.avgGap 19844037.75 # Average gap between requests | 187system.physmem.avgGap 19574218.96 # Average gap between requests |
| 188system.cpu.dtb.inst_hits 0 # ITB inst hits 189system.cpu.dtb.inst_misses 0 # ITB inst misses 190system.cpu.dtb.read_hits 0 # DTB read hits 191system.cpu.dtb.read_misses 0 # DTB read misses 192system.cpu.dtb.write_hits 0 # DTB write hits 193system.cpu.dtb.write_misses 0 # DTB write misses 194system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 195system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 223system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 224system.cpu.itb.read_accesses 0 # DTB read accesses 225system.cpu.itb.write_accesses 0 # DTB write accesses 226system.cpu.itb.inst_accesses 0 # ITB inst accesses 227system.cpu.itb.hits 0 # DTB hits 228system.cpu.itb.misses 0 # DTB misses 229system.cpu.itb.accesses 0 # DTB accesses 230system.cpu.workload.num_syscalls 400 # Number of system calls | 188system.cpu.dtb.inst_hits 0 # ITB inst hits 189system.cpu.dtb.inst_misses 0 # ITB inst misses 190system.cpu.dtb.read_hits 0 # DTB read hits 191system.cpu.dtb.read_misses 0 # DTB read misses 192system.cpu.dtb.write_hits 0 # DTB write hits 193system.cpu.dtb.write_misses 0 # DTB write misses 194system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 195system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 223system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 224system.cpu.itb.read_accesses 0 # DTB read accesses 225system.cpu.itb.write_accesses 0 # DTB write accesses 226system.cpu.itb.inst_accesses 0 # ITB inst accesses 227system.cpu.itb.hits 0 # DTB hits 228system.cpu.itb.misses 0 # DTB misses 229system.cpu.itb.accesses 0 # DTB accesses 230system.cpu.workload.num_syscalls 400 # Number of system calls |
| 231system.cpu.numCycles 151925993 # number of cpu cycles simulated | 231system.cpu.numCycles 148490065 # number of cpu cycles simulated |
| 232system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 233system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 232system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 233system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 234system.cpu.BPredUnit.lookups 96812188 # Number of BP lookups 235system.cpu.BPredUnit.condPredicted 76032236 # Number of conditional branches predicted 236system.cpu.BPredUnit.condIncorrect 6553809 # Number of conditional branches incorrect 237system.cpu.BPredUnit.BTBLookups 46446152 # Number of BTB lookups 238system.cpu.BPredUnit.BTBHits 44209779 # Number of BTB hits | 234system.cpu.BPredUnit.lookups 94824011 # Number of BP lookups 235system.cpu.BPredUnit.condPredicted 74811084 # Number of conditional branches predicted 236system.cpu.BPredUnit.condIncorrect 6283419 # Number of conditional branches incorrect 237system.cpu.BPredUnit.BTBLookups 44691419 # Number of BTB lookups 238system.cpu.BPredUnit.BTBHits 43068728 # Number of BTB hits |
| 239system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 239system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 240system.cpu.BPredUnit.usedRAS 4476893 # Number of times the RAS was used to get a target. 241system.cpu.BPredUnit.RASInCorrect 89558 # Number of incorrect RAS predictions. 242system.cpu.fetch.icacheStallCycles 40612935 # Number of cycles fetch is stalled on an Icache miss 243system.cpu.fetch.Insts 388214882 # Number of instructions fetch has processed 244system.cpu.fetch.Branches 96812188 # Number of branches that fetch encountered 245system.cpu.fetch.predictedBranches 48686672 # Number of branches that fetch has predicted taken 246system.cpu.fetch.Cycles 82228989 # Number of cycles fetch has run and was not squashing or blocked 247system.cpu.fetch.SquashCycles 28431080 # Number of cycles fetch has spent squashing 248system.cpu.fetch.BlockedCycles 7111966 # Number of cycles fetch has spent blocked 249system.cpu.fetch.MiscStallCycles 46 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 250system.cpu.fetch.PendingTrapStallCycles 9226 # Number of stall cycles due to pending traps | 240system.cpu.BPredUnit.usedRAS 4355687 # Number of times the RAS was used to get a target. 241system.cpu.BPredUnit.RASInCorrect 88461 # Number of incorrect RAS predictions. 242system.cpu.fetch.icacheStallCycles 39671704 # Number of cycles fetch is stalled on an Icache miss 243system.cpu.fetch.Insts 380334125 # Number of instructions fetch has processed 244system.cpu.fetch.Branches 94824011 # Number of branches that fetch encountered 245system.cpu.fetch.predictedBranches 47424415 # Number of branches that fetch has predicted taken 246system.cpu.fetch.Cycles 80393373 # Number of cycles fetch has run and was not squashing or blocked 247system.cpu.fetch.SquashCycles 27296286 # Number of cycles fetch has spent squashing 248system.cpu.fetch.BlockedCycles 7321256 # Number of cycles fetch has spent blocked 249system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 250system.cpu.fetch.PendingTrapStallCycles 4918 # Number of stall cycles due to pending traps |
| 251system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions | 251system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions |
| 252system.cpu.fetch.IcacheWaitRetryStallCycles 57 # Number of stall cycles due to full MSHR 253system.cpu.fetch.CacheLines 37654254 # Number of cache lines fetched 254system.cpu.fetch.IcacheSquashes 1887415 # Number of outstanding Icache misses that were squashed 255system.cpu.fetch.rateDist::samples 151824267 # Number of instructions fetched each cycle (Total) 256system.cpu.fetch.rateDist::mean 2.799061 # Number of instructions fetched each cycle (Total) 257system.cpu.fetch.rateDist::stdev 3.153208 # Number of instructions fetched each cycle (Total) | 252system.cpu.fetch.IcacheWaitRetryStallCycles 51 # Number of stall cycles due to full MSHR 253system.cpu.fetch.CacheLines 36859860 # Number of cache lines fetched 254system.cpu.fetch.IcacheSquashes 1828379 # Number of outstanding Icache misses that were squashed 255system.cpu.fetch.rateDist::samples 148388373 # Number of instructions fetched each cycle (Total) 256system.cpu.fetch.rateDist::mean 2.800016 # Number of instructions fetched each cycle (Total) 257system.cpu.fetch.rateDist::stdev 3.152801 # Number of instructions fetched each cycle (Total) |
| 258system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 258system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 259system.cpu.fetch.rateDist::0 69765849 45.95% 45.95% # Number of instructions fetched each cycle (Total) 260system.cpu.fetch.rateDist::1 5500538 3.62% 49.57% # Number of instructions fetched each cycle (Total) 261system.cpu.fetch.rateDist::2 10700560 7.05% 56.62% # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::3 10437997 6.88% 63.50% # Number of instructions fetched each cycle (Total) 263system.cpu.fetch.rateDist::4 8786758 5.79% 69.29% # Number of instructions fetched each cycle (Total) 264system.cpu.fetch.rateDist::5 6834684 4.50% 73.79% # Number of instructions fetched each cycle (Total) 265system.cpu.fetch.rateDist::6 6296298 4.15% 77.93% # Number of instructions fetched each cycle (Total) 266system.cpu.fetch.rateDist::7 8361211 5.51% 83.44% # Number of instructions fetched each cycle (Total) 267system.cpu.fetch.rateDist::8 25140372 16.56% 100.00% # Number of instructions fetched each cycle (Total) | 259system.cpu.fetch.rateDist::0 68164460 45.94% 45.94% # Number of instructions fetched each cycle (Total) 260system.cpu.fetch.rateDist::1 5263921 3.55% 49.48% # Number of instructions fetched each cycle (Total) 261system.cpu.fetch.rateDist::2 10532073 7.10% 56.58% # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::3 10289171 6.93% 63.52% # Number of instructions fetched each cycle (Total) 263system.cpu.fetch.rateDist::4 8658719 5.84% 69.35% # Number of instructions fetched each cycle (Total) 264system.cpu.fetch.rateDist::5 6556174 4.42% 73.77% # Number of instructions fetched each cycle (Total) 265system.cpu.fetch.rateDist::6 6250200 4.21% 77.98% # Number of instructions fetched each cycle (Total) 266system.cpu.fetch.rateDist::7 8011886 5.40% 83.38% # Number of instructions fetched each cycle (Total) 267system.cpu.fetch.rateDist::8 24661769 16.62% 100.00% # Number of instructions fetched each cycle (Total) |
| 268system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 269system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 270system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 268system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 269system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 270system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 271system.cpu.fetch.rateDist::total 151824267 # Number of instructions fetched each cycle (Total) 272system.cpu.fetch.branchRate 0.637233 # Number of branch fetches per cycle 273system.cpu.fetch.rate 2.555289 # Number of inst fetches per cycle 274system.cpu.decode.IdleCycles 46639472 # Number of cycles decode is idle 275system.cpu.decode.BlockedCycles 5819765 # Number of cycles decode is blocked 276system.cpu.decode.RunCycles 76543741 # Number of cycles decode is running 277system.cpu.decode.UnblockCycles 1113557 # Number of cycles decode is unblocking 278system.cpu.decode.SquashCycles 21707732 # Number of cycles decode is squashing 279system.cpu.decode.BranchResolved 14816289 # Number of times decode resolved a branch 280system.cpu.decode.BranchMispred 162918 # Number of times decode detected a branch misprediction 281system.cpu.decode.DecodedInsts 401266810 # Number of instructions handled by decode 282system.cpu.decode.SquashedInsts 729123 # Number of squashed instructions handled by decode 283system.cpu.rename.SquashCycles 21707732 # Number of cycles rename is squashing 284system.cpu.rename.IdleCycles 52145776 # Number of cycles rename is idle 285system.cpu.rename.BlockCycles 716376 # Number of cycles rename is blocking 286system.cpu.rename.serializeStallCycles 699385 # count of cycles rename stalled for serializing inst 287system.cpu.rename.RunCycles 72090483 # Number of cycles rename is running 288system.cpu.rename.UnblockCycles 4464515 # Number of cycles rename is unblocking 289system.cpu.rename.RenamedInsts 378976726 # Number of instructions processed by rename 290system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full 291system.cpu.rename.IQFullEvents 316631 # Number of times rename has blocked due to IQ full 292system.cpu.rename.LSQFullEvents 3575950 # Number of times rename has blocked due to LSQ full 293system.cpu.rename.FullRegisterEvents 15 # Number of times there has been no free registers 294system.cpu.rename.RenamedOperands 642441440 # Number of destination operands rename has renamed 295system.cpu.rename.RenameLookups 1614452334 # Number of register rename lookups that rename has made 296system.cpu.rename.int_rename_lookups 1596874036 # Number of integer rename lookups 297system.cpu.rename.fp_rename_lookups 17578298 # Number of floating rename lookups 298system.cpu.rename.CommittedMaps 298092491 # Number of HB maps that are committed 299system.cpu.rename.UndoneMaps 344348949 # Number of HB maps that are undone due to squashing 300system.cpu.rename.serializingInsts 33473 # count of serializing insts renamed 301system.cpu.rename.tempSerializingInsts 33471 # count of temporary serializing insts renamed 302system.cpu.rename.skidInsts 12628265 # count of insts added to the skid buffer 303system.cpu.memDep0.insertedLoads 43987484 # Number of loads inserted to the mem dependence unit. 304system.cpu.memDep0.insertedStores 16888261 # Number of stores inserted to the mem dependence unit. 305system.cpu.memDep0.conflictingLoads 5791013 # Number of conflicting loads. 306system.cpu.memDep0.conflictingStores 3746055 # Number of conflicting stores. 307system.cpu.iq.iqInstsAdded 334831031 # Number of instructions added to the IQ (excludes non-spec) 308system.cpu.iq.iqNonSpecInstsAdded 55567 # Number of non-speculative instructions added to the IQ 309system.cpu.iq.iqInstsIssued 252811108 # Number of instructions issued 310system.cpu.iq.iqSquashedInstsIssued 890392 # Number of squashed instructions issued 311system.cpu.iq.iqSquashedInstsExamined 144974552 # Number of squashed instructions iterated over during squash; mainly for profiling 312system.cpu.iq.iqSquashedOperandsExamined 373956822 # Number of squashed operands that are examined and possibly removed from graph 313system.cpu.iq.iqSquashedNonSpecRemoved 4307 # Number of squashed non-spec instructions that were removed 314system.cpu.iq.issued_per_cycle::samples 151824267 # Number of insts issued each cycle 315system.cpu.iq.issued_per_cycle::mean 1.665156 # Number of insts issued each cycle 316system.cpu.iq.issued_per_cycle::stdev 1.759693 # Number of insts issued each cycle | 271system.cpu.fetch.rateDist::total 148388373 # Number of instructions fetched each cycle (Total) 272system.cpu.fetch.branchRate 0.638588 # Number of branch fetches per cycle 273system.cpu.fetch.rate 2.561344 # Number of inst fetches per cycle 274system.cpu.decode.IdleCycles 45525708 # Number of cycles decode is idle 275system.cpu.decode.BlockedCycles 5988328 # Number of cycles decode is blocked 276system.cpu.decode.RunCycles 74834240 # Number of cycles decode is running 277system.cpu.decode.UnblockCycles 1196373 # Number of cycles decode is unblocking 278system.cpu.decode.SquashCycles 20843724 # Number of cycles decode is squashing 279system.cpu.decode.BranchResolved 14343881 # Number of times decode resolved a branch 280system.cpu.decode.BranchMispred 164426 # Number of times decode detected a branch misprediction 281system.cpu.decode.DecodedInsts 392938907 # Number of instructions handled by decode 282system.cpu.decode.SquashedInsts 736414 # Number of squashed instructions handled by decode 283system.cpu.rename.SquashCycles 20843724 # Number of cycles rename is squashing 284system.cpu.rename.IdleCycles 50922630 # Number of cycles rename is idle 285system.cpu.rename.BlockCycles 727420 # Number of cycles rename is blocking 286system.cpu.rename.serializeStallCycles 699991 # count of cycles rename stalled for serializing inst 287system.cpu.rename.RunCycles 70572280 # Number of cycles rename is running 288system.cpu.rename.UnblockCycles 4622328 # Number of cycles rename is unblocking 289system.cpu.rename.RenamedInsts 371457492 # Number of instructions processed by rename 290system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full 291system.cpu.rename.IQFullEvents 340569 # Number of times rename has blocked due to IQ full 292system.cpu.rename.LSQFullEvents 3661423 # Number of times rename has blocked due to LSQ full 293system.cpu.rename.FullRegisterEvents 29 # Number of times there has been no free registers 294system.cpu.rename.RenamedOperands 631852668 # Number of destination operands rename has renamed 295system.cpu.rename.RenameLookups 1582346867 # Number of register rename lookups that rename has made 296system.cpu.rename.int_rename_lookups 1565037376 # Number of integer rename lookups 297system.cpu.rename.fp_rename_lookups 17309491 # Number of floating rename lookups 298system.cpu.rename.CommittedMaps 298092811 # Number of HB maps that are committed 299system.cpu.rename.UndoneMaps 333759857 # Number of HB maps that are undone due to squashing 300system.cpu.rename.serializingInsts 32532 # count of serializing insts renamed 301system.cpu.rename.tempSerializingInsts 32528 # count of temporary serializing insts renamed 302system.cpu.rename.skidInsts 13064863 # count of insts added to the skid buffer 303system.cpu.memDep0.insertedLoads 43027461 # Number of loads inserted to the mem dependence unit. 304system.cpu.memDep0.insertedStores 16443523 # Number of stores inserted to the mem dependence unit. 305system.cpu.memDep0.conflictingLoads 5668310 # Number of conflicting loads. 306system.cpu.memDep0.conflictingStores 3691413 # Number of conflicting stores. 307system.cpu.iq.iqInstsAdded 329308816 # Number of instructions added to the IQ (excludes non-spec) 308system.cpu.iq.iqNonSpecInstsAdded 54643 # Number of non-speculative instructions added to the IQ 309system.cpu.iq.iqInstsIssued 249531465 # Number of instructions issued 310system.cpu.iq.iqSquashedInstsIssued 795533 # Number of squashed instructions issued 311system.cpu.iq.iqSquashedInstsExamined 139603170 # Number of squashed instructions iterated over during squash; mainly for profiling 312system.cpu.iq.iqSquashedOperandsExamined 362284552 # Number of squashed operands that are examined and possibly removed from graph 313system.cpu.iq.iqSquashedNonSpecRemoved 3343 # Number of squashed non-spec instructions that were removed 314system.cpu.iq.issued_per_cycle::samples 148388373 # Number of insts issued each cycle 315system.cpu.iq.issued_per_cycle::mean 1.681611 # Number of insts issued each cycle 316system.cpu.iq.issued_per_cycle::stdev 1.761108 # Number of insts issued each cycle |
| 317system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 317system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 318system.cpu.iq.issued_per_cycle::0 58367016 38.44% 38.44% # Number of insts issued each cycle 319system.cpu.iq.issued_per_cycle::1 23007793 15.15% 53.60% # Number of insts issued each cycle 320system.cpu.iq.issued_per_cycle::2 25146514 16.56% 70.16% # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::3 20482198 13.49% 83.65% # Number of insts issued each cycle 322system.cpu.iq.issued_per_cycle::4 12879503 8.48% 92.13% # Number of insts issued each cycle 323system.cpu.iq.issued_per_cycle::5 6581643 4.34% 96.47% # Number of insts issued each cycle 324system.cpu.iq.issued_per_cycle::6 4062886 2.68% 99.15% # Number of insts issued each cycle 325system.cpu.iq.issued_per_cycle::7 1113562 0.73% 99.88% # Number of insts issued each cycle 326system.cpu.iq.issued_per_cycle::8 183152 0.12% 100.00% # Number of insts issued each cycle | 318system.cpu.iq.issued_per_cycle::0 56153945 37.84% 37.84% # Number of insts issued each cycle 319system.cpu.iq.issued_per_cycle::1 22688522 15.29% 53.13% # Number of insts issued each cycle 320system.cpu.iq.issued_per_cycle::2 24821947 16.73% 69.86% # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::3 20330759 13.70% 83.56% # Number of insts issued each cycle 322system.cpu.iq.issued_per_cycle::4 12554169 8.46% 92.02% # Number of insts issued each cycle 323system.cpu.iq.issued_per_cycle::5 6514357 4.39% 96.41% # Number of insts issued each cycle 324system.cpu.iq.issued_per_cycle::6 4035019 2.72% 99.13% # Number of insts issued each cycle 325system.cpu.iq.issued_per_cycle::7 1109043 0.75% 99.88% # Number of insts issued each cycle 326system.cpu.iq.issued_per_cycle::8 180612 0.12% 100.00% # Number of insts issued each cycle |
| 327system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 328system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 329system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 327system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 328system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 329system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 330system.cpu.iq.issued_per_cycle::total 151824267 # Number of insts issued each cycle | 330system.cpu.iq.issued_per_cycle::total 148388373 # Number of insts issued each cycle |
| 331system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 331system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 332system.cpu.iq.fu_full::IntAlu 966665 37.55% 37.55% # attempts to use FU when none available 333system.cpu.iq.fu_full::IntMult 5596 0.22% 37.77% # attempts to use FU when none available 334system.cpu.iq.fu_full::IntDiv 0 0.00% 37.77% # attempts to use FU when none available 335system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.77% # attempts to use FU when none available 336system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.77% # attempts to use FU when none available 337system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.77% # attempts to use FU when none available 338system.cpu.iq.fu_full::FloatMult 0 0.00% 37.77% # attempts to use FU when none available 339system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.77% # attempts to use FU when none available 340system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.77% # attempts to use FU when none available 341system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.77% # attempts to use FU when none available 342system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.77% # attempts to use FU when none available 343system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.77% # attempts to use FU when none available 344system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.77% # attempts to use FU when none available 345system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.77% # attempts to use FU when none available 346system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.77% # attempts to use FU when none available 347system.cpu.iq.fu_full::SimdMult 0 0.00% 37.77% # attempts to use FU when none available 348system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.77% # attempts to use FU when none available 349system.cpu.iq.fu_full::SimdShift 0 0.00% 37.77% # attempts to use FU when none available 350system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.77% # attempts to use FU when none available 351system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.77% # attempts to use FU when none available 352system.cpu.iq.fu_full::SimdFloatAdd 94 0.00% 37.77% # attempts to use FU when none available 353system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.77% # attempts to use FU when none available 354system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.77% # attempts to use FU when none available 355system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 37.77% # attempts to use FU when none available 356system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.77% # attempts to use FU when none available 357system.cpu.iq.fu_full::SimdFloatMisc 27 0.00% 37.78% # attempts to use FU when none available 358system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.78% # attempts to use FU when none available 359system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.78% # attempts to use FU when none available 360system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.78% # attempts to use FU when none available 361system.cpu.iq.fu_full::MemRead 1198357 46.55% 84.33% # attempts to use FU when none available 362system.cpu.iq.fu_full::MemWrite 403391 15.67% 100.00% # attempts to use FU when none available | 332system.cpu.iq.fu_full::IntAlu 962652 38.43% 38.43% # attempts to use FU when none available 333system.cpu.iq.fu_full::IntMult 5596 0.22% 38.65% # attempts to use FU when none available 334system.cpu.iq.fu_full::IntDiv 0 0.00% 38.65% # attempts to use FU when none available 335system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.65% # attempts to use FU when none available 336system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.65% # attempts to use FU when none available 337system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.65% # attempts to use FU when none available 338system.cpu.iq.fu_full::FloatMult 0 0.00% 38.65% # attempts to use FU when none available 339system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.65% # attempts to use FU when none available 340system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.65% # attempts to use FU when none available 341system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.65% # attempts to use FU when none available 342system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.65% # attempts to use FU when none available 343system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.65% # attempts to use FU when none available 344system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.65% # attempts to use FU when none available 345system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.65% # attempts to use FU when none available 346system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.65% # attempts to use FU when none available 347system.cpu.iq.fu_full::SimdMult 0 0.00% 38.65% # attempts to use FU when none available 348system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.65% # attempts to use FU when none available 349system.cpu.iq.fu_full::SimdShift 0 0.00% 38.65% # attempts to use FU when none available 350system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.65% # attempts to use FU when none available 351system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.65% # attempts to use FU when none available 352system.cpu.iq.fu_full::SimdFloatAdd 100 0.00% 38.66% # attempts to use FU when none available 353system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.66% # attempts to use FU when none available 354system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.66% # attempts to use FU when none available 355system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.66% # attempts to use FU when none available 356system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.66% # attempts to use FU when none available 357system.cpu.iq.fu_full::SimdFloatMisc 50 0.00% 38.66% # attempts to use FU when none available 358system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.66% # attempts to use FU when none available 359system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.66% # attempts to use FU when none available 360system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.66% # attempts to use FU when none available 361system.cpu.iq.fu_full::MemRead 1162967 46.43% 85.09% # attempts to use FU when none available 362system.cpu.iq.fu_full::MemWrite 373557 14.91% 100.00% # attempts to use FU when none available |
| 363system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 364system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 365system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 363system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 364system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 365system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 366system.cpu.iq.FU_type_0::IntAlu 197328873 78.05% 78.05% # Type of FU issued 367system.cpu.iq.FU_type_0::IntMult 995382 0.39% 78.45% # Type of FU issued 368system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.45% # Type of FU issued 369system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.45% # Type of FU issued 370system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.45% # Type of FU issued 371system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.45% # Type of FU issued 372system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.45% # Type of FU issued 373system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.45% # Type of FU issued 374system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.45% # Type of FU issued 375system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.45% # Type of FU issued 376system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.45% # Type of FU issued 377system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.45% # Type of FU issued 378system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.45% # Type of FU issued 379system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.45% # Type of FU issued 380system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.45% # Type of FU issued 381system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.45% # Type of FU issued 382system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.45% # Type of FU issued 383system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.45% # Type of FU issued 384system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.45% # Type of FU issued 385system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.45% # Type of FU issued 386system.cpu.iq.FU_type_0::SimdFloatAdd 33194 0.01% 78.46% # Type of FU issued 387system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.46% # Type of FU issued 388system.cpu.iq.FU_type_0::SimdFloatCmp 163810 0.06% 78.53% # Type of FU issued 389system.cpu.iq.FU_type_0::SimdFloatCvt 255234 0.10% 78.63% # Type of FU issued 390system.cpu.iq.FU_type_0::SimdFloatDiv 76440 0.03% 78.66% # Type of FU issued 391system.cpu.iq.FU_type_0::SimdFloatMisc 467356 0.18% 78.84% # Type of FU issued 392system.cpu.iq.FU_type_0::SimdFloatMult 206283 0.08% 78.92% # Type of FU issued 393system.cpu.iq.FU_type_0::SimdFloatMultAcc 71857 0.03% 78.95% # Type of FU issued 394system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 78.95% # Type of FU issued 395system.cpu.iq.FU_type_0::MemRead 39021114 15.43% 94.39% # Type of FU issued 396system.cpu.iq.FU_type_0::MemWrite 14191245 5.61% 100.00% # Type of FU issued | 366system.cpu.iq.FU_type_0::IntAlu 194943196 78.12% 78.12% # Type of FU issued 367system.cpu.iq.FU_type_0::IntMult 980225 0.39% 78.52% # Type of FU issued 368system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued 369system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued 370system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued 371system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.52% # Type of FU issued 372system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.52% # Type of FU issued 373system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.52% # Type of FU issued 374system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.52% # Type of FU issued 375system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.52% # Type of FU issued 376system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.52% # Type of FU issued 377system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.52% # Type of FU issued 378system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.52% # Type of FU issued 379system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.52% # Type of FU issued 380system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.52% # Type of FU issued 381system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.52% # Type of FU issued 382system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Type of FU issued 383system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued 384system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued 385system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued 386system.cpu.iq.FU_type_0::SimdFloatAdd 33090 0.01% 78.53% # Type of FU issued 387system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.53% # Type of FU issued 388system.cpu.iq.FU_type_0::SimdFloatCmp 164479 0.07% 78.60% # Type of FU issued 389system.cpu.iq.FU_type_0::SimdFloatCvt 254525 0.10% 78.70% # Type of FU issued 390system.cpu.iq.FU_type_0::SimdFloatDiv 76418 0.03% 78.73% # Type of FU issued 391system.cpu.iq.FU_type_0::SimdFloatMisc 465710 0.19% 78.91% # Type of FU issued 392system.cpu.iq.FU_type_0::SimdFloatMult 206458 0.08% 79.00% # Type of FU issued 393system.cpu.iq.FU_type_0::SimdFloatMultAcc 71854 0.03% 79.03% # Type of FU issued 394system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued 395system.cpu.iq.FU_type_0::MemRead 38372441 15.38% 94.40% # Type of FU issued 396system.cpu.iq.FU_type_0::MemWrite 13962748 5.60% 100.00% # Type of FU issued |
| 397system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 398system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 397system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 398system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 399system.cpu.iq.FU_type_0::total 252811108 # Type of FU issued 400system.cpu.iq.rate 1.664041 # Inst issue rate 401system.cpu.iq.fu_busy_cnt 2574130 # FU busy when requested 402system.cpu.iq.fu_busy_rate 0.010182 # FU busy rate (busy events/executed inst) 403system.cpu.iq.int_inst_queue_reads 657138452 # Number of integer instruction queue reads 404system.cpu.iq.int_inst_queue_writes 477635375 # Number of integer instruction queue writes 405system.cpu.iq.int_inst_queue_wakeup_accesses 240576408 # Number of integer instruction queue wakeup accesses 406system.cpu.iq.fp_inst_queue_reads 3772553 # Number of floating instruction queue reads 407system.cpu.iq.fp_inst_queue_writes 2244745 # Number of floating instruction queue writes 408system.cpu.iq.fp_inst_queue_wakeup_accesses 1851453 # Number of floating instruction queue wakeup accesses 409system.cpu.iq.int_alu_accesses 253490963 # Number of integer alu accesses 410system.cpu.iq.fp_alu_accesses 1894275 # Number of floating point alu accesses 411system.cpu.iew.lsq.thread0.forwLoads 2028433 # Number of loads that had data forwarded from stores | 399system.cpu.iq.FU_type_0::total 249531465 # Type of FU issued 400system.cpu.iq.rate 1.680459 # Inst issue rate 401system.cpu.iq.fu_busy_cnt 2504922 # FU busy when requested 402system.cpu.iq.fu_busy_rate 0.010039 # FU busy rate (busy events/executed inst) 403system.cpu.iq.int_inst_queue_reads 647013011 # Number of integer instruction queue reads 404system.cpu.iq.int_inst_queue_writes 466795184 # Number of integer instruction queue writes 405system.cpu.iq.int_inst_queue_wakeup_accesses 237947786 # Number of integer instruction queue wakeup accesses 406system.cpu.iq.fp_inst_queue_reads 3738747 # Number of floating instruction queue reads 407system.cpu.iq.fp_inst_queue_writes 2189794 # Number of floating instruction queue writes 408system.cpu.iq.fp_inst_queue_wakeup_accesses 1841578 # Number of floating instruction queue wakeup accesses 409system.cpu.iq.int_alu_accesses 250160112 # Number of integer alu accesses 410system.cpu.iq.fp_alu_accesses 1876275 # Number of floating point alu accesses 411system.cpu.iew.lsq.thread0.forwLoads 2013222 # Number of loads that had data forwarded from stores |
| 412system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 412system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 413system.cpu.iew.lsq.thread0.squashedLoads 14131956 # Number of loads squashed 414system.cpu.iew.lsq.thread0.ignoredResponses 16953 # Number of memory responses ignored because the instruction is squashed 415system.cpu.iew.lsq.thread0.memOrderViolation 19730 # Number of memory ordering violations 416system.cpu.iew.lsq.thread0.squashedStores 4237583 # Number of stores squashed | 413system.cpu.iew.lsq.thread0.squashedLoads 13171893 # Number of loads squashed 414system.cpu.iew.lsq.thread0.ignoredResponses 11381 # Number of memory responses ignored because the instruction is squashed 415system.cpu.iew.lsq.thread0.memOrderViolation 18785 # Number of memory ordering violations 416system.cpu.iew.lsq.thread0.squashedStores 3792805 # Number of stores squashed |
| 417system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 418system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 417system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 418system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 419system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled 420system.cpu.iew.lsq.thread0.cacheBlocked 84 # Number of times an access to memory failed due to the cache being blocked | 419system.cpu.iew.lsq.thread0.rescheduledLoads 14 # Number of loads that were rescheduled 420system.cpu.iew.lsq.thread0.cacheBlocked 96 # Number of times an access to memory failed due to the cache being blocked |
| 421system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 421system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 422system.cpu.iew.iewSquashCycles 21707732 # Number of cycles IEW is squashing 423system.cpu.iew.iewBlockCycles 16237 # Number of cycles IEW is blocking 424system.cpu.iew.iewUnblockCycles 835 # Number of cycles IEW is unblocking 425system.cpu.iew.iewDispatchedInsts 334904365 # Number of instructions dispatched to IQ 426system.cpu.iew.iewDispSquashedInsts 834808 # Number of squashed instructions skipped by dispatch 427system.cpu.iew.iewDispLoadInsts 43987484 # Number of dispatched load instructions 428system.cpu.iew.iewDispStoreInsts 16888261 # Number of dispatched store instructions 429system.cpu.iew.iewDispNonSpecInsts 33011 # Number of dispatched non-speculative instructions 430system.cpu.iew.iewIQFullEvents 182 # Number of times the IQ has become full, causing a stall 431system.cpu.iew.iewLSQFullEvents 269 # Number of times the LSQ has become full, causing a stall 432system.cpu.iew.memOrderViolationEvents 19730 # Number of memory order violations 433system.cpu.iew.predictedTakenIncorrect 4101344 # Number of branches that were predicted taken incorrectly 434system.cpu.iew.predictedNotTakenIncorrect 3925912 # Number of branches that were predicted not taken incorrectly 435system.cpu.iew.branchMispredicts 8027256 # Number of branch mispredicts detected at execute 436system.cpu.iew.iewExecutedInsts 245818022 # Number of executed instructions 437system.cpu.iew.iewExecLoadInsts 37400003 # Number of load instructions executed 438system.cpu.iew.iewExecSquashedInsts 6993086 # Number of squashed instructions skipped in execute | 422system.cpu.iew.iewSquashCycles 20843724 # Number of cycles IEW is squashing 423system.cpu.iew.iewBlockCycles 17321 # Number of cycles IEW is blocking 424system.cpu.iew.iewUnblockCycles 891 # Number of cycles IEW is unblocking 425system.cpu.iew.iewDispatchedInsts 329380427 # Number of instructions dispatched to IQ 426system.cpu.iew.iewDispSquashedInsts 786985 # Number of squashed instructions skipped by dispatch 427system.cpu.iew.iewDispLoadInsts 43027461 # Number of dispatched load instructions 428system.cpu.iew.iewDispStoreInsts 16443523 # Number of dispatched store instructions 429system.cpu.iew.iewDispNonSpecInsts 32104 # Number of dispatched non-speculative instructions 430system.cpu.iew.iewIQFullEvents 209 # Number of times the IQ has become full, causing a stall 431system.cpu.iew.iewLSQFullEvents 288 # Number of times the LSQ has become full, causing a stall 432system.cpu.iew.memOrderViolationEvents 18785 # Number of memory order violations 433system.cpu.iew.predictedTakenIncorrect 3890771 # Number of branches that were predicted taken incorrectly 434system.cpu.iew.predictedNotTakenIncorrect 3762289 # Number of branches that were predicted not taken incorrectly 435system.cpu.iew.branchMispredicts 7653060 # Number of branch mispredicts detected at execute 436system.cpu.iew.iewExecutedInsts 243027736 # Number of executed instructions 437system.cpu.iew.iewExecLoadInsts 36864796 # Number of load instructions executed 438system.cpu.iew.iewExecSquashedInsts 6503729 # Number of squashed instructions skipped in execute |
| 439system.cpu.iew.exec_swp 0 # number of swp insts executed | 439system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 440system.cpu.iew.exec_nop 17767 # number of nop insts executed 441system.cpu.iew.exec_refs 51208402 # number of memory reference insts executed 442system.cpu.iew.exec_branches 54033495 # Number of branches executed 443system.cpu.iew.exec_stores 13808399 # Number of stores executed 444system.cpu.iew.exec_rate 1.618012 # Inst execution rate 445system.cpu.iew.wb_sent 243559168 # cumulative count of insts sent to commit 446system.cpu.iew.wb_count 242427861 # cumulative count of insts written-back 447system.cpu.iew.wb_producers 150062323 # num instructions producing a value 448system.cpu.iew.wb_consumers 269174598 # num instructions consuming a value | 440system.cpu.iew.exec_nop 16968 # number of nop insts executed 441system.cpu.iew.exec_refs 50523279 # number of memory reference insts executed 442system.cpu.iew.exec_branches 53444477 # Number of branches executed 443system.cpu.iew.exec_stores 13658483 # Number of stores executed 444system.cpu.iew.exec_rate 1.636660 # Inst execution rate 445system.cpu.iew.wb_sent 240848315 # cumulative count of insts sent to commit 446system.cpu.iew.wb_count 239789364 # cumulative count of insts written-back 447system.cpu.iew.wb_producers 148488630 # num instructions producing a value 448system.cpu.iew.wb_consumers 267300896 # num instructions consuming a value |
| 449system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 449system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 450system.cpu.iew.wb_rate 1.595697 # insts written-back per cycle 451system.cpu.iew.wb_fanout 0.557491 # average fanout of values written-back | 450system.cpu.iew.wb_rate 1.614851 # insts written-back per cycle 451system.cpu.iew.wb_fanout 0.555511 # average fanout of values written-back |
| 452system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 452system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 453system.cpu.commit.commitSquashedInsts 146203238 # The number of squashed insts skipped by commit 454system.cpu.commit.commitNonSpecStalls 51260 # The number of times commit has been forced to stall to communicate backwards 455system.cpu.commit.branchMispredicts 6400494 # The number of times a branch was mispredicted 456system.cpu.commit.committed_per_cycle::samples 130116536 # Number of insts commited each cycle 457system.cpu.commit.committed_per_cycle::mean 1.450247 # Number of insts commited each cycle 458system.cpu.commit.committed_per_cycle::stdev 2.162155 # Number of insts commited each cycle | 453system.cpu.commit.commitSquashedInsts 140679091 # The number of squashed insts skipped by commit 454system.cpu.commit.commitNonSpecStalls 51300 # The number of times commit has been forced to stall to communicate backwards 455system.cpu.commit.branchMispredicts 6130085 # The number of times a branch was mispredicted 456system.cpu.commit.committed_per_cycle::samples 127544650 # Number of insts commited each cycle 457system.cpu.commit.committed_per_cycle::mean 1.479492 # Number of insts commited each cycle 458system.cpu.commit.committed_per_cycle::stdev 2.184685 # Number of insts commited each cycle |
| 459system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 459system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 460system.cpu.commit.committed_per_cycle::0 59888298 46.03% 46.03% # Number of insts commited each cycle 461system.cpu.commit.committed_per_cycle::1 32076129 24.65% 70.68% # Number of insts commited each cycle 462system.cpu.commit.committed_per_cycle::2 13982572 10.75% 81.42% # Number of insts commited each cycle 463system.cpu.commit.committed_per_cycle::3 7654340 5.88% 87.31% # Number of insts commited each cycle 464system.cpu.commit.committed_per_cycle::4 4412681 3.39% 90.70% # Number of insts commited each cycle 465system.cpu.commit.committed_per_cycle::5 1335897 1.03% 91.73% # Number of insts commited each cycle 466system.cpu.commit.committed_per_cycle::6 1741211 1.34% 93.06% # Number of insts commited each cycle 467system.cpu.commit.committed_per_cycle::7 1283921 0.99% 94.05% # Number of insts commited each cycle 468system.cpu.commit.committed_per_cycle::8 7741487 5.95% 100.00% # Number of insts commited each cycle | 460system.cpu.commit.committed_per_cycle::0 57798190 45.32% 45.32% # Number of insts commited each cycle 461system.cpu.commit.committed_per_cycle::1 31737959 24.88% 70.20% # Number of insts commited each cycle 462system.cpu.commit.committed_per_cycle::2 13785979 10.81% 81.01% # Number of insts commited each cycle 463system.cpu.commit.committed_per_cycle::3 7635406 5.99% 87.00% # Number of insts commited each cycle 464system.cpu.commit.committed_per_cycle::4 4383857 3.44% 90.43% # Number of insts commited each cycle 465system.cpu.commit.committed_per_cycle::5 1319533 1.03% 91.47% # Number of insts commited each cycle 466system.cpu.commit.committed_per_cycle::6 1705049 1.34% 92.80% # Number of insts commited each cycle 467system.cpu.commit.committed_per_cycle::7 1307627 1.03% 93.83% # Number of insts commited each cycle 468system.cpu.commit.committed_per_cycle::8 7871050 6.17% 100.00% # Number of insts commited each cycle |
| 469system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 470system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 471system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 469system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 470system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 471system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 472system.cpu.commit.committed_per_cycle::total 130116536 # Number of insts commited each cycle 473system.cpu.commit.committedInsts 172347629 # Number of instructions committed 474system.cpu.commit.committedOps 188701111 # Number of ops (including micro ops) committed | 472system.cpu.commit.committed_per_cycle::total 127544650 # Number of insts commited each cycle 473system.cpu.commit.committedInsts 172347829 # Number of instructions committed 474system.cpu.commit.committedOps 188701311 # Number of ops (including micro ops) committed |
| 475system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 475system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 476system.cpu.commit.refs 42506206 # Number of memory references committed 477system.cpu.commit.loads 29855528 # Number of loads committed | 476system.cpu.commit.refs 42506286 # Number of memory references committed 477system.cpu.commit.loads 29855568 # Number of loads committed |
| 478system.cpu.commit.membars 22408 # Number of memory barriers committed | 478system.cpu.commit.membars 22408 # Number of memory barriers committed |
| 479system.cpu.commit.branches 40306355 # Number of branches committed | 479system.cpu.commit.branches 40306395 # Number of branches committed |
| 480system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. | 480system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. |
| 481system.cpu.commit.int_insts 150130393 # Number of committed integer instructions. | 481system.cpu.commit.int_insts 150130553 # Number of committed integer instructions. |
| 482system.cpu.commit.function_calls 1848934 # Number of function calls committed. | 482system.cpu.commit.function_calls 1848934 # Number of function calls committed. |
| 483system.cpu.commit.bw_lim_events 7741487 # number cycles where commit BW limit reached | 483system.cpu.commit.bw_lim_events 7871050 # number cycles where commit BW limit reached |
| 484system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 484system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 485system.cpu.rob.rob_reads 457274197 # The number of ROB reads 486system.cpu.rob.rob_writes 691635591 # The number of ROB writes 487system.cpu.timesIdled 2582 # Number of times that the entire CPU went into an idle state and unscheduled itself 488system.cpu.idleCycles 101726 # Total number of cycles that the CPU has spent unscheduled due to idling 489system.cpu.committedInsts 172333241 # Number of Instructions Simulated 490system.cpu.committedOps 188686723 # Number of Ops (including micro ops) Simulated 491system.cpu.committedInsts_total 172333241 # Number of Instructions Simulated 492system.cpu.cpi 0.881583 # CPI: Cycles Per Instruction 493system.cpu.cpi_total 0.881583 # CPI: Total CPI of All Threads 494system.cpu.ipc 1.134324 # IPC: Instructions Per Cycle 495system.cpu.ipc_total 1.134324 # IPC: Total IPC of All Threads 496system.cpu.int_regfile_reads 1091906245 # number of integer regfile reads 497system.cpu.int_regfile_writes 388600616 # number of integer regfile writes 498system.cpu.fp_regfile_reads 2911397 # number of floating regfile reads 499system.cpu.fp_regfile_writes 2511024 # number of floating regfile writes 500system.cpu.misc_regfile_reads 474438629 # number of misc regfile reads 501system.cpu.misc_regfile_writes 832124 # number of misc regfile writes 502system.cpu.icache.replacements 2644 # number of replacements 503system.cpu.icache.tagsinuse 1367.286315 # Cycle average of tags in use 504system.cpu.icache.total_refs 37648759 # Total number of references to valid blocks. 505system.cpu.icache.sampled_refs 4386 # Sample count of references to valid blocks. 506system.cpu.icache.avg_refs 8583.848381 # Average number of references to valid blocks. | 485system.cpu.rob.rob_reads 449048801 # The number of ROB reads 486system.cpu.rob.rob_writes 679713725 # The number of ROB writes 487system.cpu.timesIdled 2572 # Number of times that the entire CPU went into an idle state and unscheduled itself 488system.cpu.idleCycles 101692 # Total number of cycles that the CPU has spent unscheduled due to idling 489system.cpu.committedInsts 172333441 # Number of Instructions Simulated 490system.cpu.committedOps 188686923 # Number of Ops (including micro ops) Simulated 491system.cpu.committedInsts_total 172333441 # Number of Instructions Simulated 492system.cpu.cpi 0.861644 # CPI: Cycles Per Instruction 493system.cpu.cpi_total 0.861644 # CPI: Total CPI of All Threads 494system.cpu.ipc 1.160572 # IPC: Instructions Per Cycle 495system.cpu.ipc_total 1.160572 # IPC: Total IPC of All Threads 496system.cpu.int_regfile_reads 1079711901 # number of integer regfile reads 497system.cpu.int_regfile_writes 384939818 # number of integer regfile writes 498system.cpu.fp_regfile_reads 2913621 # number of floating regfile reads 499system.cpu.fp_regfile_writes 2497505 # number of floating regfile writes 500system.cpu.misc_regfile_reads 464692735 # number of misc regfile reads 501system.cpu.misc_regfile_writes 832204 # number of misc regfile writes 502system.cpu.icache.replacements 2508 # number of replacements 503system.cpu.icache.tagsinuse 1347.136586 # Cycle average of tags in use 504system.cpu.icache.total_refs 36854521 # Total number of references to valid blocks. 505system.cpu.icache.sampled_refs 4234 # Sample count of references to valid blocks. 506system.cpu.icache.avg_refs 8704.421587 # Average number of references to valid blocks. |
| 507system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 507system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 508system.cpu.icache.occ_blocks::cpu.inst 1367.286315 # Average occupied blocks per requestor 509system.cpu.icache.occ_percent::cpu.inst 0.667620 # Average percentage of cache occupancy 510system.cpu.icache.occ_percent::total 0.667620 # Average percentage of cache occupancy 511system.cpu.icache.ReadReq_hits::cpu.inst 37648759 # number of ReadReq hits 512system.cpu.icache.ReadReq_hits::total 37648759 # number of ReadReq hits 513system.cpu.icache.demand_hits::cpu.inst 37648759 # number of demand (read+write) hits 514system.cpu.icache.demand_hits::total 37648759 # number of demand (read+write) hits 515system.cpu.icache.overall_hits::cpu.inst 37648759 # number of overall hits 516system.cpu.icache.overall_hits::total 37648759 # number of overall hits 517system.cpu.icache.ReadReq_misses::cpu.inst 5495 # number of ReadReq misses 518system.cpu.icache.ReadReq_misses::total 5495 # number of ReadReq misses 519system.cpu.icache.demand_misses::cpu.inst 5495 # number of demand (read+write) misses 520system.cpu.icache.demand_misses::total 5495 # number of demand (read+write) misses 521system.cpu.icache.overall_misses::cpu.inst 5495 # number of overall misses 522system.cpu.icache.overall_misses::total 5495 # number of overall misses 523system.cpu.icache.ReadReq_miss_latency::cpu.inst 164010000 # number of ReadReq miss cycles 524system.cpu.icache.ReadReq_miss_latency::total 164010000 # number of ReadReq miss cycles 525system.cpu.icache.demand_miss_latency::cpu.inst 164010000 # number of demand (read+write) miss cycles 526system.cpu.icache.demand_miss_latency::total 164010000 # number of demand (read+write) miss cycles 527system.cpu.icache.overall_miss_latency::cpu.inst 164010000 # number of overall miss cycles 528system.cpu.icache.overall_miss_latency::total 164010000 # number of overall miss cycles 529system.cpu.icache.ReadReq_accesses::cpu.inst 37654254 # number of ReadReq accesses(hits+misses) 530system.cpu.icache.ReadReq_accesses::total 37654254 # number of ReadReq accesses(hits+misses) 531system.cpu.icache.demand_accesses::cpu.inst 37654254 # number of demand (read+write) accesses 532system.cpu.icache.demand_accesses::total 37654254 # number of demand (read+write) accesses 533system.cpu.icache.overall_accesses::cpu.inst 37654254 # number of overall (read+write) accesses 534system.cpu.icache.overall_accesses::total 37654254 # number of overall (read+write) accesses 535system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000146 # miss rate for ReadReq accesses 536system.cpu.icache.ReadReq_miss_rate::total 0.000146 # miss rate for ReadReq accesses 537system.cpu.icache.demand_miss_rate::cpu.inst 0.000146 # miss rate for demand accesses 538system.cpu.icache.demand_miss_rate::total 0.000146 # miss rate for demand accesses 539system.cpu.icache.overall_miss_rate::cpu.inst 0.000146 # miss rate for overall accesses 540system.cpu.icache.overall_miss_rate::total 0.000146 # miss rate for overall accesses 541system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29847.133758 # average ReadReq miss latency 542system.cpu.icache.ReadReq_avg_miss_latency::total 29847.133758 # average ReadReq miss latency 543system.cpu.icache.demand_avg_miss_latency::cpu.inst 29847.133758 # average overall miss latency 544system.cpu.icache.demand_avg_miss_latency::total 29847.133758 # average overall miss latency 545system.cpu.icache.overall_avg_miss_latency::cpu.inst 29847.133758 # average overall miss latency 546system.cpu.icache.overall_avg_miss_latency::total 29847.133758 # average overall miss latency 547system.cpu.icache.blocked_cycles::no_mshrs 669 # number of cycles access was blocked | 508system.cpu.icache.occ_blocks::cpu.inst 1347.136586 # Average occupied blocks per requestor 509system.cpu.icache.occ_percent::cpu.inst 0.657782 # Average percentage of cache occupancy 510system.cpu.icache.occ_percent::total 0.657782 # Average percentage of cache occupancy 511system.cpu.icache.ReadReq_hits::cpu.inst 36854521 # number of ReadReq hits 512system.cpu.icache.ReadReq_hits::total 36854521 # number of ReadReq hits 513system.cpu.icache.demand_hits::cpu.inst 36854521 # number of demand (read+write) hits 514system.cpu.icache.demand_hits::total 36854521 # number of demand (read+write) hits 515system.cpu.icache.overall_hits::cpu.inst 36854521 # number of overall hits 516system.cpu.icache.overall_hits::total 36854521 # number of overall hits 517system.cpu.icache.ReadReq_misses::cpu.inst 5339 # number of ReadReq misses 518system.cpu.icache.ReadReq_misses::total 5339 # number of ReadReq misses 519system.cpu.icache.demand_misses::cpu.inst 5339 # number of demand (read+write) misses 520system.cpu.icache.demand_misses::total 5339 # number of demand (read+write) misses 521system.cpu.icache.overall_misses::cpu.inst 5339 # number of overall misses 522system.cpu.icache.overall_misses::total 5339 # number of overall misses 523system.cpu.icache.ReadReq_miss_latency::cpu.inst 158626499 # number of ReadReq miss cycles 524system.cpu.icache.ReadReq_miss_latency::total 158626499 # number of ReadReq miss cycles 525system.cpu.icache.demand_miss_latency::cpu.inst 158626499 # number of demand (read+write) miss cycles 526system.cpu.icache.demand_miss_latency::total 158626499 # number of demand (read+write) miss cycles 527system.cpu.icache.overall_miss_latency::cpu.inst 158626499 # number of overall miss cycles 528system.cpu.icache.overall_miss_latency::total 158626499 # number of overall miss cycles 529system.cpu.icache.ReadReq_accesses::cpu.inst 36859860 # number of ReadReq accesses(hits+misses) 530system.cpu.icache.ReadReq_accesses::total 36859860 # number of ReadReq accesses(hits+misses) 531system.cpu.icache.demand_accesses::cpu.inst 36859860 # number of demand (read+write) accesses 532system.cpu.icache.demand_accesses::total 36859860 # number of demand (read+write) accesses 533system.cpu.icache.overall_accesses::cpu.inst 36859860 # number of overall (read+write) accesses 534system.cpu.icache.overall_accesses::total 36859860 # number of overall (read+write) accesses 535system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000145 # miss rate for ReadReq accesses 536system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses 537system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses 538system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses 539system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses 540system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses 541system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29710.900730 # average ReadReq miss latency 542system.cpu.icache.ReadReq_avg_miss_latency::total 29710.900730 # average ReadReq miss latency 543system.cpu.icache.demand_avg_miss_latency::cpu.inst 29710.900730 # average overall miss latency 544system.cpu.icache.demand_avg_miss_latency::total 29710.900730 # average overall miss latency 545system.cpu.icache.overall_avg_miss_latency::cpu.inst 29710.900730 # average overall miss latency 546system.cpu.icache.overall_avg_miss_latency::total 29710.900730 # average overall miss latency 547system.cpu.icache.blocked_cycles::no_mshrs 604 # number of cycles access was blocked |
| 548system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 548system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 549system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked | 549system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked |
| 550system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 550system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 551system.cpu.icache.avg_blocked_cycles::no_mshrs 37.166667 # average number of cycles each access was blocked | 551system.cpu.icache.avg_blocked_cycles::no_mshrs 35.529412 # average number of cycles each access was blocked |
| 552system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 553system.cpu.icache.fast_writes 0 # number of fast writes performed 554system.cpu.icache.cache_copies 0 # number of cache copies performed | 552system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 553system.cpu.icache.fast_writes 0 # number of fast writes performed 554system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 555system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1106 # number of ReadReq MSHR hits 556system.cpu.icache.ReadReq_mshr_hits::total 1106 # number of ReadReq MSHR hits 557system.cpu.icache.demand_mshr_hits::cpu.inst 1106 # number of demand (read+write) MSHR hits 558system.cpu.icache.demand_mshr_hits::total 1106 # number of demand (read+write) MSHR hits 559system.cpu.icache.overall_mshr_hits::cpu.inst 1106 # number of overall MSHR hits 560system.cpu.icache.overall_mshr_hits::total 1106 # number of overall MSHR hits 561system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4389 # number of ReadReq MSHR misses 562system.cpu.icache.ReadReq_mshr_misses::total 4389 # number of ReadReq MSHR misses 563system.cpu.icache.demand_mshr_misses::cpu.inst 4389 # number of demand (read+write) MSHR misses 564system.cpu.icache.demand_mshr_misses::total 4389 # number of demand (read+write) MSHR misses 565system.cpu.icache.overall_mshr_misses::cpu.inst 4389 # number of overall MSHR misses 566system.cpu.icache.overall_mshr_misses::total 4389 # number of overall MSHR misses 567system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 126227500 # number of ReadReq MSHR miss cycles 568system.cpu.icache.ReadReq_mshr_miss_latency::total 126227500 # number of ReadReq MSHR miss cycles 569system.cpu.icache.demand_mshr_miss_latency::cpu.inst 126227500 # number of demand (read+write) MSHR miss cycles 570system.cpu.icache.demand_mshr_miss_latency::total 126227500 # number of demand (read+write) MSHR miss cycles 571system.cpu.icache.overall_mshr_miss_latency::cpu.inst 126227500 # number of overall MSHR miss cycles 572system.cpu.icache.overall_mshr_miss_latency::total 126227500 # number of overall MSHR miss cycles 573system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for ReadReq accesses 574system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000117 # mshr miss rate for ReadReq accesses 575system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for demand accesses 576system.cpu.icache.demand_mshr_miss_rate::total 0.000117 # mshr miss rate for demand accesses 577system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for overall accesses 578system.cpu.icache.overall_mshr_miss_rate::total 0.000117 # mshr miss rate for overall accesses 579system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28759.968102 # average ReadReq mshr miss latency 580system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28759.968102 # average ReadReq mshr miss latency 581system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28759.968102 # average overall mshr miss latency 582system.cpu.icache.demand_avg_mshr_miss_latency::total 28759.968102 # average overall mshr miss latency 583system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28759.968102 # average overall mshr miss latency 584system.cpu.icache.overall_avg_mshr_miss_latency::total 28759.968102 # average overall mshr miss latency | 555system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1102 # number of ReadReq MSHR hits 556system.cpu.icache.ReadReq_mshr_hits::total 1102 # number of ReadReq MSHR hits 557system.cpu.icache.demand_mshr_hits::cpu.inst 1102 # number of demand (read+write) MSHR hits 558system.cpu.icache.demand_mshr_hits::total 1102 # number of demand (read+write) MSHR hits 559system.cpu.icache.overall_mshr_hits::cpu.inst 1102 # number of overall MSHR hits 560system.cpu.icache.overall_mshr_hits::total 1102 # number of overall MSHR hits 561system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4237 # number of ReadReq MSHR misses 562system.cpu.icache.ReadReq_mshr_misses::total 4237 # number of ReadReq MSHR misses 563system.cpu.icache.demand_mshr_misses::cpu.inst 4237 # number of demand (read+write) MSHR misses 564system.cpu.icache.demand_mshr_misses::total 4237 # number of demand (read+write) MSHR misses 565system.cpu.icache.overall_mshr_misses::cpu.inst 4237 # number of overall MSHR misses 566system.cpu.icache.overall_mshr_misses::total 4237 # number of overall MSHR misses 567system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122742499 # number of ReadReq MSHR miss cycles 568system.cpu.icache.ReadReq_mshr_miss_latency::total 122742499 # number of ReadReq MSHR miss cycles 569system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122742499 # number of demand (read+write) MSHR miss cycles 570system.cpu.icache.demand_mshr_miss_latency::total 122742499 # number of demand (read+write) MSHR miss cycles 571system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122742499 # number of overall MSHR miss cycles 572system.cpu.icache.overall_mshr_miss_latency::total 122742499 # number of overall MSHR miss cycles 573system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000115 # mshr miss rate for ReadReq accesses 574system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000115 # mshr miss rate for ReadReq accesses 575system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000115 # mshr miss rate for demand accesses 576system.cpu.icache.demand_mshr_miss_rate::total 0.000115 # mshr miss rate for demand accesses 577system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000115 # mshr miss rate for overall accesses 578system.cpu.icache.overall_mshr_miss_rate::total 0.000115 # mshr miss rate for overall accesses 579system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28969.199670 # average ReadReq mshr miss latency 580system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28969.199670 # average ReadReq mshr miss latency 581system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28969.199670 # average overall mshr miss latency 582system.cpu.icache.demand_avg_mshr_miss_latency::total 28969.199670 # average overall mshr miss latency 583system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28969.199670 # average overall mshr miss latency 584system.cpu.icache.overall_avg_mshr_miss_latency::total 28969.199670 # average overall mshr miss latency |
| 585system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 585system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 586system.cpu.l2cache.replacements 0 # number of replacements 587system.cpu.l2cache.tagsinuse 1961.084973 # Cycle average of tags in use 588system.cpu.l2cache.total_refs 2275 # Total number of references to valid blocks. 589system.cpu.l2cache.sampled_refs 2727 # Sample count of references to valid blocks. 590system.cpu.l2cache.avg_refs 0.834250 # Average number of references to valid blocks. 591system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 592system.cpu.l2cache.occ_blocks::writebacks 4.022996 # Average occupied blocks per requestor 593system.cpu.l2cache.occ_blocks::cpu.inst 1424.044648 # Average occupied blocks per requestor 594system.cpu.l2cache.occ_blocks::cpu.data 533.017329 # Average occupied blocks per requestor 595system.cpu.l2cache.occ_percent::writebacks 0.000123 # Average percentage of cache occupancy 596system.cpu.l2cache.occ_percent::cpu.inst 0.043458 # Average percentage of cache occupancy 597system.cpu.l2cache.occ_percent::cpu.data 0.016266 # Average percentage of cache occupancy 598system.cpu.l2cache.occ_percent::total 0.059848 # Average percentage of cache occupancy 599system.cpu.l2cache.ReadReq_hits::cpu.inst 2184 # number of ReadReq hits 600system.cpu.l2cache.ReadReq_hits::cpu.data 90 # number of ReadReq hits 601system.cpu.l2cache.ReadReq_hits::total 2274 # number of ReadReq hits 602system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits 603system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits 604system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits 605system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits 606system.cpu.l2cache.demand_hits::cpu.inst 2184 # number of demand (read+write) hits 607system.cpu.l2cache.demand_hits::cpu.data 98 # number of demand (read+write) hits 608system.cpu.l2cache.demand_hits::total 2282 # number of demand (read+write) hits 609system.cpu.l2cache.overall_hits::cpu.inst 2184 # number of overall hits 610system.cpu.l2cache.overall_hits::cpu.data 98 # number of overall hits 611system.cpu.l2cache.overall_hits::total 2282 # number of overall hits 612system.cpu.l2cache.ReadReq_misses::cpu.inst 2051 # number of ReadReq misses 613system.cpu.l2cache.ReadReq_misses::cpu.data 681 # number of ReadReq misses 614system.cpu.l2cache.ReadReq_misses::total 2732 # number of ReadReq misses 615system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses 616system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses 617system.cpu.l2cache.ReadExReq_misses::cpu.data 1075 # number of ReadExReq misses 618system.cpu.l2cache.ReadExReq_misses::total 1075 # number of ReadExReq misses 619system.cpu.l2cache.demand_misses::cpu.inst 2051 # number of demand (read+write) misses 620system.cpu.l2cache.demand_misses::cpu.data 1756 # number of demand (read+write) misses 621system.cpu.l2cache.demand_misses::total 3807 # number of demand (read+write) misses 622system.cpu.l2cache.overall_misses::cpu.inst 2051 # number of overall misses 623system.cpu.l2cache.overall_misses::cpu.data 1756 # number of overall misses 624system.cpu.l2cache.overall_misses::total 3807 # number of overall misses 625system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 96653500 # number of ReadReq miss cycles 626system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35087500 # number of ReadReq miss cycles 627system.cpu.l2cache.ReadReq_miss_latency::total 131741000 # number of ReadReq miss cycles 628system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46197000 # number of ReadExReq miss cycles 629system.cpu.l2cache.ReadExReq_miss_latency::total 46197000 # number of ReadExReq miss cycles 630system.cpu.l2cache.demand_miss_latency::cpu.inst 96653500 # number of demand (read+write) miss cycles 631system.cpu.l2cache.demand_miss_latency::cpu.data 81284500 # number of demand (read+write) miss cycles 632system.cpu.l2cache.demand_miss_latency::total 177938000 # number of demand (read+write) miss cycles 633system.cpu.l2cache.overall_miss_latency::cpu.inst 96653500 # number of overall miss cycles 634system.cpu.l2cache.overall_miss_latency::cpu.data 81284500 # number of overall miss cycles 635system.cpu.l2cache.overall_miss_latency::total 177938000 # number of overall miss cycles 636system.cpu.l2cache.ReadReq_accesses::cpu.inst 4235 # number of ReadReq accesses(hits+misses) 637system.cpu.l2cache.ReadReq_accesses::cpu.data 771 # number of ReadReq accesses(hits+misses) 638system.cpu.l2cache.ReadReq_accesses::total 5006 # number of ReadReq accesses(hits+misses) 639system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) 640system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) 641system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) 642system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) 643system.cpu.l2cache.ReadExReq_accesses::cpu.data 1083 # number of ReadExReq accesses(hits+misses) 644system.cpu.l2cache.ReadExReq_accesses::total 1083 # number of ReadExReq accesses(hits+misses) 645system.cpu.l2cache.demand_accesses::cpu.inst 4235 # number of demand (read+write) accesses 646system.cpu.l2cache.demand_accesses::cpu.data 1854 # number of demand (read+write) accesses 647system.cpu.l2cache.demand_accesses::total 6089 # number of demand (read+write) accesses 648system.cpu.l2cache.overall_accesses::cpu.inst 4235 # number of overall (read+write) accesses 649system.cpu.l2cache.overall_accesses::cpu.data 1854 # number of overall (read+write) accesses 650system.cpu.l2cache.overall_accesses::total 6089 # number of overall (read+write) accesses 651system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.484298 # miss rate for ReadReq accesses 652system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.883268 # miss rate for ReadReq accesses 653system.cpu.l2cache.ReadReq_miss_rate::total 0.545745 # miss rate for ReadReq accesses 654system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 655system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 656system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992613 # miss rate for ReadExReq accesses 657system.cpu.l2cache.ReadExReq_miss_rate::total 0.992613 # miss rate for ReadExReq accesses 658system.cpu.l2cache.demand_miss_rate::cpu.inst 0.484298 # miss rate for demand accesses 659system.cpu.l2cache.demand_miss_rate::cpu.data 0.947141 # miss rate for demand accesses 660system.cpu.l2cache.demand_miss_rate::total 0.625226 # miss rate for demand accesses 661system.cpu.l2cache.overall_miss_rate::cpu.inst 0.484298 # miss rate for overall accesses 662system.cpu.l2cache.overall_miss_rate::cpu.data 0.947141 # miss rate for overall accesses 663system.cpu.l2cache.overall_miss_rate::total 0.625226 # miss rate for overall accesses 664system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47125.060946 # average ReadReq miss latency 665system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 51523.494860 # average ReadReq miss latency 666system.cpu.l2cache.ReadReq_avg_miss_latency::total 48221.449488 # average ReadReq miss latency 667system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42973.953488 # average ReadExReq miss latency 668system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42973.953488 # average ReadExReq miss latency 669system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47125.060946 # average overall miss latency 670system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46289.578588 # average overall miss latency 671system.cpu.l2cache.demand_avg_miss_latency::total 46739.690045 # average overall miss latency 672system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47125.060946 # average overall miss latency 673system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46289.578588 # average overall miss latency 674system.cpu.l2cache.overall_avg_miss_latency::total 46739.690045 # average overall miss latency 675system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 676system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 677system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 678system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 679system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 680system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 681system.cpu.l2cache.fast_writes 0 # number of fast writes performed 682system.cpu.l2cache.cache_copies 0 # number of cache copies performed 683system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits 684system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 11 # number of ReadReq MSHR hits 685system.cpu.l2cache.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits 686system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits 687system.cpu.l2cache.demand_mshr_hits::cpu.data 11 # number of demand (read+write) MSHR hits 688system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits 689system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits 690system.cpu.l2cache.overall_mshr_hits::cpu.data 11 # number of overall MSHR hits 691system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits 692system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2048 # number of ReadReq MSHR misses 693system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 670 # number of ReadReq MSHR misses 694system.cpu.l2cache.ReadReq_mshr_misses::total 2718 # number of ReadReq MSHR misses 695system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses 696system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses 697system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1075 # number of ReadExReq MSHR misses 698system.cpu.l2cache.ReadExReq_mshr_misses::total 1075 # number of ReadExReq MSHR misses 699system.cpu.l2cache.demand_mshr_misses::cpu.inst 2048 # number of demand (read+write) MSHR misses 700system.cpu.l2cache.demand_mshr_misses::cpu.data 1745 # number of demand (read+write) MSHR misses 701system.cpu.l2cache.demand_mshr_misses::total 3793 # number of demand (read+write) MSHR misses 702system.cpu.l2cache.overall_mshr_misses::cpu.inst 2048 # number of overall MSHR misses 703system.cpu.l2cache.overall_mshr_misses::cpu.data 1745 # number of overall MSHR misses 704system.cpu.l2cache.overall_mshr_misses::total 3793 # number of overall MSHR misses 705system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70387399 # number of ReadReq MSHR miss cycles 706system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26266459 # number of ReadReq MSHR miss cycles 707system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96653858 # number of ReadReq MSHR miss cycles 708system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles 709system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles 710system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32716158 # number of ReadExReq MSHR miss cycles 711system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32716158 # number of ReadExReq MSHR miss cycles 712system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70387399 # number of demand (read+write) MSHR miss cycles 713system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 58982617 # number of demand (read+write) MSHR miss cycles 714system.cpu.l2cache.demand_mshr_miss_latency::total 129370016 # number of demand (read+write) MSHR miss cycles 715system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70387399 # number of overall MSHR miss cycles 716system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 58982617 # number of overall MSHR miss cycles 717system.cpu.l2cache.overall_mshr_miss_latency::total 129370016 # number of overall MSHR miss cycles 718system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.483589 # mshr miss rate for ReadReq accesses 719system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869001 # mshr miss rate for ReadReq accesses 720system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.542948 # mshr miss rate for ReadReq accesses 721system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 722system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 723system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992613 # mshr miss rate for ReadExReq accesses 724system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992613 # mshr miss rate for ReadExReq accesses 725system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.483589 # mshr miss rate for demand accesses 726system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941208 # mshr miss rate for demand accesses 727system.cpu.l2cache.demand_mshr_miss_rate::total 0.622927 # mshr miss rate for demand accesses 728system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.483589 # mshr miss rate for overall accesses 729system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941208 # mshr miss rate for overall accesses 730system.cpu.l2cache.overall_mshr_miss_rate::total 0.622927 # mshr miss rate for overall accesses 731system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34368.847168 # average ReadReq mshr miss latency 732system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39203.670149 # average ReadReq mshr miss latency 733system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35560.654157 # average ReadReq mshr miss latency 734system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 735system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 736system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30433.635349 # average ReadExReq mshr miss latency 737system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30433.635349 # average ReadExReq mshr miss latency 738system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34368.847168 # average overall mshr miss latency 739system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33800.926648 # average overall mshr miss latency 740system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34107.570788 # average overall mshr miss latency 741system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34368.847168 # average overall mshr miss latency 742system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33800.926648 # average overall mshr miss latency 743system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34107.570788 # average overall mshr miss latency 744system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
|
| 586system.cpu.dcache.replacements 57 # number of replacements | 745system.cpu.dcache.replacements 57 # number of replacements |
| 587system.cpu.dcache.tagsinuse 1416.459985 # Cycle average of tags in use 588system.cpu.dcache.total_refs 47307506 # Total number of references to valid blocks. 589system.cpu.dcache.sampled_refs 1862 # Sample count of references to valid blocks. 590system.cpu.dcache.avg_refs 25406.823845 # Average number of references to valid blocks. | 746system.cpu.dcache.tagsinuse 1406.445400 # Cycle average of tags in use 747system.cpu.dcache.total_refs 46805125 # Total number of references to valid blocks. 748system.cpu.dcache.sampled_refs 1854 # Sample count of references to valid blocks. 749system.cpu.dcache.avg_refs 25245.482740 # Average number of references to valid blocks. |
| 591system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 750system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 592system.cpu.dcache.occ_blocks::cpu.data 1416.459985 # Average occupied blocks per requestor 593system.cpu.dcache.occ_percent::cpu.data 0.345815 # Average percentage of cache occupancy 594system.cpu.dcache.occ_percent::total 0.345815 # Average percentage of cache occupancy 595system.cpu.dcache.ReadReq_hits::cpu.data 34892236 # number of ReadReq hits 596system.cpu.dcache.ReadReq_hits::total 34892236 # number of ReadReq hits 597system.cpu.dcache.WriteReq_hits::cpu.data 12356557 # number of WriteReq hits 598system.cpu.dcache.WriteReq_hits::total 12356557 # number of WriteReq hits 599system.cpu.dcache.LoadLockedReq_hits::cpu.data 30260 # number of LoadLockedReq hits 600system.cpu.dcache.LoadLockedReq_hits::total 30260 # number of LoadLockedReq hits 601system.cpu.dcache.StoreCondReq_hits::cpu.data 28451 # number of StoreCondReq hits 602system.cpu.dcache.StoreCondReq_hits::total 28451 # number of StoreCondReq hits 603system.cpu.dcache.demand_hits::cpu.data 47248793 # number of demand (read+write) hits 604system.cpu.dcache.demand_hits::total 47248793 # number of demand (read+write) hits 605system.cpu.dcache.overall_hits::cpu.data 47248793 # number of overall hits 606system.cpu.dcache.overall_hits::total 47248793 # number of overall hits 607system.cpu.dcache.ReadReq_misses::cpu.data 1972 # number of ReadReq misses 608system.cpu.dcache.ReadReq_misses::total 1972 # number of ReadReq misses 609system.cpu.dcache.WriteReq_misses::cpu.data 7730 # number of WriteReq misses 610system.cpu.dcache.WriteReq_misses::total 7730 # number of WriteReq misses | 751system.cpu.dcache.occ_blocks::cpu.data 1406.445400 # Average occupied blocks per requestor 752system.cpu.dcache.occ_percent::cpu.data 0.343370 # Average percentage of cache occupancy 753system.cpu.dcache.occ_percent::total 0.343370 # Average percentage of cache occupancy 754system.cpu.dcache.ReadReq_hits::cpu.data 34390274 # number of ReadReq hits 755system.cpu.dcache.ReadReq_hits::total 34390274 # number of ReadReq hits 756system.cpu.dcache.WriteReq_hits::cpu.data 12356568 # number of WriteReq hits 757system.cpu.dcache.WriteReq_hits::total 12356568 # number of WriteReq hits 758system.cpu.dcache.LoadLockedReq_hits::cpu.data 29790 # number of LoadLockedReq hits 759system.cpu.dcache.LoadLockedReq_hits::total 29790 # number of LoadLockedReq hits 760system.cpu.dcache.StoreCondReq_hits::cpu.data 28491 # number of StoreCondReq hits 761system.cpu.dcache.StoreCondReq_hits::total 28491 # number of StoreCondReq hits 762system.cpu.dcache.demand_hits::cpu.data 46746842 # number of demand (read+write) hits 763system.cpu.dcache.demand_hits::total 46746842 # number of demand (read+write) hits 764system.cpu.dcache.overall_hits::cpu.data 46746842 # number of overall hits 765system.cpu.dcache.overall_hits::total 46746842 # number of overall hits 766system.cpu.dcache.ReadReq_misses::cpu.data 1833 # number of ReadReq misses 767system.cpu.dcache.ReadReq_misses::total 1833 # number of ReadReq misses 768system.cpu.dcache.WriteReq_misses::cpu.data 7719 # number of WriteReq misses 769system.cpu.dcache.WriteReq_misses::total 7719 # number of WriteReq misses |
| 611system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 612system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses | 770system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 771system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses |
| 613system.cpu.dcache.demand_misses::cpu.data 9702 # number of demand (read+write) misses 614system.cpu.dcache.demand_misses::total 9702 # number of demand (read+write) misses 615system.cpu.dcache.overall_misses::cpu.data 9702 # number of overall misses 616system.cpu.dcache.overall_misses::total 9702 # number of overall misses 617system.cpu.dcache.ReadReq_miss_latency::cpu.data 89685500 # number of ReadReq miss cycles 618system.cpu.dcache.ReadReq_miss_latency::total 89685500 # number of ReadReq miss cycles 619system.cpu.dcache.WriteReq_miss_latency::cpu.data 298721497 # number of WriteReq miss cycles 620system.cpu.dcache.WriteReq_miss_latency::total 298721497 # number of WriteReq miss cycles | 772system.cpu.dcache.demand_misses::cpu.data 9552 # number of demand (read+write) misses 773system.cpu.dcache.demand_misses::total 9552 # number of demand (read+write) misses 774system.cpu.dcache.overall_misses::cpu.data 9552 # number of overall misses 775system.cpu.dcache.overall_misses::total 9552 # number of overall misses 776system.cpu.dcache.ReadReq_miss_latency::cpu.data 82596000 # number of ReadReq miss cycles 777system.cpu.dcache.ReadReq_miss_latency::total 82596000 # number of ReadReq miss cycles 778system.cpu.dcache.WriteReq_miss_latency::cpu.data 292720496 # number of WriteReq miss cycles 779system.cpu.dcache.WriteReq_miss_latency::total 292720496 # number of WriteReq miss cycles |
| 621system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles 622system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles | 780system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles 781system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles |
| 623system.cpu.dcache.demand_miss_latency::cpu.data 388406997 # number of demand (read+write) miss cycles 624system.cpu.dcache.demand_miss_latency::total 388406997 # number of demand (read+write) miss cycles 625system.cpu.dcache.overall_miss_latency::cpu.data 388406997 # number of overall miss cycles 626system.cpu.dcache.overall_miss_latency::total 388406997 # number of overall miss cycles 627system.cpu.dcache.ReadReq_accesses::cpu.data 34894208 # number of ReadReq accesses(hits+misses) 628system.cpu.dcache.ReadReq_accesses::total 34894208 # number of ReadReq accesses(hits+misses) | 782system.cpu.dcache.demand_miss_latency::cpu.data 375316496 # number of demand (read+write) miss cycles 783system.cpu.dcache.demand_miss_latency::total 375316496 # number of demand (read+write) miss cycles 784system.cpu.dcache.overall_miss_latency::cpu.data 375316496 # number of overall miss cycles 785system.cpu.dcache.overall_miss_latency::total 375316496 # number of overall miss cycles 786system.cpu.dcache.ReadReq_accesses::cpu.data 34392107 # number of ReadReq accesses(hits+misses) 787system.cpu.dcache.ReadReq_accesses::total 34392107 # number of ReadReq accesses(hits+misses) |
| 629system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 630system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) | 788system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 789system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) |
| 631system.cpu.dcache.LoadLockedReq_accesses::cpu.data 30262 # number of LoadLockedReq accesses(hits+misses) 632system.cpu.dcache.LoadLockedReq_accesses::total 30262 # number of LoadLockedReq accesses(hits+misses) 633system.cpu.dcache.StoreCondReq_accesses::cpu.data 28451 # number of StoreCondReq accesses(hits+misses) 634system.cpu.dcache.StoreCondReq_accesses::total 28451 # number of StoreCondReq accesses(hits+misses) 635system.cpu.dcache.demand_accesses::cpu.data 47258495 # number of demand (read+write) accesses 636system.cpu.dcache.demand_accesses::total 47258495 # number of demand (read+write) accesses 637system.cpu.dcache.overall_accesses::cpu.data 47258495 # number of overall (read+write) accesses 638system.cpu.dcache.overall_accesses::total 47258495 # number of overall (read+write) accesses 639system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000057 # miss rate for ReadReq accesses 640system.cpu.dcache.ReadReq_miss_rate::total 0.000057 # miss rate for ReadReq accesses 641system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses 642system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses 643system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000066 # miss rate for LoadLockedReq accesses 644system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000066 # miss rate for LoadLockedReq accesses 645system.cpu.dcache.demand_miss_rate::cpu.data 0.000205 # miss rate for demand accesses 646system.cpu.dcache.demand_miss_rate::total 0.000205 # miss rate for demand accesses 647system.cpu.dcache.overall_miss_rate::cpu.data 0.000205 # miss rate for overall accesses 648system.cpu.dcache.overall_miss_rate::total 0.000205 # miss rate for overall accesses 649system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45479.462475 # average ReadReq miss latency 650system.cpu.dcache.ReadReq_avg_miss_latency::total 45479.462475 # average ReadReq miss latency 651system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38644.436869 # average WriteReq miss latency 652system.cpu.dcache.WriteReq_avg_miss_latency::total 38644.436869 # average WriteReq miss latency | 790system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29792 # number of LoadLockedReq accesses(hits+misses) 791system.cpu.dcache.LoadLockedReq_accesses::total 29792 # number of LoadLockedReq accesses(hits+misses) 792system.cpu.dcache.StoreCondReq_accesses::cpu.data 28491 # number of StoreCondReq accesses(hits+misses) 793system.cpu.dcache.StoreCondReq_accesses::total 28491 # number of StoreCondReq accesses(hits+misses) 794system.cpu.dcache.demand_accesses::cpu.data 46756394 # number of demand (read+write) accesses 795system.cpu.dcache.demand_accesses::total 46756394 # number of demand (read+write) accesses 796system.cpu.dcache.overall_accesses::cpu.data 46756394 # number of overall (read+write) accesses 797system.cpu.dcache.overall_accesses::total 46756394 # number of overall (read+write) accesses 798system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses 799system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses 800system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses 801system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses 802system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses 803system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses 804system.cpu.dcache.demand_miss_rate::cpu.data 0.000204 # miss rate for demand accesses 805system.cpu.dcache.demand_miss_rate::total 0.000204 # miss rate for demand accesses 806system.cpu.dcache.overall_miss_rate::cpu.data 0.000204 # miss rate for overall accesses 807system.cpu.dcache.overall_miss_rate::total 0.000204 # miss rate for overall accesses 808system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45060.556465 # average ReadReq miss latency 809system.cpu.dcache.ReadReq_avg_miss_latency::total 45060.556465 # average ReadReq miss latency 810system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37922.074880 # average WriteReq miss latency 811system.cpu.dcache.WriteReq_avg_miss_latency::total 37922.074880 # average WriteReq miss latency |
| 653system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency 654system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency | 812system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency 813system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency |
| 655system.cpu.dcache.demand_avg_miss_latency::cpu.data 40033.704082 # average overall miss latency 656system.cpu.dcache.demand_avg_miss_latency::total 40033.704082 # average overall miss latency 657system.cpu.dcache.overall_avg_miss_latency::cpu.data 40033.704082 # average overall miss latency 658system.cpu.dcache.overall_avg_miss_latency::total 40033.704082 # average overall miss latency 659system.cpu.dcache.blocked_cycles::no_mshrs 433 # number of cycles access was blocked 660system.cpu.dcache.blocked_cycles::no_targets 45 # number of cycles access was blocked 661system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked | 814system.cpu.dcache.demand_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency 815system.cpu.dcache.demand_avg_miss_latency::total 39291.927973 # average overall miss latency 816system.cpu.dcache.overall_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency 817system.cpu.dcache.overall_avg_miss_latency::total 39291.927973 # average overall miss latency 818system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked 819system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked 820system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked |
| 662system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked | 821system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked |
| 663system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.363636 # average number of cycles each access was blocked 664system.cpu.dcache.avg_blocked_cycles::no_targets 22.500000 # average number of cycles each access was blocked | 822system.cpu.dcache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked 823system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked |
| 665system.cpu.dcache.fast_writes 0 # number of fast writes performed 666system.cpu.dcache.cache_copies 0 # number of cache copies performed 667system.cpu.dcache.writebacks::writebacks 18 # number of writebacks 668system.cpu.dcache.writebacks::total 18 # number of writebacks | 824system.cpu.dcache.fast_writes 0 # number of fast writes performed 825system.cpu.dcache.cache_copies 0 # number of cache copies performed 826system.cpu.dcache.writebacks::writebacks 18 # number of writebacks 827system.cpu.dcache.writebacks::total 18 # number of writebacks |
| 669system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1197 # number of ReadReq MSHR hits 670system.cpu.dcache.ReadReq_mshr_hits::total 1197 # number of ReadReq MSHR hits 671system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6641 # number of WriteReq MSHR hits 672system.cpu.dcache.WriteReq_mshr_hits::total 6641 # number of WriteReq MSHR hits | 828system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1062 # number of ReadReq MSHR hits 829system.cpu.dcache.ReadReq_mshr_hits::total 1062 # number of ReadReq MSHR hits 830system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits 831system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits |
| 673system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 674system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits | 832system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 833system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits |
| 675system.cpu.dcache.demand_mshr_hits::cpu.data 7838 # number of demand (read+write) MSHR hits 676system.cpu.dcache.demand_mshr_hits::total 7838 # number of demand (read+write) MSHR hits 677system.cpu.dcache.overall_mshr_hits::cpu.data 7838 # number of overall MSHR hits 678system.cpu.dcache.overall_mshr_hits::total 7838 # number of overall MSHR hits 679system.cpu.dcache.ReadReq_mshr_misses::cpu.data 775 # number of ReadReq MSHR misses 680system.cpu.dcache.ReadReq_mshr_misses::total 775 # number of ReadReq MSHR misses 681system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1089 # number of WriteReq MSHR misses 682system.cpu.dcache.WriteReq_mshr_misses::total 1089 # number of WriteReq MSHR misses 683system.cpu.dcache.demand_mshr_misses::cpu.data 1864 # number of demand (read+write) MSHR misses 684system.cpu.dcache.demand_mshr_misses::total 1864 # number of demand (read+write) MSHR misses 685system.cpu.dcache.overall_mshr_misses::cpu.data 1864 # number of overall MSHR misses 686system.cpu.dcache.overall_mshr_misses::total 1864 # number of overall MSHR misses 687system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38083000 # number of ReadReq MSHR miss cycles 688system.cpu.dcache.ReadReq_mshr_miss_latency::total 38083000 # number of ReadReq MSHR miss cycles 689system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 48635999 # number of WriteReq MSHR miss cycles 690system.cpu.dcache.WriteReq_mshr_miss_latency::total 48635999 # number of WriteReq MSHR miss cycles 691system.cpu.dcache.demand_mshr_miss_latency::cpu.data 86718999 # number of demand (read+write) MSHR miss cycles 692system.cpu.dcache.demand_mshr_miss_latency::total 86718999 # number of demand (read+write) MSHR miss cycles 693system.cpu.dcache.overall_mshr_miss_latency::cpu.data 86718999 # number of overall MSHR miss cycles 694system.cpu.dcache.overall_mshr_miss_latency::total 86718999 # number of overall MSHR miss cycles | 834system.cpu.dcache.demand_mshr_hits::cpu.data 7696 # number of demand (read+write) MSHR hits 835system.cpu.dcache.demand_mshr_hits::total 7696 # number of demand (read+write) MSHR hits 836system.cpu.dcache.overall_mshr_hits::cpu.data 7696 # number of overall MSHR hits 837system.cpu.dcache.overall_mshr_hits::total 7696 # number of overall MSHR hits 838system.cpu.dcache.ReadReq_mshr_misses::cpu.data 771 # number of ReadReq MSHR misses 839system.cpu.dcache.ReadReq_mshr_misses::total 771 # number of ReadReq MSHR misses 840system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses 841system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses 842system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses 843system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses 844system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses 845system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses 846system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36781000 # number of ReadReq MSHR miss cycles 847system.cpu.dcache.ReadReq_mshr_miss_latency::total 36781000 # number of ReadReq MSHR miss cycles 848system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47410498 # number of WriteReq MSHR miss cycles 849system.cpu.dcache.WriteReq_mshr_miss_latency::total 47410498 # number of WriteReq MSHR miss cycles 850system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84191498 # number of demand (read+write) MSHR miss cycles 851system.cpu.dcache.demand_mshr_miss_latency::total 84191498 # number of demand (read+write) MSHR miss cycles 852system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84191498 # number of overall MSHR miss cycles 853system.cpu.dcache.overall_mshr_miss_latency::total 84191498 # number of overall MSHR miss cycles |
| 695system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses 696system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses 697system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses 698system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses | 854system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses 855system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses 856system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses 857system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses |
| 699system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000039 # mshr miss rate for demand accesses 700system.cpu.dcache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses 701system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000039 # mshr miss rate for overall accesses 702system.cpu.dcache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses 703system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49139.354839 # average ReadReq mshr miss latency 704system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49139.354839 # average ReadReq mshr miss latency 705system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44661.156107 # average WriteReq mshr miss latency 706system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44661.156107 # average WriteReq mshr miss latency 707system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46523.068133 # average overall mshr miss latency 708system.cpu.dcache.demand_avg_mshr_miss_latency::total 46523.068133 # average overall mshr miss latency 709system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46523.068133 # average overall mshr miss latency 710system.cpu.dcache.overall_avg_mshr_miss_latency::total 46523.068133 # average overall mshr miss latency | 858system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses 859system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 860system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses 861system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses 862system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47705.577173 # average ReadReq mshr miss latency 863system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47705.577173 # average ReadReq mshr miss latency 864system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43696.311521 # average WriteReq mshr miss latency 865system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43696.311521 # average WriteReq mshr miss latency 866system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency 867system.cpu.dcache.demand_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency 868system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency 869system.cpu.dcache.overall_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency |
| 711system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 870system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 712system.cpu.l2cache.replacements 0 # number of replacements 713system.cpu.l2cache.tagsinuse 1988.724621 # Cycle average of tags in use 714system.cpu.l2cache.total_refs 2398 # Total number of references to valid blocks. 715system.cpu.l2cache.sampled_refs 2755 # Sample count of references to valid blocks. 716system.cpu.l2cache.avg_refs 0.870417 # Average number of references to valid blocks. 717system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 718system.cpu.l2cache.occ_blocks::writebacks 3.999610 # Average occupied blocks per requestor 719system.cpu.l2cache.occ_blocks::cpu.inst 1449.117125 # Average occupied blocks per requestor 720system.cpu.l2cache.occ_blocks::cpu.data 535.607885 # Average occupied blocks per requestor 721system.cpu.l2cache.occ_percent::writebacks 0.000122 # Average percentage of cache occupancy 722system.cpu.l2cache.occ_percent::cpu.inst 0.044224 # Average percentage of cache occupancy 723system.cpu.l2cache.occ_percent::cpu.data 0.016345 # Average percentage of cache occupancy 724system.cpu.l2cache.occ_percent::total 0.060691 # Average percentage of cache occupancy 725system.cpu.l2cache.ReadReq_hits::cpu.inst 2308 # number of ReadReq hits 726system.cpu.l2cache.ReadReq_hits::cpu.data 88 # number of ReadReq hits 727system.cpu.l2cache.ReadReq_hits::total 2396 # number of ReadReq hits 728system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits 729system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits 730system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 731system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 732system.cpu.l2cache.ReadExReq_hits::cpu.data 9 # number of ReadExReq hits 733system.cpu.l2cache.ReadExReq_hits::total 9 # number of ReadExReq hits 734system.cpu.l2cache.demand_hits::cpu.inst 2308 # number of demand (read+write) hits 735system.cpu.l2cache.demand_hits::cpu.data 97 # number of demand (read+write) hits 736system.cpu.l2cache.demand_hits::total 2405 # number of demand (read+write) hits 737system.cpu.l2cache.overall_hits::cpu.inst 2308 # number of overall hits 738system.cpu.l2cache.overall_hits::cpu.data 97 # number of overall hits 739system.cpu.l2cache.overall_hits::total 2405 # number of overall hits 740system.cpu.l2cache.ReadReq_misses::cpu.inst 2079 # number of ReadReq misses 741system.cpu.l2cache.ReadReq_misses::cpu.data 685 # number of ReadReq misses 742system.cpu.l2cache.ReadReq_misses::total 2764 # number of ReadReq misses 743system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses 744system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses 745system.cpu.l2cache.ReadExReq_misses::cpu.data 1080 # number of ReadExReq misses 746system.cpu.l2cache.ReadExReq_misses::total 1080 # number of ReadExReq misses 747system.cpu.l2cache.demand_misses::cpu.inst 2079 # number of demand (read+write) misses 748system.cpu.l2cache.demand_misses::cpu.data 1765 # number of demand (read+write) misses 749system.cpu.l2cache.demand_misses::total 3844 # number of demand (read+write) misses 750system.cpu.l2cache.overall_misses::cpu.inst 2079 # number of overall misses 751system.cpu.l2cache.overall_misses::cpu.data 1765 # number of overall misses 752system.cpu.l2cache.overall_misses::total 3844 # number of overall misses 753system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 98742500 # number of ReadReq miss cycles 754system.cpu.l2cache.ReadReq_miss_latency::cpu.data 36322000 # number of ReadReq miss cycles 755system.cpu.l2cache.ReadReq_miss_latency::total 135064500 # number of ReadReq miss cycles 756system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 47502500 # number of ReadExReq miss cycles 757system.cpu.l2cache.ReadExReq_miss_latency::total 47502500 # number of ReadExReq miss cycles 758system.cpu.l2cache.demand_miss_latency::cpu.inst 98742500 # number of demand (read+write) miss cycles 759system.cpu.l2cache.demand_miss_latency::cpu.data 83824500 # number of demand (read+write) miss cycles 760system.cpu.l2cache.demand_miss_latency::total 182567000 # number of demand (read+write) miss cycles 761system.cpu.l2cache.overall_miss_latency::cpu.inst 98742500 # number of overall miss cycles 762system.cpu.l2cache.overall_miss_latency::cpu.data 83824500 # number of overall miss cycles 763system.cpu.l2cache.overall_miss_latency::total 182567000 # number of overall miss cycles 764system.cpu.l2cache.ReadReq_accesses::cpu.inst 4387 # number of ReadReq accesses(hits+misses) 765system.cpu.l2cache.ReadReq_accesses::cpu.data 773 # number of ReadReq accesses(hits+misses) 766system.cpu.l2cache.ReadReq_accesses::total 5160 # number of ReadReq accesses(hits+misses) 767system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) 768system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) 769system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) 770system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) 771system.cpu.l2cache.ReadExReq_accesses::cpu.data 1089 # number of ReadExReq accesses(hits+misses) 772system.cpu.l2cache.ReadExReq_accesses::total 1089 # number of ReadExReq accesses(hits+misses) 773system.cpu.l2cache.demand_accesses::cpu.inst 4387 # number of demand (read+write) accesses 774system.cpu.l2cache.demand_accesses::cpu.data 1862 # number of demand (read+write) accesses 775system.cpu.l2cache.demand_accesses::total 6249 # number of demand (read+write) accesses 776system.cpu.l2cache.overall_accesses::cpu.inst 4387 # number of overall (read+write) accesses 777system.cpu.l2cache.overall_accesses::cpu.data 1862 # number of overall (read+write) accesses 778system.cpu.l2cache.overall_accesses::total 6249 # number of overall (read+write) accesses 779system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.473900 # miss rate for ReadReq accesses 780system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.886158 # miss rate for ReadReq accesses 781system.cpu.l2cache.ReadReq_miss_rate::total 0.535659 # miss rate for ReadReq accesses 782system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses 783system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses 784system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991736 # miss rate for ReadExReq accesses 785system.cpu.l2cache.ReadExReq_miss_rate::total 0.991736 # miss rate for ReadExReq accesses 786system.cpu.l2cache.demand_miss_rate::cpu.inst 0.473900 # miss rate for demand accesses 787system.cpu.l2cache.demand_miss_rate::cpu.data 0.947905 # miss rate for demand accesses 788system.cpu.l2cache.demand_miss_rate::total 0.615138 # miss rate for demand accesses 789system.cpu.l2cache.overall_miss_rate::cpu.inst 0.473900 # miss rate for overall accesses 790system.cpu.l2cache.overall_miss_rate::cpu.data 0.947905 # miss rate for overall accesses 791system.cpu.l2cache.overall_miss_rate::total 0.615138 # miss rate for overall accesses 792system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47495.189995 # average ReadReq miss latency 793system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53024.817518 # average ReadReq miss latency 794system.cpu.l2cache.ReadReq_avg_miss_latency::total 48865.593343 # average ReadReq miss latency 795system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43983.796296 # average ReadExReq miss latency 796system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43983.796296 # average ReadExReq miss latency 797system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47495.189995 # average overall miss latency 798system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47492.634561 # average overall miss latency 799system.cpu.l2cache.demand_avg_miss_latency::total 47494.016649 # average overall miss latency 800system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47495.189995 # average overall miss latency 801system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47492.634561 # average overall miss latency 802system.cpu.l2cache.overall_avg_miss_latency::total 47494.016649 # average overall miss latency 803system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 804system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 805system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 806system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 807system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 808system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 809system.cpu.l2cache.fast_writes 0 # number of fast writes performed 810system.cpu.l2cache.cache_copies 0 # number of cache copies performed 811system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits 812system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits 813system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits 814system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits 815system.cpu.l2cache.demand_mshr_hits::cpu.data 12 # number of demand (read+write) MSHR hits 816system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits 817system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits 818system.cpu.l2cache.overall_mshr_hits::cpu.data 12 # number of overall MSHR hits 819system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits 820system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2075 # number of ReadReq MSHR misses 821system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 673 # number of ReadReq MSHR misses 822system.cpu.l2cache.ReadReq_mshr_misses::total 2748 # number of ReadReq MSHR misses 823system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses 824system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses 825system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1080 # number of ReadExReq MSHR misses 826system.cpu.l2cache.ReadExReq_mshr_misses::total 1080 # number of ReadExReq MSHR misses 827system.cpu.l2cache.demand_mshr_misses::cpu.inst 2075 # number of demand (read+write) MSHR misses 828system.cpu.l2cache.demand_mshr_misses::cpu.data 1753 # number of demand (read+write) MSHR misses 829system.cpu.l2cache.demand_mshr_misses::total 3828 # number of demand (read+write) MSHR misses 830system.cpu.l2cache.overall_mshr_misses::cpu.inst 2075 # number of overall MSHR misses 831system.cpu.l2cache.overall_mshr_misses::cpu.data 1753 # number of overall MSHR misses 832system.cpu.l2cache.overall_mshr_misses::total 3828 # number of overall MSHR misses 833system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 72306456 # number of ReadReq MSHR miss cycles 834system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27405972 # number of ReadReq MSHR miss cycles 835system.cpu.l2cache.ReadReq_mshr_miss_latency::total 99712428 # number of ReadReq MSHR miss cycles 836system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles 837system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles 838system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33965187 # number of ReadExReq MSHR miss cycles 839system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33965187 # number of ReadExReq MSHR miss cycles 840system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 72306456 # number of demand (read+write) MSHR miss cycles 841system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 61371159 # number of demand (read+write) MSHR miss cycles 842system.cpu.l2cache.demand_mshr_miss_latency::total 133677615 # number of demand (read+write) MSHR miss cycles 843system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 72306456 # number of overall MSHR miss cycles 844system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 61371159 # number of overall MSHR miss cycles 845system.cpu.l2cache.overall_mshr_miss_latency::total 133677615 # number of overall MSHR miss cycles 846system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.472988 # mshr miss rate for ReadReq accesses 847system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870634 # mshr miss rate for ReadReq accesses 848system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.532558 # mshr miss rate for ReadReq accesses 849system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses 850system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses 851system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991736 # mshr miss rate for ReadExReq accesses 852system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991736 # mshr miss rate for ReadExReq accesses 853system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.472988 # mshr miss rate for demand accesses 854system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941461 # mshr miss rate for demand accesses 855system.cpu.l2cache.demand_mshr_miss_rate::total 0.612578 # mshr miss rate for demand accesses 856system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.472988 # mshr miss rate for overall accesses 857system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941461 # mshr miss rate for overall accesses 858system.cpu.l2cache.overall_mshr_miss_rate::total 0.612578 # mshr miss rate for overall accesses 859system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34846.484819 # average ReadReq mshr miss latency 860system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40722.098068 # average ReadReq mshr miss latency 861system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36285.454148 # average ReadReq mshr miss latency 862system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 863system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 864system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31449.247222 # average ReadExReq mshr miss latency 865system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31449.247222 # average ReadExReq mshr miss latency 866system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34846.484819 # average overall mshr miss latency 867system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35009.217912 # average overall mshr miss latency 868system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34921.007053 # average overall mshr miss latency 869system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34846.484819 # average overall mshr miss latency 870system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35009.217912 # average overall mshr miss latency 871system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34921.007053 # average overall mshr miss latency 872system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 873 874---------- End Simulation Statistics ---------- | 871 872---------- End Simulation Statistics ---------- |