| stats.txt (9285:9901180cd573) | stats.txt (9289:a31a1243a3ed) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.075929 # Number of seconds simulated 4sim_ticks 75929256000 # Number of ticks simulated 5final_tick 75929256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.075929 # Number of seconds simulated 4sim_ticks 75929256000 # Number of ticks simulated 5final_tick 75929256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 99785 # Simulator instruction rate (inst/s) 8host_op_rate 109254 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 43964821 # Simulator tick rate (ticks/s) 10host_mem_usage 238132 # Number of bytes of host memory used 11host_seconds 1727.05 # Real time elapsed on the host | 7host_inst_rate 126863 # Simulator instruction rate (inst/s) 8host_op_rate 138901 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 55895176 # Simulator tick rate (ticks/s) 10host_mem_usage 231880 # Number of bytes of host memory used 11host_seconds 1358.42 # Real time elapsed on the host |
| 12sim_insts 172333091 # Number of instructions simulated 13sim_ops 188686573 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 132864 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 112384 # Number of bytes read from this memory 16system.physmem.bytes_read::total 245248 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 132864 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 132864 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 2076 # Number of read requests responded to by this memory --- 472 unchanged lines hidden (view full) --- 492system.cpu.dcache.WriteReq_avg_miss_latency::total 30808.528757 # average WriteReq miss latency 493system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 34000 # average LoadLockedReq miss latency 494system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 34000 # average LoadLockedReq miss latency 495system.cpu.dcache.demand_avg_miss_latency::cpu.data 31016.696141 # average overall miss latency 496system.cpu.dcache.demand_avg_miss_latency::total 31016.696141 # average overall miss latency 497system.cpu.dcache.overall_avg_miss_latency::cpu.data 31016.696141 # average overall miss latency 498system.cpu.dcache.overall_avg_miss_latency::total 31016.696141 # average overall miss latency 499system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 12sim_insts 172333091 # Number of instructions simulated 13sim_ops 188686573 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 132864 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 112384 # Number of bytes read from this memory 16system.physmem.bytes_read::total 245248 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 132864 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 132864 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 2076 # Number of read requests responded to by this memory --- 472 unchanged lines hidden (view full) --- 492system.cpu.dcache.WriteReq_avg_miss_latency::total 30808.528757 # average WriteReq miss latency 493system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 34000 # average LoadLockedReq miss latency 494system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 34000 # average LoadLockedReq miss latency 495system.cpu.dcache.demand_avg_miss_latency::cpu.data 31016.696141 # average overall miss latency 496system.cpu.dcache.demand_avg_miss_latency::total 31016.696141 # average overall miss latency 497system.cpu.dcache.overall_avg_miss_latency::cpu.data 31016.696141 # average overall miss latency 498system.cpu.dcache.overall_avg_miss_latency::total 31016.696141 # average overall miss latency 499system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 500system.cpu.dcache.blocked_cycles::no_targets 4500 # number of cycles access was blocked | 500system.cpu.dcache.blocked_cycles::no_targets 9 # number of cycles access was blocked |
| 501system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 502system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked 503system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 501system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 502system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked 503system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 504system.cpu.dcache.avg_blocked_cycles::no_targets 4500 # average number of cycles each access was blocked | 504system.cpu.dcache.avg_blocked_cycles::no_targets 9 # average number of cycles each access was blocked |
| 505system.cpu.dcache.fast_writes 0 # number of fast writes performed 506system.cpu.dcache.cache_copies 0 # number of cache copies performed 507system.cpu.dcache.writebacks::writebacks 18 # number of writebacks 508system.cpu.dcache.writebacks::total 18 # number of writebacks 509system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1197 # number of ReadReq MSHR hits 510system.cpu.dcache.ReadReq_mshr_hits::total 1197 # number of ReadReq MSHR hits 511system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6550 # number of WriteReq MSHR hits 512system.cpu.dcache.WriteReq_mshr_hits::total 6550 # number of WriteReq MSHR hits --- 186 unchanged lines hidden --- | 505system.cpu.dcache.fast_writes 0 # number of fast writes performed 506system.cpu.dcache.cache_copies 0 # number of cache copies performed 507system.cpu.dcache.writebacks::writebacks 18 # number of writebacks 508system.cpu.dcache.writebacks::total 18 # number of writebacks 509system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1197 # number of ReadReq MSHR hits 510system.cpu.dcache.ReadReq_mshr_hits::total 1197 # number of ReadReq MSHR hits 511system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6550 # number of WriteReq MSHR hits 512system.cpu.dcache.WriteReq_mshr_hits::total 6550 # number of WriteReq MSHR hits --- 186 unchanged lines hidden --- |