| stats.txt (9223:be1c1059438b) | stats.txt (9265:8fe936e937bd) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.076018 # Number of seconds simulated 4sim_ticks 76017712000 # Number of ticks simulated 5final_tick 76017712000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.076020 # Number of seconds simulated 4sim_ticks 76020082000 # Number of ticks simulated 5final_tick 76020082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 156722 # Simulator instruction rate (inst/s) 8host_op_rate 171594 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 69131199 # Simulator tick rate (ticks/s) 10host_mem_usage 238024 # Number of bytes of host memory used 11host_seconds 1099.62 # Real time elapsed on the host 12sim_insts 172333351 # Number of instructions simulated 13sim_ops 188686833 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 131968 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 112192 # Number of bytes read from this memory 16system.physmem.bytes_read::total 244160 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 131968 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 131968 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 2062 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 1753 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 3815 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1736016 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 1475867 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 3211883 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1736016 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1736016 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1736016 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 1475867 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 3211883 # Total bandwidth to/from this memory (bytes/s) | 7host_inst_rate 108434 # Simulator instruction rate (inst/s) 8host_op_rate 118724 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 47832871 # Simulator tick rate (ticks/s) 10host_mem_usage 232824 # Number of bytes of host memory used 11host_seconds 1589.29 # Real time elapsed on the host 12sim_insts 172333166 # Number of instructions simulated 13sim_ops 188686648 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 132416 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 112256 # Number of bytes read from this memory 16system.physmem.bytes_read::total 244672 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 132416 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 132416 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 2069 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 1754 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 3823 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1741856 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 1476662 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 3218518 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1741856 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1741856 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1741856 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 1476662 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 3218518 # Total bandwidth to/from this memory (bytes/s) |
| 30system.cpu.dtb.inst_hits 0 # ITB inst hits 31system.cpu.dtb.inst_misses 0 # ITB inst misses 32system.cpu.dtb.read_hits 0 # DTB read hits 33system.cpu.dtb.read_misses 0 # DTB read misses 34system.cpu.dtb.write_hits 0 # DTB write hits 35system.cpu.dtb.write_misses 0 # DTB write misses 36system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 37system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 65system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 66system.cpu.itb.read_accesses 0 # DTB read accesses 67system.cpu.itb.write_accesses 0 # DTB write accesses 68system.cpu.itb.inst_accesses 0 # ITB inst accesses 69system.cpu.itb.hits 0 # DTB hits 70system.cpu.itb.misses 0 # DTB misses 71system.cpu.itb.accesses 0 # DTB accesses 72system.cpu.workload.num_syscalls 400 # Number of system calls | 30system.cpu.dtb.inst_hits 0 # ITB inst hits 31system.cpu.dtb.inst_misses 0 # ITB inst misses 32system.cpu.dtb.read_hits 0 # DTB read hits 33system.cpu.dtb.read_misses 0 # DTB read misses 34system.cpu.dtb.write_hits 0 # DTB write hits 35system.cpu.dtb.write_misses 0 # DTB write misses 36system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 37system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 65system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 66system.cpu.itb.read_accesses 0 # DTB read accesses 67system.cpu.itb.write_accesses 0 # DTB write accesses 68system.cpu.itb.inst_accesses 0 # ITB inst accesses 69system.cpu.itb.hits 0 # DTB hits 70system.cpu.itb.misses 0 # DTB misses 71system.cpu.itb.accesses 0 # DTB accesses 72system.cpu.workload.num_syscalls 400 # Number of system calls |
| 73system.cpu.numCycles 152035425 # number of cpu cycles simulated | 73system.cpu.numCycles 152040165 # number of cpu cycles simulated |
| 74system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 75system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 74system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 75system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 76system.cpu.BPredUnit.lookups 96736502 # Number of BP lookups 77system.cpu.BPredUnit.condPredicted 76001405 # Number of conditional branches predicted 78system.cpu.BPredUnit.condIncorrect 6554044 # Number of conditional branches incorrect 79system.cpu.BPredUnit.BTBLookups 46407824 # Number of BTB lookups 80system.cpu.BPredUnit.BTBHits 44181263 # Number of BTB hits | 76system.cpu.BPredUnit.lookups 96858484 # Number of BP lookups 77system.cpu.BPredUnit.condPredicted 76060964 # Number of conditional branches predicted 78system.cpu.BPredUnit.condIncorrect 6563923 # Number of conditional branches incorrect 79system.cpu.BPredUnit.BTBLookups 46433794 # Number of BTB lookups 80system.cpu.BPredUnit.BTBHits 44260375 # Number of BTB hits |
| 81system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 81system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 82system.cpu.BPredUnit.usedRAS 4475583 # Number of times the RAS was used to get a target. 83system.cpu.BPredUnit.RASInCorrect 89477 # Number of incorrect RAS predictions. 84system.cpu.fetch.icacheStallCycles 40615724 # Number of cycles fetch is stalled on an Icache miss 85system.cpu.fetch.Insts 388321121 # Number of instructions fetch has processed 86system.cpu.fetch.Branches 96736502 # Number of branches that fetch encountered 87system.cpu.fetch.predictedBranches 48656846 # Number of branches that fetch has predicted taken 88system.cpu.fetch.Cycles 82257766 # Number of cycles fetch has run and was not squashing or blocked 89system.cpu.fetch.SquashCycles 28468285 # Number of cycles fetch has spent squashing 90system.cpu.fetch.BlockedCycles 7213696 # Number of cycles fetch has spent blocked 91system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 92system.cpu.fetch.PendingTrapStallCycles 8844 # Number of stall cycles due to pending traps | 82system.cpu.BPredUnit.usedRAS 4475068 # Number of times the RAS was used to get a target. 83system.cpu.BPredUnit.RASInCorrect 89115 # Number of incorrect RAS predictions. 84system.cpu.fetch.icacheStallCycles 40665802 # Number of cycles fetch is stalled on an Icache miss 85system.cpu.fetch.Insts 388394971 # Number of instructions fetch has processed 86system.cpu.fetch.Branches 96858484 # Number of branches that fetch encountered 87system.cpu.fetch.predictedBranches 48735443 # Number of branches that fetch has predicted taken 88system.cpu.fetch.Cycles 82285186 # Number of cycles fetch has run and was not squashing or blocked 89system.cpu.fetch.SquashCycles 28468460 # Number of cycles fetch has spent squashing 90system.cpu.fetch.BlockedCycles 7130109 # Number of cycles fetch has spent blocked 91system.cpu.fetch.MiscStallCycles 7 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 92system.cpu.fetch.PendingTrapStallCycles 9134 # Number of stall cycles due to pending traps |
| 93system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions | 93system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions |
| 94system.cpu.fetch.CacheLines 37645633 # Number of cache lines fetched 95system.cpu.fetch.IcacheSquashes 1886253 # Number of outstanding Icache misses that were squashed 96system.cpu.fetch.rateDist::samples 151974828 # Number of instructions fetched each cycle (Total) 97system.cpu.fetch.rateDist::mean 2.798620 # Number of instructions fetched each cycle (Total) 98system.cpu.fetch.rateDist::stdev 3.154172 # Number of instructions fetched each cycle (Total) | 94system.cpu.fetch.CacheLines 37715921 # Number of cache lines fetched 95system.cpu.fetch.IcacheSquashes 1893970 # Number of outstanding Icache misses that were squashed 96system.cpu.fetch.rateDist::samples 151978869 # Number of instructions fetched each cycle (Total) 97system.cpu.fetch.rateDist::mean 2.797548 # Number of instructions fetched each cycle (Total) 98system.cpu.fetch.rateDist::stdev 3.152738 # Number of instructions fetched each cycle (Total) |
| 99system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 99system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 100system.cpu.fetch.rateDist::0 69887899 45.99% 45.99% # Number of instructions fetched each cycle (Total) 101system.cpu.fetch.rateDist::1 5501348 3.62% 49.61% # Number of instructions fetched each cycle (Total) 102system.cpu.fetch.rateDist::2 10684945 7.03% 56.64% # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::3 10435662 6.87% 63.50% # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.rateDist::4 8784636 5.78% 69.28% # Number of instructions fetched each cycle (Total) 105system.cpu.fetch.rateDist::5 6836908 4.50% 73.78% # Number of instructions fetched each cycle (Total) 106system.cpu.fetch.rateDist::6 6295744 4.14% 77.93% # Number of instructions fetched each cycle (Total) 107system.cpu.fetch.rateDist::7 8337493 5.49% 83.41% # Number of instructions fetched each cycle (Total) 108system.cpu.fetch.rateDist::8 25210193 16.59% 100.00% # Number of instructions fetched each cycle (Total) | 100system.cpu.fetch.rateDist::0 69866943 45.97% 45.97% # Number of instructions fetched each cycle (Total) 101system.cpu.fetch.rateDist::1 5495765 3.62% 49.59% # Number of instructions fetched each cycle (Total) 102system.cpu.fetch.rateDist::2 10729414 7.06% 56.65% # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::3 10452168 6.88% 63.52% # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.rateDist::4 8790327 5.78% 69.31% # Number of instructions fetched each cycle (Total) 105system.cpu.fetch.rateDist::5 6826108 4.49% 73.80% # Number of instructions fetched each cycle (Total) 106system.cpu.fetch.rateDist::6 6308927 4.15% 77.95% # Number of instructions fetched each cycle (Total) 107system.cpu.fetch.rateDist::7 8362057 5.50% 83.45% # Number of instructions fetched each cycle (Total) 108system.cpu.fetch.rateDist::8 25147160 16.55% 100.00% # Number of instructions fetched each cycle (Total) |
| 109system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 110system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 111system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 109system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 110system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 111system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 112system.cpu.fetch.rateDist::total 151974828 # Number of instructions fetched each cycle (Total) 113system.cpu.fetch.branchRate 0.636276 # Number of branch fetches per cycle 114system.cpu.fetch.rate 2.554149 # Number of inst fetches per cycle 115system.cpu.decode.IdleCycles 46658969 # Number of cycles decode is idle 116system.cpu.decode.BlockedCycles 5920762 # Number of cycles decode is blocked 117system.cpu.decode.RunCycles 76552571 # Number of cycles decode is running 118system.cpu.decode.UnblockCycles 1116980 # Number of cycles decode is unblocking 119system.cpu.decode.SquashCycles 21725546 # Number of cycles decode is squashing 120system.cpu.decode.BranchResolved 14796577 # Number of times decode resolved a branch 121system.cpu.decode.BranchMispred 162492 # Number of times decode detected a branch misprediction 122system.cpu.decode.DecodedInsts 401466473 # Number of instructions handled by decode 123system.cpu.decode.SquashedInsts 736417 # Number of squashed instructions handled by decode 124system.cpu.rename.SquashCycles 21725546 # Number of cycles rename is squashing 125system.cpu.rename.IdleCycles 52184597 # Number of cycles rename is idle 126system.cpu.rename.BlockCycles 714677 # Number of cycles rename is blocking 127system.cpu.rename.serializeStallCycles 792157 # count of cycles rename stalled for serializing inst 128system.cpu.rename.RunCycles 72083528 # Number of cycles rename is running 129system.cpu.rename.UnblockCycles 4474323 # Number of cycles rename is unblocking 130system.cpu.rename.RenamedInsts 378974639 # Number of instructions processed by rename 131system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full 132system.cpu.rename.IQFullEvents 320673 # Number of times rename has blocked due to IQ full 133system.cpu.rename.LSQFullEvents 3580560 # Number of times rename has blocked due to LSQ full 134system.cpu.rename.FullRegisterEvents 14 # Number of times there has been no free registers 135system.cpu.rename.RenamedOperands 642268895 # Number of destination operands rename has renamed 136system.cpu.rename.RenameLookups 1614410837 # Number of register rename lookups that rename has made 137system.cpu.rename.int_rename_lookups 1596806412 # Number of integer rename lookups 138system.cpu.rename.fp_rename_lookups 17604425 # Number of floating rename lookups 139system.cpu.rename.CommittedMaps 298092667 # Number of HB maps that are committed 140system.cpu.rename.UndoneMaps 344176228 # Number of HB maps that are undone due to squashing 141system.cpu.rename.serializingInsts 52668 # count of serializing insts renamed 142system.cpu.rename.tempSerializingInsts 52665 # count of temporary serializing insts renamed 143system.cpu.rename.skidInsts 12854506 # count of insts added to the skid buffer 144system.cpu.memDep0.insertedLoads 43974668 # Number of loads inserted to the mem dependence unit. 145system.cpu.memDep0.insertedStores 16894662 # Number of stores inserted to the mem dependence unit. 146system.cpu.memDep0.conflictingLoads 5833133 # Number of conflicting loads. 147system.cpu.memDep0.conflictingStores 3767851 # Number of conflicting stores. 148system.cpu.iq.iqInstsAdded 334792286 # Number of instructions added to the IQ (excludes non-spec) 149system.cpu.iq.iqNonSpecInstsAdded 74530 # Number of non-speculative instructions added to the IQ 150system.cpu.iq.iqInstsIssued 252791404 # Number of instructions issued 151system.cpu.iq.iqSquashedInstsIssued 896561 # Number of squashed instructions issued 152system.cpu.iq.iqSquashedInstsExamined 144952187 # Number of squashed instructions iterated over during squash; mainly for profiling 153system.cpu.iq.iqSquashedOperandsExamined 373840168 # Number of squashed operands that are examined and possibly removed from graph 154system.cpu.iq.iqSquashedNonSpecRemoved 23248 # Number of squashed non-spec instructions that were removed 155system.cpu.iq.issued_per_cycle::samples 151974828 # Number of insts issued each cycle 156system.cpu.iq.issued_per_cycle::mean 1.663377 # Number of insts issued each cycle 157system.cpu.iq.issued_per_cycle::stdev 1.758905 # Number of insts issued each cycle | 112system.cpu.fetch.rateDist::total 151978869 # Number of instructions fetched each cycle (Total) 113system.cpu.fetch.branchRate 0.637059 # Number of branch fetches per cycle 114system.cpu.fetch.rate 2.554555 # Number of inst fetches per cycle 115system.cpu.decode.IdleCycles 46697521 # Number of cycles decode is idle 116system.cpu.decode.BlockedCycles 5834788 # Number of cycles decode is blocked 117system.cpu.decode.RunCycles 76594287 # Number of cycles decode is running 118system.cpu.decode.UnblockCycles 1116884 # Number of cycles decode is unblocking 119system.cpu.decode.SquashCycles 21735389 # Number of cycles decode is squashing 120system.cpu.decode.BranchResolved 14843189 # Number of times decode resolved a branch 121system.cpu.decode.BranchMispred 162820 # Number of times decode detected a branch misprediction 122system.cpu.decode.DecodedInsts 401520259 # Number of instructions handled by decode 123system.cpu.decode.SquashedInsts 676254 # Number of squashed instructions handled by decode 124system.cpu.rename.SquashCycles 21735389 # Number of cycles rename is squashing 125system.cpu.rename.IdleCycles 52210117 # Number of cycles rename is idle 126system.cpu.rename.BlockCycles 723485 # Number of cycles rename is blocking 127system.cpu.rename.serializeStallCycles 695226 # count of cycles rename stalled for serializing inst 128system.cpu.rename.RunCycles 72137663 # Number of cycles rename is running 129system.cpu.rename.UnblockCycles 4476989 # Number of cycles rename is unblocking 130system.cpu.rename.RenamedInsts 379210260 # Number of instructions processed by rename 131system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full 132system.cpu.rename.IQFullEvents 320036 # Number of times rename has blocked due to IQ full 133system.cpu.rename.LSQFullEvents 3584710 # Number of times rename has blocked due to LSQ full 134system.cpu.rename.RenamedOperands 642738695 # Number of destination operands rename has renamed 135system.cpu.rename.RenameLookups 1615361151 # Number of register rename lookups that rename has made 136system.cpu.rename.int_rename_lookups 1597815620 # Number of integer rename lookups 137system.cpu.rename.fp_rename_lookups 17545531 # Number of floating rename lookups 138system.cpu.rename.CommittedMaps 298092371 # Number of HB maps that are committed 139system.cpu.rename.UndoneMaps 344646324 # Number of HB maps that are undone due to squashing 140system.cpu.rename.serializingInsts 33437 # count of serializing insts renamed 141system.cpu.rename.tempSerializingInsts 33435 # count of temporary serializing insts renamed 142system.cpu.rename.skidInsts 12677945 # count of insts added to the skid buffer 143system.cpu.memDep0.insertedLoads 44005038 # Number of loads inserted to the mem dependence unit. 144system.cpu.memDep0.insertedStores 16906133 # Number of stores inserted to the mem dependence unit. 145system.cpu.memDep0.conflictingLoads 5806665 # Number of conflicting loads. 146system.cpu.memDep0.conflictingStores 3723076 # Number of conflicting stores. 147system.cpu.iq.iqInstsAdded 335023972 # Number of instructions added to the IQ (excludes non-spec) 148system.cpu.iq.iqNonSpecInstsAdded 55533 # Number of non-speculative instructions added to the IQ 149system.cpu.iq.iqInstsIssued 252928025 # Number of instructions issued 150system.cpu.iq.iqSquashedInstsIssued 900898 # Number of squashed instructions issued 151system.cpu.iq.iqSquashedInstsExamined 145168889 # Number of squashed instructions iterated over during squash; mainly for profiling 152system.cpu.iq.iqSquashedOperandsExamined 374298631 # Number of squashed operands that are examined and possibly removed from graph 153system.cpu.iq.iqSquashedNonSpecRemoved 4288 # Number of squashed non-spec instructions that were removed 154system.cpu.iq.issued_per_cycle::samples 151978869 # Number of insts issued each cycle 155system.cpu.iq.issued_per_cycle::mean 1.664232 # Number of insts issued each cycle 156system.cpu.iq.issued_per_cycle::stdev 1.759052 # Number of insts issued each cycle |
| 158system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 157system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 159system.cpu.iq.issued_per_cycle::0 58489364 38.49% 38.49% # Number of insts issued each cycle 160system.cpu.iq.issued_per_cycle::1 23011540 15.14% 53.63% # Number of insts issued each cycle 161system.cpu.iq.issued_per_cycle::2 25193746 16.58% 70.21% # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::3 20486028 13.48% 83.69% # Number of insts issued each cycle 163system.cpu.iq.issued_per_cycle::4 12864515 8.46% 92.15% # Number of insts issued each cycle 164system.cpu.iq.issued_per_cycle::5 6577319 4.33% 96.48% # Number of insts issued each cycle 165system.cpu.iq.issued_per_cycle::6 4059001 2.67% 99.15% # Number of insts issued each cycle 166system.cpu.iq.issued_per_cycle::7 1110893 0.73% 99.88% # Number of insts issued each cycle 167system.cpu.iq.issued_per_cycle::8 182422 0.12% 100.00% # Number of insts issued each cycle | 158system.cpu.iq.issued_per_cycle::0 58441388 38.45% 38.45% # Number of insts issued each cycle 159system.cpu.iq.issued_per_cycle::1 23049169 15.17% 53.62% # Number of insts issued each cycle 160system.cpu.iq.issued_per_cycle::2 25167243 16.56% 70.18% # Number of insts issued each cycle 161system.cpu.iq.issued_per_cycle::3 20506081 13.49% 83.67% # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::4 12879623 8.47% 92.15% # Number of insts issued each cycle 163system.cpu.iq.issued_per_cycle::5 6582625 4.33% 96.48% # Number of insts issued each cycle 164system.cpu.iq.issued_per_cycle::6 4058401 2.67% 99.15% # Number of insts issued each cycle 165system.cpu.iq.issued_per_cycle::7 1110608 0.73% 99.88% # Number of insts issued each cycle 166system.cpu.iq.issued_per_cycle::8 183731 0.12% 100.00% # Number of insts issued each cycle |
| 168system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 169system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 170system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 167system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 168system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 169system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 171system.cpu.iq.issued_per_cycle::total 151974828 # Number of insts issued each cycle | 170system.cpu.iq.issued_per_cycle::total 151978869 # Number of insts issued each cycle |
| 172system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 171system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 173system.cpu.iq.fu_full::IntAlu 966666 37.58% 37.58% # attempts to use FU when none available 174system.cpu.iq.fu_full::IntMult 5596 0.22% 37.80% # attempts to use FU when none available 175system.cpu.iq.fu_full::IntDiv 0 0.00% 37.80% # attempts to use FU when none available 176system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.80% # attempts to use FU when none available 177system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.80% # attempts to use FU when none available 178system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.80% # attempts to use FU when none available 179system.cpu.iq.fu_full::FloatMult 0 0.00% 37.80% # attempts to use FU when none available 180system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.80% # attempts to use FU when none available 181system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.80% # attempts to use FU when none available 182system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.80% # attempts to use FU when none available 183system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.80% # attempts to use FU when none available 184system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.80% # attempts to use FU when none available 185system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.80% # attempts to use FU when none available 186system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.80% # attempts to use FU when none available 187system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.80% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdMult 0 0.00% 37.80% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.80% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdShift 0 0.00% 37.80% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.80% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.80% # attempts to use FU when none available 193system.cpu.iq.fu_full::SimdFloatAdd 136 0.01% 37.81% # attempts to use FU when none available 194system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.81% # attempts to use FU when none available 195system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.81% # attempts to use FU when none available 196system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 37.81% # attempts to use FU when none available 197system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.81% # attempts to use FU when none available 198system.cpu.iq.fu_full::SimdFloatMisc 25 0.00% 37.81% # attempts to use FU when none available 199system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.81% # attempts to use FU when none available 200system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.81% # attempts to use FU when none available 201system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.81% # attempts to use FU when none available 202system.cpu.iq.fu_full::MemRead 1199658 46.64% 84.45% # attempts to use FU when none available 203system.cpu.iq.fu_full::MemWrite 400010 15.55% 100.00% # attempts to use FU when none available | 172system.cpu.iq.fu_full::IntAlu 958151 37.34% 37.34% # attempts to use FU when none available 173system.cpu.iq.fu_full::IntMult 5590 0.22% 37.56% # attempts to use FU when none available 174system.cpu.iq.fu_full::IntDiv 0 0.00% 37.56% # attempts to use FU when none available 175system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.56% # attempts to use FU when none available 176system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.56% # attempts to use FU when none available 177system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.56% # attempts to use FU when none available 178system.cpu.iq.fu_full::FloatMult 0 0.00% 37.56% # attempts to use FU when none available 179system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.56% # attempts to use FU when none available 180system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.56% # attempts to use FU when none available 181system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.56% # attempts to use FU when none available 182system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.56% # attempts to use FU when none available 183system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.56% # attempts to use FU when none available 184system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.56% # attempts to use FU when none available 185system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.56% # attempts to use FU when none available 186system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.56% # attempts to use FU when none available 187system.cpu.iq.fu_full::SimdMult 0 0.00% 37.56% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.56% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdShift 0 0.00% 37.56% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.56% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.56% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdFloatAdd 95 0.00% 37.57% # attempts to use FU when none available 193system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.57% # attempts to use FU when none available 194system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.57% # attempts to use FU when none available 195system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 37.57% # attempts to use FU when none available 196system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.57% # attempts to use FU when none available 197system.cpu.iq.fu_full::SimdFloatMisc 28 0.00% 37.57% # attempts to use FU when none available 198system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.57% # attempts to use FU when none available 199system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.57% # attempts to use FU when none available 200system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.57% # attempts to use FU when none available 201system.cpu.iq.fu_full::MemRead 1196632 46.64% 84.21% # attempts to use FU when none available 202system.cpu.iq.fu_full::MemWrite 405192 15.79% 100.00% # attempts to use FU when none available |
| 204system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 205system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 206system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 203system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 204system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 205system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 207system.cpu.iq.FU_type_0::IntAlu 197331718 78.06% 78.06% # Type of FU issued 208system.cpu.iq.FU_type_0::IntMult 995910 0.39% 78.46% # Type of FU issued 209system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.46% # Type of FU issued 210system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.46% # Type of FU issued 211system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.46% # Type of FU issued 212system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.46% # Type of FU issued 213system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.46% # Type of FU issued 214system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.46% # Type of FU issued 215system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.46% # Type of FU issued 216system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.46% # Type of FU issued 217system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.46% # Type of FU issued 218system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.46% # Type of FU issued 219system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.46% # Type of FU issued 220system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.46% # Type of FU issued 221system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.46% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.46% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.46% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.46% # Type of FU issued 225system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.46% # Type of FU issued 226system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.46% # Type of FU issued 227system.cpu.iq.FU_type_0::SimdFloatAdd 33152 0.01% 78.47% # Type of FU issued 228system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.47% # Type of FU issued 229system.cpu.iq.FU_type_0::SimdFloatCmp 164284 0.06% 78.53% # Type of FU issued 230system.cpu.iq.FU_type_0::SimdFloatCvt 255235 0.10% 78.63% # Type of FU issued 231system.cpu.iq.FU_type_0::SimdFloatDiv 76457 0.03% 78.66% # Type of FU issued 232system.cpu.iq.FU_type_0::SimdFloatMisc 467994 0.19% 78.85% # Type of FU issued 233system.cpu.iq.FU_type_0::SimdFloatMult 206483 0.08% 78.93% # Type of FU issued 234system.cpu.iq.FU_type_0::SimdFloatMultAcc 71867 0.03% 78.96% # Type of FU issued 235system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 78.96% # Type of FU issued 236system.cpu.iq.FU_type_0::MemRead 38997717 15.43% 94.39% # Type of FU issued 237system.cpu.iq.FU_type_0::MemWrite 14190267 5.61% 100.00% # Type of FU issued | 206system.cpu.iq.FU_type_0::IntAlu 197423347 78.06% 78.06% # Type of FU issued 207system.cpu.iq.FU_type_0::IntMult 995576 0.39% 78.45% # Type of FU issued 208system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.45% # Type of FU issued 209system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.45% # Type of FU issued 210system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.45% # Type of FU issued 211system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.45% # Type of FU issued 212system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.45% # Type of FU issued 213system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.45% # Type of FU issued 214system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.45% # Type of FU issued 215system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.45% # Type of FU issued 216system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.45% # Type of FU issued 217system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.45% # Type of FU issued 218system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.45% # Type of FU issued 219system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.45% # Type of FU issued 220system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.45% # Type of FU issued 221system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.45% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.45% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.45% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.45% # Type of FU issued 225system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.45% # Type of FU issued 226system.cpu.iq.FU_type_0::SimdFloatAdd 33202 0.01% 78.46% # Type of FU issued 227system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.46% # Type of FU issued 228system.cpu.iq.FU_type_0::SimdFloatCmp 163925 0.06% 78.53% # Type of FU issued 229system.cpu.iq.FU_type_0::SimdFloatCvt 254716 0.10% 78.63% # Type of FU issued 230system.cpu.iq.FU_type_0::SimdFloatDiv 76426 0.03% 78.66% # Type of FU issued 231system.cpu.iq.FU_type_0::SimdFloatMisc 467079 0.18% 78.84% # Type of FU issued 232system.cpu.iq.FU_type_0::SimdFloatMult 206343 0.08% 78.92% # Type of FU issued 233system.cpu.iq.FU_type_0::SimdFloatMultAcc 71849 0.03% 78.95% # Type of FU issued 234system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.95% # Type of FU issued 235system.cpu.iq.FU_type_0::MemRead 39030082 15.43% 94.38% # Type of FU issued 236system.cpu.iq.FU_type_0::MemWrite 14205161 5.62% 100.00% # Type of FU issued |
| 238system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 239system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 237system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 238system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 240system.cpu.iq.FU_type_0::total 252791404 # Type of FU issued 241system.cpu.iq.rate 1.662714 # Inst issue rate 242system.cpu.iq.fu_busy_cnt 2572091 # FU busy when requested 243system.cpu.iq.fu_busy_rate 0.010175 # FU busy rate (busy events/executed inst) 244system.cpu.iq.int_inst_queue_reads 657257029 # Number of integer instruction queue reads 245system.cpu.iq.int_inst_queue_writes 477588320 # Number of integer instruction queue writes 246system.cpu.iq.int_inst_queue_wakeup_accesses 240562315 # Number of integer instruction queue wakeup accesses 247system.cpu.iq.fp_inst_queue_reads 3769259 # Number of floating instruction queue reads 248system.cpu.iq.fp_inst_queue_writes 2249868 # Number of floating instruction queue writes 249system.cpu.iq.fp_inst_queue_wakeup_accesses 1852626 # Number of floating instruction queue wakeup accesses 250system.cpu.iq.int_alu_accesses 253473620 # Number of integer alu accesses 251system.cpu.iq.fp_alu_accesses 1889875 # Number of floating point alu accesses 252system.cpu.iew.lsq.thread0.forwLoads 2022881 # Number of loads that had data forwarded from stores | 239system.cpu.iq.FU_type_0::total 252928025 # Type of FU issued 240system.cpu.iq.rate 1.663561 # Inst issue rate 241system.cpu.iq.fu_busy_cnt 2565688 # FU busy when requested 242system.cpu.iq.fu_busy_rate 0.010144 # FU busy rate (busy events/executed inst) 243system.cpu.iq.int_inst_queue_reads 657530631 # Number of integer instruction queue reads 244system.cpu.iq.int_inst_queue_writes 478025695 # Number of integer instruction queue writes 245system.cpu.iq.int_inst_queue_wakeup_accesses 240682393 # Number of integer instruction queue wakeup accesses 246system.cpu.iq.fp_inst_queue_reads 3770874 # Number of floating instruction queue reads 247system.cpu.iq.fp_inst_queue_writes 2241416 # Number of floating instruction queue writes 248system.cpu.iq.fp_inst_queue_wakeup_accesses 1850793 # Number of floating instruction queue wakeup accesses 249system.cpu.iq.int_alu_accesses 253600335 # Number of integer alu accesses 250system.cpu.iq.fp_alu_accesses 1893378 # Number of floating point alu accesses 251system.cpu.iew.lsq.thread0.forwLoads 2031332 # Number of loads that had data forwarded from stores |
| 253system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 252system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 254system.cpu.iew.lsq.thread0.squashedLoads 14119118 # Number of loads squashed 255system.cpu.iew.lsq.thread0.ignoredResponses 17181 # Number of memory responses ignored because the instruction is squashed 256system.cpu.iew.lsq.thread0.memOrderViolation 19942 # Number of memory ordering violations 257system.cpu.iew.lsq.thread0.squashedStores 4243962 # Number of stores squashed | 253system.cpu.iew.lsq.thread0.squashedLoads 14149525 # Number of loads squashed 254system.cpu.iew.lsq.thread0.ignoredResponses 17193 # Number of memory responses ignored because the instruction is squashed 255system.cpu.iew.lsq.thread0.memOrderViolation 19478 # Number of memory ordering violations 256system.cpu.iew.lsq.thread0.squashedStores 4255470 # Number of stores squashed |
| 258system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 259system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 257system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 258system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 260system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled | 259system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled |
| 261system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 262system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 260system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 261system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 263system.cpu.iew.iewSquashCycles 21725546 # Number of cycles IEW is squashing 264system.cpu.iew.iewBlockCycles 15871 # Number of cycles IEW is blocking | 262system.cpu.iew.iewSquashCycles 21735389 # Number of cycles IEW is squashing 263system.cpu.iew.iewBlockCycles 15851 # Number of cycles IEW is blocking |
| 265system.cpu.iew.iewUnblockCycles 654 # Number of cycles IEW is unblocking | 264system.cpu.iew.iewUnblockCycles 654 # Number of cycles IEW is unblocking |
| 266system.cpu.iew.iewDispatchedInsts 334925114 # Number of instructions dispatched to IQ 267system.cpu.iew.iewDispSquashedInsts 838955 # Number of squashed instructions skipped by dispatch 268system.cpu.iew.iewDispLoadInsts 43974668 # Number of dispatched load instructions 269system.cpu.iew.iewDispStoreInsts 16894662 # Number of dispatched store instructions 270system.cpu.iew.iewDispNonSpecInsts 51980 # Number of dispatched non-speculative instructions 271system.cpu.iew.iewIQFullEvents 159 # Number of times the IQ has become full, causing a stall | 265system.cpu.iew.iewDispatchedInsts 335097391 # Number of instructions dispatched to IQ 266system.cpu.iew.iewDispSquashedInsts 841360 # Number of squashed instructions skipped by dispatch 267system.cpu.iew.iewDispLoadInsts 44005038 # Number of dispatched load instructions 268system.cpu.iew.iewDispStoreInsts 16906133 # Number of dispatched store instructions 269system.cpu.iew.iewDispNonSpecInsts 32986 # Number of dispatched non-speculative instructions 270system.cpu.iew.iewIQFullEvents 165 # Number of times the IQ has become full, causing a stall |
| 272system.cpu.iew.iewLSQFullEvents 265 # Number of times the LSQ has become full, causing a stall | 271system.cpu.iew.iewLSQFullEvents 265 # Number of times the LSQ has become full, causing a stall |
| 273system.cpu.iew.memOrderViolationEvents 19942 # Number of memory order violations 274system.cpu.iew.predictedTakenIncorrect 4105078 # Number of branches that were predicted taken incorrectly 275system.cpu.iew.predictedNotTakenIncorrect 3945464 # Number of branches that were predicted not taken incorrectly 276system.cpu.iew.branchMispredicts 8050542 # Number of branch mispredicts detected at execute 277system.cpu.iew.iewExecutedInsts 245797206 # Number of executed instructions 278system.cpu.iew.iewExecLoadInsts 37379001 # Number of load instructions executed 279system.cpu.iew.iewExecSquashedInsts 6994198 # Number of squashed instructions skipped in execute | 272system.cpu.iew.memOrderViolationEvents 19478 # Number of memory order violations 273system.cpu.iew.predictedTakenIncorrect 4108816 # Number of branches that were predicted taken incorrectly 274system.cpu.iew.predictedNotTakenIncorrect 3932770 # Number of branches that were predicted not taken incorrectly 275system.cpu.iew.branchMispredicts 8041586 # Number of branch mispredicts detected at execute 276system.cpu.iew.iewExecutedInsts 245927260 # Number of executed instructions 277system.cpu.iew.iewExecLoadInsts 37410682 # Number of load instructions executed 278system.cpu.iew.iewExecSquashedInsts 7000765 # Number of squashed instructions skipped in execute |
| 280system.cpu.iew.exec_swp 0 # number of swp insts executed | 279system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 281system.cpu.iew.exec_nop 58298 # number of nop insts executed 282system.cpu.iew.exec_refs 51189045 # number of memory reference insts executed 283system.cpu.iew.exec_branches 54004994 # Number of branches executed 284system.cpu.iew.exec_stores 13810044 # Number of stores executed 285system.cpu.iew.exec_rate 1.616710 # Inst execution rate 286system.cpu.iew.wb_sent 243546363 # cumulative count of insts sent to commit 287system.cpu.iew.wb_count 242414941 # cumulative count of insts written-back 288system.cpu.iew.wb_producers 150055684 # num instructions producing a value 289system.cpu.iew.wb_consumers 269132262 # num instructions consuming a value | 280system.cpu.iew.exec_nop 17886 # number of nop insts executed 281system.cpu.iew.exec_refs 51227779 # number of memory reference insts executed 282system.cpu.iew.exec_branches 54055496 # Number of branches executed 283system.cpu.iew.exec_stores 13817097 # Number of stores executed 284system.cpu.iew.exec_rate 1.617515 # Inst execution rate 285system.cpu.iew.wb_sent 243665877 # cumulative count of insts sent to commit 286system.cpu.iew.wb_count 242533186 # cumulative count of insts written-back 287system.cpu.iew.wb_producers 150106940 # num instructions producing a value 288system.cpu.iew.wb_consumers 269220391 # num instructions consuming a value |
| 290system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 289system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 291system.cpu.iew.wb_rate 1.594464 # insts written-back per cycle 292system.cpu.iew.wb_fanout 0.557554 # average fanout of values written-back | 290system.cpu.iew.wb_rate 1.595192 # insts written-back per cycle 291system.cpu.iew.wb_fanout 0.557562 # average fanout of values written-back |
| 293system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 292system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 294system.cpu.commit.commitSquashedInsts 146223871 # The number of squashed insts skipped by commit 295system.cpu.commit.commitNonSpecStalls 51282 # The number of times commit has been forced to stall to communicate backwards 296system.cpu.commit.branchMispredicts 6420079 # The number of times a branch was mispredicted 297system.cpu.commit.committed_per_cycle::samples 130249283 # Number of insts commited each cycle 298system.cpu.commit.committed_per_cycle::mean 1.448770 # Number of insts commited each cycle 299system.cpu.commit.committed_per_cycle::stdev 2.161298 # Number of insts commited each cycle | 293system.cpu.commit.commitSquashedInsts 146396335 # The number of squashed insts skipped by commit 294system.cpu.commit.commitNonSpecStalls 51245 # The number of times commit has been forced to stall to communicate backwards 295system.cpu.commit.branchMispredicts 6410682 # The number of times a branch was mispredicted 296system.cpu.commit.committed_per_cycle::samples 130243481 # Number of insts commited each cycle 297system.cpu.commit.committed_per_cycle::mean 1.448833 # Number of insts commited each cycle 298system.cpu.commit.committed_per_cycle::stdev 2.161152 # Number of insts commited each cycle |
| 300system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 299system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 301system.cpu.commit.committed_per_cycle::0 60006705 46.07% 46.07% # Number of insts commited each cycle 302system.cpu.commit.committed_per_cycle::1 32087583 24.64% 70.71% # Number of insts commited each cycle 303system.cpu.commit.committed_per_cycle::2 13984606 10.74% 81.44% # Number of insts commited each cycle 304system.cpu.commit.committed_per_cycle::3 7660285 5.88% 87.32% # Number of insts commited each cycle 305system.cpu.commit.committed_per_cycle::4 4414959 3.39% 90.71% # Number of insts commited each cycle 306system.cpu.commit.committed_per_cycle::5 1331514 1.02% 91.74% # Number of insts commited each cycle 307system.cpu.commit.committed_per_cycle::6 1740633 1.34% 93.07% # Number of insts commited each cycle 308system.cpu.commit.committed_per_cycle::7 1281617 0.98% 94.06% # Number of insts commited each cycle 309system.cpu.commit.committed_per_cycle::8 7741381 5.94% 100.00% # Number of insts commited each cycle | 300system.cpu.commit.committed_per_cycle::0 59985952 46.06% 46.06% # Number of insts commited each cycle 301system.cpu.commit.committed_per_cycle::1 32109376 24.65% 70.71% # Number of insts commited each cycle 302system.cpu.commit.committed_per_cycle::2 13980234 10.73% 81.44% # Number of insts commited each cycle 303system.cpu.commit.committed_per_cycle::3 7652770 5.88% 87.32% # Number of insts commited each cycle 304system.cpu.commit.committed_per_cycle::4 4424001 3.40% 90.72% # Number of insts commited each cycle 305system.cpu.commit.committed_per_cycle::5 1333573 1.02% 91.74% # Number of insts commited each cycle 306system.cpu.commit.committed_per_cycle::6 1734640 1.33% 93.07% # Number of insts commited each cycle 307system.cpu.commit.committed_per_cycle::7 1282307 0.98% 94.06% # Number of insts commited each cycle 308system.cpu.commit.committed_per_cycle::8 7740628 5.94% 100.00% # Number of insts commited each cycle |
| 310system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 311system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 312system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 309system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 310system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 311system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 313system.cpu.commit.committed_per_cycle::total 130249283 # Number of insts commited each cycle 314system.cpu.commit.committedInsts 172347739 # Number of instructions committed 315system.cpu.commit.committedOps 188701221 # Number of ops (including micro ops) committed | 312system.cpu.commit.committed_per_cycle::total 130243481 # Number of insts commited each cycle 313system.cpu.commit.committedInsts 172347554 # Number of instructions committed 314system.cpu.commit.committedOps 188701036 # Number of ops (including micro ops) committed |
| 316system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 315system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 317system.cpu.commit.refs 42506250 # Number of memory references committed 318system.cpu.commit.loads 29855550 # Number of loads committed | 316system.cpu.commit.refs 42506176 # Number of memory references committed 317system.cpu.commit.loads 29855513 # Number of loads committed |
| 319system.cpu.commit.membars 22408 # Number of memory barriers committed | 318system.cpu.commit.membars 22408 # Number of memory barriers committed |
| 320system.cpu.commit.branches 40287748 # Number of branches committed | 319system.cpu.commit.branches 40306340 # Number of branches committed |
| 321system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. | 320system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. |
| 322system.cpu.commit.int_insts 150130481 # Number of committed integer instructions. | 321system.cpu.commit.int_insts 150130333 # Number of committed integer instructions. |
| 323system.cpu.commit.function_calls 1848934 # Number of function calls committed. | 322system.cpu.commit.function_calls 1848934 # Number of function calls committed. |
| 324system.cpu.commit.bw_lim_events 7741381 # number cycles where commit BW limit reached | 323system.cpu.commit.bw_lim_events 7740628 # number cycles where commit BW limit reached |
| 325system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 324system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 326system.cpu.rob.rob_reads 457427793 # The number of ROB reads 327system.cpu.rob.rob_writes 691694403 # The number of ROB writes 328system.cpu.timesIdled 1790 # Number of times that the entire CPU went into an idle state and unscheduled itself 329system.cpu.idleCycles 60597 # Total number of cycles that the CPU has spent unscheduled due to idling 330system.cpu.committedInsts 172333351 # Number of Instructions Simulated 331system.cpu.committedOps 188686833 # Number of Ops (including micro ops) Simulated 332system.cpu.committedInsts_total 172333351 # Number of Instructions Simulated 333system.cpu.cpi 0.882217 # CPI: Cycles Per Instruction 334system.cpu.cpi_total 0.882217 # CPI: Total CPI of All Threads 335system.cpu.ipc 1.133508 # IPC: Instructions Per Cycle 336system.cpu.ipc_total 1.133508 # IPC: Total IPC of All Threads 337system.cpu.int_regfile_reads 1091781968 # number of integer regfile reads 338system.cpu.int_regfile_writes 388588148 # number of integer regfile writes 339system.cpu.fp_regfile_reads 2914249 # number of floating regfile reads 340system.cpu.fp_regfile_writes 2512479 # number of floating regfile writes 341system.cpu.misc_regfile_reads 474590594 # number of misc regfile reads 342system.cpu.misc_regfile_writes 832168 # number of misc regfile writes 343system.cpu.icache.replacements 2661 # number of replacements 344system.cpu.icache.tagsinuse 1361.223505 # Cycle average of tags in use 345system.cpu.icache.total_refs 37640447 # Total number of references to valid blocks. 346system.cpu.icache.sampled_refs 4399 # Sample count of references to valid blocks. 347system.cpu.icache.avg_refs 8556.591725 # Average number of references to valid blocks. | 325system.cpu.rob.rob_reads 457595023 # The number of ROB reads 326system.cpu.rob.rob_writes 692049675 # The number of ROB writes 327system.cpu.timesIdled 1805 # Number of times that the entire CPU went into an idle state and unscheduled itself 328system.cpu.idleCycles 61296 # Total number of cycles that the CPU has spent unscheduled due to idling 329system.cpu.committedInsts 172333166 # Number of Instructions Simulated 330system.cpu.committedOps 188686648 # Number of Ops (including micro ops) Simulated 331system.cpu.committedInsts_total 172333166 # Number of Instructions Simulated 332system.cpu.cpi 0.882246 # CPI: Cycles Per Instruction 333system.cpu.cpi_total 0.882246 # CPI: Total CPI of All Threads 334system.cpu.ipc 1.133471 # IPC: Instructions Per Cycle 335system.cpu.ipc_total 1.133471 # IPC: Total IPC of All Threads 336system.cpu.int_regfile_reads 1092342028 # number of integer regfile reads 337system.cpu.int_regfile_writes 388769433 # number of integer regfile writes 338system.cpu.fp_regfile_reads 2911784 # number of floating regfile reads 339system.cpu.fp_regfile_writes 2509539 # number of floating regfile writes 340system.cpu.misc_regfile_reads 474699170 # number of misc regfile reads 341system.cpu.misc_regfile_writes 832094 # number of misc regfile writes 342system.cpu.icache.replacements 2665 # number of replacements 343system.cpu.icache.tagsinuse 1365.695198 # Cycle average of tags in use 344system.cpu.icache.total_refs 37710725 # Total number of references to valid blocks. 345system.cpu.icache.sampled_refs 4406 # Sample count of references to valid blocks. 346system.cpu.icache.avg_refs 8558.948025 # Average number of references to valid blocks. |
| 348system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 347system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 349system.cpu.icache.occ_blocks::cpu.inst 1361.223505 # Average occupied blocks per requestor 350system.cpu.icache.occ_percent::cpu.inst 0.664660 # Average percentage of cache occupancy 351system.cpu.icache.occ_percent::total 0.664660 # Average percentage of cache occupancy 352system.cpu.icache.ReadReq_hits::cpu.inst 37640447 # number of ReadReq hits 353system.cpu.icache.ReadReq_hits::total 37640447 # number of ReadReq hits 354system.cpu.icache.demand_hits::cpu.inst 37640447 # number of demand (read+write) hits 355system.cpu.icache.demand_hits::total 37640447 # number of demand (read+write) hits 356system.cpu.icache.overall_hits::cpu.inst 37640447 # number of overall hits 357system.cpu.icache.overall_hits::total 37640447 # number of overall hits 358system.cpu.icache.ReadReq_misses::cpu.inst 5186 # number of ReadReq misses 359system.cpu.icache.ReadReq_misses::total 5186 # number of ReadReq misses 360system.cpu.icache.demand_misses::cpu.inst 5186 # number of demand (read+write) misses 361system.cpu.icache.demand_misses::total 5186 # number of demand (read+write) misses 362system.cpu.icache.overall_misses::cpu.inst 5186 # number of overall misses 363system.cpu.icache.overall_misses::total 5186 # number of overall misses 364system.cpu.icache.ReadReq_miss_latency::cpu.inst 114498500 # number of ReadReq miss cycles 365system.cpu.icache.ReadReq_miss_latency::total 114498500 # number of ReadReq miss cycles 366system.cpu.icache.demand_miss_latency::cpu.inst 114498500 # number of demand (read+write) miss cycles 367system.cpu.icache.demand_miss_latency::total 114498500 # number of demand (read+write) miss cycles 368system.cpu.icache.overall_miss_latency::cpu.inst 114498500 # number of overall miss cycles 369system.cpu.icache.overall_miss_latency::total 114498500 # number of overall miss cycles 370system.cpu.icache.ReadReq_accesses::cpu.inst 37645633 # number of ReadReq accesses(hits+misses) 371system.cpu.icache.ReadReq_accesses::total 37645633 # number of ReadReq accesses(hits+misses) 372system.cpu.icache.demand_accesses::cpu.inst 37645633 # number of demand (read+write) accesses 373system.cpu.icache.demand_accesses::total 37645633 # number of demand (read+write) accesses 374system.cpu.icache.overall_accesses::cpu.inst 37645633 # number of overall (read+write) accesses 375system.cpu.icache.overall_accesses::total 37645633 # number of overall (read+write) accesses | 348system.cpu.icache.occ_blocks::cpu.inst 1365.695198 # Average occupied blocks per requestor 349system.cpu.icache.occ_percent::cpu.inst 0.666843 # Average percentage of cache occupancy 350system.cpu.icache.occ_percent::total 0.666843 # Average percentage of cache occupancy 351system.cpu.icache.ReadReq_hits::cpu.inst 37710725 # number of ReadReq hits 352system.cpu.icache.ReadReq_hits::total 37710725 # number of ReadReq hits 353system.cpu.icache.demand_hits::cpu.inst 37710725 # number of demand (read+write) hits 354system.cpu.icache.demand_hits::total 37710725 # number of demand (read+write) hits 355system.cpu.icache.overall_hits::cpu.inst 37710725 # number of overall hits 356system.cpu.icache.overall_hits::total 37710725 # number of overall hits 357system.cpu.icache.ReadReq_misses::cpu.inst 5196 # number of ReadReq misses 358system.cpu.icache.ReadReq_misses::total 5196 # number of ReadReq misses 359system.cpu.icache.demand_misses::cpu.inst 5196 # number of demand (read+write) misses 360system.cpu.icache.demand_misses::total 5196 # number of demand (read+write) misses 361system.cpu.icache.overall_misses::cpu.inst 5196 # number of overall misses 362system.cpu.icache.overall_misses::total 5196 # number of overall misses 363system.cpu.icache.ReadReq_miss_latency::cpu.inst 114882000 # number of ReadReq miss cycles 364system.cpu.icache.ReadReq_miss_latency::total 114882000 # number of ReadReq miss cycles 365system.cpu.icache.demand_miss_latency::cpu.inst 114882000 # number of demand (read+write) miss cycles 366system.cpu.icache.demand_miss_latency::total 114882000 # number of demand (read+write) miss cycles 367system.cpu.icache.overall_miss_latency::cpu.inst 114882000 # number of overall miss cycles 368system.cpu.icache.overall_miss_latency::total 114882000 # number of overall miss cycles 369system.cpu.icache.ReadReq_accesses::cpu.inst 37715921 # number of ReadReq accesses(hits+misses) 370system.cpu.icache.ReadReq_accesses::total 37715921 # number of ReadReq accesses(hits+misses) 371system.cpu.icache.demand_accesses::cpu.inst 37715921 # number of demand (read+write) accesses 372system.cpu.icache.demand_accesses::total 37715921 # number of demand (read+write) accesses 373system.cpu.icache.overall_accesses::cpu.inst 37715921 # number of overall (read+write) accesses 374system.cpu.icache.overall_accesses::total 37715921 # number of overall (read+write) accesses |
| 376system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000138 # miss rate for ReadReq accesses 377system.cpu.icache.ReadReq_miss_rate::total 0.000138 # miss rate for ReadReq accesses 378system.cpu.icache.demand_miss_rate::cpu.inst 0.000138 # miss rate for demand accesses 379system.cpu.icache.demand_miss_rate::total 0.000138 # miss rate for demand accesses 380system.cpu.icache.overall_miss_rate::cpu.inst 0.000138 # miss rate for overall accesses 381system.cpu.icache.overall_miss_rate::total 0.000138 # miss rate for overall accesses | 375system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000138 # miss rate for ReadReq accesses 376system.cpu.icache.ReadReq_miss_rate::total 0.000138 # miss rate for ReadReq accesses 377system.cpu.icache.demand_miss_rate::cpu.inst 0.000138 # miss rate for demand accesses 378system.cpu.icache.demand_miss_rate::total 0.000138 # miss rate for demand accesses 379system.cpu.icache.overall_miss_rate::cpu.inst 0.000138 # miss rate for overall accesses 380system.cpu.icache.overall_miss_rate::total 0.000138 # miss rate for overall accesses |
| 382system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22078.384111 # average ReadReq miss latency 383system.cpu.icache.ReadReq_avg_miss_latency::total 22078.384111 # average ReadReq miss latency 384system.cpu.icache.demand_avg_miss_latency::cpu.inst 22078.384111 # average overall miss latency 385system.cpu.icache.demand_avg_miss_latency::total 22078.384111 # average overall miss latency 386system.cpu.icache.overall_avg_miss_latency::cpu.inst 22078.384111 # average overall miss latency 387system.cpu.icache.overall_avg_miss_latency::total 22078.384111 # average overall miss latency | 381system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22109.699769 # average ReadReq miss latency 382system.cpu.icache.ReadReq_avg_miss_latency::total 22109.699769 # average ReadReq miss latency 383system.cpu.icache.demand_avg_miss_latency::cpu.inst 22109.699769 # average overall miss latency 384system.cpu.icache.demand_avg_miss_latency::total 22109.699769 # average overall miss latency 385system.cpu.icache.overall_avg_miss_latency::cpu.inst 22109.699769 # average overall miss latency 386system.cpu.icache.overall_avg_miss_latency::total 22109.699769 # average overall miss latency |
| 388system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 389system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 390system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 391system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 392system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 393system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 394system.cpu.icache.fast_writes 0 # number of fast writes performed 395system.cpu.icache.cache_copies 0 # number of cache copies performed | 387system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 388system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 389system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 390system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 391system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 392system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 393system.cpu.icache.fast_writes 0 # number of fast writes performed 394system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 396system.cpu.icache.ReadReq_mshr_hits::cpu.inst 786 # number of ReadReq MSHR hits 397system.cpu.icache.ReadReq_mshr_hits::total 786 # number of ReadReq MSHR hits 398system.cpu.icache.demand_mshr_hits::cpu.inst 786 # number of demand (read+write) MSHR hits 399system.cpu.icache.demand_mshr_hits::total 786 # number of demand (read+write) MSHR hits 400system.cpu.icache.overall_mshr_hits::cpu.inst 786 # number of overall MSHR hits 401system.cpu.icache.overall_mshr_hits::total 786 # number of overall MSHR hits 402system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4400 # number of ReadReq MSHR misses 403system.cpu.icache.ReadReq_mshr_misses::total 4400 # number of ReadReq MSHR misses 404system.cpu.icache.demand_mshr_misses::cpu.inst 4400 # number of demand (read+write) MSHR misses 405system.cpu.icache.demand_mshr_misses::total 4400 # number of demand (read+write) MSHR misses 406system.cpu.icache.overall_mshr_misses::cpu.inst 4400 # number of overall MSHR misses 407system.cpu.icache.overall_mshr_misses::total 4400 # number of overall MSHR misses 408system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 80222500 # number of ReadReq MSHR miss cycles 409system.cpu.icache.ReadReq_mshr_miss_latency::total 80222500 # number of ReadReq MSHR miss cycles 410system.cpu.icache.demand_mshr_miss_latency::cpu.inst 80222500 # number of demand (read+write) MSHR miss cycles 411system.cpu.icache.demand_mshr_miss_latency::total 80222500 # number of demand (read+write) MSHR miss cycles 412system.cpu.icache.overall_mshr_miss_latency::cpu.inst 80222500 # number of overall MSHR miss cycles 413system.cpu.icache.overall_mshr_miss_latency::total 80222500 # number of overall MSHR miss cycles | 395system.cpu.icache.ReadReq_mshr_hits::cpu.inst 790 # number of ReadReq MSHR hits 396system.cpu.icache.ReadReq_mshr_hits::total 790 # number of ReadReq MSHR hits 397system.cpu.icache.demand_mshr_hits::cpu.inst 790 # number of demand (read+write) MSHR hits 398system.cpu.icache.demand_mshr_hits::total 790 # number of demand (read+write) MSHR hits 399system.cpu.icache.overall_mshr_hits::cpu.inst 790 # number of overall MSHR hits 400system.cpu.icache.overall_mshr_hits::total 790 # number of overall MSHR hits 401system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4406 # number of ReadReq MSHR misses 402system.cpu.icache.ReadReq_mshr_misses::total 4406 # number of ReadReq MSHR misses 403system.cpu.icache.demand_mshr_misses::cpu.inst 4406 # number of demand (read+write) MSHR misses 404system.cpu.icache.demand_mshr_misses::total 4406 # number of demand (read+write) MSHR misses 405system.cpu.icache.overall_mshr_misses::cpu.inst 4406 # number of overall MSHR misses 406system.cpu.icache.overall_mshr_misses::total 4406 # number of overall MSHR misses 407system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 80533500 # number of ReadReq MSHR miss cycles 408system.cpu.icache.ReadReq_mshr_miss_latency::total 80533500 # number of ReadReq MSHR miss cycles 409system.cpu.icache.demand_mshr_miss_latency::cpu.inst 80533500 # number of demand (read+write) MSHR miss cycles 410system.cpu.icache.demand_mshr_miss_latency::total 80533500 # number of demand (read+write) MSHR miss cycles 411system.cpu.icache.overall_mshr_miss_latency::cpu.inst 80533500 # number of overall MSHR miss cycles 412system.cpu.icache.overall_mshr_miss_latency::total 80533500 # number of overall MSHR miss cycles |
| 414system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for ReadReq accesses 415system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000117 # mshr miss rate for ReadReq accesses 416system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for demand accesses 417system.cpu.icache.demand_mshr_miss_rate::total 0.000117 # mshr miss rate for demand accesses 418system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for overall accesses 419system.cpu.icache.overall_mshr_miss_rate::total 0.000117 # mshr miss rate for overall accesses | 413system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for ReadReq accesses 414system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000117 # mshr miss rate for ReadReq accesses 415system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for demand accesses 416system.cpu.icache.demand_mshr_miss_rate::total 0.000117 # mshr miss rate for demand accesses 417system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for overall accesses 418system.cpu.icache.overall_mshr_miss_rate::total 0.000117 # mshr miss rate for overall accesses |
| 420system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18232.386364 # average ReadReq mshr miss latency 421system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18232.386364 # average ReadReq mshr miss latency 422system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18232.386364 # average overall mshr miss latency 423system.cpu.icache.demand_avg_mshr_miss_latency::total 18232.386364 # average overall mshr miss latency 424system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18232.386364 # average overall mshr miss latency 425system.cpu.icache.overall_avg_mshr_miss_latency::total 18232.386364 # average overall mshr miss latency | 419system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18278.143441 # average ReadReq mshr miss latency 420system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18278.143441 # average ReadReq mshr miss latency 421system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18278.143441 # average overall mshr miss latency 422system.cpu.icache.demand_avg_mshr_miss_latency::total 18278.143441 # average overall mshr miss latency 423system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18278.143441 # average overall mshr miss latency 424system.cpu.icache.overall_avg_mshr_miss_latency::total 18278.143441 # average overall mshr miss latency |
| 426system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 425system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 427system.cpu.dcache.replacements 57 # number of replacements 428system.cpu.dcache.tagsinuse 1415.756952 # Cycle average of tags in use 429system.cpu.dcache.total_refs 47292959 # Total number of references to valid blocks. 430system.cpu.dcache.sampled_refs 1864 # Sample count of references to valid blocks. 431system.cpu.dcache.avg_refs 25371.759120 # Average number of references to valid blocks. | 426system.cpu.dcache.replacements 59 # number of replacements 427system.cpu.dcache.tagsinuse 1417.829919 # Cycle average of tags in use 428system.cpu.dcache.total_refs 47315704 # Total number of references to valid blocks. 429system.cpu.dcache.sampled_refs 1866 # Sample count of references to valid blocks. 430system.cpu.dcache.avg_refs 25356.754555 # Average number of references to valid blocks. |
| 432system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 431system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 433system.cpu.dcache.occ_blocks::cpu.data 1415.756952 # Average occupied blocks per requestor 434system.cpu.dcache.occ_percent::cpu.data 0.345644 # Average percentage of cache occupancy 435system.cpu.dcache.occ_percent::total 0.345644 # Average percentage of cache occupancy 436system.cpu.dcache.ReadReq_hits::cpu.data 34877985 # number of ReadReq hits 437system.cpu.dcache.ReadReq_hits::total 34877985 # number of ReadReq hits 438system.cpu.dcache.WriteReq_hits::cpu.data 12356653 # number of WriteReq hits 439system.cpu.dcache.WriteReq_hits::total 12356653 # number of WriteReq hits 440system.cpu.dcache.LoadLockedReq_hits::cpu.data 29848 # number of LoadLockedReq hits 441system.cpu.dcache.LoadLockedReq_hits::total 29848 # number of LoadLockedReq hits 442system.cpu.dcache.StoreCondReq_hits::cpu.data 28473 # number of StoreCondReq hits 443system.cpu.dcache.StoreCondReq_hits::total 28473 # number of StoreCondReq hits 444system.cpu.dcache.demand_hits::cpu.data 47234638 # number of demand (read+write) hits 445system.cpu.dcache.demand_hits::total 47234638 # number of demand (read+write) hits 446system.cpu.dcache.overall_hits::cpu.data 47234638 # number of overall hits 447system.cpu.dcache.overall_hits::total 47234638 # number of overall hits 448system.cpu.dcache.ReadReq_misses::cpu.data 1937 # number of ReadReq misses 449system.cpu.dcache.ReadReq_misses::total 1937 # number of ReadReq misses 450system.cpu.dcache.WriteReq_misses::cpu.data 7634 # number of WriteReq misses 451system.cpu.dcache.WriteReq_misses::total 7634 # number of WriteReq misses | 432system.cpu.dcache.occ_blocks::cpu.data 1417.829919 # Average occupied blocks per requestor 433system.cpu.dcache.occ_percent::cpu.data 0.346150 # Average percentage of cache occupancy 434system.cpu.dcache.occ_percent::total 0.346150 # Average percentage of cache occupancy 435system.cpu.dcache.ReadReq_hits::cpu.data 34900386 # number of ReadReq hits 436system.cpu.dcache.ReadReq_hits::total 34900386 # number of ReadReq hits 437system.cpu.dcache.WriteReq_hits::cpu.data 12356583 # number of WriteReq hits 438system.cpu.dcache.WriteReq_hits::total 12356583 # number of WriteReq hits 439system.cpu.dcache.LoadLockedReq_hits::cpu.data 30299 # number of LoadLockedReq hits 440system.cpu.dcache.LoadLockedReq_hits::total 30299 # number of LoadLockedReq hits 441system.cpu.dcache.StoreCondReq_hits::cpu.data 28436 # number of StoreCondReq hits 442system.cpu.dcache.StoreCondReq_hits::total 28436 # number of StoreCondReq hits 443system.cpu.dcache.demand_hits::cpu.data 47256969 # number of demand (read+write) hits 444system.cpu.dcache.demand_hits::total 47256969 # number of demand (read+write) hits 445system.cpu.dcache.overall_hits::cpu.data 47256969 # number of overall hits 446system.cpu.dcache.overall_hits::total 47256969 # number of overall hits 447system.cpu.dcache.ReadReq_misses::cpu.data 1941 # number of ReadReq misses 448system.cpu.dcache.ReadReq_misses::total 1941 # number of ReadReq misses 449system.cpu.dcache.WriteReq_misses::cpu.data 7704 # number of WriteReq misses 450system.cpu.dcache.WriteReq_misses::total 7704 # number of WriteReq misses |
| 452system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 453system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses | 451system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 452system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses |
| 454system.cpu.dcache.demand_misses::cpu.data 9571 # number of demand (read+write) misses 455system.cpu.dcache.demand_misses::total 9571 # number of demand (read+write) misses 456system.cpu.dcache.overall_misses::cpu.data 9571 # number of overall misses 457system.cpu.dcache.overall_misses::total 9571 # number of overall misses 458system.cpu.dcache.ReadReq_miss_latency::cpu.data 71164500 # number of ReadReq miss cycles 459system.cpu.dcache.ReadReq_miss_latency::total 71164500 # number of ReadReq miss cycles 460system.cpu.dcache.WriteReq_miss_latency::cpu.data 282690000 # number of WriteReq miss cycles 461system.cpu.dcache.WriteReq_miss_latency::total 282690000 # number of WriteReq miss cycles | 453system.cpu.dcache.demand_misses::cpu.data 9645 # number of demand (read+write) misses 454system.cpu.dcache.demand_misses::total 9645 # number of demand (read+write) misses 455system.cpu.dcache.overall_misses::cpu.data 9645 # number of overall misses 456system.cpu.dcache.overall_misses::total 9645 # number of overall misses 457system.cpu.dcache.ReadReq_miss_latency::cpu.data 71450500 # number of ReadReq miss cycles 458system.cpu.dcache.ReadReq_miss_latency::total 71450500 # number of ReadReq miss cycles 459system.cpu.dcache.WriteReq_miss_latency::cpu.data 284851500 # number of WriteReq miss cycles 460system.cpu.dcache.WriteReq_miss_latency::total 284851500 # number of WriteReq miss cycles |
| 462system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 80500 # number of LoadLockedReq miss cycles 463system.cpu.dcache.LoadLockedReq_miss_latency::total 80500 # number of LoadLockedReq miss cycles | 461system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 80500 # number of LoadLockedReq miss cycles 462system.cpu.dcache.LoadLockedReq_miss_latency::total 80500 # number of LoadLockedReq miss cycles |
| 464system.cpu.dcache.demand_miss_latency::cpu.data 353854500 # number of demand (read+write) miss cycles 465system.cpu.dcache.demand_miss_latency::total 353854500 # number of demand (read+write) miss cycles 466system.cpu.dcache.overall_miss_latency::cpu.data 353854500 # number of overall miss cycles 467system.cpu.dcache.overall_miss_latency::total 353854500 # number of overall miss cycles 468system.cpu.dcache.ReadReq_accesses::cpu.data 34879922 # number of ReadReq accesses(hits+misses) 469system.cpu.dcache.ReadReq_accesses::total 34879922 # number of ReadReq accesses(hits+misses) | 463system.cpu.dcache.demand_miss_latency::cpu.data 356302000 # number of demand (read+write) miss cycles 464system.cpu.dcache.demand_miss_latency::total 356302000 # number of demand (read+write) miss cycles 465system.cpu.dcache.overall_miss_latency::cpu.data 356302000 # number of overall miss cycles 466system.cpu.dcache.overall_miss_latency::total 356302000 # number of overall miss cycles 467system.cpu.dcache.ReadReq_accesses::cpu.data 34902327 # number of ReadReq accesses(hits+misses) 468system.cpu.dcache.ReadReq_accesses::total 34902327 # number of ReadReq accesses(hits+misses) |
| 470system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 471system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) | 469system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 470system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) |
| 472system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29850 # number of LoadLockedReq accesses(hits+misses) 473system.cpu.dcache.LoadLockedReq_accesses::total 29850 # number of LoadLockedReq accesses(hits+misses) 474system.cpu.dcache.StoreCondReq_accesses::cpu.data 28473 # number of StoreCondReq accesses(hits+misses) 475system.cpu.dcache.StoreCondReq_accesses::total 28473 # number of StoreCondReq accesses(hits+misses) 476system.cpu.dcache.demand_accesses::cpu.data 47244209 # number of demand (read+write) accesses 477system.cpu.dcache.demand_accesses::total 47244209 # number of demand (read+write) accesses 478system.cpu.dcache.overall_accesses::cpu.data 47244209 # number of overall (read+write) accesses 479system.cpu.dcache.overall_accesses::total 47244209 # number of overall (read+write) accesses | 471system.cpu.dcache.LoadLockedReq_accesses::cpu.data 30301 # number of LoadLockedReq accesses(hits+misses) 472system.cpu.dcache.LoadLockedReq_accesses::total 30301 # number of LoadLockedReq accesses(hits+misses) 473system.cpu.dcache.StoreCondReq_accesses::cpu.data 28436 # number of StoreCondReq accesses(hits+misses) 474system.cpu.dcache.StoreCondReq_accesses::total 28436 # number of StoreCondReq accesses(hits+misses) 475system.cpu.dcache.demand_accesses::cpu.data 47266614 # number of demand (read+write) accesses 476system.cpu.dcache.demand_accesses::total 47266614 # number of demand (read+write) accesses 477system.cpu.dcache.overall_accesses::cpu.data 47266614 # number of overall (read+write) accesses 478system.cpu.dcache.overall_accesses::total 47266614 # number of overall (read+write) accesses |
| 480system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000056 # miss rate for ReadReq accesses 481system.cpu.dcache.ReadReq_miss_rate::total 0.000056 # miss rate for ReadReq accesses | 479system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000056 # miss rate for ReadReq accesses 480system.cpu.dcache.ReadReq_miss_rate::total 0.000056 # miss rate for ReadReq accesses |
| 482system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000617 # miss rate for WriteReq accesses 483system.cpu.dcache.WriteReq_miss_rate::total 0.000617 # miss rate for WriteReq accesses 484system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses 485system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses 486system.cpu.dcache.demand_miss_rate::cpu.data 0.000203 # miss rate for demand accesses 487system.cpu.dcache.demand_miss_rate::total 0.000203 # miss rate for demand accesses 488system.cpu.dcache.overall_miss_rate::cpu.data 0.000203 # miss rate for overall accesses 489system.cpu.dcache.overall_miss_rate::total 0.000203 # miss rate for overall accesses 490system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36739.545689 # average ReadReq miss latency 491system.cpu.dcache.ReadReq_avg_miss_latency::total 36739.545689 # average ReadReq miss latency 492system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37030.390359 # average WriteReq miss latency 493system.cpu.dcache.WriteReq_avg_miss_latency::total 37030.390359 # average WriteReq miss latency | 481system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000623 # miss rate for WriteReq accesses 482system.cpu.dcache.WriteReq_miss_rate::total 0.000623 # miss rate for WriteReq accesses 483system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000066 # miss rate for LoadLockedReq accesses 484system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000066 # miss rate for LoadLockedReq accesses 485system.cpu.dcache.demand_miss_rate::cpu.data 0.000204 # miss rate for demand accesses 486system.cpu.dcache.demand_miss_rate::total 0.000204 # miss rate for demand accesses 487system.cpu.dcache.overall_miss_rate::cpu.data 0.000204 # miss rate for overall accesses 488system.cpu.dcache.overall_miss_rate::total 0.000204 # miss rate for overall accesses 489system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36811.179804 # average ReadReq miss latency 490system.cpu.dcache.ReadReq_avg_miss_latency::total 36811.179804 # average ReadReq miss latency 491system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36974.493769 # average WriteReq miss latency 492system.cpu.dcache.WriteReq_avg_miss_latency::total 36974.493769 # average WriteReq miss latency |
| 494system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 40250 # average LoadLockedReq miss latency 495system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 40250 # average LoadLockedReq miss latency | 493system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 40250 # average LoadLockedReq miss latency 494system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 40250 # average LoadLockedReq miss latency |
| 496system.cpu.dcache.demand_avg_miss_latency::cpu.data 36971.528576 # average overall miss latency 497system.cpu.dcache.demand_avg_miss_latency::total 36971.528576 # average overall miss latency 498system.cpu.dcache.overall_avg_miss_latency::cpu.data 36971.528576 # average overall miss latency 499system.cpu.dcache.overall_avg_miss_latency::total 36971.528576 # average overall miss latency | 495system.cpu.dcache.demand_avg_miss_latency::cpu.data 36941.627786 # average overall miss latency 496system.cpu.dcache.demand_avg_miss_latency::total 36941.627786 # average overall miss latency 497system.cpu.dcache.overall_avg_miss_latency::cpu.data 36941.627786 # average overall miss latency 498system.cpu.dcache.overall_avg_miss_latency::total 36941.627786 # average overall miss latency |
| 500system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 499system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 501system.cpu.dcache.blocked_cycles::no_targets 10000 # number of cycles access was blocked | 500system.cpu.dcache.blocked_cycles::no_targets 18000 # number of cycles access was blocked |
| 502system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 503system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked 504system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 501system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 502system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked 503system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 505system.cpu.dcache.avg_blocked_cycles::no_targets 5000 # average number of cycles each access was blocked | 504system.cpu.dcache.avg_blocked_cycles::no_targets 9000 # average number of cycles each access was blocked |
| 506system.cpu.dcache.fast_writes 0 # number of fast writes performed 507system.cpu.dcache.cache_copies 0 # number of cache copies performed | 505system.cpu.dcache.fast_writes 0 # number of fast writes performed 506system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 508system.cpu.dcache.writebacks::writebacks 16 # number of writebacks 509system.cpu.dcache.writebacks::total 16 # number of writebacks 510system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1154 # number of ReadReq MSHR hits 511system.cpu.dcache.ReadReq_mshr_hits::total 1154 # number of ReadReq MSHR hits 512system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6553 # number of WriteReq MSHR hits 513system.cpu.dcache.WriteReq_mshr_hits::total 6553 # number of WriteReq MSHR hits | 507system.cpu.dcache.writebacks::writebacks 18 # number of writebacks 508system.cpu.dcache.writebacks::total 18 # number of writebacks 509system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1165 # number of ReadReq MSHR hits 510system.cpu.dcache.ReadReq_mshr_hits::total 1165 # number of ReadReq MSHR hits 511system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6614 # number of WriteReq MSHR hits 512system.cpu.dcache.WriteReq_mshr_hits::total 6614 # number of WriteReq MSHR hits |
| 514system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 515system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits | 513system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 514system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits |
| 516system.cpu.dcache.demand_mshr_hits::cpu.data 7707 # number of demand (read+write) MSHR hits 517system.cpu.dcache.demand_mshr_hits::total 7707 # number of demand (read+write) MSHR hits 518system.cpu.dcache.overall_mshr_hits::cpu.data 7707 # number of overall MSHR hits 519system.cpu.dcache.overall_mshr_hits::total 7707 # number of overall MSHR hits 520system.cpu.dcache.ReadReq_mshr_misses::cpu.data 783 # number of ReadReq MSHR misses 521system.cpu.dcache.ReadReq_mshr_misses::total 783 # number of ReadReq MSHR misses 522system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1081 # number of WriteReq MSHR misses 523system.cpu.dcache.WriteReq_mshr_misses::total 1081 # number of WriteReq MSHR misses 524system.cpu.dcache.demand_mshr_misses::cpu.data 1864 # number of demand (read+write) MSHR misses 525system.cpu.dcache.demand_mshr_misses::total 1864 # number of demand (read+write) MSHR misses 526system.cpu.dcache.overall_mshr_misses::cpu.data 1864 # number of overall MSHR misses 527system.cpu.dcache.overall_mshr_misses::total 1864 # number of overall MSHR misses 528system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26652500 # number of ReadReq MSHR miss cycles 529system.cpu.dcache.ReadReq_mshr_miss_latency::total 26652500 # number of ReadReq MSHR miss cycles 530system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 38548000 # number of WriteReq MSHR miss cycles 531system.cpu.dcache.WriteReq_mshr_miss_latency::total 38548000 # number of WriteReq MSHR miss cycles 532system.cpu.dcache.demand_mshr_miss_latency::cpu.data 65200500 # number of demand (read+write) MSHR miss cycles 533system.cpu.dcache.demand_mshr_miss_latency::total 65200500 # number of demand (read+write) MSHR miss cycles 534system.cpu.dcache.overall_mshr_miss_latency::cpu.data 65200500 # number of overall MSHR miss cycles 535system.cpu.dcache.overall_mshr_miss_latency::total 65200500 # number of overall MSHR miss cycles | 515system.cpu.dcache.demand_mshr_hits::cpu.data 7779 # number of demand (read+write) MSHR hits 516system.cpu.dcache.demand_mshr_hits::total 7779 # number of demand (read+write) MSHR hits 517system.cpu.dcache.overall_mshr_hits::cpu.data 7779 # number of overall MSHR hits 518system.cpu.dcache.overall_mshr_hits::total 7779 # number of overall MSHR hits 519system.cpu.dcache.ReadReq_mshr_misses::cpu.data 776 # number of ReadReq MSHR misses 520system.cpu.dcache.ReadReq_mshr_misses::total 776 # number of ReadReq MSHR misses 521system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1090 # number of WriteReq MSHR misses 522system.cpu.dcache.WriteReq_mshr_misses::total 1090 # number of WriteReq MSHR misses 523system.cpu.dcache.demand_mshr_misses::cpu.data 1866 # number of demand (read+write) MSHR misses 524system.cpu.dcache.demand_mshr_misses::total 1866 # number of demand (read+write) MSHR misses 525system.cpu.dcache.overall_mshr_misses::cpu.data 1866 # number of overall MSHR misses 526system.cpu.dcache.overall_mshr_misses::total 1866 # number of overall MSHR misses 527system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26418500 # number of ReadReq MSHR miss cycles 528system.cpu.dcache.ReadReq_mshr_miss_latency::total 26418500 # number of ReadReq MSHR miss cycles 529system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 38775500 # number of WriteReq MSHR miss cycles 530system.cpu.dcache.WriteReq_mshr_miss_latency::total 38775500 # number of WriteReq MSHR miss cycles 531system.cpu.dcache.demand_mshr_miss_latency::cpu.data 65194000 # number of demand (read+write) MSHR miss cycles 532system.cpu.dcache.demand_mshr_miss_latency::total 65194000 # number of demand (read+write) MSHR miss cycles 533system.cpu.dcache.overall_mshr_miss_latency::cpu.data 65194000 # number of overall MSHR miss cycles 534system.cpu.dcache.overall_mshr_miss_latency::total 65194000 # number of overall MSHR miss cycles |
| 536system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses 537system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses | 535system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses 536system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses |
| 538system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses 539system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses | 537system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses 538system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses |
| 540system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000039 # mshr miss rate for demand accesses 541system.cpu.dcache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses 542system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000039 # mshr miss rate for overall accesses 543system.cpu.dcache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses | 539system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000039 # mshr miss rate for demand accesses 540system.cpu.dcache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses 541system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000039 # mshr miss rate for overall accesses 542system.cpu.dcache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses |
| 544system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34038.952746 # average ReadReq mshr miss latency 545system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34038.952746 # average ReadReq mshr miss latency 546system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35659.574468 # average WriteReq mshr miss latency 547system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35659.574468 # average WriteReq mshr miss latency 548system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34978.809013 # average overall mshr miss latency 549system.cpu.dcache.demand_avg_mshr_miss_latency::total 34978.809013 # average overall mshr miss latency 550system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34978.809013 # average overall mshr miss latency 551system.cpu.dcache.overall_avg_mshr_miss_latency::total 34978.809013 # average overall mshr miss latency | 543system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34044.458763 # average ReadReq mshr miss latency 544system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34044.458763 # average ReadReq mshr miss latency 545system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35573.853211 # average WriteReq mshr miss latency 546system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35573.853211 # average WriteReq mshr miss latency 547system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34937.834941 # average overall mshr miss latency 548system.cpu.dcache.demand_avg_mshr_miss_latency::total 34937.834941 # average overall mshr miss latency 549system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34937.834941 # average overall mshr miss latency 550system.cpu.dcache.overall_avg_mshr_miss_latency::total 34937.834941 # average overall mshr miss latency |
| 552system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 553system.cpu.l2cache.replacements 0 # number of replacements | 551system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 552system.cpu.l2cache.replacements 0 # number of replacements |
| 554system.cpu.l2cache.tagsinuse 1983.510934 # Cycle average of tags in use | 553system.cpu.l2cache.tagsinuse 1986.935708 # Cycle average of tags in use |
| 555system.cpu.l2cache.total_refs 2423 # Total number of references to valid blocks. | 554system.cpu.l2cache.total_refs 2423 # Total number of references to valid blocks. |
| 556system.cpu.l2cache.sampled_refs 2749 # Sample count of references to valid blocks. 557system.cpu.l2cache.avg_refs 0.881411 # Average number of references to valid blocks. | 555system.cpu.l2cache.sampled_refs 2750 # Sample count of references to valid blocks. 556system.cpu.l2cache.avg_refs 0.881091 # Average number of references to valid blocks. |
| 558system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 557system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 559system.cpu.l2cache.occ_blocks::writebacks 4.019168 # Average occupied blocks per requestor 560system.cpu.l2cache.occ_blocks::cpu.inst 1437.049576 # Average occupied blocks per requestor 561system.cpu.l2cache.occ_blocks::cpu.data 542.442189 # Average occupied blocks per requestor 562system.cpu.l2cache.occ_percent::writebacks 0.000123 # Average percentage of cache occupancy 563system.cpu.l2cache.occ_percent::cpu.inst 0.043855 # Average percentage of cache occupancy 564system.cpu.l2cache.occ_percent::cpu.data 0.016554 # Average percentage of cache occupancy 565system.cpu.l2cache.occ_percent::total 0.060532 # Average percentage of cache occupancy | 558system.cpu.l2cache.occ_blocks::writebacks 3.999816 # Average occupied blocks per requestor 559system.cpu.l2cache.occ_blocks::cpu.inst 1446.546837 # Average occupied blocks per requestor 560system.cpu.l2cache.occ_blocks::cpu.data 536.389055 # Average occupied blocks per requestor 561system.cpu.l2cache.occ_percent::writebacks 0.000122 # Average percentage of cache occupancy 562system.cpu.l2cache.occ_percent::cpu.inst 0.044145 # Average percentage of cache occupancy 563system.cpu.l2cache.occ_percent::cpu.data 0.016369 # Average percentage of cache occupancy 564system.cpu.l2cache.occ_percent::total 0.060636 # Average percentage of cache occupancy |
| 566system.cpu.l2cache.ReadReq_hits::cpu.inst 2332 # number of ReadReq hits 567system.cpu.l2cache.ReadReq_hits::cpu.data 90 # number of ReadReq hits 568system.cpu.l2cache.ReadReq_hits::total 2422 # number of ReadReq hits | 565system.cpu.l2cache.ReadReq_hits::cpu.inst 2332 # number of ReadReq hits 566system.cpu.l2cache.ReadReq_hits::cpu.data 90 # number of ReadReq hits 567system.cpu.l2cache.ReadReq_hits::total 2422 # number of ReadReq hits |
| 569system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits 570system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits 571system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # number of ReadExReq hits 572system.cpu.l2cache.ReadExReq_hits::total 7 # number of ReadExReq hits | 568system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits 569system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits 570system.cpu.l2cache.ReadExReq_hits::cpu.data 9 # number of ReadExReq hits 571system.cpu.l2cache.ReadExReq_hits::total 9 # number of ReadExReq hits |
| 573system.cpu.l2cache.demand_hits::cpu.inst 2332 # number of demand (read+write) hits | 572system.cpu.l2cache.demand_hits::cpu.inst 2332 # number of demand (read+write) hits |
| 574system.cpu.l2cache.demand_hits::cpu.data 97 # number of demand (read+write) hits 575system.cpu.l2cache.demand_hits::total 2429 # number of demand (read+write) hits | 573system.cpu.l2cache.demand_hits::cpu.data 99 # number of demand (read+write) hits 574system.cpu.l2cache.demand_hits::total 2431 # number of demand (read+write) hits |
| 576system.cpu.l2cache.overall_hits::cpu.inst 2332 # number of overall hits | 575system.cpu.l2cache.overall_hits::cpu.inst 2332 # number of overall hits |
| 577system.cpu.l2cache.overall_hits::cpu.data 97 # number of overall hits 578system.cpu.l2cache.overall_hits::total 2429 # number of overall hits 579system.cpu.l2cache.ReadReq_misses::cpu.inst 2068 # number of ReadReq misses 580system.cpu.l2cache.ReadReq_misses::cpu.data 693 # number of ReadReq misses 581system.cpu.l2cache.ReadReq_misses::total 2761 # number of ReadReq misses 582system.cpu.l2cache.ReadExReq_misses::cpu.data 1074 # number of ReadExReq misses 583system.cpu.l2cache.ReadExReq_misses::total 1074 # number of ReadExReq misses 584system.cpu.l2cache.demand_misses::cpu.inst 2068 # number of demand (read+write) misses | 576system.cpu.l2cache.overall_hits::cpu.data 99 # number of overall hits 577system.cpu.l2cache.overall_hits::total 2431 # number of overall hits 578system.cpu.l2cache.ReadReq_misses::cpu.inst 2074 # number of ReadReq misses 579system.cpu.l2cache.ReadReq_misses::cpu.data 685 # number of ReadReq misses 580system.cpu.l2cache.ReadReq_misses::total 2759 # number of ReadReq misses 581system.cpu.l2cache.ReadExReq_misses::cpu.data 1082 # number of ReadExReq misses 582system.cpu.l2cache.ReadExReq_misses::total 1082 # number of ReadExReq misses 583system.cpu.l2cache.demand_misses::cpu.inst 2074 # number of demand (read+write) misses |
| 585system.cpu.l2cache.demand_misses::cpu.data 1767 # number of demand (read+write) misses | 584system.cpu.l2cache.demand_misses::cpu.data 1767 # number of demand (read+write) misses |
| 586system.cpu.l2cache.demand_misses::total 3835 # number of demand (read+write) misses 587system.cpu.l2cache.overall_misses::cpu.inst 2068 # number of overall misses | 585system.cpu.l2cache.demand_misses::total 3841 # number of demand (read+write) misses 586system.cpu.l2cache.overall_misses::cpu.inst 2074 # number of overall misses |
| 588system.cpu.l2cache.overall_misses::cpu.data 1767 # number of overall misses | 587system.cpu.l2cache.overall_misses::cpu.data 1767 # number of overall misses |
| 589system.cpu.l2cache.overall_misses::total 3835 # number of overall misses 590system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 72826000 # number of ReadReq miss cycles 591system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25403500 # number of ReadReq miss cycles 592system.cpu.l2cache.ReadReq_miss_latency::total 98229500 # number of ReadReq miss cycles 593system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 37378500 # number of ReadExReq miss cycles 594system.cpu.l2cache.ReadExReq_miss_latency::total 37378500 # number of ReadExReq miss cycles 595system.cpu.l2cache.demand_miss_latency::cpu.inst 72826000 # number of demand (read+write) miss cycles 596system.cpu.l2cache.demand_miss_latency::cpu.data 62782000 # number of demand (read+write) miss cycles 597system.cpu.l2cache.demand_miss_latency::total 135608000 # number of demand (read+write) miss cycles 598system.cpu.l2cache.overall_miss_latency::cpu.inst 72826000 # number of overall miss cycles 599system.cpu.l2cache.overall_miss_latency::cpu.data 62782000 # number of overall miss cycles 600system.cpu.l2cache.overall_miss_latency::total 135608000 # number of overall miss cycles 601system.cpu.l2cache.ReadReq_accesses::cpu.inst 4400 # number of ReadReq accesses(hits+misses) 602system.cpu.l2cache.ReadReq_accesses::cpu.data 783 # number of ReadReq accesses(hits+misses) 603system.cpu.l2cache.ReadReq_accesses::total 5183 # number of ReadReq accesses(hits+misses) 604system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) 605system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) 606system.cpu.l2cache.ReadExReq_accesses::cpu.data 1081 # number of ReadExReq accesses(hits+misses) 607system.cpu.l2cache.ReadExReq_accesses::total 1081 # number of ReadExReq accesses(hits+misses) 608system.cpu.l2cache.demand_accesses::cpu.inst 4400 # number of demand (read+write) accesses 609system.cpu.l2cache.demand_accesses::cpu.data 1864 # number of demand (read+write) accesses 610system.cpu.l2cache.demand_accesses::total 6264 # number of demand (read+write) accesses 611system.cpu.l2cache.overall_accesses::cpu.inst 4400 # number of overall (read+write) accesses 612system.cpu.l2cache.overall_accesses::cpu.data 1864 # number of overall (read+write) accesses 613system.cpu.l2cache.overall_accesses::total 6264 # number of overall (read+write) accesses 614system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.470000 # miss rate for ReadReq accesses 615system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.885057 # miss rate for ReadReq accesses 616system.cpu.l2cache.ReadReq_miss_rate::total 0.532703 # miss rate for ReadReq accesses 617system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993525 # miss rate for ReadExReq accesses 618system.cpu.l2cache.ReadExReq_miss_rate::total 0.993525 # miss rate for ReadExReq accesses 619system.cpu.l2cache.demand_miss_rate::cpu.inst 0.470000 # miss rate for demand accesses 620system.cpu.l2cache.demand_miss_rate::cpu.data 0.947961 # miss rate for demand accesses 621system.cpu.l2cache.demand_miss_rate::total 0.612229 # miss rate for demand accesses 622system.cpu.l2cache.overall_miss_rate::cpu.inst 0.470000 # miss rate for overall accesses 623system.cpu.l2cache.overall_miss_rate::cpu.data 0.947961 # miss rate for overall accesses 624system.cpu.l2cache.overall_miss_rate::total 0.612229 # miss rate for overall accesses 625system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35215.667311 # average ReadReq miss latency 626system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36657.287157 # average ReadReq miss latency 627system.cpu.l2cache.ReadReq_avg_miss_latency::total 35577.508149 # average ReadReq miss latency 628system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34803.072626 # average ReadExReq miss latency 629system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34803.072626 # average ReadExReq miss latency 630system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35215.667311 # average overall miss latency 631system.cpu.l2cache.demand_avg_miss_latency::cpu.data 35530.277306 # average overall miss latency 632system.cpu.l2cache.demand_avg_miss_latency::total 35360.625815 # average overall miss latency 633system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35215.667311 # average overall miss latency 634system.cpu.l2cache.overall_avg_miss_latency::cpu.data 35530.277306 # average overall miss latency 635system.cpu.l2cache.overall_avg_miss_latency::total 35360.625815 # average overall miss latency | 588system.cpu.l2cache.overall_misses::total 3841 # number of overall misses 589system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 73125000 # number of ReadReq miss cycles 590system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25174500 # number of ReadReq miss cycles 591system.cpu.l2cache.ReadReq_miss_latency::total 98299500 # number of ReadReq miss cycles 592system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 37623500 # number of ReadExReq miss cycles 593system.cpu.l2cache.ReadExReq_miss_latency::total 37623500 # number of ReadExReq miss cycles 594system.cpu.l2cache.demand_miss_latency::cpu.inst 73125000 # number of demand (read+write) miss cycles 595system.cpu.l2cache.demand_miss_latency::cpu.data 62798000 # number of demand (read+write) miss cycles 596system.cpu.l2cache.demand_miss_latency::total 135923000 # number of demand (read+write) miss cycles 597system.cpu.l2cache.overall_miss_latency::cpu.inst 73125000 # number of overall miss cycles 598system.cpu.l2cache.overall_miss_latency::cpu.data 62798000 # number of overall miss cycles 599system.cpu.l2cache.overall_miss_latency::total 135923000 # number of overall miss cycles 600system.cpu.l2cache.ReadReq_accesses::cpu.inst 4406 # number of ReadReq accesses(hits+misses) 601system.cpu.l2cache.ReadReq_accesses::cpu.data 775 # number of ReadReq accesses(hits+misses) 602system.cpu.l2cache.ReadReq_accesses::total 5181 # number of ReadReq accesses(hits+misses) 603system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) 604system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) 605system.cpu.l2cache.ReadExReq_accesses::cpu.data 1091 # number of ReadExReq accesses(hits+misses) 606system.cpu.l2cache.ReadExReq_accesses::total 1091 # number of ReadExReq accesses(hits+misses) 607system.cpu.l2cache.demand_accesses::cpu.inst 4406 # number of demand (read+write) accesses 608system.cpu.l2cache.demand_accesses::cpu.data 1866 # number of demand (read+write) accesses 609system.cpu.l2cache.demand_accesses::total 6272 # number of demand (read+write) accesses 610system.cpu.l2cache.overall_accesses::cpu.inst 4406 # number of overall (read+write) accesses 611system.cpu.l2cache.overall_accesses::cpu.data 1866 # number of overall (read+write) accesses 612system.cpu.l2cache.overall_accesses::total 6272 # number of overall (read+write) accesses 613system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.470722 # miss rate for ReadReq accesses 614system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.883871 # miss rate for ReadReq accesses 615system.cpu.l2cache.ReadReq_miss_rate::total 0.532523 # miss rate for ReadReq accesses 616system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991751 # miss rate for ReadExReq accesses 617system.cpu.l2cache.ReadExReq_miss_rate::total 0.991751 # miss rate for ReadExReq accesses 618system.cpu.l2cache.demand_miss_rate::cpu.inst 0.470722 # miss rate for demand accesses 619system.cpu.l2cache.demand_miss_rate::cpu.data 0.946945 # miss rate for demand accesses 620system.cpu.l2cache.demand_miss_rate::total 0.612404 # miss rate for demand accesses 621system.cpu.l2cache.overall_miss_rate::cpu.inst 0.470722 # miss rate for overall accesses 622system.cpu.l2cache.overall_miss_rate::cpu.data 0.946945 # miss rate for overall accesses 623system.cpu.l2cache.overall_miss_rate::total 0.612404 # miss rate for overall accesses 624system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35257.955641 # average ReadReq miss latency 625system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36751.094891 # average ReadReq miss latency 626system.cpu.l2cache.ReadReq_avg_miss_latency::total 35628.669808 # average ReadReq miss latency 627system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34772.181146 # average ReadExReq miss latency 628system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34772.181146 # average ReadExReq miss latency 629system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35257.955641 # average overall miss latency 630system.cpu.l2cache.demand_avg_miss_latency::cpu.data 35539.332201 # average overall miss latency 631system.cpu.l2cache.demand_avg_miss_latency::total 35387.399115 # average overall miss latency 632system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35257.955641 # average overall miss latency 633system.cpu.l2cache.overall_avg_miss_latency::cpu.data 35539.332201 # average overall miss latency 634system.cpu.l2cache.overall_avg_miss_latency::total 35387.399115 # average overall miss latency |
| 636system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 637system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 638system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 639system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 640system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 641system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 642system.cpu.l2cache.fast_writes 0 # number of fast writes performed 643system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 635system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 636system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 637system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 638system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 639system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 640system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 641system.cpu.l2cache.fast_writes 0 # number of fast writes performed 642system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 644system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits 645system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 14 # number of ReadReq MSHR hits 646system.cpu.l2cache.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits 647system.cpu.l2cache.demand_mshr_hits::cpu.inst 6 # number of demand (read+write) MSHR hits 648system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits 649system.cpu.l2cache.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits 650system.cpu.l2cache.overall_mshr_hits::cpu.inst 6 # number of overall MSHR hits 651system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits 652system.cpu.l2cache.overall_mshr_hits::total 20 # number of overall MSHR hits 653system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2062 # number of ReadReq MSHR misses 654system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 679 # number of ReadReq MSHR misses | 643system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits 644system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 13 # number of ReadReq MSHR hits 645system.cpu.l2cache.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits 646system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits 647system.cpu.l2cache.demand_mshr_hits::cpu.data 13 # number of demand (read+write) MSHR hits 648system.cpu.l2cache.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits 649system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits 650system.cpu.l2cache.overall_mshr_hits::cpu.data 13 # number of overall MSHR hits 651system.cpu.l2cache.overall_mshr_hits::total 18 # number of overall MSHR hits 652system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2069 # number of ReadReq MSHR misses 653system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 672 # number of ReadReq MSHR misses |
| 655system.cpu.l2cache.ReadReq_mshr_misses::total 2741 # number of ReadReq MSHR misses | 654system.cpu.l2cache.ReadReq_mshr_misses::total 2741 # number of ReadReq MSHR misses |
| 656system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1074 # number of ReadExReq MSHR misses 657system.cpu.l2cache.ReadExReq_mshr_misses::total 1074 # number of ReadExReq MSHR misses 658system.cpu.l2cache.demand_mshr_misses::cpu.inst 2062 # number of demand (read+write) MSHR misses 659system.cpu.l2cache.demand_mshr_misses::cpu.data 1753 # number of demand (read+write) MSHR misses 660system.cpu.l2cache.demand_mshr_misses::total 3815 # number of demand (read+write) MSHR misses 661system.cpu.l2cache.overall_mshr_misses::cpu.inst 2062 # number of overall MSHR misses 662system.cpu.l2cache.overall_mshr_misses::cpu.data 1753 # number of overall MSHR misses 663system.cpu.l2cache.overall_mshr_misses::total 3815 # number of overall MSHR misses 664system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 66124000 # number of ReadReq MSHR miss cycles 665system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 22800500 # number of ReadReq MSHR miss cycles 666system.cpu.l2cache.ReadReq_mshr_miss_latency::total 88924500 # number of ReadReq MSHR miss cycles 667system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33930000 # number of ReadExReq MSHR miss cycles 668system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33930000 # number of ReadExReq MSHR miss cycles 669system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66124000 # number of demand (read+write) MSHR miss cycles 670system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 56730500 # number of demand (read+write) MSHR miss cycles 671system.cpu.l2cache.demand_mshr_miss_latency::total 122854500 # number of demand (read+write) MSHR miss cycles 672system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66124000 # number of overall MSHR miss cycles 673system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 56730500 # number of overall MSHR miss cycles 674system.cpu.l2cache.overall_mshr_miss_latency::total 122854500 # number of overall MSHR miss cycles 675system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.468636 # mshr miss rate for ReadReq accesses 676system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867178 # mshr miss rate for ReadReq accesses 677system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.528844 # mshr miss rate for ReadReq accesses 678system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993525 # mshr miss rate for ReadExReq accesses 679system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993525 # mshr miss rate for ReadExReq accesses 680system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.468636 # mshr miss rate for demand accesses 681system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.940451 # mshr miss rate for demand accesses 682system.cpu.l2cache.demand_mshr_miss_rate::total 0.609036 # mshr miss rate for demand accesses 683system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.468636 # mshr miss rate for overall accesses 684system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940451 # mshr miss rate for overall accesses 685system.cpu.l2cache.overall_mshr_miss_rate::total 0.609036 # mshr miss rate for overall accesses 686system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32067.895247 # average ReadReq mshr miss latency 687system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33579.528719 # average ReadReq mshr miss latency 688system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32442.356804 # average ReadReq mshr miss latency 689system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31592.178771 # average ReadExReq mshr miss latency 690system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31592.178771 # average ReadExReq mshr miss latency 691system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32067.895247 # average overall mshr miss latency 692system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32361.950941 # average overall mshr miss latency 693system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32203.014417 # average overall mshr miss latency 694system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32067.895247 # average overall mshr miss latency 695system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32361.950941 # average overall mshr miss latency 696system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32203.014417 # average overall mshr miss latency | 655system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1082 # number of ReadExReq MSHR misses 656system.cpu.l2cache.ReadExReq_mshr_misses::total 1082 # number of ReadExReq MSHR misses 657system.cpu.l2cache.demand_mshr_misses::cpu.inst 2069 # number of demand (read+write) MSHR misses 658system.cpu.l2cache.demand_mshr_misses::cpu.data 1754 # number of demand (read+write) MSHR misses 659system.cpu.l2cache.demand_mshr_misses::total 3823 # number of demand (read+write) MSHR misses 660system.cpu.l2cache.overall_mshr_misses::cpu.inst 2069 # number of overall MSHR misses 661system.cpu.l2cache.overall_mshr_misses::cpu.data 1754 # number of overall MSHR misses 662system.cpu.l2cache.overall_mshr_misses::total 3823 # number of overall MSHR misses 663system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 66421500 # number of ReadReq MSHR miss cycles 664system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 22618000 # number of ReadReq MSHR miss cycles 665system.cpu.l2cache.ReadReq_mshr_miss_latency::total 89039500 # number of ReadReq MSHR miss cycles 666system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 34148500 # number of ReadExReq MSHR miss cycles 667system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 34148500 # number of ReadExReq MSHR miss cycles 668system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66421500 # number of demand (read+write) MSHR miss cycles 669system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 56766500 # number of demand (read+write) MSHR miss cycles 670system.cpu.l2cache.demand_mshr_miss_latency::total 123188000 # number of demand (read+write) MSHR miss cycles 671system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66421500 # number of overall MSHR miss cycles 672system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 56766500 # number of overall MSHR miss cycles 673system.cpu.l2cache.overall_mshr_miss_latency::total 123188000 # number of overall MSHR miss cycles 674system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.469587 # mshr miss rate for ReadReq accesses 675system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867097 # mshr miss rate for ReadReq accesses 676system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.529048 # mshr miss rate for ReadReq accesses 677system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991751 # mshr miss rate for ReadExReq accesses 678system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991751 # mshr miss rate for ReadExReq accesses 679system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.469587 # mshr miss rate for demand accesses 680system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.939979 # mshr miss rate for demand accesses 681system.cpu.l2cache.demand_mshr_miss_rate::total 0.609534 # mshr miss rate for demand accesses 682system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.469587 # mshr miss rate for overall accesses 683system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.939979 # mshr miss rate for overall accesses 684system.cpu.l2cache.overall_mshr_miss_rate::total 0.609534 # mshr miss rate for overall accesses 685system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32103.189947 # average ReadReq mshr miss latency 686system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33657.738095 # average ReadReq mshr miss latency 687system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32484.312295 # average ReadReq mshr miss latency 688system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31560.536044 # average ReadExReq mshr miss latency 689system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31560.536044 # average ReadExReq mshr miss latency 690system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32103.189947 # average overall mshr miss latency 691system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32364.025086 # average overall mshr miss latency 692system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32222.861627 # average overall mshr miss latency 693system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32103.189947 # average overall mshr miss latency 694system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32364.025086 # average overall mshr miss latency 695system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32222.861627 # average overall mshr miss latency |
| 697system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 698 699---------- End Simulation Statistics ---------- | 696system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 697 698---------- End Simulation Statistics ---------- |