| stats.txt (9055:38f1926fb599) | stats.txt (9079:9a244ebdc3c9) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.076323 # Number of seconds simulated 4sim_ticks 76322764500 # Number of ticks simulated 5final_tick 76322764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.076050 # Number of seconds simulated 4sim_ticks 76049800000 # Number of ticks simulated 5final_tick 76049800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 95790 # Simulator instruction rate (inst/s) 8host_op_rate 104880 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 42423254 # Simulator tick rate (ticks/s) 10host_mem_usage 235620 # Number of bytes of host memory used 11host_seconds 1799.08 # Real time elapsed on the host 12sim_insts 172333279 # Number of instructions simulated 13sim_ops 188686762 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 133376 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 113216 # Number of bytes read from this memory 16system.physmem.bytes_read::total 246592 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 133376 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 133376 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 2084 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 1769 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 3853 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1747526 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 1483384 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 3230910 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1747526 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1747526 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1747526 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 1483384 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 3230910 # Total bandwidth to/from this memory (bytes/s) | 7host_inst_rate 156056 # Simulator instruction rate (inst/s) 8host_op_rate 170865 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 68866655 # Simulator tick rate (ticks/s) 10host_mem_usage 238096 # Number of bytes of host memory used 11host_seconds 1104.31 # Real time elapsed on the host 12sim_insts 172333196 # Number of instructions simulated 13sim_ops 188686678 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 132416 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 112128 # Number of bytes read from this memory 16system.physmem.bytes_read::total 244544 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 132416 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 132416 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 2069 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 1752 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 3821 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1741175 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 1474402 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 3215577 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1741175 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1741175 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1741175 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 1474402 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 3215577 # Total bandwidth to/from this memory (bytes/s) |
| 30system.cpu.dtb.inst_hits 0 # ITB inst hits 31system.cpu.dtb.inst_misses 0 # ITB inst misses 32system.cpu.dtb.read_hits 0 # DTB read hits 33system.cpu.dtb.read_misses 0 # DTB read misses 34system.cpu.dtb.write_hits 0 # DTB write hits 35system.cpu.dtb.write_misses 0 # DTB write misses 36system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 37system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 65system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 66system.cpu.itb.read_accesses 0 # DTB read accesses 67system.cpu.itb.write_accesses 0 # DTB write accesses 68system.cpu.itb.inst_accesses 0 # ITB inst accesses 69system.cpu.itb.hits 0 # DTB hits 70system.cpu.itb.misses 0 # DTB misses 71system.cpu.itb.accesses 0 # DTB accesses 72system.cpu.workload.num_syscalls 400 # Number of system calls | 30system.cpu.dtb.inst_hits 0 # ITB inst hits 31system.cpu.dtb.inst_misses 0 # ITB inst misses 32system.cpu.dtb.read_hits 0 # DTB read hits 33system.cpu.dtb.read_misses 0 # DTB read misses 34system.cpu.dtb.write_hits 0 # DTB write hits 35system.cpu.dtb.write_misses 0 # DTB write misses 36system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 37system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 65system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 66system.cpu.itb.read_accesses 0 # DTB read accesses 67system.cpu.itb.write_accesses 0 # DTB write accesses 68system.cpu.itb.inst_accesses 0 # ITB inst accesses 69system.cpu.itb.hits 0 # DTB hits 70system.cpu.itb.misses 0 # DTB misses 71system.cpu.itb.accesses 0 # DTB accesses 72system.cpu.workload.num_syscalls 400 # Number of system calls |
| 73system.cpu.numCycles 152645530 # number of cpu cycles simulated | 73system.cpu.numCycles 152099601 # number of cpu cycles simulated |
| 74system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 75system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 74system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 75system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 76system.cpu.BPredUnit.lookups 97143446 # Number of BP lookups 77system.cpu.BPredUnit.condPredicted 76317615 # Number of conditional branches predicted 78system.cpu.BPredUnit.condIncorrect 6623022 # Number of conditional branches incorrect 79system.cpu.BPredUnit.BTBLookups 46654244 # Number of BTB lookups 80system.cpu.BPredUnit.BTBHits 44354550 # Number of BTB hits | 76system.cpu.BPredUnit.lookups 96837963 # Number of BP lookups 77system.cpu.BPredUnit.condPredicted 76071776 # Number of conditional branches predicted 78system.cpu.BPredUnit.condIncorrect 6557528 # Number of conditional branches incorrect 79system.cpu.BPredUnit.BTBLookups 46441082 # Number of BTB lookups 80system.cpu.BPredUnit.BTBHits 44202196 # Number of BTB hits |
| 81system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 81system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 82system.cpu.BPredUnit.usedRAS 4440290 # Number of times the RAS was used to get a target. 83system.cpu.BPredUnit.RASInCorrect 115738 # Number of incorrect RAS predictions. 84system.cpu.fetch.icacheStallCycles 40856932 # Number of cycles fetch is stalled on an Icache miss 85system.cpu.fetch.Insts 389909160 # Number of instructions fetch has processed 86system.cpu.fetch.Branches 97143446 # Number of branches that fetch encountered 87system.cpu.fetch.predictedBranches 48794840 # Number of branches that fetch has predicted taken 88system.cpu.fetch.Cycles 82559996 # Number of cycles fetch has run and was not squashing or blocked 89system.cpu.fetch.SquashCycles 28665024 # Number of cycles fetch has spent squashing 90system.cpu.fetch.BlockedCycles 7154273 # Number of cycles fetch has spent blocked 91system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 92system.cpu.fetch.PendingTrapStallCycles 8876 # Number of stall cycles due to pending traps | 82system.cpu.BPredUnit.usedRAS 4477911 # Number of times the RAS was used to get a target. 83system.cpu.BPredUnit.RASInCorrect 89401 # Number of incorrect RAS predictions. 84system.cpu.fetch.icacheStallCycles 40623947 # Number of cycles fetch is stalled on an Icache miss 85system.cpu.fetch.Insts 388565051 # Number of instructions fetch has processed 86system.cpu.fetch.Branches 96837963 # Number of branches that fetch encountered 87system.cpu.fetch.predictedBranches 48680107 # Number of branches that fetch has predicted taken 88system.cpu.fetch.Cycles 82289244 # Number of cycles fetch has run and was not squashing or blocked 89system.cpu.fetch.SquashCycles 28490098 # Number of cycles fetch has spent squashing 90system.cpu.fetch.BlockedCycles 7220589 # Number of cycles fetch has spent blocked 91system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 92system.cpu.fetch.PendingTrapStallCycles 8612 # Number of stall cycles due to pending traps |
| 93system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions | 93system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions |
| 94system.cpu.fetch.CacheLines 37841460 # Number of cache lines fetched 95system.cpu.fetch.IcacheSquashes 1897566 # Number of outstanding Icache misses that were squashed 96system.cpu.fetch.rateDist::samples 152586857 # Number of instructions fetched each cycle (Total) 97system.cpu.fetch.rateDist::mean 2.799629 # Number of instructions fetched each cycle (Total) 98system.cpu.fetch.rateDist::stdev 3.155476 # Number of instructions fetched each cycle (Total) | 94system.cpu.fetch.CacheLines 37659031 # Number of cache lines fetched 95system.cpu.fetch.IcacheSquashes 1889609 # Number of outstanding Icache misses that were squashed 96system.cpu.fetch.rateDist::samples 152039589 # Number of instructions fetched each cycle (Total) 97system.cpu.fetch.rateDist::mean 2.799223 # Number of instructions fetched each cycle (Total) 98system.cpu.fetch.rateDist::stdev 3.154384 # Number of instructions fetched each cycle (Total) |
| 99system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 99system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 100system.cpu.fetch.rateDist::0 70197419 46.00% 46.00% # Number of instructions fetched each cycle (Total) 101system.cpu.fetch.rateDist::1 5514909 3.61% 49.62% # Number of instructions fetched each cycle (Total) 102system.cpu.fetch.rateDist::2 10699531 7.01% 56.63% # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::3 10457896 6.85% 63.48% # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.rateDist::4 8809329 5.77% 69.26% # Number of instructions fetched each cycle (Total) 105system.cpu.fetch.rateDist::5 6861836 4.50% 73.76% # Number of instructions fetched each cycle (Total) 106system.cpu.fetch.rateDist::6 6316245 4.14% 77.89% # Number of instructions fetched each cycle (Total) 107system.cpu.fetch.rateDist::7 8382546 5.49% 83.39% # Number of instructions fetched each cycle (Total) 108system.cpu.fetch.rateDist::8 25347146 16.61% 100.00% # Number of instructions fetched each cycle (Total) | 100system.cpu.fetch.rateDist::0 69920012 45.99% 45.99% # Number of instructions fetched each cycle (Total) 101system.cpu.fetch.rateDist::1 5487559 3.61% 49.60% # Number of instructions fetched each cycle (Total) 102system.cpu.fetch.rateDist::2 10685692 7.03% 56.63% # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::3 10438123 6.87% 63.49% # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.rateDist::4 8795207 5.78% 69.28% # Number of instructions fetched each cycle (Total) 105system.cpu.fetch.rateDist::5 6832085 4.49% 73.77% # Number of instructions fetched each cycle (Total) 106system.cpu.fetch.rateDist::6 6301825 4.14% 77.91% # Number of instructions fetched each cycle (Total) 107system.cpu.fetch.rateDist::7 8365502 5.50% 83.42% # Number of instructions fetched each cycle (Total) 108system.cpu.fetch.rateDist::8 25213584 16.58% 100.00% # Number of instructions fetched each cycle (Total) |
| 109system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 110system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 111system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 109system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 110system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 111system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 112system.cpu.fetch.rateDist::total 152586857 # Number of instructions fetched each cycle (Total) 113system.cpu.fetch.branchRate 0.636399 # Number of branch fetches per cycle 114system.cpu.fetch.rate 2.554344 # Number of inst fetches per cycle 115system.cpu.decode.IdleCycles 46935408 # Number of cycles decode is idle 116system.cpu.decode.BlockedCycles 5876258 # Number of cycles decode is blocked 117system.cpu.decode.RunCycles 76807695 # Number of cycles decode is running 118system.cpu.decode.UnblockCycles 1114753 # Number of cycles decode is unblocking 119system.cpu.decode.SquashCycles 21852743 # Number of cycles decode is squashing 120system.cpu.decode.BranchResolved 14847820 # Number of times decode resolved a branch 121system.cpu.decode.BranchMispred 163458 # Number of times decode detected a branch misprediction 122system.cpu.decode.DecodedInsts 403001894 # Number of instructions handled by decode 123system.cpu.decode.SquashedInsts 745204 # Number of squashed instructions handled by decode 124system.cpu.rename.SquashCycles 21852743 # Number of cycles rename is squashing 125system.cpu.rename.IdleCycles 52498514 # Number of cycles rename is idle 126system.cpu.rename.BlockCycles 705487 # Number of cycles rename is blocking 127system.cpu.rename.serializeStallCycles 794640 # count of cycles rename stalled for serializing inst 128system.cpu.rename.RunCycles 72299255 # Number of cycles rename is running 129system.cpu.rename.UnblockCycles 4436218 # Number of cycles rename is unblocking 130system.cpu.rename.RenamedInsts 380239935 # Number of instructions processed by rename 131system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full 132system.cpu.rename.IQFullEvents 319922 # Number of times rename has blocked due to IQ full 133system.cpu.rename.LSQFullEvents 3547314 # Number of times rename has blocked due to LSQ full 134system.cpu.rename.RenamedOperands 643715569 # Number of destination operands rename has renamed 135system.cpu.rename.RenameLookups 1619843514 # Number of register rename lookups that rename has made 136system.cpu.rename.int_rename_lookups 1602242427 # Number of integer rename lookups 137system.cpu.rename.fp_rename_lookups 17601087 # Number of floating rename lookups 138system.cpu.rename.CommittedMaps 298092552 # Number of HB maps that are committed 139system.cpu.rename.UndoneMaps 345623017 # Number of HB maps that are undone due to squashing 140system.cpu.rename.serializingInsts 60567 # count of serializing insts renamed 141system.cpu.rename.tempSerializingInsts 60564 # count of temporary serializing insts renamed 142system.cpu.rename.skidInsts 12828776 # count of insts added to the skid buffer 143system.cpu.memDep0.insertedLoads 44110344 # Number of loads inserted to the mem dependence unit. 144system.cpu.memDep0.insertedStores 16988908 # Number of stores inserted to the mem dependence unit. 145system.cpu.memDep0.conflictingLoads 5691426 # Number of conflicting loads. 146system.cpu.memDep0.conflictingStores 3676812 # Number of conflicting stores. 147system.cpu.iq.iqInstsAdded 335623795 # Number of instructions added to the IQ (excludes non-spec) 148system.cpu.iq.iqNonSpecInstsAdded 80679 # Number of non-speculative instructions added to the IQ 149system.cpu.iq.iqInstsIssued 253280777 # Number of instructions issued 150system.cpu.iq.iqSquashedInstsIssued 910888 # Number of squashed instructions issued 151system.cpu.iq.iqSquashedInstsExamined 145778004 # Number of squashed instructions iterated over during squash; mainly for profiling 152system.cpu.iq.iqSquashedOperandsExamined 375851378 # Number of squashed operands that are examined and possibly removed from graph 153system.cpu.iq.iqSquashedNonSpecRemoved 29413 # Number of squashed non-spec instructions that were removed 154system.cpu.iq.issued_per_cycle::samples 152586857 # Number of insts issued each cycle 155system.cpu.iq.issued_per_cycle::mean 1.659912 # Number of insts issued each cycle 156system.cpu.iq.issued_per_cycle::stdev 1.759603 # Number of insts issued each cycle | 112system.cpu.fetch.rateDist::total 152039589 # Number of instructions fetched each cycle (Total) 113system.cpu.fetch.branchRate 0.636675 # Number of branch fetches per cycle 114system.cpu.fetch.rate 2.554675 # Number of inst fetches per cycle 115system.cpu.decode.IdleCycles 46670430 # Number of cycles decode is idle 116system.cpu.decode.BlockedCycles 5932664 # Number of cycles decode is blocked 117system.cpu.decode.RunCycles 76574160 # Number of cycles decode is running 118system.cpu.decode.UnblockCycles 1118361 # Number of cycles decode is unblocking 119system.cpu.decode.SquashCycles 21743974 # Number of cycles decode is squashing 120system.cpu.decode.BranchResolved 14821262 # Number of times decode resolved a branch 121system.cpu.decode.BranchMispred 162795 # Number of times decode detected a branch misprediction 122system.cpu.decode.DecodedInsts 401681988 # Number of instructions handled by decode 123system.cpu.decode.SquashedInsts 736800 # Number of squashed instructions handled by decode 124system.cpu.rename.SquashCycles 21743974 # Number of cycles rename is squashing 125system.cpu.rename.IdleCycles 52193760 # Number of cycles rename is idle 126system.cpu.rename.BlockCycles 715909 # Number of cycles rename is blocking 127system.cpu.rename.serializeStallCycles 791714 # count of cycles rename stalled for serializing inst 128system.cpu.rename.RunCycles 72108942 # Number of cycles rename is running 129system.cpu.rename.UnblockCycles 4485290 # Number of cycles rename is unblocking 130system.cpu.rename.RenamedInsts 379159906 # Number of instructions processed by rename 131system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full 132system.cpu.rename.IQFullEvents 316677 # Number of times rename has blocked due to IQ full 133system.cpu.rename.LSQFullEvents 3600241 # Number of times rename has blocked due to LSQ full 134system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers 135system.cpu.rename.RenamedOperands 642535255 # Number of destination operands rename has renamed 136system.cpu.rename.RenameLookups 1615137204 # Number of register rename lookups that rename has made 137system.cpu.rename.int_rename_lookups 1597539210 # Number of integer rename lookups 138system.cpu.rename.fp_rename_lookups 17597994 # Number of floating rename lookups 139system.cpu.rename.CommittedMaps 298092419 # Number of HB maps that are committed 140system.cpu.rename.UndoneMaps 344442836 # Number of HB maps that are undone due to squashing 141system.cpu.rename.serializingInsts 52681 # count of serializing insts renamed 142system.cpu.rename.tempSerializingInsts 52677 # count of temporary serializing insts renamed 143system.cpu.rename.skidInsts 12879836 # count of insts added to the skid buffer 144system.cpu.memDep0.insertedLoads 44010443 # Number of loads inserted to the mem dependence unit. 145system.cpu.memDep0.insertedStores 16892323 # Number of stores inserted to the mem dependence unit. 146system.cpu.memDep0.conflictingLoads 5849879 # Number of conflicting loads. 147system.cpu.memDep0.conflictingStores 3738879 # Number of conflicting stores. 148system.cpu.iq.iqInstsAdded 334925831 # Number of instructions added to the IQ (excludes non-spec) 149system.cpu.iq.iqNonSpecInstsAdded 74527 # Number of non-speculative instructions added to the IQ 150system.cpu.iq.iqInstsIssued 252866200 # Number of instructions issued 151system.cpu.iq.iqSquashedInstsIssued 897062 # Number of squashed instructions issued 152system.cpu.iq.iqSquashedInstsExamined 145077714 # Number of squashed instructions iterated over during squash; mainly for profiling 153system.cpu.iq.iqSquashedOperandsExamined 374156671 # Number of squashed operands that are examined and possibly removed from graph 154system.cpu.iq.iqSquashedNonSpecRemoved 23276 # Number of squashed non-spec instructions that were removed 155system.cpu.iq.issued_per_cycle::samples 152039589 # Number of insts issued each cycle 156system.cpu.iq.issued_per_cycle::mean 1.663160 # Number of insts issued each cycle 157system.cpu.iq.issued_per_cycle::stdev 1.758894 # Number of insts issued each cycle |
| 157system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 158system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 158system.cpu.iq.issued_per_cycle::0 58969897 38.65% 38.65% # Number of insts issued each cycle 159system.cpu.iq.issued_per_cycle::1 23051369 15.11% 53.75% # Number of insts issued each cycle 160system.cpu.iq.issued_per_cycle::2 25143684 16.48% 70.23% # Number of insts issued each cycle 161system.cpu.iq.issued_per_cycle::3 20551680 13.47% 83.70% # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::4 12918795 8.47% 92.17% # Number of insts issued each cycle 163system.cpu.iq.issued_per_cycle::5 6596322 4.32% 96.49% # Number of insts issued each cycle 164system.cpu.iq.issued_per_cycle::6 4048422 2.65% 99.14% # Number of insts issued each cycle 165system.cpu.iq.issued_per_cycle::7 1113826 0.73% 99.87% # Number of insts issued each cycle 166system.cpu.iq.issued_per_cycle::8 192862 0.13% 100.00% # Number of insts issued each cycle | 159system.cpu.iq.issued_per_cycle::0 58521655 38.49% 38.49% # Number of insts issued each cycle 160system.cpu.iq.issued_per_cycle::1 23034636 15.15% 53.64% # Number of insts issued each cycle 161system.cpu.iq.issued_per_cycle::2 25191735 16.57% 70.21% # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::3 20480082 13.47% 83.68% # Number of insts issued each cycle 163system.cpu.iq.issued_per_cycle::4 12877411 8.47% 92.15% # Number of insts issued each cycle 164system.cpu.iq.issued_per_cycle::5 6577788 4.33% 96.48% # Number of insts issued each cycle 165system.cpu.iq.issued_per_cycle::6 4065173 2.67% 99.15% # Number of insts issued each cycle 166system.cpu.iq.issued_per_cycle::7 1110646 0.73% 99.88% # Number of insts issued each cycle 167system.cpu.iq.issued_per_cycle::8 180463 0.12% 100.00% # Number of insts issued each cycle |
| 167system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 168system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 169system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 168system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 169system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 170system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 170system.cpu.iq.issued_per_cycle::total 152586857 # Number of insts issued each cycle | 171system.cpu.iq.issued_per_cycle::total 152039589 # Number of insts issued each cycle |
| 171system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 172system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 172system.cpu.iq.fu_full::IntAlu 968336 37.79% 37.79% # attempts to use FU when none available 173system.cpu.iq.fu_full::IntMult 5589 0.22% 38.01% # attempts to use FU when none available 174system.cpu.iq.fu_full::IntDiv 0 0.00% 38.01% # attempts to use FU when none available 175system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.01% # attempts to use FU when none available 176system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.01% # attempts to use FU when none available 177system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.01% # attempts to use FU when none available 178system.cpu.iq.fu_full::FloatMult 0 0.00% 38.01% # attempts to use FU when none available 179system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.01% # attempts to use FU when none available 180system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.01% # attempts to use FU when none available 181system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.01% # attempts to use FU when none available 182system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.01% # attempts to use FU when none available 183system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.01% # attempts to use FU when none available 184system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.01% # attempts to use FU when none available 185system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.01% # attempts to use FU when none available 186system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.01% # attempts to use FU when none available 187system.cpu.iq.fu_full::SimdMult 0 0.00% 38.01% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.01% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdShift 0 0.00% 38.01% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.01% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.01% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdFloatAdd 91 0.00% 38.01% # attempts to use FU when none available 193system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.01% # attempts to use FU when none available 194system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.01% # attempts to use FU when none available 195system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.01% # attempts to use FU when none available 196system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.01% # attempts to use FU when none available 197system.cpu.iq.fu_full::SimdFloatMisc 33 0.00% 38.01% # attempts to use FU when none available 198system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.01% # attempts to use FU when none available 199system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.01% # attempts to use FU when none available 200system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.01% # attempts to use FU when none available 201system.cpu.iq.fu_full::MemRead 1185185 46.25% 84.27% # attempts to use FU when none available 202system.cpu.iq.fu_full::MemWrite 403164 15.73% 100.00% # attempts to use FU when none available | 173system.cpu.iq.fu_full::IntAlu 967418 37.56% 37.56% # attempts to use FU when none available 174system.cpu.iq.fu_full::IntMult 5599 0.22% 37.78% # attempts to use FU when none available 175system.cpu.iq.fu_full::IntDiv 0 0.00% 37.78% # attempts to use FU when none available 176system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.78% # attempts to use FU when none available 177system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.78% # attempts to use FU when none available 178system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.78% # attempts to use FU when none available 179system.cpu.iq.fu_full::FloatMult 0 0.00% 37.78% # attempts to use FU when none available 180system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.78% # attempts to use FU when none available 181system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.78% # attempts to use FU when none available 182system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.78% # attempts to use FU when none available 183system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.78% # attempts to use FU when none available 184system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.78% # attempts to use FU when none available 185system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.78% # attempts to use FU when none available 186system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.78% # attempts to use FU when none available 187system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.78% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdMult 0 0.00% 37.78% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.78% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdShift 0 0.00% 37.78% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.78% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.78% # attempts to use FU when none available 193system.cpu.iq.fu_full::SimdFloatAdd 146 0.01% 37.79% # attempts to use FU when none available 194system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.79% # attempts to use FU when none available 195system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.79% # attempts to use FU when none available 196system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 37.79% # attempts to use FU when none available 197system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.79% # attempts to use FU when none available 198system.cpu.iq.fu_full::SimdFloatMisc 21 0.00% 37.79% # attempts to use FU when none available 199system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.79% # attempts to use FU when none available 200system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.79% # attempts to use FU when none available 201system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.79% # attempts to use FU when none available 202system.cpu.iq.fu_full::MemRead 1198100 46.52% 84.30% # attempts to use FU when none available 203system.cpu.iq.fu_full::MemWrite 404230 15.70% 100.00% # attempts to use FU when none available |
| 203system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 204system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 205system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 204system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 205system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 206system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 206system.cpu.iq.FU_type_0::IntAlu 197697657 78.05% 78.05% # Type of FU issued 207system.cpu.iq.FU_type_0::IntMult 995408 0.39% 78.45% # Type of FU issued | 207system.cpu.iq.FU_type_0::IntAlu 197377765 78.06% 78.06% # Type of FU issued 208system.cpu.iq.FU_type_0::IntMult 996285 0.39% 78.45% # Type of FU issued |
| 208system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.45% # Type of FU issued 209system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.45% # Type of FU issued 210system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.45% # Type of FU issued 211system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.45% # Type of FU issued 212system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.45% # Type of FU issued 213system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.45% # Type of FU issued 214system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.45% # Type of FU issued 215system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.45% # Type of FU issued 216system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.45% # Type of FU issued 217system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.45% # Type of FU issued 218system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.45% # Type of FU issued 219system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.45% # Type of FU issued 220system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.45% # Type of FU issued 221system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.45% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.45% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.45% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.45% # Type of FU issued 225system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.45% # Type of FU issued | 209system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.45% # Type of FU issued 210system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.45% # Type of FU issued 211system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.45% # Type of FU issued 212system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.45% # Type of FU issued 213system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.45% # Type of FU issued 214system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.45% # Type of FU issued 215system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.45% # Type of FU issued 216system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.45% # Type of FU issued 217system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.45% # Type of FU issued 218system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.45% # Type of FU issued 219system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.45% # Type of FU issued 220system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.45% # Type of FU issued 221system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.45% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.45% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.45% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.45% # Type of FU issued 225system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.45% # Type of FU issued 226system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.45% # Type of FU issued |
| 226system.cpu.iq.FU_type_0::SimdFloatAdd 33135 0.01% 78.46% # Type of FU issued | 227system.cpu.iq.FU_type_0::SimdFloatAdd 33143 0.01% 78.46% # Type of FU issued |
| 227system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.46% # Type of FU issued | 228system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.46% # Type of FU issued |
| 228system.cpu.iq.FU_type_0::SimdFloatCmp 164107 0.06% 78.53% # Type of FU issued 229system.cpu.iq.FU_type_0::SimdFloatCvt 254969 0.10% 78.63% # Type of FU issued 230system.cpu.iq.FU_type_0::SimdFloatDiv 76438 0.03% 78.66% # Type of FU issued 231system.cpu.iq.FU_type_0::SimdFloatMisc 467546 0.18% 78.84% # Type of FU issued 232system.cpu.iq.FU_type_0::SimdFloatMult 206313 0.08% 78.92% # Type of FU issued 233system.cpu.iq.FU_type_0::SimdFloatMultAcc 71855 0.03% 78.95% # Type of FU issued 234system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 78.95% # Type of FU issued 235system.cpu.iq.FU_type_0::MemRead 39090450 15.43% 94.38% # Type of FU issued 236system.cpu.iq.FU_type_0::MemWrite 14222579 5.62% 100.00% # Type of FU issued | 229system.cpu.iq.FU_type_0::SimdFloatCmp 164246 0.06% 78.53% # Type of FU issued 230system.cpu.iq.FU_type_0::SimdFloatCvt 255557 0.10% 78.63% # Type of FU issued 231system.cpu.iq.FU_type_0::SimdFloatDiv 76455 0.03% 78.66% # Type of FU issued 232system.cpu.iq.FU_type_0::SimdFloatMisc 467877 0.19% 78.84% # Type of FU issued 233system.cpu.iq.FU_type_0::SimdFloatMult 206463 0.08% 78.93% # Type of FU issued 234system.cpu.iq.FU_type_0::SimdFloatMultAcc 71866 0.03% 78.95% # Type of FU issued 235system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.95% # Type of FU issued 236system.cpu.iq.FU_type_0::MemRead 39025783 15.43% 94.39% # Type of FU issued 237system.cpu.iq.FU_type_0::MemWrite 14190441 5.61% 100.00% # Type of FU issued |
| 237system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 238system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 238system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 239system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 239system.cpu.iq.FU_type_0::total 253280777 # Type of FU issued 240system.cpu.iq.rate 1.659274 # Inst issue rate 241system.cpu.iq.fu_busy_cnt 2562398 # FU busy when requested 242system.cpu.iq.fu_busy_rate 0.010117 # FU busy rate (busy events/executed inst) 243system.cpu.iq.int_inst_queue_reads 658846824 # Number of integer instruction queue reads 244system.cpu.iq.int_inst_queue_writes 479250938 # Number of integer instruction queue writes 245system.cpu.iq.int_inst_queue_wakeup_accesses 240868765 # Number of integer instruction queue wakeup accesses 246system.cpu.iq.fp_inst_queue_reads 3774873 # Number of floating instruction queue reads 247system.cpu.iq.fp_inst_queue_writes 2250330 # Number of floating instruction queue writes 248system.cpu.iq.fp_inst_queue_wakeup_accesses 1852271 # Number of floating instruction queue wakeup accesses 249system.cpu.iq.int_alu_accesses 253948063 # Number of integer alu accesses 250system.cpu.iq.fp_alu_accesses 1895112 # Number of floating point alu accesses 251system.cpu.iew.lsq.thread0.forwLoads 2034666 # Number of loads that had data forwarded from stores | 240system.cpu.iq.FU_type_0::total 252866200 # Type of FU issued 241system.cpu.iq.rate 1.662504 # Inst issue rate 242system.cpu.iq.fu_busy_cnt 2575514 # FU busy when requested 243system.cpu.iq.fu_busy_rate 0.010185 # FU busy rate (busy events/executed inst) 244system.cpu.iq.int_inst_queue_reads 657470724 # Number of integer instruction queue reads 245system.cpu.iq.int_inst_queue_writes 477849498 # Number of integer instruction queue writes 246system.cpu.iq.int_inst_queue_wakeup_accesses 240611060 # Number of integer instruction queue wakeup accesses 247system.cpu.iq.fp_inst_queue_reads 3773841 # Number of floating instruction queue reads 248system.cpu.iq.fp_inst_queue_writes 2247636 # Number of floating instruction queue writes 249system.cpu.iq.fp_inst_queue_wakeup_accesses 1852910 # Number of floating instruction queue wakeup accesses 250system.cpu.iq.int_alu_accesses 253547208 # Number of integer alu accesses 251system.cpu.iq.fp_alu_accesses 1894506 # Number of floating point alu accesses 252system.cpu.iew.lsq.thread0.forwLoads 2021626 # Number of loads that had data forwarded from stores |
| 252system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 253system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 253system.cpu.iew.lsq.thread0.squashedLoads 14254809 # Number of loads squashed 254system.cpu.iew.lsq.thread0.ignoredResponses 18806 # Number of memory responses ignored because the instruction is squashed 255system.cpu.iew.lsq.thread0.memOrderViolation 19550 # Number of memory ordering violations 256system.cpu.iew.lsq.thread0.squashedStores 4338224 # Number of stores squashed | 254system.cpu.iew.lsq.thread0.squashedLoads 14154924 # Number of loads squashed 255system.cpu.iew.lsq.thread0.ignoredResponses 16760 # Number of memory responses ignored because the instruction is squashed 256system.cpu.iew.lsq.thread0.memOrderViolation 19840 # Number of memory ordering violations 257system.cpu.iew.lsq.thread0.squashedStores 4241654 # Number of stores squashed |
| 257system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 258system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 258system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 259system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 259system.cpu.iew.lsq.thread0.rescheduledLoads 46 # Number of loads that were rescheduled | 260system.cpu.iew.lsq.thread0.rescheduledLoads 11 # Number of loads that were rescheduled |
| 260system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 261system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 261system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 262system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 262system.cpu.iew.iewSquashCycles 21852743 # Number of cycles IEW is squashing 263system.cpu.iew.iewBlockCycles 13300 # Number of cycles IEW is blocking 264system.cpu.iew.iewUnblockCycles 608 # Number of cycles IEW is unblocking 265system.cpu.iew.iewDispatchedInsts 335763367 # Number of instructions dispatched to IQ 266system.cpu.iew.iewDispSquashedInsts 963800 # Number of squashed instructions skipped by dispatch 267system.cpu.iew.iewDispLoadInsts 44110344 # Number of dispatched load instructions 268system.cpu.iew.iewDispStoreInsts 16988908 # Number of dispatched store instructions 269system.cpu.iew.iewDispNonSpecInsts 58117 # Number of dispatched non-speculative instructions 270system.cpu.iew.iewIQFullEvents 150 # Number of times the IQ has become full, causing a stall 271system.cpu.iew.iewLSQFullEvents 281 # Number of times the LSQ has become full, causing a stall 272system.cpu.iew.memOrderViolationEvents 19550 # Number of memory order violations 273system.cpu.iew.predictedTakenIncorrect 4170846 # Number of branches that were predicted taken incorrectly 274system.cpu.iew.predictedNotTakenIncorrect 3956659 # Number of branches that were predicted not taken incorrectly 275system.cpu.iew.branchMispredicts 8127505 # Number of branch mispredicts detected at execute 276system.cpu.iew.iewExecutedInsts 246138856 # Number of executed instructions 277system.cpu.iew.iewExecLoadInsts 37439094 # Number of load instructions executed 278system.cpu.iew.iewExecSquashedInsts 7141921 # Number of squashed instructions skipped in execute | 263system.cpu.iew.iewSquashCycles 21743974 # Number of cycles IEW is squashing 264system.cpu.iew.iewBlockCycles 13418 # Number of cycles IEW is blocking 265system.cpu.iew.iewUnblockCycles 622 # Number of cycles IEW is unblocking 266system.cpu.iew.iewDispatchedInsts 335058586 # Number of instructions dispatched to IQ 267system.cpu.iew.iewDispSquashedInsts 832362 # Number of squashed instructions skipped by dispatch 268system.cpu.iew.iewDispLoadInsts 44010443 # Number of dispatched load instructions 269system.cpu.iew.iewDispStoreInsts 16892323 # Number of dispatched store instructions 270system.cpu.iew.iewDispNonSpecInsts 51985 # Number of dispatched non-speculative instructions 271system.cpu.iew.iewIQFullEvents 162 # Number of times the IQ has become full, causing a stall 272system.cpu.iew.iewLSQFullEvents 263 # Number of times the LSQ has become full, causing a stall 273system.cpu.iew.memOrderViolationEvents 19840 # Number of memory order violations 274system.cpu.iew.predictedTakenIncorrect 4108839 # Number of branches that were predicted taken incorrectly 275system.cpu.iew.predictedNotTakenIncorrect 3946041 # Number of branches that were predicted not taken incorrectly 276system.cpu.iew.branchMispredicts 8054880 # Number of branch mispredicts detected at execute 277system.cpu.iew.iewExecutedInsts 245860683 # Number of executed instructions 278system.cpu.iew.iewExecLoadInsts 37402341 # Number of load instructions executed 279system.cpu.iew.iewExecSquashedInsts 7005517 # Number of squashed instructions skipped in execute |
| 279system.cpu.iew.exec_swp 0 # number of swp insts executed | 280system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 280system.cpu.iew.exec_nop 58893 # number of nop insts executed 281system.cpu.iew.exec_refs 51255438 # number of memory reference insts executed 282system.cpu.iew.exec_branches 54101167 # Number of branches executed 283system.cpu.iew.exec_stores 13816344 # Number of stores executed 284system.cpu.iew.exec_rate 1.612486 # Inst execution rate 285system.cpu.iew.wb_sent 243866975 # cumulative count of insts sent to commit 286system.cpu.iew.wb_count 242721036 # cumulative count of insts written-back 287system.cpu.iew.wb_producers 150184249 # num instructions producing a value 288system.cpu.iew.wb_consumers 269391648 # num instructions consuming a value | 281system.cpu.iew.exec_nop 58228 # number of nop insts executed 282system.cpu.iew.exec_refs 51211338 # number of memory reference insts executed 283system.cpu.iew.exec_branches 54022808 # Number of branches executed 284system.cpu.iew.exec_stores 13808997 # Number of stores executed 285system.cpu.iew.exec_rate 1.616445 # Inst execution rate 286system.cpu.iew.wb_sent 243598204 # cumulative count of insts sent to commit 287system.cpu.iew.wb_count 242463970 # cumulative count of insts written-back 288system.cpu.iew.wb_producers 150083518 # num instructions producing a value 289system.cpu.iew.wb_consumers 269173561 # num instructions consuming a value |
| 289system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 290system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 290system.cpu.iew.wb_rate 1.590096 # insts written-back per cycle 291system.cpu.iew.wb_fanout 0.557494 # average fanout of values written-back | 291system.cpu.iew.wb_rate 1.594113 # insts written-back per cycle 292system.cpu.iew.wb_fanout 0.557572 # average fanout of values written-back |
| 292system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 293system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 293system.cpu.commit.commitCommittedInsts 172347667 # The number of committed instructions 294system.cpu.commit.commitCommittedOps 188701150 # The number of committed instructions 295system.cpu.commit.commitSquashedInsts 147062192 # The number of squashed insts skipped by commit 296system.cpu.commit.commitNonSpecStalls 51266 # The number of times commit has been forced to stall to communicate backwards 297system.cpu.commit.branchMispredicts 6488296 # The number of times a branch was mispredicted 298system.cpu.commit.committed_per_cycle::samples 130734115 # Number of insts commited each cycle 299system.cpu.commit.committed_per_cycle::mean 1.443396 # Number of insts commited each cycle 300system.cpu.commit.committed_per_cycle::stdev 2.157229 # Number of insts commited each cycle | 294system.cpu.commit.commitCommittedInsts 172347584 # The number of committed instructions 295system.cpu.commit.commitCommittedOps 188701066 # The number of committed instructions 296system.cpu.commit.commitSquashedInsts 146357504 # The number of squashed insts skipped by commit 297system.cpu.commit.commitNonSpecStalls 51251 # The number of times commit has been forced to stall to communicate backwards 298system.cpu.commit.branchMispredicts 6423604 # The number of times a branch was mispredicted 299system.cpu.commit.committed_per_cycle::samples 130295616 # Number of insts commited each cycle 300system.cpu.commit.committed_per_cycle::mean 1.448253 # Number of insts commited each cycle 301system.cpu.commit.committed_per_cycle::stdev 2.160604 # Number of insts commited each cycle |
| 301system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 302system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 302system.cpu.commit.committed_per_cycle::0 60440090 46.23% 46.23% # Number of insts commited each cycle 303system.cpu.commit.committed_per_cycle::1 32094015 24.55% 70.78% # Number of insts commited each cycle 304system.cpu.commit.committed_per_cycle::2 14011020 10.72% 81.50% # Number of insts commited each cycle 305system.cpu.commit.committed_per_cycle::3 7691837 5.88% 87.38% # Number of insts commited each cycle 306system.cpu.commit.committed_per_cycle::4 4423613 3.38% 90.76% # Number of insts commited each cycle 307system.cpu.commit.committed_per_cycle::5 1340820 1.03% 91.79% # Number of insts commited each cycle 308system.cpu.commit.committed_per_cycle::6 1731909 1.32% 93.12% # Number of insts commited each cycle 309system.cpu.commit.committed_per_cycle::7 1286910 0.98% 94.10% # Number of insts commited each cycle 310system.cpu.commit.committed_per_cycle::8 7713901 5.90% 100.00% # Number of insts commited each cycle | 303system.cpu.commit.committed_per_cycle::0 60033353 46.07% 46.07% # Number of insts commited each cycle 304system.cpu.commit.committed_per_cycle::1 32093498 24.63% 70.71% # Number of insts commited each cycle 305system.cpu.commit.committed_per_cycle::2 14006031 10.75% 81.46% # Number of insts commited each cycle 306system.cpu.commit.committed_per_cycle::3 7653781 5.87% 87.33% # Number of insts commited each cycle 307system.cpu.commit.committed_per_cycle::4 4421161 3.39% 90.72% # Number of insts commited each cycle 308system.cpu.commit.committed_per_cycle::5 1332201 1.02% 91.75% # Number of insts commited each cycle 309system.cpu.commit.committed_per_cycle::6 1737103 1.33% 93.08% # Number of insts commited each cycle 310system.cpu.commit.committed_per_cycle::7 1282008 0.98% 94.06% # Number of insts commited each cycle 311system.cpu.commit.committed_per_cycle::8 7736480 5.94% 100.00% # Number of insts commited each cycle |
| 311system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 312system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 313system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 312system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 313system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 314system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 314system.cpu.commit.committed_per_cycle::total 130734115 # Number of insts commited each cycle 315system.cpu.commit.committedInsts 172347667 # Number of instructions committed 316system.cpu.commit.committedOps 188701150 # Number of ops (including micro ops) committed | 315system.cpu.commit.committed_per_cycle::total 130295616 # Number of insts commited each cycle 316system.cpu.commit.committedInsts 172347584 # Number of instructions committed 317system.cpu.commit.committedOps 188701066 # Number of ops (including micro ops) committed |
| 317system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 318system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 318system.cpu.commit.refs 42506219 # Number of memory references committed 319system.cpu.commit.loads 29855535 # Number of loads committed | 319system.cpu.commit.refs 42506188 # Number of memory references committed 320system.cpu.commit.loads 29855519 # Number of loads committed |
| 320system.cpu.commit.membars 22408 # Number of memory barriers committed | 321system.cpu.commit.membars 22408 # Number of memory barriers committed |
| 321system.cpu.commit.branches 40287733 # Number of branches committed | 322system.cpu.commit.branches 40287717 # Number of branches committed |
| 322system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. | 323system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. |
| 323system.cpu.commit.int_insts 150130425 # Number of committed integer instructions. | 324system.cpu.commit.int_insts 150130357 # Number of committed integer instructions. |
| 324system.cpu.commit.function_calls 1848934 # Number of function calls committed. | 325system.cpu.commit.function_calls 1848934 # Number of function calls committed. |
| 325system.cpu.commit.bw_lim_events 7713901 # number cycles where commit BW limit reached | 326system.cpu.commit.bw_lim_events 7736480 # number cycles where commit BW limit reached |
| 326system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 327system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 327system.cpu.rob.rob_reads 458778355 # The number of ROB reads 328system.cpu.rob.rob_writes 693498788 # The number of ROB writes 329system.cpu.timesIdled 1746 # Number of times that the entire CPU went into an idle state and unscheduled itself 330system.cpu.idleCycles 58673 # Total number of cycles that the CPU has spent unscheduled due to idling 331system.cpu.committedInsts 172333279 # Number of Instructions Simulated 332system.cpu.committedOps 188686762 # Number of Ops (including micro ops) Simulated 333system.cpu.committedInsts_total 172333279 # Number of Instructions Simulated 334system.cpu.cpi 0.885758 # CPI: Cycles Per Instruction 335system.cpu.cpi_total 0.885758 # CPI: Total CPI of All Threads 336system.cpu.ipc 1.128977 # IPC: Instructions Per Cycle 337system.cpu.ipc_total 1.128977 # IPC: Total IPC of All Threads 338system.cpu.int_regfile_reads 1093182861 # number of integer regfile reads 339system.cpu.int_regfile_writes 388952433 # number of integer regfile writes 340system.cpu.fp_regfile_reads 2911975 # number of floating regfile reads 341system.cpu.fp_regfile_writes 2511798 # number of floating regfile writes 342system.cpu.misc_regfile_reads 476343702 # number of misc regfile reads 343system.cpu.misc_regfile_writes 832136 # number of misc regfile writes 344system.cpu.icache.replacements 2645 # number of replacements 345system.cpu.icache.tagsinuse 1374.603363 # Cycle average of tags in use 346system.cpu.icache.total_refs 37836261 # Total number of references to valid blocks. 347system.cpu.icache.sampled_refs 4394 # Sample count of references to valid blocks. 348system.cpu.icache.avg_refs 8610.892353 # Average number of references to valid blocks. | 328system.cpu.rob.rob_reads 457612505 # The number of ROB reads 329system.cpu.rob.rob_writes 691979598 # The number of ROB writes 330system.cpu.timesIdled 1775 # Number of times that the entire CPU went into an idle state and unscheduled itself 331system.cpu.idleCycles 60012 # Total number of cycles that the CPU has spent unscheduled due to idling 332system.cpu.committedInsts 172333196 # Number of Instructions Simulated 333system.cpu.committedOps 188686678 # Number of Ops (including micro ops) Simulated 334system.cpu.committedInsts_total 172333196 # Number of Instructions Simulated 335system.cpu.cpi 0.882590 # CPI: Cycles Per Instruction 336system.cpu.cpi_total 0.882590 # CPI: Total CPI of All Threads 337system.cpu.ipc 1.133029 # IPC: Instructions Per Cycle 338system.cpu.ipc_total 1.133029 # IPC: Total IPC of All Threads 339system.cpu.int_regfile_reads 1092071141 # number of integer regfile reads 340system.cpu.int_regfile_writes 388656879 # number of integer regfile writes 341system.cpu.fp_regfile_reads 2914235 # number of floating regfile reads 342system.cpu.fp_regfile_writes 2512527 # number of floating regfile writes 343system.cpu.misc_regfile_reads 474801777 # number of misc regfile reads 344system.cpu.misc_regfile_writes 832106 # number of misc regfile writes 345system.cpu.icache.replacements 2596 # number of replacements 346system.cpu.icache.tagsinuse 1365.085421 # Cycle average of tags in use 347system.cpu.icache.total_refs 37653918 # Total number of references to valid blocks. 348system.cpu.icache.sampled_refs 4338 # Sample count of references to valid blocks. 349system.cpu.icache.avg_refs 8680.017981 # Average number of references to valid blocks. |
| 349system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 350system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 350system.cpu.icache.occ_blocks::cpu.inst 1374.603363 # Average occupied blocks per requestor 351system.cpu.icache.occ_percent::cpu.inst 0.671193 # Average percentage of cache occupancy 352system.cpu.icache.occ_percent::total 0.671193 # Average percentage of cache occupancy 353system.cpu.icache.ReadReq_hits::cpu.inst 37836261 # number of ReadReq hits 354system.cpu.icache.ReadReq_hits::total 37836261 # number of ReadReq hits 355system.cpu.icache.demand_hits::cpu.inst 37836261 # number of demand (read+write) hits 356system.cpu.icache.demand_hits::total 37836261 # number of demand (read+write) hits 357system.cpu.icache.overall_hits::cpu.inst 37836261 # number of overall hits 358system.cpu.icache.overall_hits::total 37836261 # number of overall hits 359system.cpu.icache.ReadReq_misses::cpu.inst 5199 # number of ReadReq misses 360system.cpu.icache.ReadReq_misses::total 5199 # number of ReadReq misses 361system.cpu.icache.demand_misses::cpu.inst 5199 # number of demand (read+write) misses 362system.cpu.icache.demand_misses::total 5199 # number of demand (read+write) misses 363system.cpu.icache.overall_misses::cpu.inst 5199 # number of overall misses 364system.cpu.icache.overall_misses::total 5199 # number of overall misses 365system.cpu.icache.ReadReq_miss_latency::cpu.inst 112756500 # number of ReadReq miss cycles 366system.cpu.icache.ReadReq_miss_latency::total 112756500 # number of ReadReq miss cycles 367system.cpu.icache.demand_miss_latency::cpu.inst 112756500 # number of demand (read+write) miss cycles 368system.cpu.icache.demand_miss_latency::total 112756500 # number of demand (read+write) miss cycles 369system.cpu.icache.overall_miss_latency::cpu.inst 112756500 # number of overall miss cycles 370system.cpu.icache.overall_miss_latency::total 112756500 # number of overall miss cycles 371system.cpu.icache.ReadReq_accesses::cpu.inst 37841460 # number of ReadReq accesses(hits+misses) 372system.cpu.icache.ReadReq_accesses::total 37841460 # number of ReadReq accesses(hits+misses) 373system.cpu.icache.demand_accesses::cpu.inst 37841460 # number of demand (read+write) accesses 374system.cpu.icache.demand_accesses::total 37841460 # number of demand (read+write) accesses 375system.cpu.icache.overall_accesses::cpu.inst 37841460 # number of overall (read+write) accesses 376system.cpu.icache.overall_accesses::total 37841460 # number of overall (read+write) accesses 377system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000137 # miss rate for ReadReq accesses 378system.cpu.icache.ReadReq_miss_rate::total 0.000137 # miss rate for ReadReq accesses 379system.cpu.icache.demand_miss_rate::cpu.inst 0.000137 # miss rate for demand accesses 380system.cpu.icache.demand_miss_rate::total 0.000137 # miss rate for demand accesses 381system.cpu.icache.overall_miss_rate::cpu.inst 0.000137 # miss rate for overall accesses 382system.cpu.icache.overall_miss_rate::total 0.000137 # miss rate for overall accesses 383system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21688.113099 # average ReadReq miss latency 384system.cpu.icache.ReadReq_avg_miss_latency::total 21688.113099 # average ReadReq miss latency 385system.cpu.icache.demand_avg_miss_latency::cpu.inst 21688.113099 # average overall miss latency 386system.cpu.icache.demand_avg_miss_latency::total 21688.113099 # average overall miss latency 387system.cpu.icache.overall_avg_miss_latency::cpu.inst 21688.113099 # average overall miss latency 388system.cpu.icache.overall_avg_miss_latency::total 21688.113099 # average overall miss latency | 351system.cpu.icache.occ_blocks::cpu.inst 1365.085421 # Average occupied blocks per requestor 352system.cpu.icache.occ_percent::cpu.inst 0.666546 # Average percentage of cache occupancy 353system.cpu.icache.occ_percent::total 0.666546 # Average percentage of cache occupancy 354system.cpu.icache.ReadReq_hits::cpu.inst 37653921 # number of ReadReq hits 355system.cpu.icache.ReadReq_hits::total 37653921 # number of ReadReq hits 356system.cpu.icache.demand_hits::cpu.inst 37653921 # number of demand (read+write) hits 357system.cpu.icache.demand_hits::total 37653921 # number of demand (read+write) hits 358system.cpu.icache.overall_hits::cpu.inst 37653921 # number of overall hits 359system.cpu.icache.overall_hits::total 37653921 # number of overall hits 360system.cpu.icache.ReadReq_misses::cpu.inst 5110 # number of ReadReq misses 361system.cpu.icache.ReadReq_misses::total 5110 # number of ReadReq misses 362system.cpu.icache.demand_misses::cpu.inst 5110 # number of demand (read+write) misses 363system.cpu.icache.demand_misses::total 5110 # number of demand (read+write) misses 364system.cpu.icache.overall_misses::cpu.inst 5110 # number of overall misses 365system.cpu.icache.overall_misses::total 5110 # number of overall misses 366system.cpu.icache.ReadReq_miss_latency::cpu.inst 111334000 # number of ReadReq miss cycles 367system.cpu.icache.ReadReq_miss_latency::total 111334000 # number of ReadReq miss cycles 368system.cpu.icache.demand_miss_latency::cpu.inst 111334000 # number of demand (read+write) miss cycles 369system.cpu.icache.demand_miss_latency::total 111334000 # number of demand (read+write) miss cycles 370system.cpu.icache.overall_miss_latency::cpu.inst 111334000 # number of overall miss cycles 371system.cpu.icache.overall_miss_latency::total 111334000 # number of overall miss cycles 372system.cpu.icache.ReadReq_accesses::cpu.inst 37659031 # number of ReadReq accesses(hits+misses) 373system.cpu.icache.ReadReq_accesses::total 37659031 # number of ReadReq accesses(hits+misses) 374system.cpu.icache.demand_accesses::cpu.inst 37659031 # number of demand (read+write) accesses 375system.cpu.icache.demand_accesses::total 37659031 # number of demand (read+write) accesses 376system.cpu.icache.overall_accesses::cpu.inst 37659031 # number of overall (read+write) accesses 377system.cpu.icache.overall_accesses::total 37659031 # number of overall (read+write) accesses 378system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000136 # miss rate for ReadReq accesses 379system.cpu.icache.ReadReq_miss_rate::total 0.000136 # miss rate for ReadReq accesses 380system.cpu.icache.demand_miss_rate::cpu.inst 0.000136 # miss rate for demand accesses 381system.cpu.icache.demand_miss_rate::total 0.000136 # miss rate for demand accesses 382system.cpu.icache.overall_miss_rate::cpu.inst 0.000136 # miss rate for overall accesses 383system.cpu.icache.overall_miss_rate::total 0.000136 # miss rate for overall accesses 384system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21787.475538 # average ReadReq miss latency 385system.cpu.icache.ReadReq_avg_miss_latency::total 21787.475538 # average ReadReq miss latency 386system.cpu.icache.demand_avg_miss_latency::cpu.inst 21787.475538 # average overall miss latency 387system.cpu.icache.demand_avg_miss_latency::total 21787.475538 # average overall miss latency 388system.cpu.icache.overall_avg_miss_latency::cpu.inst 21787.475538 # average overall miss latency 389system.cpu.icache.overall_avg_miss_latency::total 21787.475538 # average overall miss latency |
| 389system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 390system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 391system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 392system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 393system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 394system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 395system.cpu.icache.fast_writes 0 # number of fast writes performed 396system.cpu.icache.cache_copies 0 # number of cache copies performed | 390system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 391system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 392system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 393system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 394system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 395system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 396system.cpu.icache.fast_writes 0 # number of fast writes performed 397system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 397system.cpu.icache.ReadReq_mshr_hits::cpu.inst 804 # number of ReadReq MSHR hits 398system.cpu.icache.ReadReq_mshr_hits::total 804 # number of ReadReq MSHR hits 399system.cpu.icache.demand_mshr_hits::cpu.inst 804 # number of demand (read+write) MSHR hits 400system.cpu.icache.demand_mshr_hits::total 804 # number of demand (read+write) MSHR hits 401system.cpu.icache.overall_mshr_hits::cpu.inst 804 # number of overall MSHR hits 402system.cpu.icache.overall_mshr_hits::total 804 # number of overall MSHR hits 403system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4395 # number of ReadReq MSHR misses 404system.cpu.icache.ReadReq_mshr_misses::total 4395 # number of ReadReq MSHR misses 405system.cpu.icache.demand_mshr_misses::cpu.inst 4395 # number of demand (read+write) MSHR misses 406system.cpu.icache.demand_mshr_misses::total 4395 # number of demand (read+write) MSHR misses 407system.cpu.icache.overall_mshr_misses::cpu.inst 4395 # number of overall MSHR misses 408system.cpu.icache.overall_mshr_misses::total 4395 # number of overall MSHR misses 409system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 78893000 # number of ReadReq MSHR miss cycles 410system.cpu.icache.ReadReq_mshr_miss_latency::total 78893000 # number of ReadReq MSHR miss cycles 411system.cpu.icache.demand_mshr_miss_latency::cpu.inst 78893000 # number of demand (read+write) MSHR miss cycles 412system.cpu.icache.demand_mshr_miss_latency::total 78893000 # number of demand (read+write) MSHR miss cycles 413system.cpu.icache.overall_mshr_miss_latency::cpu.inst 78893000 # number of overall MSHR miss cycles 414system.cpu.icache.overall_mshr_miss_latency::total 78893000 # number of overall MSHR miss cycles 415system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for ReadReq accesses 416system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000116 # mshr miss rate for ReadReq accesses 417system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for demand accesses 418system.cpu.icache.demand_mshr_miss_rate::total 0.000116 # mshr miss rate for demand accesses 419system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for overall accesses 420system.cpu.icache.overall_mshr_miss_rate::total 0.000116 # mshr miss rate for overall accesses 421system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17950.625711 # average ReadReq mshr miss latency 422system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17950.625711 # average ReadReq mshr miss latency 423system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17950.625711 # average overall mshr miss latency 424system.cpu.icache.demand_avg_mshr_miss_latency::total 17950.625711 # average overall mshr miss latency 425system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17950.625711 # average overall mshr miss latency 426system.cpu.icache.overall_avg_mshr_miss_latency::total 17950.625711 # average overall mshr miss latency | 398system.cpu.icache.ReadReq_mshr_hits::cpu.inst 768 # number of ReadReq MSHR hits 399system.cpu.icache.ReadReq_mshr_hits::total 768 # number of ReadReq MSHR hits 400system.cpu.icache.demand_mshr_hits::cpu.inst 768 # number of demand (read+write) MSHR hits 401system.cpu.icache.demand_mshr_hits::total 768 # number of demand (read+write) MSHR hits 402system.cpu.icache.overall_mshr_hits::cpu.inst 768 # number of overall MSHR hits 403system.cpu.icache.overall_mshr_hits::total 768 # number of overall MSHR hits 404system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4342 # number of ReadReq MSHR misses 405system.cpu.icache.ReadReq_mshr_misses::total 4342 # number of ReadReq MSHR misses 406system.cpu.icache.demand_mshr_misses::cpu.inst 4342 # number of demand (read+write) MSHR misses 407system.cpu.icache.demand_mshr_misses::total 4342 # number of demand (read+write) MSHR misses 408system.cpu.icache.overall_mshr_misses::cpu.inst 4342 # number of overall MSHR misses 409system.cpu.icache.overall_mshr_misses::total 4342 # number of overall MSHR misses 410system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 78323000 # number of ReadReq MSHR miss cycles 411system.cpu.icache.ReadReq_mshr_miss_latency::total 78323000 # number of ReadReq MSHR miss cycles 412system.cpu.icache.demand_mshr_miss_latency::cpu.inst 78323000 # number of demand (read+write) MSHR miss cycles 413system.cpu.icache.demand_mshr_miss_latency::total 78323000 # number of demand (read+write) MSHR miss cycles 414system.cpu.icache.overall_mshr_miss_latency::cpu.inst 78323000 # number of overall MSHR miss cycles 415system.cpu.icache.overall_mshr_miss_latency::total 78323000 # number of overall MSHR miss cycles 416system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000115 # mshr miss rate for ReadReq accesses 417system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000115 # mshr miss rate for ReadReq accesses 418system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000115 # mshr miss rate for demand accesses 419system.cpu.icache.demand_mshr_miss_rate::total 0.000115 # mshr miss rate for demand accesses 420system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000115 # mshr miss rate for overall accesses 421system.cpu.icache.overall_mshr_miss_rate::total 0.000115 # mshr miss rate for overall accesses 422system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18038.461538 # average ReadReq mshr miss latency 423system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18038.461538 # average ReadReq mshr miss latency 424system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18038.461538 # average overall mshr miss latency 425system.cpu.icache.demand_avg_mshr_miss_latency::total 18038.461538 # average overall mshr miss latency 426system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18038.461538 # average overall mshr miss latency 427system.cpu.icache.overall_avg_mshr_miss_latency::total 18038.461538 # average overall mshr miss latency |
| 427system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 428system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 428system.cpu.dcache.replacements 59 # number of replacements 429system.cpu.dcache.tagsinuse 1421.643782 # Cycle average of tags in use 430system.cpu.dcache.total_refs 47334662 # Total number of references to valid blocks. 431system.cpu.dcache.sampled_refs 1881 # Sample count of references to valid blocks. 432system.cpu.dcache.avg_refs 25164.626263 # Average number of references to valid blocks. | 429system.cpu.dcache.replacements 58 # number of replacements 430system.cpu.dcache.tagsinuse 1413.439257 # Cycle average of tags in use 431system.cpu.dcache.total_refs 47316793 # Total number of references to valid blocks. 432system.cpu.dcache.sampled_refs 1865 # Sample count of references to valid blocks. 433system.cpu.dcache.avg_refs 25370.934584 # Average number of references to valid blocks. |
| 433system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 434system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 434system.cpu.dcache.occ_blocks::cpu.data 1421.643782 # Average occupied blocks per requestor 435system.cpu.dcache.occ_percent::cpu.data 0.347081 # Average percentage of cache occupancy 436system.cpu.dcache.occ_percent::total 0.347081 # Average percentage of cache occupancy 437system.cpu.dcache.ReadReq_hits::cpu.data 34919209 # number of ReadReq hits 438system.cpu.dcache.ReadReq_hits::total 34919209 # number of ReadReq hits 439system.cpu.dcache.WriteReq_hits::cpu.data 12356677 # number of WriteReq hits 440system.cpu.dcache.WriteReq_hits::total 12356677 # number of WriteReq hits 441system.cpu.dcache.LoadLockedReq_hits::cpu.data 30319 # number of LoadLockedReq hits 442system.cpu.dcache.LoadLockedReq_hits::total 30319 # number of LoadLockedReq hits 443system.cpu.dcache.StoreCondReq_hits::cpu.data 28457 # number of StoreCondReq hits 444system.cpu.dcache.StoreCondReq_hits::total 28457 # number of StoreCondReq hits 445system.cpu.dcache.demand_hits::cpu.data 47275886 # number of demand (read+write) hits 446system.cpu.dcache.demand_hits::total 47275886 # number of demand (read+write) hits 447system.cpu.dcache.overall_hits::cpu.data 47275886 # number of overall hits 448system.cpu.dcache.overall_hits::total 47275886 # number of overall hits 449system.cpu.dcache.ReadReq_misses::cpu.data 1860 # number of ReadReq misses 450system.cpu.dcache.ReadReq_misses::total 1860 # number of ReadReq misses 451system.cpu.dcache.WriteReq_misses::cpu.data 7610 # number of WriteReq misses 452system.cpu.dcache.WriteReq_misses::total 7610 # number of WriteReq misses | 435system.cpu.dcache.occ_blocks::cpu.data 1413.439257 # Average occupied blocks per requestor 436system.cpu.dcache.occ_percent::cpu.data 0.345078 # Average percentage of cache occupancy 437system.cpu.dcache.occ_percent::total 0.345078 # Average percentage of cache occupancy 438system.cpu.dcache.ReadReq_hits::cpu.data 34901837 # number of ReadReq hits 439system.cpu.dcache.ReadReq_hits::total 34901837 # number of ReadReq hits 440system.cpu.dcache.WriteReq_hits::cpu.data 12356702 # number of WriteReq hits 441system.cpu.dcache.WriteReq_hits::total 12356702 # number of WriteReq hits 442system.cpu.dcache.LoadLockedReq_hits::cpu.data 29806 # number of LoadLockedReq hits 443system.cpu.dcache.LoadLockedReq_hits::total 29806 # number of LoadLockedReq hits 444system.cpu.dcache.StoreCondReq_hits::cpu.data 28442 # number of StoreCondReq hits 445system.cpu.dcache.StoreCondReq_hits::total 28442 # number of StoreCondReq hits 446system.cpu.dcache.demand_hits::cpu.data 47258539 # number of demand (read+write) hits 447system.cpu.dcache.demand_hits::total 47258539 # number of demand (read+write) hits 448system.cpu.dcache.overall_hits::cpu.data 47258539 # number of overall hits 449system.cpu.dcache.overall_hits::total 47258539 # number of overall hits 450system.cpu.dcache.ReadReq_misses::cpu.data 1853 # number of ReadReq misses 451system.cpu.dcache.ReadReq_misses::total 1853 # number of ReadReq misses 452system.cpu.dcache.WriteReq_misses::cpu.data 7585 # number of WriteReq misses 453system.cpu.dcache.WriteReq_misses::total 7585 # number of WriteReq misses |
| 453system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 454system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses | 454system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 455system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses |
| 455system.cpu.dcache.demand_misses::cpu.data 9470 # number of demand (read+write) misses 456system.cpu.dcache.demand_misses::total 9470 # number of demand (read+write) misses 457system.cpu.dcache.overall_misses::cpu.data 9470 # number of overall misses 458system.cpu.dcache.overall_misses::total 9470 # number of overall misses 459system.cpu.dcache.ReadReq_miss_latency::cpu.data 60591000 # number of ReadReq miss cycles 460system.cpu.dcache.ReadReq_miss_latency::total 60591000 # number of ReadReq miss cycles 461system.cpu.dcache.WriteReq_miss_latency::cpu.data 237329500 # number of WriteReq miss cycles 462system.cpu.dcache.WriteReq_miss_latency::total 237329500 # number of WriteReq miss cycles | 456system.cpu.dcache.demand_misses::cpu.data 9438 # number of demand (read+write) misses 457system.cpu.dcache.demand_misses::total 9438 # number of demand (read+write) misses 458system.cpu.dcache.overall_misses::cpu.data 9438 # number of overall misses 459system.cpu.dcache.overall_misses::total 9438 # number of overall misses 460system.cpu.dcache.ReadReq_miss_latency::cpu.data 59897500 # number of ReadReq miss cycles 461system.cpu.dcache.ReadReq_miss_latency::total 59897500 # number of ReadReq miss cycles 462system.cpu.dcache.WriteReq_miss_latency::cpu.data 237415000 # number of WriteReq miss cycles 463system.cpu.dcache.WriteReq_miss_latency::total 237415000 # number of WriteReq miss cycles |
| 463system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 64000 # number of LoadLockedReq miss cycles 464system.cpu.dcache.LoadLockedReq_miss_latency::total 64000 # number of LoadLockedReq miss cycles | 464system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 64000 # number of LoadLockedReq miss cycles 465system.cpu.dcache.LoadLockedReq_miss_latency::total 64000 # number of LoadLockedReq miss cycles |
| 465system.cpu.dcache.demand_miss_latency::cpu.data 297920500 # number of demand (read+write) miss cycles 466system.cpu.dcache.demand_miss_latency::total 297920500 # number of demand (read+write) miss cycles 467system.cpu.dcache.overall_miss_latency::cpu.data 297920500 # number of overall miss cycles 468system.cpu.dcache.overall_miss_latency::total 297920500 # number of overall miss cycles 469system.cpu.dcache.ReadReq_accesses::cpu.data 34921069 # number of ReadReq accesses(hits+misses) 470system.cpu.dcache.ReadReq_accesses::total 34921069 # number of ReadReq accesses(hits+misses) | 466system.cpu.dcache.demand_miss_latency::cpu.data 297312500 # number of demand (read+write) miss cycles 467system.cpu.dcache.demand_miss_latency::total 297312500 # number of demand (read+write) miss cycles 468system.cpu.dcache.overall_miss_latency::cpu.data 297312500 # number of overall miss cycles 469system.cpu.dcache.overall_miss_latency::total 297312500 # number of overall miss cycles 470system.cpu.dcache.ReadReq_accesses::cpu.data 34903690 # number of ReadReq accesses(hits+misses) 471system.cpu.dcache.ReadReq_accesses::total 34903690 # number of ReadReq accesses(hits+misses) |
| 471system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 472system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) | 472system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 473system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) |
| 473system.cpu.dcache.LoadLockedReq_accesses::cpu.data 30321 # number of LoadLockedReq accesses(hits+misses) 474system.cpu.dcache.LoadLockedReq_accesses::total 30321 # number of LoadLockedReq accesses(hits+misses) 475system.cpu.dcache.StoreCondReq_accesses::cpu.data 28457 # number of StoreCondReq accesses(hits+misses) 476system.cpu.dcache.StoreCondReq_accesses::total 28457 # number of StoreCondReq accesses(hits+misses) 477system.cpu.dcache.demand_accesses::cpu.data 47285356 # number of demand (read+write) accesses 478system.cpu.dcache.demand_accesses::total 47285356 # number of demand (read+write) accesses 479system.cpu.dcache.overall_accesses::cpu.data 47285356 # number of overall (read+write) accesses 480system.cpu.dcache.overall_accesses::total 47285356 # number of overall (read+write) accesses | 474system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29808 # number of LoadLockedReq accesses(hits+misses) 475system.cpu.dcache.LoadLockedReq_accesses::total 29808 # number of LoadLockedReq accesses(hits+misses) 476system.cpu.dcache.StoreCondReq_accesses::cpu.data 28442 # number of StoreCondReq accesses(hits+misses) 477system.cpu.dcache.StoreCondReq_accesses::total 28442 # number of StoreCondReq accesses(hits+misses) 478system.cpu.dcache.demand_accesses::cpu.data 47267977 # number of demand (read+write) accesses 479system.cpu.dcache.demand_accesses::total 47267977 # number of demand (read+write) accesses 480system.cpu.dcache.overall_accesses::cpu.data 47267977 # number of overall (read+write) accesses 481system.cpu.dcache.overall_accesses::total 47267977 # number of overall (read+write) accesses |
| 481system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses 482system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses | 482system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses 483system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses |
| 483system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000615 # miss rate for WriteReq accesses 484system.cpu.dcache.WriteReq_miss_rate::total 0.000615 # miss rate for WriteReq accesses 485system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000066 # miss rate for LoadLockedReq accesses 486system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000066 # miss rate for LoadLockedReq accesses | 484system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000613 # miss rate for WriteReq accesses 485system.cpu.dcache.WriteReq_miss_rate::total 0.000613 # miss rate for WriteReq accesses 486system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses 487system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses |
| 487system.cpu.dcache.demand_miss_rate::cpu.data 0.000200 # miss rate for demand accesses 488system.cpu.dcache.demand_miss_rate::total 0.000200 # miss rate for demand accesses 489system.cpu.dcache.overall_miss_rate::cpu.data 0.000200 # miss rate for overall accesses 490system.cpu.dcache.overall_miss_rate::total 0.000200 # miss rate for overall accesses | 488system.cpu.dcache.demand_miss_rate::cpu.data 0.000200 # miss rate for demand accesses 489system.cpu.dcache.demand_miss_rate::total 0.000200 # miss rate for demand accesses 490system.cpu.dcache.overall_miss_rate::cpu.data 0.000200 # miss rate for overall accesses 491system.cpu.dcache.overall_miss_rate::total 0.000200 # miss rate for overall accesses |
| 491system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32575.806452 # average ReadReq miss latency 492system.cpu.dcache.ReadReq_avg_miss_latency::total 32575.806452 # average ReadReq miss latency 493system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31186.530880 # average WriteReq miss latency 494system.cpu.dcache.WriteReq_avg_miss_latency::total 31186.530880 # average WriteReq miss latency | 492system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32324.608743 # average ReadReq miss latency 493system.cpu.dcache.ReadReq_avg_miss_latency::total 32324.608743 # average ReadReq miss latency 494system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31300.593276 # average WriteReq miss latency 495system.cpu.dcache.WriteReq_avg_miss_latency::total 31300.593276 # average WriteReq miss latency |
| 495system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32000 # average LoadLockedReq miss latency 496system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 32000 # average LoadLockedReq miss latency | 496system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32000 # average LoadLockedReq miss latency 497system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 32000 # average LoadLockedReq miss latency |
| 497system.cpu.dcache.demand_avg_miss_latency::cpu.data 31459.398099 # average overall miss latency 498system.cpu.dcache.demand_avg_miss_latency::total 31459.398099 # average overall miss latency 499system.cpu.dcache.overall_avg_miss_latency::cpu.data 31459.398099 # average overall miss latency 500system.cpu.dcache.overall_avg_miss_latency::total 31459.398099 # average overall miss latency | 498system.cpu.dcache.demand_avg_miss_latency::cpu.data 31501.642297 # average overall miss latency 499system.cpu.dcache.demand_avg_miss_latency::total 31501.642297 # average overall miss latency 500system.cpu.dcache.overall_avg_miss_latency::cpu.data 31501.642297 # average overall miss latency 501system.cpu.dcache.overall_avg_miss_latency::total 31501.642297 # average overall miss latency |
| 501system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 502system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 502system.cpu.dcache.blocked_cycles::no_targets 19500 # number of cycles access was blocked | 503system.cpu.dcache.blocked_cycles::no_targets 10000 # number of cycles access was blocked |
| 503system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 504system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked 505system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 504system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 505system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked 506system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 506system.cpu.dcache.avg_blocked_cycles::no_targets 9750 # average number of cycles each access was blocked | 507system.cpu.dcache.avg_blocked_cycles::no_targets 5000 # average number of cycles each access was blocked |
| 507system.cpu.dcache.fast_writes 0 # number of fast writes performed 508system.cpu.dcache.cache_copies 0 # number of cache copies performed 509system.cpu.dcache.writebacks::writebacks 18 # number of writebacks 510system.cpu.dcache.writebacks::total 18 # number of writebacks | 508system.cpu.dcache.fast_writes 0 # number of fast writes performed 509system.cpu.dcache.cache_copies 0 # number of cache copies performed 510system.cpu.dcache.writebacks::writebacks 18 # number of writebacks 511system.cpu.dcache.writebacks::total 18 # number of writebacks |
| 511system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1056 # number of ReadReq MSHR hits 512system.cpu.dcache.ReadReq_mshr_hits::total 1056 # number of ReadReq MSHR hits 513system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6533 # number of WriteReq MSHR hits 514system.cpu.dcache.WriteReq_mshr_hits::total 6533 # number of WriteReq MSHR hits | 512system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1071 # number of ReadReq MSHR hits 513system.cpu.dcache.ReadReq_mshr_hits::total 1071 # number of ReadReq MSHR hits 514system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6498 # number of WriteReq MSHR hits 515system.cpu.dcache.WriteReq_mshr_hits::total 6498 # number of WriteReq MSHR hits |
| 515system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 516system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits | 516system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 517system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits |
| 517system.cpu.dcache.demand_mshr_hits::cpu.data 7589 # number of demand (read+write) MSHR hits 518system.cpu.dcache.demand_mshr_hits::total 7589 # number of demand (read+write) MSHR hits 519system.cpu.dcache.overall_mshr_hits::cpu.data 7589 # number of overall MSHR hits 520system.cpu.dcache.overall_mshr_hits::total 7589 # number of overall MSHR hits 521system.cpu.dcache.ReadReq_mshr_misses::cpu.data 804 # number of ReadReq MSHR misses 522system.cpu.dcache.ReadReq_mshr_misses::total 804 # number of ReadReq MSHR misses 523system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses 524system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses 525system.cpu.dcache.demand_mshr_misses::cpu.data 1881 # number of demand (read+write) MSHR misses 526system.cpu.dcache.demand_mshr_misses::total 1881 # number of demand (read+write) MSHR misses 527system.cpu.dcache.overall_mshr_misses::cpu.data 1881 # number of overall MSHR misses 528system.cpu.dcache.overall_mshr_misses::total 1881 # number of overall MSHR misses 529system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25610500 # number of ReadReq MSHR miss cycles 530system.cpu.dcache.ReadReq_mshr_miss_latency::total 25610500 # number of ReadReq MSHR miss cycles 531system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 37862500 # number of WriteReq MSHR miss cycles 532system.cpu.dcache.WriteReq_mshr_miss_latency::total 37862500 # number of WriteReq MSHR miss cycles 533system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63473000 # number of demand (read+write) MSHR miss cycles 534system.cpu.dcache.demand_mshr_miss_latency::total 63473000 # number of demand (read+write) MSHR miss cycles 535system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63473000 # number of overall MSHR miss cycles 536system.cpu.dcache.overall_mshr_miss_latency::total 63473000 # number of overall MSHR miss cycles 537system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses 538system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses 539system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses 540system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses | 518system.cpu.dcache.demand_mshr_hits::cpu.data 7569 # number of demand (read+write) MSHR hits 519system.cpu.dcache.demand_mshr_hits::total 7569 # number of demand (read+write) MSHR hits 520system.cpu.dcache.overall_mshr_hits::cpu.data 7569 # number of overall MSHR hits 521system.cpu.dcache.overall_mshr_hits::total 7569 # number of overall MSHR hits 522system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782 # number of ReadReq MSHR misses 523system.cpu.dcache.ReadReq_mshr_misses::total 782 # number of ReadReq MSHR misses 524system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1087 # number of WriteReq MSHR misses 525system.cpu.dcache.WriteReq_mshr_misses::total 1087 # number of WriteReq MSHR misses 526system.cpu.dcache.demand_mshr_misses::cpu.data 1869 # number of demand (read+write) MSHR misses 527system.cpu.dcache.demand_mshr_misses::total 1869 # number of demand (read+write) MSHR misses 528system.cpu.dcache.overall_mshr_misses::cpu.data 1869 # number of overall MSHR misses 529system.cpu.dcache.overall_mshr_misses::total 1869 # number of overall MSHR misses 530system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24727500 # number of ReadReq MSHR miss cycles 531system.cpu.dcache.ReadReq_mshr_miss_latency::total 24727500 # number of ReadReq MSHR miss cycles 532system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 38087000 # number of WriteReq MSHR miss cycles 533system.cpu.dcache.WriteReq_mshr_miss_latency::total 38087000 # number of WriteReq MSHR miss cycles 534system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62814500 # number of demand (read+write) MSHR miss cycles 535system.cpu.dcache.demand_mshr_miss_latency::total 62814500 # number of demand (read+write) MSHR miss cycles 536system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62814500 # number of overall MSHR miss cycles 537system.cpu.dcache.overall_mshr_miss_latency::total 62814500 # number of overall MSHR miss cycles 538system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses 539system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses 540system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses 541system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses |
| 541system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses 542system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 543system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses 544system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses | 542system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses 543system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 544system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses 545system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses |
| 545system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31853.855721 # average ReadReq mshr miss latency 546system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31853.855721 # average ReadReq mshr miss latency 547system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35155.524605 # average WriteReq mshr miss latency 548system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35155.524605 # average WriteReq mshr miss latency 549system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33744.284955 # average overall mshr miss latency 550system.cpu.dcache.demand_avg_mshr_miss_latency::total 33744.284955 # average overall mshr miss latency 551system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33744.284955 # average overall mshr miss latency 552system.cpu.dcache.overall_avg_mshr_miss_latency::total 33744.284955 # average overall mshr miss latency | 546system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31620.843990 # average ReadReq mshr miss latency 547system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31620.843990 # average ReadReq mshr miss latency 548system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35038.638454 # average WriteReq mshr miss latency 549system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35038.638454 # average WriteReq mshr miss latency 550system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33608.614232 # average overall mshr miss latency 551system.cpu.dcache.demand_avg_mshr_miss_latency::total 33608.614232 # average overall mshr miss latency 552system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33608.614232 # average overall mshr miss latency 553system.cpu.dcache.overall_avg_mshr_miss_latency::total 33608.614232 # average overall mshr miss latency |
| 553system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 554system.cpu.l2cache.replacements 0 # number of replacements | 554system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 555system.cpu.l2cache.replacements 0 # number of replacements |
| 555system.cpu.l2cache.tagsinuse 2017.739485 # Cycle average of tags in use 556system.cpu.l2cache.total_refs 2396 # Total number of references to valid blocks. 557system.cpu.l2cache.sampled_refs 2793 # Sample count of references to valid blocks. 558system.cpu.l2cache.avg_refs 0.857859 # Average number of references to valid blocks. | 556system.cpu.l2cache.tagsinuse 1980.325503 # Cycle average of tags in use 557system.cpu.l2cache.total_refs 2358 # Total number of references to valid blocks. 558system.cpu.l2cache.sampled_refs 2751 # Sample count of references to valid blocks. 559system.cpu.l2cache.avg_refs 0.857143 # Average number of references to valid blocks. |
| 559system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 560system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 560system.cpu.l2cache.occ_blocks::writebacks 4.002094 # Average occupied blocks per requestor 561system.cpu.l2cache.occ_blocks::cpu.inst 1457.512395 # Average occupied blocks per requestor 562system.cpu.l2cache.occ_blocks::cpu.data 556.224996 # Average occupied blocks per requestor 563system.cpu.l2cache.occ_percent::writebacks 0.000122 # Average percentage of cache occupancy 564system.cpu.l2cache.occ_percent::cpu.inst 0.044480 # Average percentage of cache occupancy 565system.cpu.l2cache.occ_percent::cpu.data 0.016975 # Average percentage of cache occupancy 566system.cpu.l2cache.occ_percent::total 0.061577 # Average percentage of cache occupancy 567system.cpu.l2cache.ReadReq_hits::cpu.inst 2308 # number of ReadReq hits 568system.cpu.l2cache.ReadReq_hits::cpu.data 88 # number of ReadReq hits 569system.cpu.l2cache.ReadReq_hits::total 2396 # number of ReadReq hits | 561system.cpu.l2cache.occ_blocks::writebacks 3.028951 # Average occupied blocks per requestor 562system.cpu.l2cache.occ_blocks::cpu.inst 1438.887241 # Average occupied blocks per requestor 563system.cpu.l2cache.occ_blocks::cpu.data 538.409312 # Average occupied blocks per requestor 564system.cpu.l2cache.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy 565system.cpu.l2cache.occ_percent::cpu.inst 0.043911 # Average percentage of cache occupancy 566system.cpu.l2cache.occ_percent::cpu.data 0.016431 # Average percentage of cache occupancy 567system.cpu.l2cache.occ_percent::total 0.060435 # Average percentage of cache occupancy 568system.cpu.l2cache.ReadReq_hits::cpu.inst 2267 # number of ReadReq hits 569system.cpu.l2cache.ReadReq_hits::cpu.data 92 # number of ReadReq hits 570system.cpu.l2cache.ReadReq_hits::total 2359 # number of ReadReq hits |
| 570system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits 571system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits | 571system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits 572system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits |
| 573system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 574system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits |
|
| 572system.cpu.l2cache.ReadExReq_hits::cpu.data 9 # number of ReadExReq hits 573system.cpu.l2cache.ReadExReq_hits::total 9 # number of ReadExReq hits | 575system.cpu.l2cache.ReadExReq_hits::cpu.data 9 # number of ReadExReq hits 576system.cpu.l2cache.ReadExReq_hits::total 9 # number of ReadExReq hits |
| 574system.cpu.l2cache.demand_hits::cpu.inst 2308 # number of demand (read+write) hits 575system.cpu.l2cache.demand_hits::cpu.data 97 # number of demand (read+write) hits 576system.cpu.l2cache.demand_hits::total 2405 # number of demand (read+write) hits 577system.cpu.l2cache.overall_hits::cpu.inst 2308 # number of overall hits 578system.cpu.l2cache.overall_hits::cpu.data 97 # number of overall hits 579system.cpu.l2cache.overall_hits::total 2405 # number of overall hits 580system.cpu.l2cache.ReadReq_misses::cpu.inst 2087 # number of ReadReq misses 581system.cpu.l2cache.ReadReq_misses::cpu.data 716 # number of ReadReq misses 582system.cpu.l2cache.ReadReq_misses::total 2803 # number of ReadReq misses 583system.cpu.l2cache.ReadExReq_misses::cpu.data 1068 # number of ReadExReq misses 584system.cpu.l2cache.ReadExReq_misses::total 1068 # number of ReadExReq misses 585system.cpu.l2cache.demand_misses::cpu.inst 2087 # number of demand (read+write) misses 586system.cpu.l2cache.demand_misses::cpu.data 1784 # number of demand (read+write) misses 587system.cpu.l2cache.demand_misses::total 3871 # number of demand (read+write) misses 588system.cpu.l2cache.overall_misses::cpu.inst 2087 # number of overall misses 589system.cpu.l2cache.overall_misses::cpu.data 1784 # number of overall misses 590system.cpu.l2cache.overall_misses::total 3871 # number of overall misses 591system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71492500 # number of ReadReq miss cycles 592system.cpu.l2cache.ReadReq_miss_latency::cpu.data 24574000 # number of ReadReq miss cycles 593system.cpu.l2cache.ReadReq_miss_latency::total 96066500 # number of ReadReq miss cycles 594system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 36706000 # number of ReadExReq miss cycles 595system.cpu.l2cache.ReadExReq_miss_latency::total 36706000 # number of ReadExReq miss cycles 596system.cpu.l2cache.demand_miss_latency::cpu.inst 71492500 # number of demand (read+write) miss cycles 597system.cpu.l2cache.demand_miss_latency::cpu.data 61280000 # number of demand (read+write) miss cycles 598system.cpu.l2cache.demand_miss_latency::total 132772500 # number of demand (read+write) miss cycles 599system.cpu.l2cache.overall_miss_latency::cpu.inst 71492500 # number of overall miss cycles 600system.cpu.l2cache.overall_miss_latency::cpu.data 61280000 # number of overall miss cycles 601system.cpu.l2cache.overall_miss_latency::total 132772500 # number of overall miss cycles 602system.cpu.l2cache.ReadReq_accesses::cpu.inst 4395 # number of ReadReq accesses(hits+misses) 603system.cpu.l2cache.ReadReq_accesses::cpu.data 804 # number of ReadReq accesses(hits+misses) 604system.cpu.l2cache.ReadReq_accesses::total 5199 # number of ReadReq accesses(hits+misses) | 577system.cpu.l2cache.demand_hits::cpu.inst 2267 # number of demand (read+write) hits 578system.cpu.l2cache.demand_hits::cpu.data 101 # number of demand (read+write) hits 579system.cpu.l2cache.demand_hits::total 2368 # number of demand (read+write) hits 580system.cpu.l2cache.overall_hits::cpu.inst 2267 # number of overall hits 581system.cpu.l2cache.overall_hits::cpu.data 101 # number of overall hits 582system.cpu.l2cache.overall_hits::total 2368 # number of overall hits 583system.cpu.l2cache.ReadReq_misses::cpu.inst 2073 # number of ReadReq misses 584system.cpu.l2cache.ReadReq_misses::cpu.data 689 # number of ReadReq misses 585system.cpu.l2cache.ReadReq_misses::total 2762 # number of ReadReq misses 586system.cpu.l2cache.ReadExReq_misses::cpu.data 1075 # number of ReadExReq misses 587system.cpu.l2cache.ReadExReq_misses::total 1075 # number of ReadExReq misses 588system.cpu.l2cache.demand_misses::cpu.inst 2073 # number of demand (read+write) misses 589system.cpu.l2cache.demand_misses::cpu.data 1764 # number of demand (read+write) misses 590system.cpu.l2cache.demand_misses::total 3837 # number of demand (read+write) misses 591system.cpu.l2cache.overall_misses::cpu.inst 2073 # number of overall misses 592system.cpu.l2cache.overall_misses::cpu.data 1764 # number of overall misses 593system.cpu.l2cache.overall_misses::total 3837 # number of overall misses 594system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71046500 # number of ReadReq miss cycles 595system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23679500 # number of ReadReq miss cycles 596system.cpu.l2cache.ReadReq_miss_latency::total 94726000 # number of ReadReq miss cycles 597system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 36948500 # number of ReadExReq miss cycles 598system.cpu.l2cache.ReadExReq_miss_latency::total 36948500 # number of ReadExReq miss cycles 599system.cpu.l2cache.demand_miss_latency::cpu.inst 71046500 # number of demand (read+write) miss cycles 600system.cpu.l2cache.demand_miss_latency::cpu.data 60628000 # number of demand (read+write) miss cycles 601system.cpu.l2cache.demand_miss_latency::total 131674500 # number of demand (read+write) miss cycles 602system.cpu.l2cache.overall_miss_latency::cpu.inst 71046500 # number of overall miss cycles 603system.cpu.l2cache.overall_miss_latency::cpu.data 60628000 # number of overall miss cycles 604system.cpu.l2cache.overall_miss_latency::total 131674500 # number of overall miss cycles 605system.cpu.l2cache.ReadReq_accesses::cpu.inst 4340 # number of ReadReq accesses(hits+misses) 606system.cpu.l2cache.ReadReq_accesses::cpu.data 781 # number of ReadReq accesses(hits+misses) 607system.cpu.l2cache.ReadReq_accesses::total 5121 # number of ReadReq accesses(hits+misses) |
| 605system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) 606system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) | 608system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) 609system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) |
| 607system.cpu.l2cache.ReadExReq_accesses::cpu.data 1077 # number of ReadExReq accesses(hits+misses) 608system.cpu.l2cache.ReadExReq_accesses::total 1077 # number of ReadExReq accesses(hits+misses) 609system.cpu.l2cache.demand_accesses::cpu.inst 4395 # number of demand (read+write) accesses 610system.cpu.l2cache.demand_accesses::cpu.data 1881 # number of demand (read+write) accesses 611system.cpu.l2cache.demand_accesses::total 6276 # number of demand (read+write) accesses 612system.cpu.l2cache.overall_accesses::cpu.inst 4395 # number of overall (read+write) accesses 613system.cpu.l2cache.overall_accesses::cpu.data 1881 # number of overall (read+write) accesses 614system.cpu.l2cache.overall_accesses::total 6276 # number of overall (read+write) accesses 615system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.474858 # miss rate for ReadReq accesses 616system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.890547 # miss rate for ReadReq accesses 617system.cpu.l2cache.ReadReq_miss_rate::total 0.539142 # miss rate for ReadReq accesses 618system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991643 # miss rate for ReadExReq accesses 619system.cpu.l2cache.ReadExReq_miss_rate::total 0.991643 # miss rate for ReadExReq accesses 620system.cpu.l2cache.demand_miss_rate::cpu.inst 0.474858 # miss rate for demand accesses 621system.cpu.l2cache.demand_miss_rate::cpu.data 0.948432 # miss rate for demand accesses 622system.cpu.l2cache.demand_miss_rate::total 0.616794 # miss rate for demand accesses 623system.cpu.l2cache.overall_miss_rate::cpu.inst 0.474858 # miss rate for overall accesses 624system.cpu.l2cache.overall_miss_rate::cpu.data 0.948432 # miss rate for overall accesses 625system.cpu.l2cache.overall_miss_rate::total 0.616794 # miss rate for overall accesses 626system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34256.109248 # average ReadReq miss latency 627system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34321.229050 # average ReadReq miss latency 628system.cpu.l2cache.ReadReq_avg_miss_latency::total 34272.743489 # average ReadReq miss latency 629system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34368.913858 # average ReadExReq miss latency 630system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34368.913858 # average ReadExReq miss latency 631system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34256.109248 # average overall miss latency 632system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34349.775785 # average overall miss latency 633system.cpu.l2cache.demand_avg_miss_latency::total 34299.276673 # average overall miss latency 634system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34256.109248 # average overall miss latency 635system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34349.775785 # average overall miss latency 636system.cpu.l2cache.overall_avg_miss_latency::total 34299.276673 # average overall miss latency | 610system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4 # number of UpgradeReq accesses(hits+misses) 611system.cpu.l2cache.UpgradeReq_accesses::total 4 # number of UpgradeReq accesses(hits+misses) 612system.cpu.l2cache.ReadExReq_accesses::cpu.data 1084 # number of ReadExReq accesses(hits+misses) 613system.cpu.l2cache.ReadExReq_accesses::total 1084 # number of ReadExReq accesses(hits+misses) 614system.cpu.l2cache.demand_accesses::cpu.inst 4340 # number of demand (read+write) accesses 615system.cpu.l2cache.demand_accesses::cpu.data 1865 # number of demand (read+write) accesses 616system.cpu.l2cache.demand_accesses::total 6205 # number of demand (read+write) accesses 617system.cpu.l2cache.overall_accesses::cpu.inst 4340 # number of overall (read+write) accesses 618system.cpu.l2cache.overall_accesses::cpu.data 1865 # number of overall (read+write) accesses 619system.cpu.l2cache.overall_accesses::total 6205 # number of overall (read+write) accesses 620system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.477650 # miss rate for ReadReq accesses 621system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.882202 # miss rate for ReadReq accesses 622system.cpu.l2cache.ReadReq_miss_rate::total 0.539348 # miss rate for ReadReq accesses 623system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991697 # miss rate for ReadExReq accesses 624system.cpu.l2cache.ReadExReq_miss_rate::total 0.991697 # miss rate for ReadExReq accesses 625system.cpu.l2cache.demand_miss_rate::cpu.inst 0.477650 # miss rate for demand accesses 626system.cpu.l2cache.demand_miss_rate::cpu.data 0.945845 # miss rate for demand accesses 627system.cpu.l2cache.demand_miss_rate::total 0.618372 # miss rate for demand accesses 628system.cpu.l2cache.overall_miss_rate::cpu.inst 0.477650 # miss rate for overall accesses 629system.cpu.l2cache.overall_miss_rate::cpu.data 0.945845 # miss rate for overall accesses 630system.cpu.l2cache.overall_miss_rate::total 0.618372 # miss rate for overall accesses 631system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34272.310661 # average ReadReq miss latency 632system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34367.924528 # average ReadReq miss latency 633system.cpu.l2cache.ReadReq_avg_miss_latency::total 34296.162201 # average ReadReq miss latency 634system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34370.697674 # average ReadExReq miss latency 635system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34370.697674 # average ReadExReq miss latency 636system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34272.310661 # average overall miss latency 637system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34369.614512 # average overall miss latency 638system.cpu.l2cache.demand_avg_miss_latency::total 34317.044566 # average overall miss latency 639system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34272.310661 # average overall miss latency 640system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34369.614512 # average overall miss latency 641system.cpu.l2cache.overall_avg_miss_latency::total 34317.044566 # average overall miss latency |
| 637system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 638system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 639system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 640system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 641system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 642system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 643system.cpu.l2cache.fast_writes 0 # number of fast writes performed 644system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 642system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 643system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 644system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 645system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 646system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 647system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 648system.cpu.l2cache.fast_writes 0 # number of fast writes performed 649system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 645system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits 646system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 15 # number of ReadReq MSHR hits 647system.cpu.l2cache.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits 648system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits 649system.cpu.l2cache.demand_mshr_hits::cpu.data 15 # number of demand (read+write) MSHR hits 650system.cpu.l2cache.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits 651system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits 652system.cpu.l2cache.overall_mshr_hits::cpu.data 15 # number of overall MSHR hits 653system.cpu.l2cache.overall_mshr_hits::total 18 # number of overall MSHR hits 654system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2084 # number of ReadReq MSHR misses 655system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 701 # number of ReadReq MSHR misses 656system.cpu.l2cache.ReadReq_mshr_misses::total 2785 # number of ReadReq MSHR misses 657system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1068 # number of ReadExReq MSHR misses 658system.cpu.l2cache.ReadExReq_mshr_misses::total 1068 # number of ReadExReq MSHR misses 659system.cpu.l2cache.demand_mshr_misses::cpu.inst 2084 # number of demand (read+write) MSHR misses 660system.cpu.l2cache.demand_mshr_misses::cpu.data 1769 # number of demand (read+write) MSHR misses 661system.cpu.l2cache.demand_mshr_misses::total 3853 # number of demand (read+write) MSHR misses 662system.cpu.l2cache.overall_mshr_misses::cpu.inst 2084 # number of overall MSHR misses 663system.cpu.l2cache.overall_mshr_misses::cpu.data 1769 # number of overall MSHR misses 664system.cpu.l2cache.overall_mshr_misses::total 3853 # number of overall MSHR misses 665system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 64692000 # number of ReadReq MSHR miss cycles 666system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 21857000 # number of ReadReq MSHR miss cycles 667system.cpu.l2cache.ReadReq_mshr_miss_latency::total 86549000 # number of ReadReq MSHR miss cycles 668system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33156000 # number of ReadExReq MSHR miss cycles 669system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33156000 # number of ReadExReq MSHR miss cycles 670system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64692000 # number of demand (read+write) MSHR miss cycles 671system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 55013000 # number of demand (read+write) MSHR miss cycles 672system.cpu.l2cache.demand_mshr_miss_latency::total 119705000 # number of demand (read+write) MSHR miss cycles 673system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64692000 # number of overall MSHR miss cycles 674system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 55013000 # number of overall MSHR miss cycles 675system.cpu.l2cache.overall_mshr_miss_latency::total 119705000 # number of overall MSHR miss cycles 676system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for ReadReq accesses 677system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871891 # mshr miss rate for ReadReq accesses 678system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.535680 # mshr miss rate for ReadReq accesses 679system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991643 # mshr miss rate for ReadExReq accesses 680system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991643 # mshr miss rate for ReadExReq accesses 681system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for demand accesses 682system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.940457 # mshr miss rate for demand accesses 683system.cpu.l2cache.demand_mshr_miss_rate::total 0.613926 # mshr miss rate for demand accesses 684system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for overall accesses 685system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940457 # mshr miss rate for overall accesses 686system.cpu.l2cache.overall_mshr_miss_rate::total 0.613926 # mshr miss rate for overall accesses 687system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31042.226488 # average ReadReq mshr miss latency 688system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31179.743224 # average ReadReq mshr miss latency 689system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31076.840215 # average ReadReq mshr miss latency 690system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31044.943820 # average ReadExReq mshr miss latency 691system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31044.943820 # average ReadExReq mshr miss latency 692system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31042.226488 # average overall mshr miss latency 693system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31098.360656 # average overall mshr miss latency 694system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31067.998962 # average overall mshr miss latency 695system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31042.226488 # average overall mshr miss latency 696system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31098.360656 # average overall mshr miss latency 697system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31067.998962 # average overall mshr miss latency | 650system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits 651system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits 652system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits 653system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits 654system.cpu.l2cache.demand_mshr_hits::cpu.data 12 # number of demand (read+write) MSHR hits 655system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits 656system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits 657system.cpu.l2cache.overall_mshr_hits::cpu.data 12 # number of overall MSHR hits 658system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits 659system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2069 # number of ReadReq MSHR misses 660system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 677 # number of ReadReq MSHR misses 661system.cpu.l2cache.ReadReq_mshr_misses::total 2746 # number of ReadReq MSHR misses 662system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1075 # number of ReadExReq MSHR misses 663system.cpu.l2cache.ReadExReq_mshr_misses::total 1075 # number of ReadExReq MSHR misses 664system.cpu.l2cache.demand_mshr_misses::cpu.inst 2069 # number of demand (read+write) MSHR misses 665system.cpu.l2cache.demand_mshr_misses::cpu.data 1752 # number of demand (read+write) MSHR misses 666system.cpu.l2cache.demand_mshr_misses::total 3821 # number of demand (read+write) MSHR misses 667system.cpu.l2cache.overall_mshr_misses::cpu.inst 2069 # number of overall MSHR misses 668system.cpu.l2cache.overall_mshr_misses::cpu.data 1752 # number of overall MSHR misses 669system.cpu.l2cache.overall_mshr_misses::total 3821 # number of overall MSHR misses 670system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 64256500 # number of ReadReq MSHR miss cycles 671system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 21124000 # number of ReadReq MSHR miss cycles 672system.cpu.l2cache.ReadReq_mshr_miss_latency::total 85380500 # number of ReadReq MSHR miss cycles 673system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33377000 # number of ReadExReq MSHR miss cycles 674system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33377000 # number of ReadExReq MSHR miss cycles 675system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64256500 # number of demand (read+write) MSHR miss cycles 676system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 54501000 # number of demand (read+write) MSHR miss cycles 677system.cpu.l2cache.demand_mshr_miss_latency::total 118757500 # number of demand (read+write) MSHR miss cycles 678system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64256500 # number of overall MSHR miss cycles 679system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54501000 # number of overall MSHR miss cycles 680system.cpu.l2cache.overall_mshr_miss_latency::total 118757500 # number of overall MSHR miss cycles 681system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.476728 # mshr miss rate for ReadReq accesses 682system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.866837 # mshr miss rate for ReadReq accesses 683system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.536223 # mshr miss rate for ReadReq accesses 684system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991697 # mshr miss rate for ReadExReq accesses 685system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991697 # mshr miss rate for ReadExReq accesses 686system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.476728 # mshr miss rate for demand accesses 687system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.939410 # mshr miss rate for demand accesses 688system.cpu.l2cache.demand_mshr_miss_rate::total 0.615794 # mshr miss rate for demand accesses 689system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.476728 # mshr miss rate for overall accesses 690system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.939410 # mshr miss rate for overall accesses 691system.cpu.l2cache.overall_mshr_miss_rate::total 0.615794 # mshr miss rate for overall accesses 692system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31056.790720 # average ReadReq mshr miss latency 693system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31202.363368 # average ReadReq mshr miss latency 694system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31092.680262 # average ReadReq mshr miss latency 695system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31048.372093 # average ReadExReq mshr miss latency 696system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31048.372093 # average ReadExReq mshr miss latency 697system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31056.790720 # average overall mshr miss latency 698system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31107.876712 # average overall mshr miss latency 699system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31080.214604 # average overall mshr miss latency 700system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31056.790720 # average overall mshr miss latency 701system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31107.876712 # average overall mshr miss latency 702system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31080.214604 # average overall mshr miss latency |
| 698system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 699 700---------- End Simulation Statistics ---------- | 703system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 704 705---------- End Simulation Statistics ---------- |