| stats.txt (8911:4da2ea94319f) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.076323 # Number of seconds simulated 4sim_ticks 76322764500 # Number of ticks simulated 5final_tick 76322764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.076323 # Number of seconds simulated 4sim_ticks 76322764500 # Number of ticks simulated 5final_tick 76322764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 160991 # Simulator instruction rate (inst/s) 8host_op_rate 176268 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 71299389 # Simulator tick rate (ticks/s) 10host_mem_usage 228164 # Number of bytes of host memory used 11host_seconds 1070.45 # Real time elapsed on the host | 7host_inst_rate 57710 # Simulator instruction rate (inst/s) 8host_op_rate 63186 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 25558377 # Simulator tick rate (ticks/s) 10host_mem_usage 235176 # Number of bytes of host memory used 11host_seconds 2986.21 # Real time elapsed on the host |
| 12sim_insts 172333279 # Number of instructions simulated 13sim_ops 188686762 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 246592 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 133376 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 3853 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 352 unchanged lines hidden (view full) --- 372system.cpu.icache.overall_miss_rate::cpu.inst 0.000137 # miss rate for overall accesses 373system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21688.113099 # average ReadReq miss latency 374system.cpu.icache.demand_avg_miss_latency::cpu.inst 21688.113099 # average overall miss latency 375system.cpu.icache.overall_avg_miss_latency::cpu.inst 21688.113099 # average overall miss latency 376system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 377system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 378system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 379system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 172333279 # Number of instructions simulated 13sim_ops 188686762 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 246592 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 133376 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 3853 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 352 unchanged lines hidden (view full) --- 372system.cpu.icache.overall_miss_rate::cpu.inst 0.000137 # miss rate for overall accesses 373system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21688.113099 # average ReadReq miss latency 374system.cpu.icache.demand_avg_miss_latency::cpu.inst 21688.113099 # average overall miss latency 375system.cpu.icache.overall_avg_miss_latency::cpu.inst 21688.113099 # average overall miss latency 376system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 377system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 378system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 379system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 380system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 381system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 380system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 381system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 382system.cpu.icache.fast_writes 0 # number of fast writes performed 383system.cpu.icache.cache_copies 0 # number of cache copies performed 384system.cpu.icache.ReadReq_mshr_hits::cpu.inst 804 # number of ReadReq MSHR hits 385system.cpu.icache.ReadReq_mshr_hits::total 804 # number of ReadReq MSHR hits 386system.cpu.icache.demand_mshr_hits::cpu.inst 804 # number of demand (read+write) MSHR hits 387system.cpu.icache.demand_mshr_hits::total 804 # number of demand (read+write) MSHR hits 388system.cpu.icache.overall_mshr_hits::cpu.inst 804 # number of overall MSHR hits 389system.cpu.icache.overall_mshr_hits::total 804 # number of overall MSHR hits --- 78 unchanged lines hidden (view full) --- 468system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31186.530880 # average WriteReq miss latency 469system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32000 # average LoadLockedReq miss latency 470system.cpu.dcache.demand_avg_miss_latency::cpu.data 31459.398099 # average overall miss latency 471system.cpu.dcache.overall_avg_miss_latency::cpu.data 31459.398099 # average overall miss latency 472system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 473system.cpu.dcache.blocked_cycles::no_targets 19500 # number of cycles access was blocked 474system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 475system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked | 382system.cpu.icache.fast_writes 0 # number of fast writes performed 383system.cpu.icache.cache_copies 0 # number of cache copies performed 384system.cpu.icache.ReadReq_mshr_hits::cpu.inst 804 # number of ReadReq MSHR hits 385system.cpu.icache.ReadReq_mshr_hits::total 804 # number of ReadReq MSHR hits 386system.cpu.icache.demand_mshr_hits::cpu.inst 804 # number of demand (read+write) MSHR hits 387system.cpu.icache.demand_mshr_hits::total 804 # number of demand (read+write) MSHR hits 388system.cpu.icache.overall_mshr_hits::cpu.inst 804 # number of overall MSHR hits 389system.cpu.icache.overall_mshr_hits::total 804 # number of overall MSHR hits --- 78 unchanged lines hidden (view full) --- 468system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31186.530880 # average WriteReq miss latency 469system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32000 # average LoadLockedReq miss latency 470system.cpu.dcache.demand_avg_miss_latency::cpu.data 31459.398099 # average overall miss latency 471system.cpu.dcache.overall_avg_miss_latency::cpu.data 31459.398099 # average overall miss latency 472system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 473system.cpu.dcache.blocked_cycles::no_targets 19500 # number of cycles access was blocked 474system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 475system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked |
| 476system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked | 476system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 477system.cpu.dcache.avg_blocked_cycles::no_targets 9750 # average number of cycles each access was blocked 478system.cpu.dcache.fast_writes 0 # number of fast writes performed 479system.cpu.dcache.cache_copies 0 # number of cache copies performed 480system.cpu.dcache.writebacks::writebacks 18 # number of writebacks 481system.cpu.dcache.writebacks::total 18 # number of writebacks 482system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1056 # number of ReadReq MSHR hits 483system.cpu.dcache.ReadReq_mshr_hits::total 1056 # number of ReadReq MSHR hits 484system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6533 # number of WriteReq MSHR hits --- 103 unchanged lines hidden (view full) --- 588system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34256.109248 # average overall miss latency 589system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34349.775785 # average overall miss latency 590system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34256.109248 # average overall miss latency 591system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34349.775785 # average overall miss latency 592system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 593system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 594system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 595system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 477system.cpu.dcache.avg_blocked_cycles::no_targets 9750 # average number of cycles each access was blocked 478system.cpu.dcache.fast_writes 0 # number of fast writes performed 479system.cpu.dcache.cache_copies 0 # number of cache copies performed 480system.cpu.dcache.writebacks::writebacks 18 # number of writebacks 481system.cpu.dcache.writebacks::total 18 # number of writebacks 482system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1056 # number of ReadReq MSHR hits 483system.cpu.dcache.ReadReq_mshr_hits::total 1056 # number of ReadReq MSHR hits 484system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6533 # number of WriteReq MSHR hits --- 103 unchanged lines hidden (view full) --- 588system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34256.109248 # average overall miss latency 589system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34349.775785 # average overall miss latency 590system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34256.109248 # average overall miss latency 591system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34349.775785 # average overall miss latency 592system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 593system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 594system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 595system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 596system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 597system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 596system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 597system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 598system.cpu.l2cache.fast_writes 0 # number of fast writes performed 599system.cpu.l2cache.cache_copies 0 # number of cache copies performed 600system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits 601system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 15 # number of ReadReq MSHR hits 602system.cpu.l2cache.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits 603system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits 604system.cpu.l2cache.demand_mshr_hits::cpu.data 15 # number of demand (read+write) MSHR hits 605system.cpu.l2cache.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits --- 42 unchanged lines hidden --- | 598system.cpu.l2cache.fast_writes 0 # number of fast writes performed 599system.cpu.l2cache.cache_copies 0 # number of cache copies performed 600system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits 601system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 15 # number of ReadReq MSHR hits 602system.cpu.l2cache.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits 603system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits 604system.cpu.l2cache.demand_mshr_hits::cpu.data 15 # number of demand (read+write) MSHR hits 605system.cpu.l2cache.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits --- 42 unchanged lines hidden --- |