Cross Reference: /gem5/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 0.086149 # Number of seconds simulated
4sim_ticks 86149358000 # Number of ticks simulated
5final_tick 86149358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 0.085986 # Number of seconds simulated
4sim_ticks 85986203000 # Number of ticks simulated
5final_tick 85986203000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 240669 # Simulator instruction rate (inst/s)
8host_op_rate 253706 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 120331720 # Simulator tick rate (ticks/s)
10host_mem_usage 272336 # Number of bytes of host memory used
11host_seconds 715.93 # Real time elapsed on the host

7host_inst_rate 210936 # Simulator instruction rate (inst/s)
8host_op_rate 222361 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 105265513 # Simulator tick rate (ticks/s)
10host_mem_usage 272504 # Number of bytes of host memory used
11host_seconds 816.85 # Real time elapsed on the host

12sim_insts 172303022 # Number of instructions simulated
13sim_ops 181635954 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.inst 652096 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 192896 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.l2cache.prefetcher 71744 # Number of bytes read from this memory
20system.physmem.bytes_read::total 916736 # Number of bytes read from this memory
21system.physmem.bytes_inst_read::cpu.inst 652096 # Number of instructions bytes read from this memory
22system.physmem.bytes_inst_read::total 652096 # Number of instructions bytes read from this memory
23system.physmem.num_reads::cpu.inst 10189 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.data 3014 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.l2cache.prefetcher 1121 # Number of read requests responded to by this memory
26system.physmem.num_reads::total 14324 # Number of read requests responded to by this memory
27system.physmem.bw_read::cpu.inst 7569366 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::cpu.data 2239088 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.l2cache.prefetcher 832786 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 10641240 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 7569366 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 7569366 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_total::cpu.inst 7569366 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.data 2239088 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.l2cache.prefetcher 832786 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 10641240 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.readReqs 14324 # Number of read requests accepted

16system.physmem.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.inst 651776 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 193408 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.l2cache.prefetcher 71680 # Number of bytes read from this memory
20system.physmem.bytes_read::total 916864 # Number of bytes read from this memory
21system.physmem.bytes_inst_read::cpu.inst 651776 # Number of instructions bytes read from this memory
22system.physmem.bytes_inst_read::total 651776 # Number of instructions bytes read from this memory
23system.physmem.num_reads::cpu.inst 10184 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.data 3022 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.l2cache.prefetcher 1120 # Number of read requests responded to by this memory
26system.physmem.num_reads::total 14326 # Number of read requests responded to by this memory
27system.physmem.bw_read::cpu.inst 7580007 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::cpu.data 2249291 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.l2cache.prefetcher 833622 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 10662920 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 7580007 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 7580007 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_total::cpu.inst 7580007 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.data 2249291 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.l2cache.prefetcher 833622 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 10662920 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.readReqs 14327 # Number of read requests accepted

38system.physmem.writeReqs 0 # Number of write requests accepted

39system.physmem.readBursts 14324 # Number of DRAM read bursts, including those serviced by the write queue

39system.physmem.readBursts 14327 # Number of DRAM read bursts, including those serviced by the write queue

40system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue

41system.physmem.bytesReadDRAM 916736 # Total number of bytes read from DRAM

41system.physmem.bytesReadDRAM 916928 # Total number of bytes read from DRAM

42system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
43system.physmem.bytesWritten 0 # Total number of bytes written to DRAM

44system.physmem.bytesReadSys 916736 # Total read bytes from the system interface side

44system.physmem.bytesReadSys 916928 # Total read bytes from the system interface side

45system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
46system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
47system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
48system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write

49system.physmem.perBankRdBursts::0 1375 # Per bank write bursts
50system.physmem.perBankRdBursts::1 498 # Per bank write bursts
51system.physmem.perBankRdBursts::2 5101 # Per bank write bursts
52system.physmem.perBankRdBursts::3 808 # Per bank write bursts
53system.physmem.perBankRdBursts::4 2279 # Per bank write bursts
54system.physmem.perBankRdBursts::5 424 # Per bank write bursts
55system.physmem.perBankRdBursts::6 384 # Per bank write bursts
56system.physmem.perBankRdBursts::7 628 # Per bank write bursts

49system.physmem.perBankRdBursts::0 1379 # Per bank write bursts
50system.physmem.perBankRdBursts::1 501 # Per bank write bursts
51system.physmem.perBankRdBursts::2 5100 # Per bank write bursts
52system.physmem.perBankRdBursts::3 815 # Per bank write bursts
53system.physmem.perBankRdBursts::4 2265 # Per bank write bursts
54system.physmem.perBankRdBursts::5 427 # Per bank write bursts
55system.physmem.perBankRdBursts::6 394 # Per bank write bursts
56system.physmem.perBankRdBursts::7 623 # Per bank write bursts

57system.physmem.perBankRdBursts::8 270 # Per bank write bursts

58system.physmem.perBankRdBursts::9 231 # Per bank write bursts

58system.physmem.perBankRdBursts::9 230 # Per bank write bursts

59system.physmem.perBankRdBursts::10 354 # Per bank write bursts

60system.physmem.perBankRdBursts::11 348 # Per bank write bursts
61system.physmem.perBankRdBursts::12 320 # Per bank write bursts
62system.physmem.perBankRdBursts::13 267 # Per bank write bursts
63system.physmem.perBankRdBursts::14 240 # Per bank write bursts
64system.physmem.perBankRdBursts::15 797 # Per bank write bursts

60system.physmem.perBankRdBursts::11 345 # Per bank write bursts
61system.physmem.perBankRdBursts::12 321 # Per bank write bursts
62system.physmem.perBankRdBursts::13 266 # Per bank write bursts
63system.physmem.perBankRdBursts::14 239 # Per bank write bursts
64system.physmem.perBankRdBursts::15 798 # Per bank write bursts

65system.physmem.perBankWrBursts::0 0 # Per bank write bursts
66system.physmem.perBankWrBursts::1 0 # Per bank write bursts
67system.physmem.perBankWrBursts::2 0 # Per bank write bursts
68system.physmem.perBankWrBursts::3 0 # Per bank write bursts
69system.physmem.perBankWrBursts::4 0 # Per bank write bursts
70system.physmem.perBankWrBursts::5 0 # Per bank write bursts
71system.physmem.perBankWrBursts::6 0 # Per bank write bursts
72system.physmem.perBankWrBursts::7 0 # Per bank write bursts
73system.physmem.perBankWrBursts::8 0 # Per bank write bursts
74system.physmem.perBankWrBursts::9 0 # Per bank write bursts
75system.physmem.perBankWrBursts::10 0 # Per bank write bursts
76system.physmem.perBankWrBursts::11 0 # Per bank write bursts
77system.physmem.perBankWrBursts::12 0 # Per bank write bursts
78system.physmem.perBankWrBursts::13 0 # Per bank write bursts
79system.physmem.perBankWrBursts::14 0 # Per bank write bursts
80system.physmem.perBankWrBursts::15 0 # Per bank write bursts
81system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
82system.physmem.numWrRetry 0 # Number of times write queue was full causing retry

83system.physmem.totGap 86149299500 # Total gap between requests

83system.physmem.totGap 85986194000 # Total gap between requests

84system.physmem.readPktSize::0 0 # Read request sizes (log2)
85system.physmem.readPktSize::1 0 # Read request sizes (log2)
86system.physmem.readPktSize::2 0 # Read request sizes (log2)
87system.physmem.readPktSize::3 0 # Read request sizes (log2)
88system.physmem.readPktSize::4 0 # Read request sizes (log2)
89system.physmem.readPktSize::5 0 # Read request sizes (log2)

90system.physmem.readPktSize::6 14324 # Read request sizes (log2)

90system.physmem.readPktSize::6 14327 # Read request sizes (log2)

91system.physmem.writePktSize::0 0 # Write request sizes (log2)
92system.physmem.writePktSize::1 0 # Write request sizes (log2)
93system.physmem.writePktSize::2 0 # Write request sizes (log2)
94system.physmem.writePktSize::3 0 # Write request sizes (log2)
95system.physmem.writePktSize::4 0 # Write request sizes (log2)
96system.physmem.writePktSize::5 0 # Write request sizes (log2)
97system.physmem.writePktSize::6 0 # Write request sizes (log2)

98system.physmem.rdQLenPdf::0 12783 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::1 1071 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::2 182 # What read queue length does an incoming req see

98system.physmem.rdQLenPdf::0 12781 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::1 1074 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::2 181 # What read queue length does an incoming req see

101system.physmem.rdQLenPdf::3 85 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see

103system.physmem.rdQLenPdf::5 41 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::6 36 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see

103system.physmem.rdQLenPdf::5 42 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::8 31 # What read queue length does an incoming req see

107system.physmem.rdQLenPdf::9 3 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see

--- 71 unchanged lines hidden (view full) ---

186system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see

194system.physmem.bytesPerActivate::samples 8487 # Bytes accessed per row activation
195system.physmem.bytesPerActivate::mean 107.956168 # Bytes accessed per row activation
196system.physmem.bytesPerActivate::gmean 86.535791 # Bytes accessed per row activation
197system.physmem.bytesPerActivate::stdev 122.736079 # Bytes accessed per row activation
198system.physmem.bytesPerActivate::0-127 5894 69.45% 69.45% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::128-255 2098 24.72% 94.17% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::256-383 256 3.02% 97.18% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::384-511 63 0.74% 97.93% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::512-639 36 0.42% 98.35% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::640-767 32 0.38% 98.73% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::768-895 19 0.22% 98.95% # Bytes accessed per row activation

194system.physmem.bytesPerActivate::samples 8483 # Bytes accessed per row activation
195system.physmem.bytesPerActivate::mean 107.969350 # Bytes accessed per row activation
196system.physmem.bytesPerActivate::gmean 86.508882 # Bytes accessed per row activation
197system.physmem.bytesPerActivate::stdev 122.734500 # Bytes accessed per row activation
198system.physmem.bytesPerActivate::0-127 5897 69.52% 69.52% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::128-255 2092 24.66% 94.18% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::256-383 251 2.96% 97.14% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::384-511 65 0.77% 97.90% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::512-639 38 0.45% 98.35% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::640-767 36 0.42% 98.77% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::768-895 15 0.18% 98.95% # Bytes accessed per row activation

205system.physmem.bytesPerActivate::896-1023 10 0.12% 99.07% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::1024-1151 79 0.93% 100.00% # Bytes accessed per row activation

207system.physmem.bytesPerActivate::total 8487 # Bytes accessed per row activation
208system.physmem.totQLat 1500750524 # Total ticks spent queuing
209system.physmem.totMemAccLat 1769325524 # Total ticks spent from burst creation until serviced by the DRAM
210system.physmem.totBusLat 71620000 # Total ticks spent in databus transfers
211system.physmem.avgQLat 104771.75 # Average queueing delay per DRAM burst

207system.physmem.bytesPerActivate::total 8483 # Bytes accessed per row activation
208system.physmem.totQLat 1497477800 # Total ticks spent queuing
209system.physmem.totMemAccLat 1766109050 # Total ticks spent from burst creation until serviced by the DRAM
210system.physmem.totBusLat 71635000 # Total ticks spent in databus transfers
211system.physmem.avgQLat 104521.38 # Average queueing delay per DRAM burst

212system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst

213system.physmem.avgMemAccLat 123521.75 # Average memory access latency per DRAM burst
214system.physmem.avgRdBW 10.64 # Average DRAM read bandwidth in MiByte/s

213system.physmem.avgMemAccLat 123271.38 # Average memory access latency per DRAM burst
214system.physmem.avgRdBW 10.66 # Average DRAM read bandwidth in MiByte/s

215system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s

216system.physmem.avgRdBWSys 10.64 # Average system read bandwidth in MiByte/s

216system.physmem.avgRdBWSys 10.66 # Average system read bandwidth in MiByte/s

217system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
218system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
219system.physmem.busUtil 0.08 # Data bus utilization in percentage
220system.physmem.busUtilRead 0.08 # Data bus utilization in percentage for reads
221system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
222system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
223system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing

224system.physmem.readRowHits 5833 # Number of row buffer hits during reads

224system.physmem.readRowHits 5838 # Number of row buffer hits during reads

225system.physmem.writeRowHits 0 # Number of row buffer hits during writes

226system.physmem.readRowHitRate 40.72 # Row buffer hit rate for reads

226system.physmem.readRowHitRate 40.75 # Row buffer hit rate for reads

227system.physmem.writeRowHitRate nan # Row buffer hit rate for writes

228system.physmem.avgGap 6014332.55 # Average gap between requests
229system.physmem.pageHitRate 40.72 # Row buffer hit rate, read and write combined
230system.physmem_0.actEnergy 51543660 # Energy for activate commands per rank (pJ)
231system.physmem_0.preEnergy 27384720 # Energy for precharge commands per rank (pJ)
232system.physmem_0.readEnergy 82088580 # Energy for read commands per rank (pJ)

228system.physmem.avgGap 6001688.70 # Average gap between requests
229system.physmem.pageHitRate 40.75 # Row buffer hit rate, read and write combined
230system.physmem_0.actEnergy 51557940 # Energy for activate commands per rank (pJ)
231system.physmem_0.preEnergy 27392310 # Energy for precharge commands per rank (pJ)
232system.physmem_0.readEnergy 82138560 # Energy for read commands per rank (pJ)

233system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)

234system.physmem_0.refreshEnergy 5186946960.000001 # Energy for refresh commands per rank (pJ)
235system.physmem_0.actBackEnergy 1121176890 # Energy for active background per rank (pJ)
236system.physmem_0.preBackEnergy 276161760 # Energy for precharge background per rank (pJ)
237system.physmem_0.actPowerDownEnergy 12273342600 # Energy for active power-down per rank (pJ)
238system.physmem_0.prePowerDownEnergy 8346662400 # Energy for precharge power-down per rank (pJ)
239system.physmem_0.selfRefreshEnergy 9294814230 # Energy for self refresh per rank (pJ)
240system.physmem_0.totalEnergy 36662152740 # Total energy per rank (pJ)
241system.physmem_0.averagePower 425.565010 # Core power per rank (mW)
242system.physmem_0.totalIdleTime 82965211526 # Total Idle time Per DRAM Rank
243system.physmem_0.memoryStateTime::IDLE 532687000 # Time in different power states
244system.physmem_0.memoryStateTime::REF 2205840000 # Time in different power states
245system.physmem_0.memoryStateTime::SREF 34315599752 # Time in different power states
246system.physmem_0.memoryStateTime::PRE_PDN 21736059604 # Time in different power states
247system.physmem_0.memoryStateTime::ACT 443979474 # Time in different power states
248system.physmem_0.memoryStateTime::ACT_PDN 26915192170 # Time in different power states
249system.physmem_1.actEnergy 9082080 # Energy for activate commands per rank (pJ)
250system.physmem_1.preEnergy 4823445 # Energy for precharge commands per rank (pJ)
251system.physmem_1.readEnergy 20184780 # Energy for read commands per rank (pJ)

234system.physmem_0.refreshEnergy 5188176240.000001 # Energy for refresh commands per rank (pJ)
235system.physmem_0.actBackEnergy 1121049780 # Energy for active background per rank (pJ)
236system.physmem_0.preBackEnergy 275286240 # Energy for precharge background per rank (pJ)
237system.physmem_0.actPowerDownEnergy 12230933460 # Energy for active power-down per rank (pJ)
238system.physmem_0.prePowerDownEnergy 8389841280 # Energy for precharge power-down per rank (pJ)
239system.physmem_0.selfRefreshEnergy 9251896980 # Energy for self refresh per rank (pJ)
240system.physmem_0.totalEnergy 36621408690 # Total energy per rank (pJ)
241system.physmem_0.averagePower 425.898657 # Core power per rank (mW)
242system.physmem_0.totalIdleTime 82802255264 # Total Idle time Per DRAM Rank
243system.physmem_0.memoryStateTime::IDLE 532741000 # Time in different power states
244system.physmem_0.memoryStateTime::REF 2206324000 # Time in different power states
245system.physmem_0.memoryStateTime::SREF 34133171250 # Time in different power states
246system.physmem_0.memoryStateTime::PRE_PDN 21848572364 # Time in different power states
247system.physmem_0.memoryStateTime::ACT 443169236 # Time in different power states
248system.physmem_0.memoryStateTime::ACT_PDN 26822225150 # Time in different power states
249system.physmem_1.actEnergy 9046380 # Energy for activate commands per rank (pJ)
250system.physmem_1.preEnergy 4800675 # Energy for precharge commands per rank (pJ)
251system.physmem_1.readEnergy 20149080 # Energy for read commands per rank (pJ)

252system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)

253system.physmem_1.refreshEnergy 883852320.000000 # Energy for refresh commands per rank (pJ)
254system.physmem_1.actBackEnergy 198703710 # Energy for active background per rank (pJ)
255system.physmem_1.preBackEnergy 50905920 # Energy for precharge background per rank (pJ)
256system.physmem_1.actPowerDownEnergy 1989700140 # Energy for active power-down per rank (pJ)
257system.physmem_1.prePowerDownEnergy 1383894720 # Energy for precharge power-down per rank (pJ)
258system.physmem_1.selfRefreshEnergy 18830063895 # Energy for self refresh per rank (pJ)
259system.physmem_1.totalEnergy 23371485780 # Total energy per rank (pJ)
260system.physmem_1.averagePower 271.290305 # Core power per rank (mW)
261system.physmem_1.totalIdleTime 85580460271 # Total Idle time Per DRAM Rank
262system.physmem_1.memoryStateTime::IDLE 101384000 # Time in different power states
263system.physmem_1.memoryStateTime::REF 376118000 # Time in different power states
264system.physmem_1.memoryStateTime::SREF 77613150500 # Time in different power states
265system.physmem_1.memoryStateTime::PRE_PDN 3603890386 # Time in different power states
266system.physmem_1.memoryStateTime::ACT 91368979 # Time in different power states
267system.physmem_1.memoryStateTime::ACT_PDN 4363446135 # Time in different power states
268system.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states
269system.cpu.branchPred.lookups 85639426 # Number of BP lookups
270system.cpu.branchPred.condPredicted 68185953 # Number of conditional branches predicted
271system.cpu.branchPred.condIncorrect 5937258 # Number of conditional branches incorrect
272system.cpu.branchPred.BTBLookups 39949340 # Number of BTB lookups
273system.cpu.branchPred.BTBHits 38185565 # Number of BTB hits

253system.physmem_1.refreshEnergy 880164480.000000 # Energy for refresh commands per rank (pJ)
254system.physmem_1.actBackEnergy 198118890 # Energy for active background per rank (pJ)
255system.physmem_1.preBackEnergy 50592480 # Energy for precharge background per rank (pJ)
256system.physmem_1.actPowerDownEnergy 1982659500 # Energy for active power-down per rank (pJ)
257system.physmem_1.prePowerDownEnergy 1381296480 # Energy for precharge power-down per rank (pJ)
258system.physmem_1.selfRefreshEnergy 18795083175 # Energy for self refresh per rank (pJ)
259system.physmem_1.totalEnergy 23322152130 # Total energy per rank (pJ)
260system.physmem_1.averagePower 271.231327 # Core power per rank (mW)
261system.physmem_1.totalIdleTime 85419499755 # Total Idle time Per DRAM Rank
262system.physmem_1.memoryStateTime::IDLE 100592000 # Time in different power states
263system.physmem_1.memoryStateTime::REF 374546000 # Time in different power states
264system.physmem_1.memoryStateTime::SREF 77474388250 # Time in different power states
265system.physmem_1.memoryStateTime::PRE_PDN 3597111150 # Time in different power states
266system.physmem_1.memoryStateTime::ACT 91565245 # Time in different power states
267system.physmem_1.memoryStateTime::ACT_PDN 4348000355 # Time in different power states
268system.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states
269system.cpu.branchPred.lookups 85644201 # Number of BP lookups
270system.cpu.branchPred.condPredicted 68263451 # Number of conditional branches predicted
271system.cpu.branchPred.condIncorrect 5948841 # Number of conditional branches incorrect
272system.cpu.branchPred.BTBLookups 39900262 # Number of BTB lookups
273system.cpu.branchPred.BTBHits 38156956 # Number of BTB hits

274system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.

275system.cpu.branchPred.BTBHitPct 95.584971 # BTB Hit Percentage
276system.cpu.branchPred.usedRAS 3683095 # Number of times the RAS was used to get a target.
277system.cpu.branchPred.RASInCorrect 81909 # Number of incorrect RAS predictions.
278system.cpu.branchPred.indirectLookups 681696 # Number of indirect predictor lookups.
279system.cpu.branchPred.indirectHits 653573 # Number of indirect target hits.
280system.cpu.branchPred.indirectMisses 28123 # Number of indirect misses.
281system.cpu.branchPredindirectMispredicted 40352 # Number of mispredicted indirect branches.

275system.cpu.branchPred.BTBHitPct 95.630841 # BTB Hit Percentage
276system.cpu.branchPred.usedRAS 3658994 # Number of times the RAS was used to get a target.
277system.cpu.branchPred.RASInCorrect 81907 # Number of incorrect RAS predictions.
278system.cpu.branchPred.indirectLookups 654149 # Number of indirect predictor lookups.
279system.cpu.branchPred.indirectHits 629298 # Number of indirect target hits.
280system.cpu.branchPred.indirectMisses 24851 # Number of indirect misses.
281system.cpu.branchPredindirectMispredicted 40566 # Number of mispredicted indirect branches.

282system.cpu_clk_domain.clock 500 # Clock period in ticks

283system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states

283system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states

284system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
285system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
286system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
287system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
288system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
289system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
290system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
291system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

305system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
306system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
307system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
308system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
309system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
310system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
311system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
312system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

313system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states

313system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states

314system.cpu.dtb.walker.walks 0 # Table walker walks requested
315system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
316system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
317system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
318system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
319system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
320system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
321system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

335system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
336system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
337system.cpu.dtb.read_accesses 0 # DTB read accesses
338system.cpu.dtb.write_accesses 0 # DTB write accesses
339system.cpu.dtb.inst_accesses 0 # ITB inst accesses
340system.cpu.dtb.hits 0 # DTB hits
341system.cpu.dtb.misses 0 # DTB misses
342system.cpu.dtb.accesses 0 # DTB accesses

343system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states

343system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states

344system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
345system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
346system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
347system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
348system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
349system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
350system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
351system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

365system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
366system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
367system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
368system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
369system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
370system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
371system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
372system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

373system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states

373system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states

374system.cpu.itb.walker.walks 0 # Table walker walks requested
375system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
376system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
377system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
378system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
379system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
380system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
381system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

396system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
397system.cpu.itb.read_accesses 0 # DTB read accesses
398system.cpu.itb.write_accesses 0 # DTB write accesses
399system.cpu.itb.inst_accesses 0 # ITB inst accesses
400system.cpu.itb.hits 0 # DTB hits
401system.cpu.itb.misses 0 # DTB misses
402system.cpu.itb.accesses 0 # DTB accesses
403system.cpu.workload.num_syscalls 400 # Number of system calls

404system.cpu.pwrStateResidencyTicks::ON 86149358000 # Cumulative time (in ticks) in various power states
405system.cpu.numCycles 172298717 # number of cpu cycles simulated

404system.cpu.pwrStateResidencyTicks::ON 85986203000 # Cumulative time (in ticks) in various power states
405system.cpu.numCycles 171972407 # number of cpu cycles simulated

406system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
407system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed

408system.cpu.fetch.icacheStallCycles 5689617 # Number of cycles fetch is stalled on an Icache miss
409system.cpu.fetch.Insts 347266831 # Number of instructions fetch has processed
410system.cpu.fetch.Branches 85639426 # Number of branches that fetch encountered
411system.cpu.fetch.predictedBranches 42522233 # Number of branches that fetch has predicted taken
412system.cpu.fetch.Cycles 158380748 # Number of cycles fetch has run and was not squashing or blocked
413system.cpu.fetch.SquashCycles 11888463 # Number of cycles fetch has spent squashing
414system.cpu.fetch.MiscStallCycles 4145 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs

408system.cpu.fetch.icacheStallCycles 5684699 # Number of cycles fetch is stalled on an Icache miss
409system.cpu.fetch.Insts 346733793 # Number of instructions fetch has processed
410system.cpu.fetch.Branches 85644201 # Number of branches that fetch encountered
411system.cpu.fetch.predictedBranches 42445248 # Number of branches that fetch has predicted taken
412system.cpu.fetch.Cycles 158074641 # Number of cycles fetch has run and was not squashing or blocked
413system.cpu.fetch.SquashCycles 11911485 # Number of cycles fetch has spent squashing
414system.cpu.fetch.MiscStallCycles 4331 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs

415system.cpu.fetch.PendingQuiesceStallCycles 80 # Number of stall cycles due to pending quiesce instructions

416system.cpu.fetch.IcacheWaitRetryStallCycles 4281 # Number of stall cycles due to full MSHR
417system.cpu.fetch.CacheLines 78346664 # Number of cache lines fetched
418system.cpu.fetch.IcacheSquashes 18062 # Number of outstanding Icache misses that were squashed
419system.cpu.fetch.rateDist::samples 170023102 # Number of instructions fetched each cycle (Total)
420system.cpu.fetch.rateDist::mean 2.137102 # Number of instructions fetched each cycle (Total)
421system.cpu.fetch.rateDist::stdev 1.057569 # Number of instructions fetched each cycle (Total)

416system.cpu.fetch.IcacheWaitRetryStallCycles 4750 # Number of stall cycles due to full MSHR
417system.cpu.fetch.CacheLines 78152122 # Number of cache lines fetched
418system.cpu.fetch.IcacheSquashes 17905 # Number of outstanding Icache misses that were squashed
419system.cpu.fetch.rateDist::samples 169724243 # Number of instructions fetched each cycle (Total)
420system.cpu.fetch.rateDist::mean 2.137034 # Number of instructions fetched each cycle (Total)
421system.cpu.fetch.rateDist::stdev 1.057596 # Number of instructions fetched each cycle (Total)

422system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

423system.cpu.fetch.rateDist::0 18318468 10.77% 10.77% # Number of instructions fetched each cycle (Total)
424system.cpu.fetch.rateDist::1 30068726 17.69% 28.46% # Number of instructions fetched each cycle (Total)
425system.cpu.fetch.rateDist::2 31619725 18.60% 47.06% # Number of instructions fetched each cycle (Total)
426system.cpu.fetch.rateDist::3 90016183 52.94% 100.00% # Number of instructions fetched each cycle (Total)

423system.cpu.fetch.rateDist::0 18311667 10.79% 10.79% # Number of instructions fetched each cycle (Total)
424system.cpu.fetch.rateDist::1 29948653 17.65% 28.43% # Number of instructions fetched each cycle (Total)
425system.cpu.fetch.rateDist::2 31633861 18.64% 47.07% # Number of instructions fetched each cycle (Total)
426system.cpu.fetch.rateDist::3 89830062 52.93% 100.00% # Number of instructions fetched each cycle (Total)

427system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
428system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
429system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)

430system.cpu.fetch.rateDist::total 170023102 # Number of instructions fetched each cycle (Total)
431system.cpu.fetch.branchRate 0.497040 # Number of branch fetches per cycle
432system.cpu.fetch.rate 2.015493 # Number of inst fetches per cycle
433system.cpu.decode.IdleCycles 17554244 # Number of cycles decode is idle
434system.cpu.decode.BlockedCycles 18101467 # Number of cycles decode is blocked
435system.cpu.decode.RunCycles 121824905 # Number of cycles decode is running
436system.cpu.decode.UnblockCycles 6773054 # Number of cycles decode is unblocking
437system.cpu.decode.SquashCycles 5769432 # Number of cycles decode is squashing
438system.cpu.decode.BranchResolved 11065775 # Number of times decode resolved a branch
439system.cpu.decode.BranchMispred 189948 # Number of times decode detected a branch misprediction
440system.cpu.decode.DecodedInsts 305038109 # Number of instructions handled by decode
441system.cpu.decode.SquashedInsts 27237354 # Number of squashed instructions handled by decode
442system.cpu.rename.SquashCycles 5769432 # Number of cycles rename is squashing
443system.cpu.rename.IdleCycles 37539679 # Number of cycles rename is idle
444system.cpu.rename.BlockCycles 8956907 # Number of cycles rename is blocking
445system.cpu.rename.serializeStallCycles 601126 # count of cycles rename stalled for serializing inst
446system.cpu.rename.RunCycles 108322423 # Number of cycles rename is running
447system.cpu.rename.UnblockCycles 8833535 # Number of cycles rename is unblocking
448system.cpu.rename.RenamedInsts 277447852 # Number of instructions processed by rename
449system.cpu.rename.SquashedInsts 13184486 # Number of squashed instructions processed by rename
450system.cpu.rename.ROBFullEvents 3097243 # Number of times rename has blocked due to ROB full
451system.cpu.rename.IQFullEvents 842563 # Number of times rename has blocked due to IQ full
452system.cpu.rename.LQFullEvents 2612762 # Number of times rename has blocked due to LQ full
453system.cpu.rename.SQFullEvents 40533 # Number of times rename has blocked due to SQ full
454system.cpu.rename.FullRegisterEvents 26849 # Number of times there has been no free registers
455system.cpu.rename.RenamedOperands 481448776 # Number of destination operands rename has renamed
456system.cpu.rename.RenameLookups 1187920227 # Number of register rename lookups that rename has made
457system.cpu.rename.int_rename_lookups 296497585 # Number of integer rename lookups
458system.cpu.rename.fp_rename_lookups 3005089 # Number of floating rename lookups

430system.cpu.fetch.rateDist::total 169724243 # Number of instructions fetched each cycle (Total)
431system.cpu.fetch.branchRate 0.498011 # Number of branch fetches per cycle
432system.cpu.fetch.rate 2.016218 # Number of inst fetches per cycle
433system.cpu.decode.IdleCycles 17545924 # Number of cycles decode is idle
434system.cpu.decode.BlockedCycles 18077628 # Number of cycles decode is blocked
435system.cpu.decode.RunCycles 121579812 # Number of cycles decode is running
436system.cpu.decode.UnblockCycles 6764631 # Number of cycles decode is unblocking
437system.cpu.decode.SquashCycles 5756248 # Number of cycles decode is squashing
438system.cpu.decode.BranchResolved 32661376 # Number of times decode resolved a branch
439system.cpu.decode.BranchMispred 214759 # Number of times decode detected a branch misprediction
440system.cpu.decode.DecodedInsts 304427843 # Number of instructions handled by decode
441system.cpu.decode.SquashedInsts 27289068 # Number of squashed instructions handled by decode
442system.cpu.rename.SquashCycles 5756248 # Number of cycles rename is squashing
443system.cpu.rename.IdleCycles 37507593 # Number of cycles rename is idle
444system.cpu.rename.BlockCycles 8946109 # Number of cycles rename is blocking
445system.cpu.rename.serializeStallCycles 602389 # count of cycles rename stalled for serializing inst
446system.cpu.rename.RunCycles 108088153 # Number of cycles rename is running
447system.cpu.rename.UnblockCycles 8823751 # Number of cycles rename is unblocking
448system.cpu.rename.RenamedInsts 276998119 # Number of instructions processed by rename
449system.cpu.rename.SquashedInsts 13097154 # Number of squashed instructions processed by rename
450system.cpu.rename.ROBFullEvents 3089202 # Number of times rename has blocked due to ROB full
451system.cpu.rename.IQFullEvents 850461 # Number of times rename has blocked due to IQ full
452system.cpu.rename.LQFullEvents 2596711 # Number of times rename has blocked due to LQ full
453system.cpu.rename.SQFullEvents 40764 # Number of times rename has blocked due to SQ full
454system.cpu.rename.FullRegisterEvents 26854 # Number of times there has been no free registers
455system.cpu.rename.RenamedOperands 480912034 # Number of destination operands rename has renamed
456system.cpu.rename.RenameLookups 1185877305 # Number of register rename lookups that rename has made
457system.cpu.rename.int_rename_lookups 296009785 # Number of integer rename lookups
458system.cpu.rename.fp_rename_lookups 3004340 # Number of floating rename lookups

459system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed

460system.cpu.rename.UndoneMaps 188471847 # Number of HB maps that are undone due to squashing
461system.cpu.rename.serializingInsts 23626 # count of serializing insts renamed
462system.cpu.rename.tempSerializingInsts 23625 # count of temporary serializing insts renamed
463system.cpu.rename.skidInsts 13449474 # count of insts added to the skid buffer
464system.cpu.memDep0.insertedLoads 33921609 # Number of loads inserted to the mem dependence unit.
465system.cpu.memDep0.insertedStores 14424624 # Number of stores inserted to the mem dependence unit.
466system.cpu.memDep0.conflictingLoads 2552614 # Number of conflicting loads.
467system.cpu.memDep0.conflictingStores 1816807 # Number of conflicting stores.
468system.cpu.iq.iqInstsAdded 263824183 # Number of instructions added to the IQ (excludes non-spec)
469system.cpu.iq.iqNonSpecInstsAdded 45978 # Number of non-speculative instructions added to the IQ
470system.cpu.iq.iqInstsIssued 214443460 # Number of instructions issued
471system.cpu.iq.iqSquashedInstsIssued 5190288 # Number of squashed instructions issued
472system.cpu.iq.iqSquashedInstsExamined 82234207 # Number of squashed instructions iterated over during squash; mainly for profiling
473system.cpu.iq.iqSquashedOperandsExamined 216932052 # Number of squashed operands that are examined and possibly removed from graph
474system.cpu.iq.iqSquashedNonSpecRemoved 762 # Number of squashed non-spec instructions that were removed
475system.cpu.iq.issued_per_cycle::samples 170023102 # Number of insts issued each cycle
476system.cpu.iq.issued_per_cycle::mean 1.261261 # Number of insts issued each cycle
477system.cpu.iq.issued_per_cycle::stdev 1.018489 # Number of insts issued each cycle

460system.cpu.rename.UndoneMaps 187935105 # Number of HB maps that are undone due to squashing
461system.cpu.rename.serializingInsts 23572 # count of serializing insts renamed
462system.cpu.rename.tempSerializingInsts 23567 # count of temporary serializing insts renamed
463system.cpu.rename.skidInsts 13428642 # count of insts added to the skid buffer
464system.cpu.memDep0.insertedLoads 33801265 # Number of loads inserted to the mem dependence unit.
465system.cpu.memDep0.insertedStores 14384966 # Number of stores inserted to the mem dependence unit.
466system.cpu.memDep0.conflictingLoads 2539582 # Number of conflicting loads.
467system.cpu.memDep0.conflictingStores 1819756 # Number of conflicting stores.
468system.cpu.iq.iqInstsAdded 263460878 # Number of instructions added to the IQ (excludes non-spec)
469system.cpu.iq.iqNonSpecInstsAdded 45929 # Number of non-speculative instructions added to the IQ
470system.cpu.iq.iqInstsIssued 214221426 # Number of instructions issued
471system.cpu.iq.iqSquashedInstsIssued 5142742 # Number of squashed instructions issued
472system.cpu.iq.iqSquashedInstsExamined 81870853 # Number of squashed instructions iterated over during squash; mainly for profiling
473system.cpu.iq.iqSquashedOperandsExamined 215931448 # Number of squashed operands that are examined and possibly removed from graph
474system.cpu.iq.iqSquashedNonSpecRemoved 713 # Number of squashed non-spec instructions that were removed
475system.cpu.iq.issued_per_cycle::samples 169724243 # Number of insts issued each cycle
476system.cpu.iq.issued_per_cycle::mean 1.262173 # Number of insts issued each cycle
477system.cpu.iq.issued_per_cycle::stdev 1.018049 # Number of insts issued each cycle

478system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

479system.cpu.iq.issued_per_cycle::0 53215331 31.30% 31.30% # Number of insts issued each cycle
480system.cpu.iq.issued_per_cycle::1 36043504 21.20% 52.50% # Number of insts issued each cycle
481system.cpu.iq.issued_per_cycle::2 65536118 38.55% 91.04% # Number of insts issued each cycle
482system.cpu.iq.issued_per_cycle::3 13631246 8.02% 99.06% # Number of insts issued each cycle
483system.cpu.iq.issued_per_cycle::4 1550810 0.91% 99.97% # Number of insts issued each cycle
484system.cpu.iq.issued_per_cycle::5 45816 0.03% 100.00% # Number of insts issued each cycle
485system.cpu.iq.issued_per_cycle::6 277 0.00% 100.00% # Number of insts issued each cycle

479system.cpu.iq.issued_per_cycle::0 53012533 31.23% 31.23% # Number of insts issued each cycle
480system.cpu.iq.issued_per_cycle::1 36041444 21.24% 52.47% # Number of insts issued each cycle
481system.cpu.iq.issued_per_cycle::2 65469642 38.57% 91.04% # Number of insts issued each cycle
482system.cpu.iq.issued_per_cycle::3 13608265 8.02% 99.06% # Number of insts issued each cycle
483system.cpu.iq.issued_per_cycle::4 1546158 0.91% 99.97% # Number of insts issued each cycle
484system.cpu.iq.issued_per_cycle::5 45935 0.03% 100.00% # Number of insts issued each cycle
485system.cpu.iq.issued_per_cycle::6 266 0.00% 100.00% # Number of insts issued each cycle

486system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
487system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
488system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
489system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
490system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle

491system.cpu.iq.issued_per_cycle::total 170023102 # Number of insts issued each cycle

491system.cpu.iq.issued_per_cycle::total 169724243 # Number of insts issued each cycle

492system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

493system.cpu.iq.fu_full::IntAlu 35671391 66.13% 66.13% # attempts to use FU when none available
494system.cpu.iq.fu_full::IntMult 153271 0.28% 66.41% # attempts to use FU when none available
495system.cpu.iq.fu_full::IntDiv 0 0.00% 66.41% # attempts to use FU when none available
496system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.41% # attempts to use FU when none available
497system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.41% # attempts to use FU when none available
498system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.41% # attempts to use FU when none available
499system.cpu.iq.fu_full::FloatMult 0 0.00% 66.41% # attempts to use FU when none available
500system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 66.41% # attempts to use FU when none available
501system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.41% # attempts to use FU when none available
502system.cpu.iq.fu_full::FloatMisc 0 0.00% 66.41% # attempts to use FU when none available
503system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.41% # attempts to use FU when none available
504system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.41% # attempts to use FU when none available
505system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.41% # attempts to use FU when none available
506system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.41% # attempts to use FU when none available
507system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.41% # attempts to use FU when none available
508system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.41% # attempts to use FU when none available
509system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.41% # attempts to use FU when none available
510system.cpu.iq.fu_full::SimdMult 0 0.00% 66.41% # attempts to use FU when none available
511system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.41% # attempts to use FU when none available
512system.cpu.iq.fu_full::SimdShift 0 0.00% 66.41% # attempts to use FU when none available
513system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.41% # attempts to use FU when none available
514system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.41% # attempts to use FU when none available
515system.cpu.iq.fu_full::SimdFloatAdd 1065 0.00% 66.42% # attempts to use FU when none available
516system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.42% # attempts to use FU when none available
517system.cpu.iq.fu_full::SimdFloatCmp 35712 0.07% 66.48% # attempts to use FU when none available
518system.cpu.iq.fu_full::SimdFloatCvt 263 0.00% 66.48% # attempts to use FU when none available
519system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.48% # attempts to use FU when none available
520system.cpu.iq.fu_full::SimdFloatMisc 556 0.00% 66.48% # attempts to use FU when none available
521system.cpu.iq.fu_full::SimdFloatMult 40135 0.07% 66.56% # attempts to use FU when none available
522system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.56% # attempts to use FU when none available
523system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.56% # attempts to use FU when none available
524system.cpu.iq.fu_full::MemRead 13909773 25.79% 92.35% # attempts to use FU when none available
525system.cpu.iq.fu_full::MemWrite 3850022 7.14% 99.48% # attempts to use FU when none available
526system.cpu.iq.fu_full::FloatMemRead 142020 0.26% 99.75% # attempts to use FU when none available
527system.cpu.iq.fu_full::FloatMemWrite 136319 0.25% 100.00% # attempts to use FU when none available

493system.cpu.iq.fu_full::IntAlu 35637562 66.14% 66.14% # attempts to use FU when none available
494system.cpu.iq.fu_full::IntMult 153239 0.28% 66.43% # attempts to use FU when none available
495system.cpu.iq.fu_full::IntDiv 0 0.00% 66.43% # attempts to use FU when none available
496system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.43% # attempts to use FU when none available
497system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.43% # attempts to use FU when none available
498system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.43% # attempts to use FU when none available
499system.cpu.iq.fu_full::FloatMult 0 0.00% 66.43% # attempts to use FU when none available
500system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 66.43% # attempts to use FU when none available
501system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.43% # attempts to use FU when none available
502system.cpu.iq.fu_full::FloatMisc 0 0.00% 66.43% # attempts to use FU when none available
503system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.43% # attempts to use FU when none available
504system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.43% # attempts to use FU when none available
505system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.43% # attempts to use FU when none available
506system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.43% # attempts to use FU when none available
507system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.43% # attempts to use FU when none available
508system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.43% # attempts to use FU when none available
509system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.43% # attempts to use FU when none available
510system.cpu.iq.fu_full::SimdMult 0 0.00% 66.43% # attempts to use FU when none available
511system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.43% # attempts to use FU when none available
512system.cpu.iq.fu_full::SimdShift 0 0.00% 66.43% # attempts to use FU when none available
513system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.43% # attempts to use FU when none available
514system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.43% # attempts to use FU when none available
515system.cpu.iq.fu_full::SimdFloatAdd 1065 0.00% 66.43% # attempts to use FU when none available
516system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.43% # attempts to use FU when none available
517system.cpu.iq.fu_full::SimdFloatCmp 35742 0.07% 66.49% # attempts to use FU when none available
518system.cpu.iq.fu_full::SimdFloatCvt 263 0.00% 66.50% # attempts to use FU when none available
519system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.50% # attempts to use FU when none available
520system.cpu.iq.fu_full::SimdFloatMisc 559 0.00% 66.50% # attempts to use FU when none available
521system.cpu.iq.fu_full::SimdFloatMult 40182 0.07% 66.57% # attempts to use FU when none available
522system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.57% # attempts to use FU when none available
523system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.57% # attempts to use FU when none available
524system.cpu.iq.fu_full::MemRead 13886588 25.77% 92.34% # attempts to use FU when none available
525system.cpu.iq.fu_full::MemWrite 3846845 7.14% 99.48% # attempts to use FU when none available
526system.cpu.iq.fu_full::FloatMemRead 141772 0.26% 99.75% # attempts to use FU when none available
527system.cpu.iq.fu_full::FloatMemWrite 136229 0.25% 100.00% # attempts to use FU when none available

528system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
529system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
530system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

531system.cpu.iq.FU_type_0::IntAlu 167011334 77.88% 77.88% # Type of FU issued
532system.cpu.iq.FU_type_0::IntMult 919426 0.43% 78.31% # Type of FU issued
533system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.31% # Type of FU issued
534system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.31% # Type of FU issued
535system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.31% # Type of FU issued
536system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.31% # Type of FU issued
537system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.31% # Type of FU issued
538system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 78.31% # Type of FU issued
539system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.31% # Type of FU issued
540system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 78.31% # Type of FU issued
541system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.31% # Type of FU issued
542system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.31% # Type of FU issued
543system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.31% # Type of FU issued
544system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.31% # Type of FU issued
545system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.31% # Type of FU issued
546system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.31% # Type of FU issued
547system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.31% # Type of FU issued
548system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.31% # Type of FU issued
549system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.31% # Type of FU issued
550system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.31% # Type of FU issued
551system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.31% # Type of FU issued
552system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.31% # Type of FU issued
553system.cpu.iq.FU_type_0::SimdFloatAdd 33015 0.02% 78.33% # Type of FU issued
554system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.33% # Type of FU issued
555system.cpu.iq.FU_type_0::SimdFloatCmp 165180 0.08% 78.40% # Type of FU issued
556system.cpu.iq.FU_type_0::SimdFloatCvt 245708 0.11% 78.52% # Type of FU issued
557system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.55% # Type of FU issued
558system.cpu.iq.FU_type_0::SimdFloatMisc 460349 0.21% 78.77% # Type of FU issued
559system.cpu.iq.FU_type_0::SimdFloatMult 206623 0.10% 78.86% # Type of FU issued
560system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.90% # Type of FU issued
561system.cpu.iq.FU_type_0::SimdFloatSqrt 318 0.00% 78.90% # Type of FU issued
562system.cpu.iq.FU_type_0::MemRead 31296412 14.59% 93.49% # Type of FU issued
563system.cpu.iq.FU_type_0::MemWrite 13233182 6.17% 99.66% # Type of FU issued
564system.cpu.iq.FU_type_0::FloatMemRead 576648 0.27% 99.93% # Type of FU issued
565system.cpu.iq.FU_type_0::FloatMemWrite 147624 0.07% 100.00% # Type of FU issued

531system.cpu.iq.FU_type_0::IntAlu 166877725 77.90% 77.90% # Type of FU issued
532system.cpu.iq.FU_type_0::IntMult 919560 0.43% 78.33% # Type of FU issued
533system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.33% # Type of FU issued
534system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.33% # Type of FU issued
535system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.33% # Type of FU issued
536system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.33% # Type of FU issued
537system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.33% # Type of FU issued
538system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 78.33% # Type of FU issued
539system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.33% # Type of FU issued
540system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 78.33% # Type of FU issued
541system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.33% # Type of FU issued
542system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.33% # Type of FU issued
543system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.33% # Type of FU issued
544system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.33% # Type of FU issued
545system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.33% # Type of FU issued
546system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.33% # Type of FU issued
547system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.33% # Type of FU issued
548system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.33% # Type of FU issued
549system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.33% # Type of FU issued
550system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.33% # Type of FU issued
551system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.33% # Type of FU issued
552system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.33% # Type of FU issued
553system.cpu.iq.FU_type_0::SimdFloatAdd 33017 0.02% 78.34% # Type of FU issued
554system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.34% # Type of FU issued
555system.cpu.iq.FU_type_0::SimdFloatCmp 165187 0.08% 78.42% # Type of FU issued
556system.cpu.iq.FU_type_0::SimdFloatCvt 245719 0.11% 78.54% # Type of FU issued
557system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.57% # Type of FU issued
558system.cpu.iq.FU_type_0::SimdFloatMisc 460300 0.21% 78.79% # Type of FU issued
559system.cpu.iq.FU_type_0::SimdFloatMult 206641 0.10% 78.88% # Type of FU issued
560system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.92% # Type of FU issued
561system.cpu.iq.FU_type_0::SimdFloatSqrt 318 0.00% 78.92% # Type of FU issued
562system.cpu.iq.FU_type_0::MemRead 31220842 14.57% 93.49% # Type of FU issued
563system.cpu.iq.FU_type_0::MemWrite 13220710 6.17% 99.66% # Type of FU issued
564system.cpu.iq.FU_type_0::FloatMemRead 576371 0.27% 99.93% # Type of FU issued
565system.cpu.iq.FU_type_0::FloatMemWrite 147395 0.07% 100.00% # Type of FU issued

566system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
567system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

568system.cpu.iq.FU_type_0::total 214443460 # Type of FU issued
569system.cpu.iq.rate 1.244603 # Inst issue rate
570system.cpu.iq.fu_busy_cnt 53940732 # FU busy when requested
571system.cpu.iq.fu_busy_rate 0.251538 # FU busy rate (busy events/executed inst)
572system.cpu.iq.int_inst_queue_reads 654047721 # Number of integer instruction queue reads
573system.cpu.iq.int_inst_queue_writes 344100630 # Number of integer instruction queue writes
574system.cpu.iq.int_inst_queue_wakeup_accesses 204290427 # Number of integer instruction queue wakeup accesses
575system.cpu.iq.fp_inst_queue_reads 3993321 # Number of floating instruction queue reads
576system.cpu.iq.fp_inst_queue_writes 2010682 # Number of floating instruction queue writes
577system.cpu.iq.fp_inst_queue_wakeup_accesses 1806323 # Number of floating instruction queue wakeup accesses
578system.cpu.iq.int_alu_accesses 266209914 # Number of integer alu accesses
579system.cpu.iq.fp_alu_accesses 2174278 # Number of floating point alu accesses
580system.cpu.iew.lsq.thread0.forwLoads 1590245 # Number of loads that had data forwarded from stores

568system.cpu.iq.FU_type_0::total 214221426 # Type of FU issued
569system.cpu.iq.rate 1.245673 # Inst issue rate
570system.cpu.iq.fu_busy_cnt 53880251 # FU busy when requested
571system.cpu.iq.fu_busy_rate 0.251517 # FU busy rate (busy events/executed inst)
572system.cpu.iq.int_inst_queue_reads 653198075 # Number of integer instruction queue reads
573system.cpu.iq.int_inst_queue_writes 343375917 # Number of integer instruction queue writes
574system.cpu.iq.int_inst_queue_wakeup_accesses 204156399 # Number of integer instruction queue wakeup accesses
575system.cpu.iq.fp_inst_queue_reads 3992013 # Number of floating instruction queue reads
576system.cpu.iq.fp_inst_queue_writes 2008700 # Number of floating instruction queue writes
577system.cpu.iq.fp_inst_queue_wakeup_accesses 1806249 # Number of floating instruction queue wakeup accesses
578system.cpu.iq.int_alu_accesses 265928183 # Number of integer alu accesses
579system.cpu.iq.fp_alu_accesses 2173494 # Number of floating point alu accesses
580system.cpu.iew.lsq.thread0.forwLoads 1586831 # Number of loads that had data forwarded from stores

581system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

582system.cpu.iew.lsq.thread0.squashedLoads 6025465 # Number of loads squashed
583system.cpu.iew.lsq.thread0.ignoredResponses 7430 # Number of memory responses ignored because the instruction is squashed
584system.cpu.iew.lsq.thread0.memOrderViolation 7094 # Number of memory ordering violations
585system.cpu.iew.lsq.thread0.squashedStores 1779990 # Number of stores squashed

582system.cpu.iew.lsq.thread0.squashedLoads 5905121 # Number of loads squashed
583system.cpu.iew.lsq.thread0.ignoredResponses 6947 # Number of memory responses ignored because the instruction is squashed
584system.cpu.iew.lsq.thread0.memOrderViolation 7000 # Number of memory ordering violations
585system.cpu.iew.lsq.thread0.squashedStores 1740332 # Number of stores squashed

586system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
587system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding

588system.cpu.iew.lsq.thread0.rescheduledLoads 25605 # Number of loads that were rescheduled
589system.cpu.iew.lsq.thread0.cacheBlocked 790 # Number of times an access to memory failed due to the cache being blocked

588system.cpu.iew.lsq.thread0.rescheduledLoads 25012 # Number of loads that were rescheduled
589system.cpu.iew.lsq.thread0.cacheBlocked 810 # Number of times an access to memory failed due to the cache being blocked

590system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle

591system.cpu.iew.iewSquashCycles 5769432 # Number of cycles IEW is squashing
592system.cpu.iew.iewBlockCycles 5627104 # Number of cycles IEW is blocking
593system.cpu.iew.iewUnblockCycles 174387 # Number of cycles IEW is unblocking
594system.cpu.iew.iewDispatchedInsts 263890272 # Number of instructions dispatched to IQ

591system.cpu.iew.iewSquashCycles 5756248 # Number of cycles IEW is squashing
592system.cpu.iew.iewBlockCycles 5611049 # Number of cycles IEW is blocking
593system.cpu.iew.iewUnblockCycles 173372 # Number of cycles IEW is unblocking
594system.cpu.iew.iewDispatchedInsts 263527171 # Number of instructions dispatched to IQ

595system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch

596system.cpu.iew.iewDispLoadInsts 33921609 # Number of dispatched load instructions
597system.cpu.iew.iewDispStoreInsts 14424624 # Number of dispatched store instructions
598system.cpu.iew.iewDispNonSpecInsts 23570 # Number of dispatched non-speculative instructions
599system.cpu.iew.iewIQFullEvents 3854 # Number of times the IQ has become full, causing a stall
600system.cpu.iew.iewLSQFullEvents 167353 # Number of times the LSQ has become full, causing a stall
601system.cpu.iew.memOrderViolationEvents 7094 # Number of memory order violations
602system.cpu.iew.predictedTakenIncorrect 3148097 # Number of branches that were predicted taken incorrectly
603system.cpu.iew.predictedNotTakenIncorrect 3247402 # Number of branches that were predicted not taken incorrectly
604system.cpu.iew.branchMispredicts 6395499 # Number of branch mispredicts detected at execute
605system.cpu.iew.iewExecutedInsts 207161825 # Number of executed instructions
606system.cpu.iew.iewExecLoadInsts 30639651 # Number of load instructions executed
607system.cpu.iew.iewExecSquashedInsts 7281635 # Number of squashed instructions skipped in execute

596system.cpu.iew.iewDispLoadInsts 33801265 # Number of dispatched load instructions
597system.cpu.iew.iewDispStoreInsts 14384966 # Number of dispatched store instructions
598system.cpu.iew.iewDispNonSpecInsts 23521 # Number of dispatched non-speculative instructions
599system.cpu.iew.iewIQFullEvents 3789 # Number of times the IQ has become full, causing a stall
600system.cpu.iew.iewLSQFullEvents 166382 # Number of times the LSQ has become full, causing a stall
601system.cpu.iew.memOrderViolationEvents 7000 # Number of memory order violations
602system.cpu.iew.predictedTakenIncorrect 3130012 # Number of branches that were predicted taken incorrectly
603system.cpu.iew.predictedNotTakenIncorrect 3255540 # Number of branches that were predicted not taken incorrectly
604system.cpu.iew.branchMispredicts 6385552 # Number of branch mispredicts detected at execute
605system.cpu.iew.iewExecutedInsts 206995589 # Number of executed instructions
606system.cpu.iew.iewExecLoadInsts 30591856 # Number of load instructions executed
607system.cpu.iew.iewExecSquashedInsts 7225837 # Number of squashed instructions skipped in execute

608system.cpu.iew.exec_swp 0 # number of swp insts executed

609system.cpu.iew.exec_nop 20111 # number of nop insts executed
610system.cpu.iew.exec_refs 43786600 # number of memory reference insts executed
611system.cpu.iew.exec_branches 44861358 # Number of branches executed
612system.cpu.iew.exec_stores 13146949 # Number of stores executed
613system.cpu.iew.exec_rate 1.202341 # Inst execution rate
614system.cpu.iew.wb_sent 206406222 # cumulative count of insts sent to commit
615system.cpu.iew.wb_count 206096750 # cumulative count of insts written-back
616system.cpu.iew.wb_producers 129381204 # num instructions producing a value
617system.cpu.iew.wb_consumers 221650091 # num instructions consuming a value
618system.cpu.iew.wb_rate 1.196160 # insts written-back per cycle
619system.cpu.iew.wb_fanout 0.583718 # average fanout of values written-back
620system.cpu.commit.commitSquashedInsts 68697467 # The number of squashed insts skipped by commit

609system.cpu.iew.exec_nop 20364 # number of nop insts executed
610system.cpu.iew.exec_refs 43730352 # number of memory reference insts executed
611system.cpu.iew.exec_branches 44853428 # Number of branches executed
612system.cpu.iew.exec_stores 13138496 # Number of stores executed
613system.cpu.iew.exec_rate 1.203656 # Inst execution rate
614system.cpu.iew.wb_sent 206269583 # cumulative count of insts sent to commit
615system.cpu.iew.wb_count 205962648 # cumulative count of insts written-back
616system.cpu.iew.wb_producers 129302452 # num instructions producing a value
617system.cpu.iew.wb_consumers 221536410 # num instructions consuming a value
618system.cpu.iew.wb_rate 1.197649 # insts written-back per cycle
619system.cpu.iew.wb_fanout 0.583662 # average fanout of values written-back
620system.cpu.commit.commitSquashedInsts 68402964 # The number of squashed insts skipped by commit

621system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards

622system.cpu.commit.branchMispredicts 5762459 # The number of times a branch was mispredicted
623system.cpu.commit.committed_per_cycle::samples 158721175 # Number of insts commited each cycle
624system.cpu.commit.committed_per_cycle::mean 1.144462 # Number of insts commited each cycle
625system.cpu.commit.committed_per_cycle::stdev 1.650716 # Number of insts commited each cycle

622system.cpu.commit.branchMispredicts 5749347 # The number of times a branch was mispredicted
623system.cpu.commit.committed_per_cycle::samples 158452610 # Number of insts commited each cycle
624system.cpu.commit.committed_per_cycle::mean 1.146402 # Number of insts commited each cycle
625system.cpu.commit.committed_per_cycle::stdev 1.651768 # Number of insts commited each cycle

626system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

627system.cpu.commit.committed_per_cycle::0 74120611 46.70% 46.70% # Number of insts commited each cycle
628system.cpu.commit.committed_per_cycle::1 41150811 25.93% 72.63% # Number of insts commited each cycle
629system.cpu.commit.committed_per_cycle::2 22560961 14.21% 86.84% # Number of insts commited each cycle
630system.cpu.commit.committed_per_cycle::3 9504738 5.99% 92.83% # Number of insts commited each cycle
631system.cpu.commit.committed_per_cycle::4 3552513 2.24% 95.07% # Number of insts commited each cycle
632system.cpu.commit.committed_per_cycle::5 2129219 1.34% 96.41% # Number of insts commited each cycle
633system.cpu.commit.committed_per_cycle::6 1299436 0.82% 97.23% # Number of insts commited each cycle
634system.cpu.commit.committed_per_cycle::7 1012456 0.64% 97.86% # Number of insts commited each cycle
635system.cpu.commit.committed_per_cycle::8 3390430 2.14% 100.00% # Number of insts commited each cycle

627system.cpu.commit.committed_per_cycle::0 73893836 46.63% 46.63% # Number of insts commited each cycle
628system.cpu.commit.committed_per_cycle::1 41104048 25.94% 72.58% # Number of insts commited each cycle
629system.cpu.commit.committed_per_cycle::2 22555911 14.24% 86.81% # Number of insts commited each cycle
630system.cpu.commit.committed_per_cycle::3 9496527 5.99% 92.80% # Number of insts commited each cycle
631system.cpu.commit.committed_per_cycle::4 3557786 2.25% 95.05% # Number of insts commited each cycle
632system.cpu.commit.committed_per_cycle::5 2129951 1.34% 96.39% # Number of insts commited each cycle
633system.cpu.commit.committed_per_cycle::6 1320929 0.83% 97.23% # Number of insts commited each cycle
634system.cpu.commit.committed_per_cycle::7 1010558 0.64% 97.86% # Number of insts commited each cycle
635system.cpu.commit.committed_per_cycle::8 3383064 2.14% 100.00% # Number of insts commited each cycle

636system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
637system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
638system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

639system.cpu.commit.committed_per_cycle::total 158721175 # Number of insts commited each cycle

639system.cpu.commit.committed_per_cycle::total 158452610 # Number of insts commited each cycle

640system.cpu.commit.committedInsts 172317410 # Number of instructions committed
641system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed
642system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
643system.cpu.commit.refs 40540778 # Number of memory references committed
644system.cpu.commit.loads 27896144 # Number of loads committed
645system.cpu.commit.membars 22408 # Number of memory barriers committed
646system.cpu.commit.branches 40300312 # Number of branches committed
647system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions.

--- 33 unchanged lines hidden (view full) ---

681system.cpu.commit.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction
682system.cpu.commit.op_class_0::MemRead 27348059 15.06% 92.74% # Class of committed instruction
683system.cpu.commit.op_class_0::MemWrite 12498388 6.88% 99.62% # Class of committed instruction
684system.cpu.commit.op_class_0::FloatMemRead 548085 0.30% 99.92% # Class of committed instruction
685system.cpu.commit.op_class_0::FloatMemWrite 146246 0.08% 100.00% # Class of committed instruction
686system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
687system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
688system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction

689system.cpu.commit.bw_lim_events 3390430 # number cycles where commit BW limit reached
690system.cpu.rob.rob_reads 405673353 # The number of ROB reads
691system.cpu.rob.rob_writes 512011515 # The number of ROB writes
692system.cpu.timesIdled 9971 # Number of times that the entire CPU went into an idle state and unscheduled itself
693system.cpu.idleCycles 2275615 # Total number of cycles that the CPU has spent unscheduled due to idling

689system.cpu.commit.bw_lim_events 3383064 # number cycles where commit BW limit reached
690system.cpu.rob.rob_reads 405117651 # The number of ROB reads
691system.cpu.rob.rob_writes 511394543 # The number of ROB writes
692system.cpu.timesIdled 9924 # Number of times that the entire CPU went into an idle state and unscheduled itself
693system.cpu.idleCycles 2248164 # Total number of cycles that the CPU has spent unscheduled due to idling

694system.cpu.committedInsts 172303022 # Number of Instructions Simulated
695system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated

696system.cpu.cpi 0.999975 # CPI: Cycles Per Instruction
697system.cpu.cpi_total 0.999975 # CPI: Total CPI of All Threads
698system.cpu.ipc 1.000025 # IPC: Instructions Per Cycle
699system.cpu.ipc_total 1.000025 # IPC: Total IPC of All Threads
700system.cpu.int_regfile_reads 218762027 # number of integer regfile reads
701system.cpu.int_regfile_writes 114194444 # number of integer regfile writes
702system.cpu.fp_regfile_reads 2903946 # number of floating regfile reads
703system.cpu.fp_regfile_writes 2441681 # number of floating regfile writes
704system.cpu.cc_regfile_reads 708323214 # number of cc regfile reads
705system.cpu.cc_regfile_writes 229513810 # number of cc regfile writes
706system.cpu.misc_regfile_reads 57456345 # number of misc regfile reads

696system.cpu.cpi 0.998081 # CPI: Cycles Per Instruction
697system.cpu.cpi_total 0.998081 # CPI: Total CPI of All Threads
698system.cpu.ipc 1.001922 # IPC: Instructions Per Cycle
699system.cpu.ipc_total 1.001922 # IPC: Total IPC of All Threads
700system.cpu.int_regfile_reads 218599432 # number of integer regfile reads
701system.cpu.int_regfile_writes 114087616 # number of integer regfile writes
702system.cpu.fp_regfile_reads 2903991 # number of floating regfile reads
703system.cpu.fp_regfile_writes 2441715 # number of floating regfile writes
704system.cpu.cc_regfile_reads 707769294 # number of cc regfile reads
705system.cpu.cc_regfile_writes 229397390 # number of cc regfile writes
706system.cpu.misc_regfile_reads 57427586 # number of misc regfile reads

707system.cpu.misc_regfile_writes 820036 # number of misc regfile writes

708system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states
709system.cpu.dcache.tags.replacements 72586 # number of replacements
710system.cpu.dcache.tags.tagsinuse 511.401008 # Cycle average of tags in use
711system.cpu.dcache.tags.total_refs 41045518 # Total number of references to valid blocks.
712system.cpu.dcache.tags.sampled_refs 73098 # Sample count of references to valid blocks.
713system.cpu.dcache.tags.avg_refs 561.513557 # Average number of references to valid blocks.
714system.cpu.dcache.tags.warmup_cycle 555248500 # Cycle when the warmup percentage was hit.
715system.cpu.dcache.tags.occ_blocks::cpu.data 511.401008 # Average occupied blocks per requestor
716system.cpu.dcache.tags.occ_percent::cpu.data 0.998830 # Average percentage of cache occupancy
717system.cpu.dcache.tags.occ_percent::total 0.998830 # Average percentage of cache occupancy

708system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states
709system.cpu.dcache.tags.replacements 72391 # number of replacements
710system.cpu.dcache.tags.tagsinuse 511.400200 # Cycle average of tags in use
711system.cpu.dcache.tags.total_refs 40997604 # Total number of references to valid blocks.
712system.cpu.dcache.tags.sampled_refs 72903 # Sample count of references to valid blocks.
713system.cpu.dcache.tags.avg_refs 562.358257 # Average number of references to valid blocks.
714system.cpu.dcache.tags.warmup_cycle 554902500 # Cycle when the warmup percentage was hit.
715system.cpu.dcache.tags.occ_blocks::cpu.data 511.400200 # Average occupied blocks per requestor
716system.cpu.dcache.tags.occ_percent::cpu.data 0.998829 # Average percentage of cache occupancy
717system.cpu.dcache.tags.occ_percent::total 0.998829 # Average percentage of cache occupancy

718system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id

719system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
720system.cpu.dcache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id

719system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
720system.cpu.dcache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id

721system.cpu.dcache.tags.age_task_id_blocks_1024::2 230 # Occupied blocks per task id
722system.cpu.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id
723system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id
724system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id

725system.cpu.dcache.tags.tag_accesses 82389396 # Number of tag accesses
726system.cpu.dcache.tags.data_accesses 82389396 # Number of data accesses
727system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states
728system.cpu.dcache.ReadReq_hits::cpu.data 28659277 # number of ReadReq hits
729system.cpu.dcache.ReadReq_hits::total 28659277 # number of ReadReq hits
730system.cpu.dcache.WriteReq_hits::cpu.data 12341322 # number of WriteReq hits
731system.cpu.dcache.WriteReq_hits::total 12341322 # number of WriteReq hits
732system.cpu.dcache.SoftPFReq_hits::cpu.data 365 # number of SoftPFReq hits
733system.cpu.dcache.SoftPFReq_hits::total 365 # number of SoftPFReq hits
734system.cpu.dcache.LoadLockedReq_hits::cpu.data 22147 # number of LoadLockedReq hits
735system.cpu.dcache.LoadLockedReq_hits::total 22147 # number of LoadLockedReq hits

725system.cpu.dcache.tags.tag_accesses 82292817 # Number of tag accesses
726system.cpu.dcache.tags.data_accesses 82292817 # Number of data accesses
727system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states
728system.cpu.dcache.ReadReq_hits::cpu.data 28611296 # number of ReadReq hits
729system.cpu.dcache.ReadReq_hits::total 28611296 # number of ReadReq hits
730system.cpu.dcache.WriteReq_hits::cpu.data 12341384 # number of WriteReq hits
731system.cpu.dcache.WriteReq_hits::total 12341384 # number of WriteReq hits
732system.cpu.dcache.SoftPFReq_hits::cpu.data 362 # number of SoftPFReq hits
733system.cpu.dcache.SoftPFReq_hits::total 362 # number of SoftPFReq hits
734system.cpu.dcache.LoadLockedReq_hits::cpu.data 22154 # number of LoadLockedReq hits
735system.cpu.dcache.LoadLockedReq_hits::total 22154 # number of LoadLockedReq hits

736system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
737system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits

738system.cpu.dcache.demand_hits::cpu.data 41000599 # number of demand (read+write) hits
739system.cpu.dcache.demand_hits::total 41000599 # number of demand (read+write) hits
740system.cpu.dcache.overall_hits::cpu.data 41000964 # number of overall hits
741system.cpu.dcache.overall_hits::total 41000964 # number of overall hits
742system.cpu.dcache.ReadReq_misses::cpu.data 89290 # number of ReadReq misses
743system.cpu.dcache.ReadReq_misses::total 89290 # number of ReadReq misses
744system.cpu.dcache.WriteReq_misses::cpu.data 22965 # number of WriteReq misses
745system.cpu.dcache.WriteReq_misses::total 22965 # number of WriteReq misses
746system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses
747system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses
748system.cpu.dcache.LoadLockedReq_misses::cpu.data 260 # number of LoadLockedReq misses
749system.cpu.dcache.LoadLockedReq_misses::total 260 # number of LoadLockedReq misses
750system.cpu.dcache.demand_misses::cpu.data 112255 # number of demand (read+write) misses
751system.cpu.dcache.demand_misses::total 112255 # number of demand (read+write) misses
752system.cpu.dcache.overall_misses::cpu.data 112371 # number of overall misses
753system.cpu.dcache.overall_misses::total 112371 # number of overall misses
754system.cpu.dcache.ReadReq_miss_latency::cpu.data 1989594500 # number of ReadReq miss cycles
755system.cpu.dcache.ReadReq_miss_latency::total 1989594500 # number of ReadReq miss cycles
756system.cpu.dcache.WriteReq_miss_latency::cpu.data 244666499 # number of WriteReq miss cycles
757system.cpu.dcache.WriteReq_miss_latency::total 244666499 # number of WriteReq miss cycles
758system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2316500 # number of LoadLockedReq miss cycles
759system.cpu.dcache.LoadLockedReq_miss_latency::total 2316500 # number of LoadLockedReq miss cycles
760system.cpu.dcache.demand_miss_latency::cpu.data 2234260999 # number of demand (read+write) miss cycles
761system.cpu.dcache.demand_miss_latency::total 2234260999 # number of demand (read+write) miss cycles
762system.cpu.dcache.overall_miss_latency::cpu.data 2234260999 # number of overall miss cycles
763system.cpu.dcache.overall_miss_latency::total 2234260999 # number of overall miss cycles
764system.cpu.dcache.ReadReq_accesses::cpu.data 28748567 # number of ReadReq accesses(hits+misses)
765system.cpu.dcache.ReadReq_accesses::total 28748567 # number of ReadReq accesses(hits+misses)

738system.cpu.dcache.demand_hits::cpu.data 40952680 # number of demand (read+write) hits
739system.cpu.dcache.demand_hits::total 40952680 # number of demand (read+write) hits
740system.cpu.dcache.overall_hits::cpu.data 40953042 # number of overall hits
741system.cpu.dcache.overall_hits::total 40953042 # number of overall hits
742system.cpu.dcache.ReadReq_misses::cpu.data 89081 # number of ReadReq misses
743system.cpu.dcache.ReadReq_misses::total 89081 # number of ReadReq misses
744system.cpu.dcache.WriteReq_misses::cpu.data 22903 # number of WriteReq misses
745system.cpu.dcache.WriteReq_misses::total 22903 # number of WriteReq misses
746system.cpu.dcache.SoftPFReq_misses::cpu.data 117 # number of SoftPFReq misses
747system.cpu.dcache.SoftPFReq_misses::total 117 # number of SoftPFReq misses
748system.cpu.dcache.LoadLockedReq_misses::cpu.data 253 # number of LoadLockedReq misses
749system.cpu.dcache.LoadLockedReq_misses::total 253 # number of LoadLockedReq misses
750system.cpu.dcache.demand_misses::cpu.data 111984 # number of demand (read+write) misses
751system.cpu.dcache.demand_misses::total 111984 # number of demand (read+write) misses
752system.cpu.dcache.overall_misses::cpu.data 112101 # number of overall misses
753system.cpu.dcache.overall_misses::total 112101 # number of overall misses
754system.cpu.dcache.ReadReq_miss_latency::cpu.data 1981259500 # number of ReadReq miss cycles
755system.cpu.dcache.ReadReq_miss_latency::total 1981259500 # number of ReadReq miss cycles
756system.cpu.dcache.WriteReq_miss_latency::cpu.data 246570499 # number of WriteReq miss cycles
757system.cpu.dcache.WriteReq_miss_latency::total 246570499 # number of WriteReq miss cycles
758system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2257000 # number of LoadLockedReq miss cycles
759system.cpu.dcache.LoadLockedReq_miss_latency::total 2257000 # number of LoadLockedReq miss cycles
760system.cpu.dcache.demand_miss_latency::cpu.data 2227829999 # number of demand (read+write) miss cycles
761system.cpu.dcache.demand_miss_latency::total 2227829999 # number of demand (read+write) miss cycles
762system.cpu.dcache.overall_miss_latency::cpu.data 2227829999 # number of overall miss cycles
763system.cpu.dcache.overall_miss_latency::total 2227829999 # number of overall miss cycles
764system.cpu.dcache.ReadReq_accesses::cpu.data 28700377 # number of ReadReq accesses(hits+misses)
765system.cpu.dcache.ReadReq_accesses::total 28700377 # number of ReadReq accesses(hits+misses)

766system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
767system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)

768system.cpu.dcache.SoftPFReq_accesses::cpu.data 481 # number of SoftPFReq accesses(hits+misses)
769system.cpu.dcache.SoftPFReq_accesses::total 481 # number of SoftPFReq accesses(hits+misses)

768system.cpu.dcache.SoftPFReq_accesses::cpu.data 479 # number of SoftPFReq accesses(hits+misses)
769system.cpu.dcache.SoftPFReq_accesses::total 479 # number of SoftPFReq accesses(hits+misses)

770system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
771system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
772system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
773system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)

774system.cpu.dcache.demand_accesses::cpu.data 41112854 # number of demand (read+write) accesses
775system.cpu.dcache.demand_accesses::total 41112854 # number of demand (read+write) accesses
776system.cpu.dcache.overall_accesses::cpu.data 41113335 # number of overall (read+write) accesses
777system.cpu.dcache.overall_accesses::total 41113335 # number of overall (read+write) accesses
778system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003106 # miss rate for ReadReq accesses
779system.cpu.dcache.ReadReq_miss_rate::total 0.003106 # miss rate for ReadReq accesses
780system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001857 # miss rate for WriteReq accesses
781system.cpu.dcache.WriteReq_miss_rate::total 0.001857 # miss rate for WriteReq accesses
782system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.241164 # miss rate for SoftPFReq accesses
783system.cpu.dcache.SoftPFReq_miss_rate::total 0.241164 # miss rate for SoftPFReq accesses
784system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011604 # miss rate for LoadLockedReq accesses
785system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011604 # miss rate for LoadLockedReq accesses
786system.cpu.dcache.demand_miss_rate::cpu.data 0.002730 # miss rate for demand accesses
787system.cpu.dcache.demand_miss_rate::total 0.002730 # miss rate for demand accesses
788system.cpu.dcache.overall_miss_rate::cpu.data 0.002733 # miss rate for overall accesses
789system.cpu.dcache.overall_miss_rate::total 0.002733 # miss rate for overall accesses
790system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22282.388845 # average ReadReq miss latency
791system.cpu.dcache.ReadReq_avg_miss_latency::total 22282.388845 # average ReadReq miss latency
792system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10653.886305 # average WriteReq miss latency
793system.cpu.dcache.WriteReq_avg_miss_latency::total 10653.886305 # average WriteReq miss latency
794system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8909.615385 # average LoadLockedReq miss latency
795system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8909.615385 # average LoadLockedReq miss latency
796system.cpu.dcache.demand_avg_miss_latency::cpu.data 19903.443045 # average overall miss latency
797system.cpu.dcache.demand_avg_miss_latency::total 19903.443045 # average overall miss latency
798system.cpu.dcache.overall_avg_miss_latency::cpu.data 19882.896824 # average overall miss latency
799system.cpu.dcache.overall_avg_miss_latency::total 19882.896824 # average overall miss latency

774system.cpu.dcache.demand_accesses::cpu.data 41064664 # number of demand (read+write) accesses
775system.cpu.dcache.demand_accesses::total 41064664 # number of demand (read+write) accesses
776system.cpu.dcache.overall_accesses::cpu.data 41065143 # number of overall (read+write) accesses
777system.cpu.dcache.overall_accesses::total 41065143 # number of overall (read+write) accesses
778system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003104 # miss rate for ReadReq accesses
779system.cpu.dcache.ReadReq_miss_rate::total 0.003104 # miss rate for ReadReq accesses
780system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001852 # miss rate for WriteReq accesses
781system.cpu.dcache.WriteReq_miss_rate::total 0.001852 # miss rate for WriteReq accesses
782system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.244259 # miss rate for SoftPFReq accesses
783system.cpu.dcache.SoftPFReq_miss_rate::total 0.244259 # miss rate for SoftPFReq accesses
784system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011291 # miss rate for LoadLockedReq accesses
785system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011291 # miss rate for LoadLockedReq accesses
786system.cpu.dcache.demand_miss_rate::cpu.data 0.002727 # miss rate for demand accesses
787system.cpu.dcache.demand_miss_rate::total 0.002727 # miss rate for demand accesses
788system.cpu.dcache.overall_miss_rate::cpu.data 0.002730 # miss rate for overall accesses
789system.cpu.dcache.overall_miss_rate::total 0.002730 # miss rate for overall accesses
790system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22241.100796 # average ReadReq miss latency
791system.cpu.dcache.ReadReq_avg_miss_latency::total 22241.100796 # average ReadReq miss latency
792system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10765.860324 # average WriteReq miss latency
793system.cpu.dcache.WriteReq_avg_miss_latency::total 10765.860324 # average WriteReq miss latency
794system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8920.948617 # average LoadLockedReq miss latency
795system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8920.948617 # average LoadLockedReq miss latency
796system.cpu.dcache.demand_avg_miss_latency::cpu.data 19894.181303 # average overall miss latency
797system.cpu.dcache.demand_avg_miss_latency::total 19894.181303 # average overall miss latency
798system.cpu.dcache.overall_avg_miss_latency::cpu.data 19873.417713 # average overall miss latency
799system.cpu.dcache.overall_avg_miss_latency::total 19873.417713 # average overall miss latency

800system.cpu.dcache.blocked_cycles::no_mshrs 180 # number of cycles access was blocked

801system.cpu.dcache.blocked_cycles::no_targets 11152 # number of cycles access was blocked

801system.cpu.dcache.blocked_cycles::no_targets 11209 # number of cycles access was blocked

802system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked

803system.cpu.dcache.blocked::no_targets 864 # number of cycles access was blocked

803system.cpu.dcache.blocked::no_targets 865 # number of cycles access was blocked

804system.cpu.dcache.avg_blocked_cycles::no_mshrs 90 # average number of cycles each access was blocked

805system.cpu.dcache.avg_blocked_cycles::no_targets 12.907407 # average number of cycles each access was blocked
806system.cpu.dcache.writebacks::writebacks 72586 # number of writebacks
807system.cpu.dcache.writebacks::total 72586 # number of writebacks
808system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24872 # number of ReadReq MSHR hits
809system.cpu.dcache.ReadReq_mshr_hits::total 24872 # number of ReadReq MSHR hits
810system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14398 # number of WriteReq MSHR hits
811system.cpu.dcache.WriteReq_mshr_hits::total 14398 # number of WriteReq MSHR hits
812system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 260 # number of LoadLockedReq MSHR hits
813system.cpu.dcache.LoadLockedReq_mshr_hits::total 260 # number of LoadLockedReq MSHR hits
814system.cpu.dcache.demand_mshr_hits::cpu.data 39270 # number of demand (read+write) MSHR hits
815system.cpu.dcache.demand_mshr_hits::total 39270 # number of demand (read+write) MSHR hits
816system.cpu.dcache.overall_mshr_hits::cpu.data 39270 # number of overall MSHR hits
817system.cpu.dcache.overall_mshr_hits::total 39270 # number of overall MSHR hits
818system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64418 # number of ReadReq MSHR misses
819system.cpu.dcache.ReadReq_mshr_misses::total 64418 # number of ReadReq MSHR misses
820system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8567 # number of WriteReq MSHR misses
821system.cpu.dcache.WriteReq_mshr_misses::total 8567 # number of WriteReq MSHR misses
822system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 113 # number of SoftPFReq MSHR misses
823system.cpu.dcache.SoftPFReq_mshr_misses::total 113 # number of SoftPFReq MSHR misses
824system.cpu.dcache.demand_mshr_misses::cpu.data 72985 # number of demand (read+write) MSHR misses
825system.cpu.dcache.demand_mshr_misses::total 72985 # number of demand (read+write) MSHR misses
826system.cpu.dcache.overall_mshr_misses::cpu.data 73098 # number of overall MSHR misses
827system.cpu.dcache.overall_mshr_misses::total 73098 # number of overall MSHR misses
828system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1060539500 # number of ReadReq MSHR miss cycles
829system.cpu.dcache.ReadReq_mshr_miss_latency::total 1060539500 # number of ReadReq MSHR miss cycles
830system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 87795999 # number of WriteReq MSHR miss cycles
831system.cpu.dcache.WriteReq_mshr_miss_latency::total 87795999 # number of WriteReq MSHR miss cycles
832system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 969000 # number of SoftPFReq MSHR miss cycles
833system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 969000 # number of SoftPFReq MSHR miss cycles
834system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1148335499 # number of demand (read+write) MSHR miss cycles
835system.cpu.dcache.demand_mshr_miss_latency::total 1148335499 # number of demand (read+write) MSHR miss cycles
836system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1149304499 # number of overall MSHR miss cycles
837system.cpu.dcache.overall_mshr_miss_latency::total 1149304499 # number of overall MSHR miss cycles
838system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002241 # mshr miss rate for ReadReq accesses
839system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002241 # mshr miss rate for ReadReq accesses
840system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000693 # mshr miss rate for WriteReq accesses
841system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000693 # mshr miss rate for WriteReq accesses
842system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.234927 # mshr miss rate for SoftPFReq accesses
843system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.234927 # mshr miss rate for SoftPFReq accesses
844system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001775 # mshr miss rate for demand accesses
845system.cpu.dcache.demand_mshr_miss_rate::total 0.001775 # mshr miss rate for demand accesses
846system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001778 # mshr miss rate for overall accesses
847system.cpu.dcache.overall_mshr_miss_rate::total 0.001778 # mshr miss rate for overall accesses
848system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16463.403086 # average ReadReq mshr miss latency
849system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16463.403086 # average ReadReq mshr miss latency
850system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10248.161433 # average WriteReq mshr miss latency
851system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10248.161433 # average WriteReq mshr miss latency
852system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8575.221239 # average SoftPFReq mshr miss latency
853system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8575.221239 # average SoftPFReq mshr miss latency
854system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15733.856258 # average overall mshr miss latency
855system.cpu.dcache.demand_avg_mshr_miss_latency::total 15733.856258 # average overall mshr miss latency
856system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15722.789940 # average overall mshr miss latency
857system.cpu.dcache.overall_avg_mshr_miss_latency::total 15722.789940 # average overall mshr miss latency
858system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states
859system.cpu.icache.tags.replacements 53582 # number of replacements
860system.cpu.icache.tags.tagsinuse 510.578561 # Cycle average of tags in use
861system.cpu.icache.tags.total_refs 78288973 # Total number of references to valid blocks.
862system.cpu.icache.tags.sampled_refs 54094 # Sample count of references to valid blocks.
863system.cpu.icache.tags.avg_refs 1447.276463 # Average number of references to valid blocks.
864system.cpu.icache.tags.warmup_cycle 85378568500 # Cycle when the warmup percentage was hit.
865system.cpu.icache.tags.occ_blocks::cpu.inst 510.578561 # Average occupied blocks per requestor
866system.cpu.icache.tags.occ_percent::cpu.inst 0.997224 # Average percentage of cache occupancy
867system.cpu.icache.tags.occ_percent::total 0.997224 # Average percentage of cache occupancy

805system.cpu.dcache.avg_blocked_cycles::no_targets 12.958382 # average number of cycles each access was blocked
806system.cpu.dcache.writebacks::writebacks 72391 # number of writebacks
807system.cpu.dcache.writebacks::total 72391 # number of writebacks
808system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24849 # number of ReadReq MSHR hits
809system.cpu.dcache.ReadReq_mshr_hits::total 24849 # number of ReadReq MSHR hits
810system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14345 # number of WriteReq MSHR hits
811system.cpu.dcache.WriteReq_mshr_hits::total 14345 # number of WriteReq MSHR hits
812system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 253 # number of LoadLockedReq MSHR hits
813system.cpu.dcache.LoadLockedReq_mshr_hits::total 253 # number of LoadLockedReq MSHR hits
814system.cpu.dcache.demand_mshr_hits::cpu.data 39194 # number of demand (read+write) MSHR hits
815system.cpu.dcache.demand_mshr_hits::total 39194 # number of demand (read+write) MSHR hits
816system.cpu.dcache.overall_mshr_hits::cpu.data 39194 # number of overall MSHR hits
817system.cpu.dcache.overall_mshr_hits::total 39194 # number of overall MSHR hits
818system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64232 # number of ReadReq MSHR misses
819system.cpu.dcache.ReadReq_mshr_misses::total 64232 # number of ReadReq MSHR misses
820system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8558 # number of WriteReq MSHR misses
821system.cpu.dcache.WriteReq_mshr_misses::total 8558 # number of WriteReq MSHR misses
822system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 114 # number of SoftPFReq MSHR misses
823system.cpu.dcache.SoftPFReq_mshr_misses::total 114 # number of SoftPFReq MSHR misses
824system.cpu.dcache.demand_mshr_misses::cpu.data 72790 # number of demand (read+write) MSHR misses
825system.cpu.dcache.demand_mshr_misses::total 72790 # number of demand (read+write) MSHR misses
826system.cpu.dcache.overall_mshr_misses::cpu.data 72904 # number of overall MSHR misses
827system.cpu.dcache.overall_mshr_misses::total 72904 # number of overall MSHR misses
828system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1056234000 # number of ReadReq MSHR miss cycles
829system.cpu.dcache.ReadReq_mshr_miss_latency::total 1056234000 # number of ReadReq MSHR miss cycles
830system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 88380499 # number of WriteReq MSHR miss cycles
831system.cpu.dcache.WriteReq_mshr_miss_latency::total 88380499 # number of WriteReq MSHR miss cycles
832system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 977000 # number of SoftPFReq MSHR miss cycles
833system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 977000 # number of SoftPFReq MSHR miss cycles
834system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1144614499 # number of demand (read+write) MSHR miss cycles
835system.cpu.dcache.demand_mshr_miss_latency::total 1144614499 # number of demand (read+write) MSHR miss cycles
836system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1145591499 # number of overall MSHR miss cycles
837system.cpu.dcache.overall_mshr_miss_latency::total 1145591499 # number of overall MSHR miss cycles
838system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002238 # mshr miss rate for ReadReq accesses
839system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002238 # mshr miss rate for ReadReq accesses
840system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses
841system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000692 # mshr miss rate for WriteReq accesses
842system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.237996 # mshr miss rate for SoftPFReq accesses
843system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.237996 # mshr miss rate for SoftPFReq accesses
844system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001773 # mshr miss rate for demand accesses
845system.cpu.dcache.demand_mshr_miss_rate::total 0.001773 # mshr miss rate for demand accesses
846system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001775 # mshr miss rate for overall accesses
847system.cpu.dcache.overall_mshr_miss_rate::total 0.001775 # mshr miss rate for overall accesses
848system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16444.046581 # average ReadReq mshr miss latency
849system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16444.046581 # average ReadReq mshr miss latency
850system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10327.237556 # average WriteReq mshr miss latency
851system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10327.237556 # average WriteReq mshr miss latency
852system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8570.175439 # average SoftPFReq mshr miss latency
853system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8570.175439 # average SoftPFReq mshr miss latency
854system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15724.886647 # average overall mshr miss latency
855system.cpu.dcache.demand_avg_mshr_miss_latency::total 15724.886647 # average overall mshr miss latency
856system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15713.698823 # average overall mshr miss latency
857system.cpu.dcache.overall_avg_mshr_miss_latency::total 15713.698823 # average overall mshr miss latency
858system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states
859system.cpu.icache.tags.replacements 53106 # number of replacements
860system.cpu.icache.tags.tagsinuse 510.578015 # Cycle average of tags in use
861system.cpu.icache.tags.total_refs 78094905 # Total number of references to valid blocks.
862system.cpu.icache.tags.sampled_refs 53618 # Sample count of references to valid blocks.
863system.cpu.icache.tags.avg_refs 1456.505371 # Average number of references to valid blocks.
864system.cpu.icache.tags.warmup_cycle 85215430500 # Cycle when the warmup percentage was hit.
865system.cpu.icache.tags.occ_blocks::cpu.inst 510.578015 # Average occupied blocks per requestor
866system.cpu.icache.tags.occ_percent::cpu.inst 0.997223 # Average percentage of cache occupancy
867system.cpu.icache.tags.occ_percent::total 0.997223 # Average percentage of cache occupancy

868system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id

869system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id
870system.cpu.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id

869system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id
870system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id

871system.cpu.icache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id
872system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
873system.cpu.icache.tags.age_task_id_blocks_1024::4 49 # Occupied blocks per task id
874system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id

875system.cpu.icache.tags.tag_accesses 156747350 # Number of tag accesses
876system.cpu.icache.tags.data_accesses 156747350 # Number of data accesses
877system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states
878system.cpu.icache.ReadReq_hits::cpu.inst 78288973 # number of ReadReq hits
879system.cpu.icache.ReadReq_hits::total 78288973 # number of ReadReq hits
880system.cpu.icache.demand_hits::cpu.inst 78288973 # number of demand (read+write) hits
881system.cpu.icache.demand_hits::total 78288973 # number of demand (read+write) hits
882system.cpu.icache.overall_hits::cpu.inst 78288973 # number of overall hits
883system.cpu.icache.overall_hits::total 78288973 # number of overall hits
884system.cpu.icache.ReadReq_misses::cpu.inst 57655 # number of ReadReq misses
885system.cpu.icache.ReadReq_misses::total 57655 # number of ReadReq misses
886system.cpu.icache.demand_misses::cpu.inst 57655 # number of demand (read+write) misses
887system.cpu.icache.demand_misses::total 57655 # number of demand (read+write) misses
888system.cpu.icache.overall_misses::cpu.inst 57655 # number of overall misses
889system.cpu.icache.overall_misses::total 57655 # number of overall misses
890system.cpu.icache.ReadReq_miss_latency::cpu.inst 2247853926 # number of ReadReq miss cycles
891system.cpu.icache.ReadReq_miss_latency::total 2247853926 # number of ReadReq miss cycles
892system.cpu.icache.demand_miss_latency::cpu.inst 2247853926 # number of demand (read+write) miss cycles
893system.cpu.icache.demand_miss_latency::total 2247853926 # number of demand (read+write) miss cycles
894system.cpu.icache.overall_miss_latency::cpu.inst 2247853926 # number of overall miss cycles
895system.cpu.icache.overall_miss_latency::total 2247853926 # number of overall miss cycles
896system.cpu.icache.ReadReq_accesses::cpu.inst 78346628 # number of ReadReq accesses(hits+misses)
897system.cpu.icache.ReadReq_accesses::total 78346628 # number of ReadReq accesses(hits+misses)
898system.cpu.icache.demand_accesses::cpu.inst 78346628 # number of demand (read+write) accesses
899system.cpu.icache.demand_accesses::total 78346628 # number of demand (read+write) accesses
900system.cpu.icache.overall_accesses::cpu.inst 78346628 # number of overall (read+write) accesses
901system.cpu.icache.overall_accesses::total 78346628 # number of overall (read+write) accesses
902system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000736 # miss rate for ReadReq accesses
903system.cpu.icache.ReadReq_miss_rate::total 0.000736 # miss rate for ReadReq accesses
904system.cpu.icache.demand_miss_rate::cpu.inst 0.000736 # miss rate for demand accesses
905system.cpu.icache.demand_miss_rate::total 0.000736 # miss rate for demand accesses
906system.cpu.icache.overall_miss_rate::cpu.inst 0.000736 # miss rate for overall accesses
907system.cpu.icache.overall_miss_rate::total 0.000736 # miss rate for overall accesses
908system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38988.013633 # average ReadReq miss latency
909system.cpu.icache.ReadReq_avg_miss_latency::total 38988.013633 # average ReadReq miss latency
910system.cpu.icache.demand_avg_miss_latency::cpu.inst 38988.013633 # average overall miss latency
911system.cpu.icache.demand_avg_miss_latency::total 38988.013633 # average overall miss latency
912system.cpu.icache.overall_avg_miss_latency::cpu.inst 38988.013633 # average overall miss latency
913system.cpu.icache.overall_avg_miss_latency::total 38988.013633 # average overall miss latency
914system.cpu.icache.blocked_cycles::no_mshrs 94468 # number of cycles access was blocked
915system.cpu.icache.blocked_cycles::no_targets 55 # number of cycles access was blocked
916system.cpu.icache.blocked::no_mshrs 3203 # number of cycles access was blocked
917system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
918system.cpu.icache.avg_blocked_cycles::no_mshrs 29.493600 # average number of cycles each access was blocked
919system.cpu.icache.avg_blocked_cycles::no_targets 27.500000 # average number of cycles each access was blocked
920system.cpu.icache.writebacks::writebacks 53582 # number of writebacks
921system.cpu.icache.writebacks::total 53582 # number of writebacks
922system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3560 # number of ReadReq MSHR hits
923system.cpu.icache.ReadReq_mshr_hits::total 3560 # number of ReadReq MSHR hits
924system.cpu.icache.demand_mshr_hits::cpu.inst 3560 # number of demand (read+write) MSHR hits
925system.cpu.icache.demand_mshr_hits::total 3560 # number of demand (read+write) MSHR hits
926system.cpu.icache.overall_mshr_hits::cpu.inst 3560 # number of overall MSHR hits
927system.cpu.icache.overall_mshr_hits::total 3560 # number of overall MSHR hits
928system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54095 # number of ReadReq MSHR misses
929system.cpu.icache.ReadReq_mshr_misses::total 54095 # number of ReadReq MSHR misses
930system.cpu.icache.demand_mshr_misses::cpu.inst 54095 # number of demand (read+write) MSHR misses
931system.cpu.icache.demand_mshr_misses::total 54095 # number of demand (read+write) MSHR misses
932system.cpu.icache.overall_mshr_misses::cpu.inst 54095 # number of overall MSHR misses
933system.cpu.icache.overall_mshr_misses::total 54095 # number of overall MSHR misses
934system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2052751452 # number of ReadReq MSHR miss cycles
935system.cpu.icache.ReadReq_mshr_miss_latency::total 2052751452 # number of ReadReq MSHR miss cycles
936system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2052751452 # number of demand (read+write) MSHR miss cycles
937system.cpu.icache.demand_mshr_miss_latency::total 2052751452 # number of demand (read+write) MSHR miss cycles
938system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2052751452 # number of overall MSHR miss cycles
939system.cpu.icache.overall_mshr_miss_latency::total 2052751452 # number of overall MSHR miss cycles
940system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000690 # mshr miss rate for ReadReq accesses
941system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000690 # mshr miss rate for ReadReq accesses
942system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000690 # mshr miss rate for demand accesses
943system.cpu.icache.demand_mshr_miss_rate::total 0.000690 # mshr miss rate for demand accesses
944system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000690 # mshr miss rate for overall accesses
945system.cpu.icache.overall_mshr_miss_rate::total 0.000690 # mshr miss rate for overall accesses
946system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37947.156891 # average ReadReq mshr miss latency
947system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37947.156891 # average ReadReq mshr miss latency
948system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37947.156891 # average overall mshr miss latency
949system.cpu.icache.demand_avg_mshr_miss_latency::total 37947.156891 # average overall mshr miss latency
950system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37947.156891 # average overall mshr miss latency
951system.cpu.icache.overall_avg_mshr_miss_latency::total 37947.156891 # average overall mshr miss latency
952system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states
953system.cpu.l2cache.prefetcher.num_hwpf_issued 9257 # number of hwpf issued
954system.cpu.l2cache.prefetcher.pfIdentified 9257 # number of prefetch candidates identified

875system.cpu.icache.tags.tag_accesses 156357779 # Number of tag accesses
876system.cpu.icache.tags.data_accesses 156357779 # Number of data accesses
877system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states
878system.cpu.icache.ReadReq_hits::cpu.inst 78094905 # number of ReadReq hits
879system.cpu.icache.ReadReq_hits::total 78094905 # number of ReadReq hits
880system.cpu.icache.demand_hits::cpu.inst 78094905 # number of demand (read+write) hits
881system.cpu.icache.demand_hits::total 78094905 # number of demand (read+write) hits
882system.cpu.icache.overall_hits::cpu.inst 78094905 # number of overall hits
883system.cpu.icache.overall_hits::total 78094905 # number of overall hits
884system.cpu.icache.ReadReq_misses::cpu.inst 57175 # number of ReadReq misses
885system.cpu.icache.ReadReq_misses::total 57175 # number of ReadReq misses
886system.cpu.icache.demand_misses::cpu.inst 57175 # number of demand (read+write) misses
887system.cpu.icache.demand_misses::total 57175 # number of demand (read+write) misses
888system.cpu.icache.overall_misses::cpu.inst 57175 # number of overall misses
889system.cpu.icache.overall_misses::total 57175 # number of overall misses
890system.cpu.icache.ReadReq_miss_latency::cpu.inst 2239186435 # number of ReadReq miss cycles
891system.cpu.icache.ReadReq_miss_latency::total 2239186435 # number of ReadReq miss cycles
892system.cpu.icache.demand_miss_latency::cpu.inst 2239186435 # number of demand (read+write) miss cycles
893system.cpu.icache.demand_miss_latency::total 2239186435 # number of demand (read+write) miss cycles
894system.cpu.icache.overall_miss_latency::cpu.inst 2239186435 # number of overall miss cycles
895system.cpu.icache.overall_miss_latency::total 2239186435 # number of overall miss cycles
896system.cpu.icache.ReadReq_accesses::cpu.inst 78152080 # number of ReadReq accesses(hits+misses)
897system.cpu.icache.ReadReq_accesses::total 78152080 # number of ReadReq accesses(hits+misses)
898system.cpu.icache.demand_accesses::cpu.inst 78152080 # number of demand (read+write) accesses
899system.cpu.icache.demand_accesses::total 78152080 # number of demand (read+write) accesses
900system.cpu.icache.overall_accesses::cpu.inst 78152080 # number of overall (read+write) accesses
901system.cpu.icache.overall_accesses::total 78152080 # number of overall (read+write) accesses
902system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000732 # miss rate for ReadReq accesses
903system.cpu.icache.ReadReq_miss_rate::total 0.000732 # miss rate for ReadReq accesses
904system.cpu.icache.demand_miss_rate::cpu.inst 0.000732 # miss rate for demand accesses
905system.cpu.icache.demand_miss_rate::total 0.000732 # miss rate for demand accesses
906system.cpu.icache.overall_miss_rate::cpu.inst 0.000732 # miss rate for overall accesses
907system.cpu.icache.overall_miss_rate::total 0.000732 # miss rate for overall accesses
908system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39163.733013 # average ReadReq miss latency
909system.cpu.icache.ReadReq_avg_miss_latency::total 39163.733013 # average ReadReq miss latency
910system.cpu.icache.demand_avg_miss_latency::cpu.inst 39163.733013 # average overall miss latency
911system.cpu.icache.demand_avg_miss_latency::total 39163.733013 # average overall miss latency
912system.cpu.icache.overall_avg_miss_latency::cpu.inst 39163.733013 # average overall miss latency
913system.cpu.icache.overall_avg_miss_latency::total 39163.733013 # average overall miss latency
914system.cpu.icache.blocked_cycles::no_mshrs 91615 # number of cycles access was blocked
915system.cpu.icache.blocked_cycles::no_targets 88 # number of cycles access was blocked
916system.cpu.icache.blocked::no_mshrs 3140 # number of cycles access was blocked
917system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
918system.cpu.icache.avg_blocked_cycles::no_mshrs 29.176752 # average number of cycles each access was blocked
919system.cpu.icache.avg_blocked_cycles::no_targets 29.333333 # average number of cycles each access was blocked
920system.cpu.icache.writebacks::writebacks 53106 # number of writebacks
921system.cpu.icache.writebacks::total 53106 # number of writebacks
922system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3554 # number of ReadReq MSHR hits
923system.cpu.icache.ReadReq_mshr_hits::total 3554 # number of ReadReq MSHR hits
924system.cpu.icache.demand_mshr_hits::cpu.inst 3554 # number of demand (read+write) MSHR hits
925system.cpu.icache.demand_mshr_hits::total 3554 # number of demand (read+write) MSHR hits
926system.cpu.icache.overall_mshr_hits::cpu.inst 3554 # number of overall MSHR hits
927system.cpu.icache.overall_mshr_hits::total 3554 # number of overall MSHR hits
928system.cpu.icache.ReadReq_mshr_misses::cpu.inst 53621 # number of ReadReq MSHR misses
929system.cpu.icache.ReadReq_mshr_misses::total 53621 # number of ReadReq MSHR misses
930system.cpu.icache.demand_mshr_misses::cpu.inst 53621 # number of demand (read+write) MSHR misses
931system.cpu.icache.demand_mshr_misses::total 53621 # number of demand (read+write) MSHR misses
932system.cpu.icache.overall_mshr_misses::cpu.inst 53621 # number of overall MSHR misses
933system.cpu.icache.overall_mshr_misses::total 53621 # number of overall MSHR misses
934system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2047106952 # number of ReadReq MSHR miss cycles
935system.cpu.icache.ReadReq_mshr_miss_latency::total 2047106952 # number of ReadReq MSHR miss cycles
936system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2047106952 # number of demand (read+write) MSHR miss cycles
937system.cpu.icache.demand_mshr_miss_latency::total 2047106952 # number of demand (read+write) MSHR miss cycles
938system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2047106952 # number of overall MSHR miss cycles
939system.cpu.icache.overall_mshr_miss_latency::total 2047106952 # number of overall MSHR miss cycles
940system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for ReadReq accesses
941system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000686 # mshr miss rate for ReadReq accesses
942system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for demand accesses
943system.cpu.icache.demand_mshr_miss_rate::total 0.000686 # mshr miss rate for demand accesses
944system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for overall accesses
945system.cpu.icache.overall_mshr_miss_rate::total 0.000686 # mshr miss rate for overall accesses
946system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38177.336342 # average ReadReq mshr miss latency
947system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38177.336342 # average ReadReq mshr miss latency
948system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38177.336342 # average overall mshr miss latency
949system.cpu.icache.demand_avg_mshr_miss_latency::total 38177.336342 # average overall mshr miss latency
950system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38177.336342 # average overall mshr miss latency
951system.cpu.icache.overall_avg_mshr_miss_latency::total 38177.336342 # average overall mshr miss latency
952system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states
953system.cpu.l2cache.prefetcher.num_hwpf_issued 9132 # number of hwpf issued
954system.cpu.l2cache.prefetcher.pfIdentified 9132 # number of prefetch candidates identified

955system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
956system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
957system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size

958system.cpu.l2cache.prefetcher.pfSpanPage 1327 # number of prefetches not generated due to page crossing
959system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states

958system.cpu.l2cache.prefetcher.pfSpanPage 1308 # number of prefetches not generated due to page crossing
959system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states

960system.cpu.l2cache.tags.replacements 0 # number of replacements

961system.cpu.l2cache.tags.tagsinuse 1809.107747 # Cycle average of tags in use
962system.cpu.l2cache.tags.total_refs 98955 # Total number of references to valid blocks.
963system.cpu.l2cache.tags.sampled_refs 2836 # Sample count of references to valid blocks.
964system.cpu.l2cache.tags.avg_refs 34.892454 # Average number of references to valid blocks.

961system.cpu.l2cache.tags.tagsinuse 1811.625085 # Cycle average of tags in use
962system.cpu.l2cache.tags.total_refs 98153 # Total number of references to valid blocks.
963system.cpu.l2cache.tags.sampled_refs 2844 # Sample count of references to valid blocks.
964system.cpu.l2cache.tags.avg_refs 34.512307 # Average number of references to valid blocks.

965system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

966system.cpu.l2cache.tags.occ_blocks::writebacks 1727.095683 # Average occupied blocks per requestor
967system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 82.012064 # Average occupied blocks per requestor
968system.cpu.l2cache.tags.occ_percent::writebacks 0.105414 # Average percentage of cache occupancy
969system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.005006 # Average percentage of cache occupancy
970system.cpu.l2cache.tags.occ_percent::total 0.110419 # Average percentage of cache occupancy
971system.cpu.l2cache.tags.occ_task_id_blocks::1022 131 # Occupied blocks per task id
972system.cpu.l2cache.tags.occ_task_id_blocks::1024 2705 # Occupied blocks per task id
973system.cpu.l2cache.tags.age_task_id_blocks_1022::1 19 # Occupied blocks per task id

966system.cpu.l2cache.tags.occ_blocks::writebacks 1727.578627 # Average occupied blocks per requestor
967system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 84.046457 # Average occupied blocks per requestor
968system.cpu.l2cache.tags.occ_percent::writebacks 0.105443 # Average percentage of cache occupancy
969system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.005130 # Average percentage of cache occupancy
970system.cpu.l2cache.tags.occ_percent::total 0.110573 # Average percentage of cache occupancy
971system.cpu.l2cache.tags.occ_task_id_blocks::1022 138 # Occupied blocks per task id
972system.cpu.l2cache.tags.occ_task_id_blocks::1024 2706 # Occupied blocks per task id
973system.cpu.l2cache.tags.age_task_id_blocks_1022::1 15 # Occupied blocks per task id

974system.cpu.l2cache.tags.age_task_id_blocks_1022::2 46 # Occupied blocks per task id

975system.cpu.l2cache.tags.age_task_id_blocks_1022::4 66 # Occupied blocks per task id
976system.cpu.l2cache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id

975system.cpu.l2cache.tags.age_task_id_blocks_1022::4 77 # Occupied blocks per task id
976system.cpu.l2cache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id

977system.cpu.l2cache.tags.age_task_id_blocks_1024::1 283 # Occupied blocks per task id

978system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1127 # Occupied blocks per task id
979system.cpu.l2cache.tags.age_task_id_blocks_1024::3 198 # Occupied blocks per task id
980system.cpu.l2cache.tags.age_task_id_blocks_1024::4 958 # Occupied blocks per task id
981system.cpu.l2cache.tags.occ_task_id_percent::1022 0.007996 # Percentage of cache occupancy per task id
982system.cpu.l2cache.tags.occ_task_id_percent::1024 0.165100 # Percentage of cache occupancy per task id
983system.cpu.l2cache.tags.tag_accesses 4002973 # Number of tag accesses
984system.cpu.l2cache.tags.data_accesses 4002973 # Number of data accesses
985system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states
986system.cpu.l2cache.WritebackDirty_hits::writebacks 64701 # number of WritebackDirty hits
987system.cpu.l2cache.WritebackDirty_hits::total 64701 # number of WritebackDirty hits
988system.cpu.l2cache.WritebackClean_hits::writebacks 50991 # number of WritebackClean hits
989system.cpu.l2cache.WritebackClean_hits::total 50991 # number of WritebackClean hits
990system.cpu.l2cache.ReadExReq_hits::cpu.data 8404 # number of ReadExReq hits
991system.cpu.l2cache.ReadExReq_hits::total 8404 # number of ReadExReq hits
992system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 43901 # number of ReadCleanReq hits
993system.cpu.l2cache.ReadCleanReq_hits::total 43901 # number of ReadCleanReq hits
994system.cpu.l2cache.ReadSharedReq_hits::cpu.data 61671 # number of ReadSharedReq hits
995system.cpu.l2cache.ReadSharedReq_hits::total 61671 # number of ReadSharedReq hits
996system.cpu.l2cache.demand_hits::cpu.inst 43901 # number of demand (read+write) hits
997system.cpu.l2cache.demand_hits::cpu.data 70075 # number of demand (read+write) hits
998system.cpu.l2cache.demand_hits::total 113976 # number of demand (read+write) hits
999system.cpu.l2cache.overall_hits::cpu.inst 43901 # number of overall hits
1000system.cpu.l2cache.overall_hits::cpu.data 70075 # number of overall hits
1001system.cpu.l2cache.overall_hits::total 113976 # number of overall hits
1002system.cpu.l2cache.ReadExReq_misses::cpu.data 230 # number of ReadExReq misses
1003system.cpu.l2cache.ReadExReq_misses::total 230 # number of ReadExReq misses
1004system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10194 # number of ReadCleanReq misses
1005system.cpu.l2cache.ReadCleanReq_misses::total 10194 # number of ReadCleanReq misses
1006system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2793 # number of ReadSharedReq misses
1007system.cpu.l2cache.ReadSharedReq_misses::total 2793 # number of ReadSharedReq misses
1008system.cpu.l2cache.demand_misses::cpu.inst 10194 # number of demand (read+write) misses
1009system.cpu.l2cache.demand_misses::cpu.data 3023 # number of demand (read+write) misses
1010system.cpu.l2cache.demand_misses::total 13217 # number of demand (read+write) misses
1011system.cpu.l2cache.overall_misses::cpu.inst 10194 # number of overall misses
1012system.cpu.l2cache.overall_misses::cpu.data 3023 # number of overall misses
1013system.cpu.l2cache.overall_misses::total 13217 # number of overall misses
1014system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 20353000 # number of ReadExReq miss cycles
1015system.cpu.l2cache.ReadExReq_miss_latency::total 20353000 # number of ReadExReq miss cycles
1016system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1710678000 # number of ReadCleanReq miss cycles
1017system.cpu.l2cache.ReadCleanReq_miss_latency::total 1710678000 # number of ReadCleanReq miss cycles
1018system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 556147500 # number of ReadSharedReq miss cycles
1019system.cpu.l2cache.ReadSharedReq_miss_latency::total 556147500 # number of ReadSharedReq miss cycles
1020system.cpu.l2cache.demand_miss_latency::cpu.inst 1710678000 # number of demand (read+write) miss cycles
1021system.cpu.l2cache.demand_miss_latency::cpu.data 576500500 # number of demand (read+write) miss cycles
1022system.cpu.l2cache.demand_miss_latency::total 2287178500 # number of demand (read+write) miss cycles
1023system.cpu.l2cache.overall_miss_latency::cpu.inst 1710678000 # number of overall miss cycles
1024system.cpu.l2cache.overall_miss_latency::cpu.data 576500500 # number of overall miss cycles
1025system.cpu.l2cache.overall_miss_latency::total 2287178500 # number of overall miss cycles
1026system.cpu.l2cache.WritebackDirty_accesses::writebacks 64701 # number of WritebackDirty accesses(hits+misses)
1027system.cpu.l2cache.WritebackDirty_accesses::total 64701 # number of WritebackDirty accesses(hits+misses)
1028system.cpu.l2cache.WritebackClean_accesses::writebacks 50991 # number of WritebackClean accesses(hits+misses)
1029system.cpu.l2cache.WritebackClean_accesses::total 50991 # number of WritebackClean accesses(hits+misses)
1030system.cpu.l2cache.ReadExReq_accesses::cpu.data 8634 # number of ReadExReq accesses(hits+misses)
1031system.cpu.l2cache.ReadExReq_accesses::total 8634 # number of ReadExReq accesses(hits+misses)
1032system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 54095 # number of ReadCleanReq accesses(hits+misses)
1033system.cpu.l2cache.ReadCleanReq_accesses::total 54095 # number of ReadCleanReq accesses(hits+misses)
1034system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64464 # number of ReadSharedReq accesses(hits+misses)
1035system.cpu.l2cache.ReadSharedReq_accesses::total 64464 # number of ReadSharedReq accesses(hits+misses)
1036system.cpu.l2cache.demand_accesses::cpu.inst 54095 # number of demand (read+write) accesses
1037system.cpu.l2cache.demand_accesses::cpu.data 73098 # number of demand (read+write) accesses
1038system.cpu.l2cache.demand_accesses::total 127193 # number of demand (read+write) accesses
1039system.cpu.l2cache.overall_accesses::cpu.inst 54095 # number of overall (read+write) accesses
1040system.cpu.l2cache.overall_accesses::cpu.data 73098 # number of overall (read+write) accesses
1041system.cpu.l2cache.overall_accesses::total 127193 # number of overall (read+write) accesses
1042system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.026639 # miss rate for ReadExReq accesses
1043system.cpu.l2cache.ReadExReq_miss_rate::total 0.026639 # miss rate for ReadExReq accesses
1044system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.188446 # miss rate for ReadCleanReq accesses
1045system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.188446 # miss rate for ReadCleanReq accesses
1046system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043327 # miss rate for ReadSharedReq accesses
1047system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043327 # miss rate for ReadSharedReq accesses
1048system.cpu.l2cache.demand_miss_rate::cpu.inst 0.188446 # miss rate for demand accesses
1049system.cpu.l2cache.demand_miss_rate::cpu.data 0.041355 # miss rate for demand accesses
1050system.cpu.l2cache.demand_miss_rate::total 0.103913 # miss rate for demand accesses
1051system.cpu.l2cache.overall_miss_rate::cpu.inst 0.188446 # miss rate for overall accesses
1052system.cpu.l2cache.overall_miss_rate::cpu.data 0.041355 # miss rate for overall accesses
1053system.cpu.l2cache.overall_miss_rate::total 0.103913 # miss rate for overall accesses
1054system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88491.304348 # average ReadExReq miss latency
1055system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88491.304348 # average ReadExReq miss latency
1056system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 167812.242496 # average ReadCleanReq miss latency
1057system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 167812.242496 # average ReadCleanReq miss latency
1058system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 199121.911923 # average ReadSharedReq miss latency
1059system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 199121.911923 # average ReadSharedReq miss latency
1060system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 167812.242496 # average overall miss latency
1061system.cpu.l2cache.demand_avg_miss_latency::cpu.data 190704.763480 # average overall miss latency
1062system.cpu.l2cache.demand_avg_miss_latency::total 173048.233336 # average overall miss latency
1063system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 167812.242496 # average overall miss latency
1064system.cpu.l2cache.overall_avg_miss_latency::cpu.data 190704.763480 # average overall miss latency
1065system.cpu.l2cache.overall_avg_miss_latency::total 173048.233336 # average overall miss latency

978system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1128 # Occupied blocks per task id
979system.cpu.l2cache.tags.age_task_id_blocks_1024::3 205 # Occupied blocks per task id
980system.cpu.l2cache.tags.age_task_id_blocks_1024::4 955 # Occupied blocks per task id
981system.cpu.l2cache.tags.occ_task_id_percent::1022 0.008423 # Percentage of cache occupancy per task id
982system.cpu.l2cache.tags.occ_task_id_percent::1024 0.165161 # Percentage of cache occupancy per task id
983system.cpu.l2cache.tags.tag_accesses 3980963 # Number of tag accesses
984system.cpu.l2cache.tags.data_accesses 3980963 # Number of data accesses
985system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states
986system.cpu.l2cache.WritebackDirty_hits::writebacks 64558 # number of WritebackDirty hits
987system.cpu.l2cache.WritebackDirty_hits::total 64558 # number of WritebackDirty hits
988system.cpu.l2cache.WritebackClean_hits::writebacks 50469 # number of WritebackClean hits
989system.cpu.l2cache.WritebackClean_hits::total 50469 # number of WritebackClean hits
990system.cpu.l2cache.ReadExReq_hits::cpu.data 8390 # number of ReadExReq hits
991system.cpu.l2cache.ReadExReq_hits::total 8390 # number of ReadExReq hits
992system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 43430 # number of ReadCleanReq hits
993system.cpu.l2cache.ReadCleanReq_hits::total 43430 # number of ReadCleanReq hits
994system.cpu.l2cache.ReadSharedReq_hits::cpu.data 61482 # number of ReadSharedReq hits
995system.cpu.l2cache.ReadSharedReq_hits::total 61482 # number of ReadSharedReq hits
996system.cpu.l2cache.demand_hits::cpu.inst 43430 # number of demand (read+write) hits
997system.cpu.l2cache.demand_hits::cpu.data 69872 # number of demand (read+write) hits
998system.cpu.l2cache.demand_hits::total 113302 # number of demand (read+write) hits
999system.cpu.l2cache.overall_hits::cpu.inst 43430 # number of overall hits
1000system.cpu.l2cache.overall_hits::cpu.data 69872 # number of overall hits
1001system.cpu.l2cache.overall_hits::total 113302 # number of overall hits
1002system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses
1003system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses
1004system.cpu.l2cache.ReadExReq_misses::cpu.data 236 # number of ReadExReq misses
1005system.cpu.l2cache.ReadExReq_misses::total 236 # number of ReadExReq misses
1006system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10190 # number of ReadCleanReq misses
1007system.cpu.l2cache.ReadCleanReq_misses::total 10190 # number of ReadCleanReq misses
1008system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2795 # number of ReadSharedReq misses
1009system.cpu.l2cache.ReadSharedReq_misses::total 2795 # number of ReadSharedReq misses
1010system.cpu.l2cache.demand_misses::cpu.inst 10190 # number of demand (read+write) misses
1011system.cpu.l2cache.demand_misses::cpu.data 3031 # number of demand (read+write) misses
1012system.cpu.l2cache.demand_misses::total 13221 # number of demand (read+write) misses
1013system.cpu.l2cache.overall_misses::cpu.inst 10190 # number of overall misses
1014system.cpu.l2cache.overall_misses::cpu.data 3031 # number of overall misses
1015system.cpu.l2cache.overall_misses::total 13221 # number of overall misses
1016system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 21033000 # number of ReadExReq miss cycles
1017system.cpu.l2cache.ReadExReq_miss_latency::total 21033000 # number of ReadExReq miss cycles
1018system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1708556000 # number of ReadCleanReq miss cycles
1019system.cpu.l2cache.ReadCleanReq_miss_latency::total 1708556000 # number of ReadCleanReq miss cycles
1020system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 553419500 # number of ReadSharedReq miss cycles
1021system.cpu.l2cache.ReadSharedReq_miss_latency::total 553419500 # number of ReadSharedReq miss cycles
1022system.cpu.l2cache.demand_miss_latency::cpu.inst 1708556000 # number of demand (read+write) miss cycles
1023system.cpu.l2cache.demand_miss_latency::cpu.data 574452500 # number of demand (read+write) miss cycles
1024system.cpu.l2cache.demand_miss_latency::total 2283008500 # number of demand (read+write) miss cycles
1025system.cpu.l2cache.overall_miss_latency::cpu.inst 1708556000 # number of overall miss cycles
1026system.cpu.l2cache.overall_miss_latency::cpu.data 574452500 # number of overall miss cycles
1027system.cpu.l2cache.overall_miss_latency::total 2283008500 # number of overall miss cycles
1028system.cpu.l2cache.WritebackDirty_accesses::writebacks 64558 # number of WritebackDirty accesses(hits+misses)
1029system.cpu.l2cache.WritebackDirty_accesses::total 64558 # number of WritebackDirty accesses(hits+misses)
1030system.cpu.l2cache.WritebackClean_accesses::writebacks 50469 # number of WritebackClean accesses(hits+misses)
1031system.cpu.l2cache.WritebackClean_accesses::total 50469 # number of WritebackClean accesses(hits+misses)
1032system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses)
1033system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses)
1034system.cpu.l2cache.ReadExReq_accesses::cpu.data 8626 # number of ReadExReq accesses(hits+misses)
1035system.cpu.l2cache.ReadExReq_accesses::total 8626 # number of ReadExReq accesses(hits+misses)
1036system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 53620 # number of ReadCleanReq accesses(hits+misses)
1037system.cpu.l2cache.ReadCleanReq_accesses::total 53620 # number of ReadCleanReq accesses(hits+misses)
1038system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64277 # number of ReadSharedReq accesses(hits+misses)
1039system.cpu.l2cache.ReadSharedReq_accesses::total 64277 # number of ReadSharedReq accesses(hits+misses)
1040system.cpu.l2cache.demand_accesses::cpu.inst 53620 # number of demand (read+write) accesses
1041system.cpu.l2cache.demand_accesses::cpu.data 72903 # number of demand (read+write) accesses
1042system.cpu.l2cache.demand_accesses::total 126523 # number of demand (read+write) accesses
1043system.cpu.l2cache.overall_accesses::cpu.inst 53620 # number of overall (read+write) accesses
1044system.cpu.l2cache.overall_accesses::cpu.data 72903 # number of overall (read+write) accesses
1045system.cpu.l2cache.overall_accesses::total 126523 # number of overall (read+write) accesses
1046system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
1047system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
1048system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.027359 # miss rate for ReadExReq accesses
1049system.cpu.l2cache.ReadExReq_miss_rate::total 0.027359 # miss rate for ReadExReq accesses
1050system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.190041 # miss rate for ReadCleanReq accesses
1051system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.190041 # miss rate for ReadCleanReq accesses
1052system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043484 # miss rate for ReadSharedReq accesses
1053system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043484 # miss rate for ReadSharedReq accesses
1054system.cpu.l2cache.demand_miss_rate::cpu.inst 0.190041 # miss rate for demand accesses
1055system.cpu.l2cache.demand_miss_rate::cpu.data 0.041576 # miss rate for demand accesses
1056system.cpu.l2cache.demand_miss_rate::total 0.104495 # miss rate for demand accesses
1057system.cpu.l2cache.overall_miss_rate::cpu.inst 0.190041 # miss rate for overall accesses
1058system.cpu.l2cache.overall_miss_rate::cpu.data 0.041576 # miss rate for overall accesses
1059system.cpu.l2cache.overall_miss_rate::total 0.104495 # miss rate for overall accesses
1060system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89122.881356 # average ReadExReq miss latency
1061system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89122.881356 # average ReadExReq miss latency
1062system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 167669.872424 # average ReadCleanReq miss latency
1063system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 167669.872424 # average ReadCleanReq miss latency
1064system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 198003.398927 # average ReadSharedReq miss latency
1065system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 198003.398927 # average ReadSharedReq miss latency
1066system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 167669.872424 # average overall miss latency
1067system.cpu.l2cache.demand_avg_miss_latency::cpu.data 189525.734081 # average overall miss latency
1068system.cpu.l2cache.demand_avg_miss_latency::total 172680.470464 # average overall miss latency
1069system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 167669.872424 # average overall miss latency
1070system.cpu.l2cache.overall_avg_miss_latency::cpu.data 189525.734081 # average overall miss latency
1071system.cpu.l2cache.overall_avg_miss_latency::total 172680.470464 # average overall miss latency

1066system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1067system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1068system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1069system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1070system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1071system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1072system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1 # number of ReadExReq MSHR hits
1073system.cpu.l2cache.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits
1074system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits
1075system.cpu.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits
1076system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 8 # number of ReadSharedReq MSHR hits
1077system.cpu.l2cache.ReadSharedReq_mshr_hits::total 8 # number of ReadSharedReq MSHR hits
1078system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
1079system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits
1080system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits
1081system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
1082system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits
1083system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits

1072system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1073system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1074system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1075system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1076system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1077system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1078system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1 # number of ReadExReq MSHR hits
1079system.cpu.l2cache.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits
1080system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits
1081system.cpu.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits
1082system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 8 # number of ReadSharedReq MSHR hits
1083system.cpu.l2cache.ReadSharedReq_mshr_hits::total 8 # number of ReadSharedReq MSHR hits
1084system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
1085system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits
1086system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits
1087system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
1088system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits
1089system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits

1084system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 2048 # number of HardPFReq MSHR misses
1085system.cpu.l2cache.HardPFReq_mshr_misses::total 2048 # number of HardPFReq MSHR misses
1086system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 229 # number of ReadExReq MSHR misses
1087system.cpu.l2cache.ReadExReq_mshr_misses::total 229 # number of ReadExReq MSHR misses
1088system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10189 # number of ReadCleanReq MSHR misses
1089system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10189 # number of ReadCleanReq MSHR misses
1090system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2785 # number of ReadSharedReq MSHR misses
1091system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2785 # number of ReadSharedReq MSHR misses
1092system.cpu.l2cache.demand_mshr_misses::cpu.inst 10189 # number of demand (read+write) MSHR misses
1093system.cpu.l2cache.demand_mshr_misses::cpu.data 3014 # number of demand (read+write) MSHR misses
1094system.cpu.l2cache.demand_mshr_misses::total 13203 # number of demand (read+write) MSHR misses
1095system.cpu.l2cache.overall_mshr_misses::cpu.inst 10189 # number of overall MSHR misses
1096system.cpu.l2cache.overall_mshr_misses::cpu.data 3014 # number of overall MSHR misses
1097system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 2048 # number of overall MSHR misses
1098system.cpu.l2cache.overall_mshr_misses::total 15251 # number of overall MSHR misses
1099system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 98123639 # number of HardPFReq MSHR miss cycles
1100system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 98123639 # number of HardPFReq MSHR miss cycles
1101system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 18771000 # number of ReadExReq MSHR miss cycles
1102system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 18771000 # number of ReadExReq MSHR miss cycles
1103system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1648684500 # number of ReadCleanReq MSHR miss cycles
1104system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1648684500 # number of ReadCleanReq MSHR miss cycles
1105system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 538898000 # number of ReadSharedReq MSHR miss cycles
1106system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 538898000 # number of ReadSharedReq MSHR miss cycles
1107system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1648684500 # number of demand (read+write) MSHR miss cycles
1108system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 557669000 # number of demand (read+write) MSHR miss cycles
1109system.cpu.l2cache.demand_mshr_miss_latency::total 2206353500 # number of demand (read+write) MSHR miss cycles
1110system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1648684500 # number of overall MSHR miss cycles
1111system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 557669000 # number of overall MSHR miss cycles
1112system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 98123639 # number of overall MSHR miss cycles
1113system.cpu.l2cache.overall_mshr_miss_latency::total 2304477139 # number of overall MSHR miss cycles

1090system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1986 # number of HardPFReq MSHR misses
1091system.cpu.l2cache.HardPFReq_mshr_misses::total 1986 # number of HardPFReq MSHR misses
1092system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses
1093system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses
1094system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 235 # number of ReadExReq MSHR misses
1095system.cpu.l2cache.ReadExReq_mshr_misses::total 235 # number of ReadExReq MSHR misses
1096system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10185 # number of ReadCleanReq MSHR misses
1097system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10185 # number of ReadCleanReq MSHR misses
1098system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2787 # number of ReadSharedReq MSHR misses
1099system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2787 # number of ReadSharedReq MSHR misses
1100system.cpu.l2cache.demand_mshr_misses::cpu.inst 10185 # number of demand (read+write) MSHR misses
1101system.cpu.l2cache.demand_mshr_misses::cpu.data 3022 # number of demand (read+write) MSHR misses
1102system.cpu.l2cache.demand_mshr_misses::total 13207 # number of demand (read+write) MSHR misses
1103system.cpu.l2cache.overall_mshr_misses::cpu.inst 10185 # number of overall MSHR misses
1104system.cpu.l2cache.overall_mshr_misses::cpu.data 3022 # number of overall MSHR misses
1105system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1986 # number of overall MSHR misses
1106system.cpu.l2cache.overall_mshr_misses::total 15193 # number of overall MSHR misses
1107system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 99174661 # number of HardPFReq MSHR miss cycles
1108system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 99174661 # number of HardPFReq MSHR miss cycles
1109system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 16000 # number of UpgradeReq MSHR miss cycles
1110system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 16000 # number of UpgradeReq MSHR miss cycles
1111system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 19399000 # number of ReadExReq MSHR miss cycles
1112system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 19399000 # number of ReadExReq MSHR miss cycles
1113system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1646592500 # number of ReadCleanReq MSHR miss cycles
1114system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1646592500 # number of ReadCleanReq MSHR miss cycles
1115system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 536158000 # number of ReadSharedReq MSHR miss cycles
1116system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 536158000 # number of ReadSharedReq MSHR miss cycles
1117system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1646592500 # number of demand (read+write) MSHR miss cycles
1118system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 555557000 # number of demand (read+write) MSHR miss cycles
1119system.cpu.l2cache.demand_mshr_miss_latency::total 2202149500 # number of demand (read+write) MSHR miss cycles
1120system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1646592500 # number of overall MSHR miss cycles
1121system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 555557000 # number of overall MSHR miss cycles
1122system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 99174661 # number of overall MSHR miss cycles
1123system.cpu.l2cache.overall_mshr_miss_latency::total 2301324161 # number of overall MSHR miss cycles

1114system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1115system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses

1124system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1125system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses

1116system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.026523 # mshr miss rate for ReadExReq accesses
1117system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.026523 # mshr miss rate for ReadExReq accesses
1118system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.188354 # mshr miss rate for ReadCleanReq accesses
1119system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.188354 # mshr miss rate for ReadCleanReq accesses
1120system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043202 # mshr miss rate for ReadSharedReq accesses
1121system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043202 # mshr miss rate for ReadSharedReq accesses
1122system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.188354 # mshr miss rate for demand accesses
1123system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.041232 # mshr miss rate for demand accesses
1124system.cpu.l2cache.demand_mshr_miss_rate::total 0.103803 # mshr miss rate for demand accesses
1125system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.188354 # mshr miss rate for overall accesses
1126system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.041232 # mshr miss rate for overall accesses

1126system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
1127system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
1128system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027243 # mshr miss rate for ReadExReq accesses
1129system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027243 # mshr miss rate for ReadExReq accesses
1130system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.189948 # mshr miss rate for ReadCleanReq accesses
1131system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.189948 # mshr miss rate for ReadCleanReq accesses
1132system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043359 # mshr miss rate for ReadSharedReq accesses
1133system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043359 # mshr miss rate for ReadSharedReq accesses
1134system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.189948 # mshr miss rate for demand accesses
1135system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.041452 # mshr miss rate for demand accesses
1136system.cpu.l2cache.demand_mshr_miss_rate::total 0.104384 # mshr miss rate for demand accesses
1137system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.189948 # mshr miss rate for overall accesses
1138system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.041452 # mshr miss rate for overall accesses

1127system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses

1139system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses

1128system.cpu.l2cache.overall_mshr_miss_rate::total 0.119904 # mshr miss rate for overall accesses
1129system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 47911.933105 # average HardPFReq mshr miss latency
1130system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 47911.933105 # average HardPFReq mshr miss latency
1131system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81969.432314 # average ReadExReq mshr miss latency
1132system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81969.432314 # average ReadExReq mshr miss latency
1133system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 161810.236530 # average ReadCleanReq mshr miss latency
1134system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 161810.236530 # average ReadCleanReq mshr miss latency
1135system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 193500.179533 # average ReadSharedReq mshr miss latency
1136system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 193500.179533 # average ReadSharedReq mshr miss latency
1137system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 161810.236530 # average overall mshr miss latency
1138system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185026.211015 # average overall mshr miss latency
1139system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167110.012876 # average overall mshr miss latency
1140system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 161810.236530 # average overall mshr miss latency
1141system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185026.211015 # average overall mshr miss latency
1142system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 47911.933105 # average overall mshr miss latency
1143system.cpu.l2cache.overall_avg_mshr_miss_latency::total 151103.346600 # average overall mshr miss latency
1144system.cpu.toL2Bus.snoop_filter.tot_requests 253361 # Total number of requests made to the snoop filter.
1145system.cpu.toL2Bus.snoop_filter.hit_single_requests 126188 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1146system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10476 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1147system.cpu.toL2Bus.snoop_filter.tot_snoops 927 # Total number of snoops made to the snoop filter.
1148system.cpu.toL2Bus.snoop_filter.hit_single_snoops 926 # Number of snoops hitting in the snoop filter with a single holder of the requested data.

1140system.cpu.l2cache.overall_mshr_miss_rate::total 0.120081 # mshr miss rate for overall accesses
1141system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 49936.888721 # average HardPFReq mshr miss latency
1142system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 49936.888721 # average HardPFReq mshr miss latency
1143system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16000 # average UpgradeReq mshr miss latency
1144system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16000 # average UpgradeReq mshr miss latency
1145system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82548.936170 # average ReadExReq mshr miss latency
1146system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82548.936170 # average ReadExReq mshr miss latency
1147system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 161668.384880 # average ReadCleanReq mshr miss latency
1148system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 161668.384880 # average ReadCleanReq mshr miss latency
1149system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 192378.184428 # average ReadSharedReq mshr miss latency
1150system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 192378.184428 # average ReadSharedReq mshr miss latency
1151system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 161668.384880 # average overall mshr miss latency
1152system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 183837.524818 # average overall mshr miss latency
1153system.cpu.l2cache.demand_avg_mshr_miss_latency::total 166741.084273 # average overall mshr miss latency
1154system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 161668.384880 # average overall mshr miss latency
1155system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 183837.524818 # average overall mshr miss latency
1156system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 49936.888721 # average overall mshr miss latency
1157system.cpu.l2cache.overall_avg_mshr_miss_latency::total 151472.662476 # average overall mshr miss latency
1158system.cpu.toL2Bus.snoop_filter.tot_requests 252022 # Total number of requests made to the snoop filter.
1159system.cpu.toL2Bus.snoop_filter.hit_single_requests 125518 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1160system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10474 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1161system.cpu.toL2Bus.snoop_filter.tot_snoops 866 # Total number of snoops made to the snoop filter.
1162system.cpu.toL2Bus.snoop_filter.hit_single_snoops 865 # Number of snoops hitting in the snoop filter with a single holder of the requested data.

1149system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

1163system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

1150system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states
1151system.cpu.toL2Bus.trans_dist::ReadResp 118558 # Transaction distribution
1152system.cpu.toL2Bus.trans_dist::WritebackDirty 64701 # Transaction distribution
1153system.cpu.toL2Bus.trans_dist::WritebackClean 61467 # Transaction distribution
1154system.cpu.toL2Bus.trans_dist::HardPFReq 2398 # Transaction distribution
1155system.cpu.toL2Bus.trans_dist::ReadExReq 8634 # Transaction distribution
1156system.cpu.toL2Bus.trans_dist::ReadExResp 8634 # Transaction distribution
1157system.cpu.toL2Bus.trans_dist::ReadCleanReq 54095 # Transaction distribution
1158system.cpu.toL2Bus.trans_dist::ReadSharedReq 64464 # Transaction distribution
1159system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161771 # Packet count per connected master and slave (bytes)
1160system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218782 # Packet count per connected master and slave (bytes)
1161system.cpu.toL2Bus.pkt_count::total 380553 # Packet count per connected master and slave (bytes)
1162system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6891264 # Cumulative packet size per connected master and slave (bytes)
1163system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9323776 # Cumulative packet size per connected master and slave (bytes)
1164system.cpu.toL2Bus.pkt_size::total 16215040 # Cumulative packet size per connected master and slave (bytes)
1165system.cpu.toL2Bus.snoops 2398 # Total snoops (count)
1166system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
1167system.cpu.toL2Bus.snoop_fanout::samples 129591 # Request fanout histogram
1168system.cpu.toL2Bus.snoop_fanout::mean 0.088154 # Request fanout histogram
1169system.cpu.toL2Bus.snoop_fanout::stdev 0.283547 # Request fanout histogram

1164system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states
1165system.cpu.toL2Bus.trans_dist::ReadResp 117896 # Transaction distribution
1166system.cpu.toL2Bus.trans_dist::WritebackDirty 64558 # Transaction distribution
1167system.cpu.toL2Bus.trans_dist::WritebackClean 60939 # Transaction distribution
1168system.cpu.toL2Bus.trans_dist::HardPFReq 2337 # Transaction distribution
1169system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution
1170system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution
1171system.cpu.toL2Bus.trans_dist::ReadExReq 8626 # Transaction distribution
1172system.cpu.toL2Bus.trans_dist::ReadExResp 8626 # Transaction distribution
1173system.cpu.toL2Bus.trans_dist::ReadCleanReq 53621 # Transaction distribution
1174system.cpu.toL2Bus.trans_dist::ReadSharedReq 64277 # Transaction distribution
1175system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 160345 # Packet count per connected master and slave (bytes)
1176system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218199 # Packet count per connected master and slave (bytes)
1177system.cpu.toL2Bus.pkt_count::total 378544 # Packet count per connected master and slave (bytes)
1178system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6830336 # Cumulative packet size per connected master and slave (bytes)
1179system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9298816 # Cumulative packet size per connected master and slave (bytes)
1180system.cpu.toL2Bus.pkt_size::total 16129152 # Cumulative packet size per connected master and slave (bytes)
1181system.cpu.toL2Bus.snoops 2338 # Total snoops (count)
1182system.cpu.toL2Bus.snoopTraffic 64 # Total snoop traffic (bytes)
1183system.cpu.toL2Bus.snoop_fanout::samples 128862 # Request fanout histogram
1184system.cpu.toL2Bus.snoop_fanout::mean 0.088172 # Request fanout histogram
1185system.cpu.toL2Bus.snoop_fanout::stdev 0.283573 # Request fanout histogram

1170system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

1186system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

1171system.cpu.toL2Bus.snoop_fanout::0 118168 91.19% 91.19% # Request fanout histogram
1172system.cpu.toL2Bus.snoop_fanout::1 11422 8.81% 100.00% # Request fanout histogram

1187system.cpu.toL2Bus.snoop_fanout::0 117501 91.18% 91.18% # Request fanout histogram
1188system.cpu.toL2Bus.snoop_fanout::1 11360 8.82% 100.00% # Request fanout histogram

1173system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram
1174system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1175system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1176system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram

1189system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram
1190system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1191system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1192system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram

1177system.cpu.toL2Bus.snoop_fanout::total 129591 # Request fanout histogram
1178system.cpu.toL2Bus.reqLayer0.occupancy 252848500 # Layer occupancy (ticks)

1193system.cpu.toL2Bus.snoop_fanout::total 128862 # Request fanout histogram
1194system.cpu.toL2Bus.reqLayer0.occupancy 251508000 # Layer occupancy (ticks)

1179system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)

1195system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)

1180system.cpu.toL2Bus.respLayer0.occupancy 81149483 # Layer occupancy (ticks)

1196system.cpu.toL2Bus.respLayer0.occupancy 80437981 # Layer occupancy (ticks)

1181system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)

1197system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)

1182system.cpu.toL2Bus.respLayer1.occupancy 109651491 # Layer occupancy (ticks)

1198system.cpu.toL2Bus.respLayer1.occupancy 109359491 # Layer occupancy (ticks)

1183system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)

1199system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)

1184system.membus.snoop_filter.tot_requests 14324 # Total number of requests made to the snoop filter.
1185system.membus.snoop_filter.hit_single_requests 10483 # Number of requests hitting in the snoop filter with a single holder of the requested data.

1200system.membus.snoop_filter.tot_requests 14328 # Total number of requests made to the snoop filter.
1201system.membus.snoop_filter.hit_single_requests 10478 # Number of requests hitting in the snoop filter with a single holder of the requested data.

1186system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1187system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1188system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1189system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

1202system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1203system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1204system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1205system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

1190system.membus.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states
1191system.membus.trans_dist::ReadResp 14094 # Transaction distribution
1192system.membus.trans_dist::ReadExReq 229 # Transaction distribution
1193system.membus.trans_dist::ReadExResp 229 # Transaction distribution
1194system.membus.trans_dist::ReadSharedReq 14095 # Transaction distribution
1195system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28647 # Packet count per connected master and slave (bytes)
1196system.membus.pkt_count::total 28647 # Packet count per connected master and slave (bytes)
1197system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 916672 # Cumulative packet size per connected master and slave (bytes)
1198system.membus.pkt_size::total 916672 # Cumulative packet size per connected master and slave (bytes)

1206system.membus.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states
1207system.membus.trans_dist::ReadResp 14090 # Transaction distribution
1208system.membus.trans_dist::UpgradeReq 1 # Transaction distribution
1209system.membus.trans_dist::ReadExReq 235 # Transaction distribution
1210system.membus.trans_dist::ReadExResp 235 # Transaction distribution
1211system.membus.trans_dist::ReadSharedReq 14092 # Transaction distribution
1212system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28653 # Packet count per connected master and slave (bytes)
1213system.membus.pkt_count::total 28653 # Packet count per connected master and slave (bytes)
1214system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 916800 # Cumulative packet size per connected master and slave (bytes)
1215system.membus.pkt_size::total 916800 # Cumulative packet size per connected master and slave (bytes)

1199system.membus.snoops 0 # Total snoops (count)
1200system.membus.snoopTraffic 0 # Total snoop traffic (bytes)

1216system.membus.snoops 0 # Total snoops (count)
1217system.membus.snoopTraffic 0 # Total snoop traffic (bytes)

1201system.membus.snoop_fanout::samples 14324 # Request fanout histogram

1218system.membus.snoop_fanout::samples 14328 # Request fanout histogram

1202system.membus.snoop_fanout::mean 0 # Request fanout histogram
1203system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1204system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

1219system.membus.snoop_fanout::mean 0 # Request fanout histogram
1220system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1221system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

1205system.membus.snoop_fanout::0 14324 100.00% 100.00% # Request fanout histogram

1222system.membus.snoop_fanout::0 14328 100.00% 100.00% # Request fanout histogram

1206system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1207system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1208system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1209system.membus.snoop_fanout::max_value 0 # Request fanout histogram

1223system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1224system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1225system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1226system.membus.snoop_fanout::max_value 0 # Request fanout histogram

1210system.membus.snoop_fanout::total 14324 # Request fanout histogram
1211system.membus.reqLayer0.occupancy 18004660 # Layer occupancy (ticks)

1227system.membus.snoop_fanout::total 14328 # Request fanout histogram
1228system.membus.reqLayer0.occupancy 18011178 # Layer occupancy (ticks)

1212system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)

1229system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)

1213system.membus.respLayer1.occupancy 77243027 # Layer occupancy (ticks)

1230system.membus.respLayer1.occupancy 77254535 # Layer occupancy (ticks)