| stats.txt (11606:6b749761c398) | stats.txt (11680:b4d943429dc6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.085052 # Number of seconds simulated 4sim_ticks 85051506000 # Number of ticks simulated 5final_tick 85051506000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.086053 # Number of seconds simulated 4sim_ticks 86053034000 # Number of ticks simulated 5final_tick 86053034000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 137318 # Simulator instruction rate (inst/s) 8host_op_rate 144756 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 67782320 # Simulator tick rate (ticks/s) 10host_mem_usage 272616 # Number of bytes of host memory used 11host_seconds 1254.77 # Real time elapsed on the host | 7host_inst_rate 114393 # Simulator instruction rate (inst/s) 8host_op_rate 120589 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 57131119 # Simulator tick rate (ticks/s) 10host_mem_usage 270696 # Number of bytes of host memory used 11host_seconds 1506.24 # Real time elapsed on the host |
| 12sim_insts 172303022 # Number of instructions simulated 13sim_ops 181635954 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 172303022 # Number of instructions simulated 13sim_ops 181635954 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 651584 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 192256 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.l2cache.prefetcher 71040 # Number of bytes read from this memory 20system.physmem.bytes_read::total 914880 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 651584 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 651584 # Number of instructions bytes read from this memory 23system.physmem.num_reads::cpu.inst 10181 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 3004 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.l2cache.prefetcher 1110 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 14295 # Number of read requests responded to by this memory 27system.physmem.bw_read::cpu.inst 7661052 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::cpu.data 2260466 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.l2cache.prefetcher 835259 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 10756776 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 7661052 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 7661052 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_total::cpu.inst 7661052 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.data 2260466 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.l2cache.prefetcher 835259 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 10756776 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 14295 # Number of read requests accepted | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 652224 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 193472 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.l2cache.prefetcher 70848 # Number of bytes read from this memory 20system.physmem.bytes_read::total 916544 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 652224 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 652224 # Number of instructions bytes read from this memory 23system.physmem.num_reads::cpu.inst 10191 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 3023 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.l2cache.prefetcher 1107 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 14321 # Number of read requests responded to by this memory 27system.physmem.bw_read::cpu.inst 7579326 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::cpu.data 2248288 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.l2cache.prefetcher 823306 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 10650920 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 7579326 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 7579326 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_total::cpu.inst 7579326 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.data 2248288 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.l2cache.prefetcher 823306 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 10650920 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 14321 # Number of read requests accepted |
| 38system.physmem.writeReqs 0 # Number of write requests accepted | 38system.physmem.writeReqs 0 # Number of write requests accepted |
| 39system.physmem.readBursts 14295 # Number of DRAM read bursts, including those serviced by the write queue | 39system.physmem.readBursts 14321 # Number of DRAM read bursts, including those serviced by the write queue |
| 40system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 40system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 41system.physmem.bytesReadDRAM 914880 # Total number of bytes read from DRAM | 41system.physmem.bytesReadDRAM 916544 # Total number of bytes read from DRAM |
| 42system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 43system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 42system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 43system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 44system.physmem.bytesReadSys 914880 # Total read bytes from the system interface side | 44system.physmem.bytesReadSys 916544 # Total read bytes from the system interface side |
| 45system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 46system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 47system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 48system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 45system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 46system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 47system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 48system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 49system.physmem.perBankRdBursts::0 1374 # Per bank write bursts 50system.physmem.perBankRdBursts::1 495 # Per bank write bursts 51system.physmem.perBankRdBursts::2 5094 # Per bank write bursts 52system.physmem.perBankRdBursts::3 807 # Per bank write bursts 53system.physmem.perBankRdBursts::4 2274 # Per bank write bursts | 49system.physmem.perBankRdBursts::0 1378 # Per bank write bursts 50system.physmem.perBankRdBursts::1 501 # Per bank write bursts 51system.physmem.perBankRdBursts::2 5089 # Per bank write bursts 52system.physmem.perBankRdBursts::3 804 # Per bank write bursts 53system.physmem.perBankRdBursts::4 2285 # Per bank write bursts |
| 54system.physmem.perBankRdBursts::5 424 # Per bank write bursts 55system.physmem.perBankRdBursts::6 384 # Per bank write bursts | 54system.physmem.perBankRdBursts::5 424 # Per bank write bursts 55system.physmem.perBankRdBursts::6 384 # Per bank write bursts |
| 56system.physmem.perBankRdBursts::7 621 # Per bank write bursts | 56system.physmem.perBankRdBursts::7 628 # Per bank write bursts |
| 57system.physmem.perBankRdBursts::8 270 # Per bank write bursts | 57system.physmem.perBankRdBursts::8 270 # Per bank write bursts |
| 58system.physmem.perBankRdBursts::9 230 # Per bank write bursts | 58system.physmem.perBankRdBursts::9 231 # Per bank write bursts |
| 59system.physmem.perBankRdBursts::10 354 # Per bank write bursts 60system.physmem.perBankRdBursts::11 348 # Per bank write bursts | 59system.physmem.perBankRdBursts::10 354 # Per bank write bursts 60system.physmem.perBankRdBursts::11 348 # Per bank write bursts |
| 61system.physmem.perBankRdBursts::12 319 # Per bank write bursts | 61system.physmem.perBankRdBursts::12 321 # Per bank write bursts |
| 62system.physmem.perBankRdBursts::13 267 # Per bank write bursts | 62system.physmem.perBankRdBursts::13 267 # Per bank write bursts |
| 63system.physmem.perBankRdBursts::14 239 # Per bank write bursts 64system.physmem.perBankRdBursts::15 795 # Per bank write bursts | 63system.physmem.perBankRdBursts::14 240 # Per bank write bursts 64system.physmem.perBankRdBursts::15 797 # Per bank write bursts |
| 65system.physmem.perBankWrBursts::0 0 # Per bank write bursts 66system.physmem.perBankWrBursts::1 0 # Per bank write bursts 67system.physmem.perBankWrBursts::2 0 # Per bank write bursts 68system.physmem.perBankWrBursts::3 0 # Per bank write bursts 69system.physmem.perBankWrBursts::4 0 # Per bank write bursts 70system.physmem.perBankWrBursts::5 0 # Per bank write bursts 71system.physmem.perBankWrBursts::6 0 # Per bank write bursts 72system.physmem.perBankWrBursts::7 0 # Per bank write bursts 73system.physmem.perBankWrBursts::8 0 # Per bank write bursts 74system.physmem.perBankWrBursts::9 0 # Per bank write bursts 75system.physmem.perBankWrBursts::10 0 # Per bank write bursts 76system.physmem.perBankWrBursts::11 0 # Per bank write bursts 77system.physmem.perBankWrBursts::12 0 # Per bank write bursts 78system.physmem.perBankWrBursts::13 0 # Per bank write bursts 79system.physmem.perBankWrBursts::14 0 # Per bank write bursts 80system.physmem.perBankWrBursts::15 0 # Per bank write bursts 81system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 82system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 65system.physmem.perBankWrBursts::0 0 # Per bank write bursts 66system.physmem.perBankWrBursts::1 0 # Per bank write bursts 67system.physmem.perBankWrBursts::2 0 # Per bank write bursts 68system.physmem.perBankWrBursts::3 0 # Per bank write bursts 69system.physmem.perBankWrBursts::4 0 # Per bank write bursts 70system.physmem.perBankWrBursts::5 0 # Per bank write bursts 71system.physmem.perBankWrBursts::6 0 # Per bank write bursts 72system.physmem.perBankWrBursts::7 0 # Per bank write bursts 73system.physmem.perBankWrBursts::8 0 # Per bank write bursts 74system.physmem.perBankWrBursts::9 0 # Per bank write bursts 75system.physmem.perBankWrBursts::10 0 # Per bank write bursts 76system.physmem.perBankWrBursts::11 0 # Per bank write bursts 77system.physmem.perBankWrBursts::12 0 # Per bank write bursts 78system.physmem.perBankWrBursts::13 0 # Per bank write bursts 79system.physmem.perBankWrBursts::14 0 # Per bank write bursts 80system.physmem.perBankWrBursts::15 0 # Per bank write bursts 81system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 82system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 83system.physmem.totGap 85051447500 # Total gap between requests | 83system.physmem.totGap 86052975500 # Total gap between requests |
| 84system.physmem.readPktSize::0 0 # Read request sizes (log2) 85system.physmem.readPktSize::1 0 # Read request sizes (log2) 86system.physmem.readPktSize::2 0 # Read request sizes (log2) 87system.physmem.readPktSize::3 0 # Read request sizes (log2) 88system.physmem.readPktSize::4 0 # Read request sizes (log2) 89system.physmem.readPktSize::5 0 # Read request sizes (log2) | 84system.physmem.readPktSize::0 0 # Read request sizes (log2) 85system.physmem.readPktSize::1 0 # Read request sizes (log2) 86system.physmem.readPktSize::2 0 # Read request sizes (log2) 87system.physmem.readPktSize::3 0 # Read request sizes (log2) 88system.physmem.readPktSize::4 0 # Read request sizes (log2) 89system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 90system.physmem.readPktSize::6 14295 # Read request sizes (log2) | 90system.physmem.readPktSize::6 14321 # Read request sizes (log2) |
| 91system.physmem.writePktSize::0 0 # Write request sizes (log2) 92system.physmem.writePktSize::1 0 # Write request sizes (log2) 93system.physmem.writePktSize::2 0 # Write request sizes (log2) 94system.physmem.writePktSize::3 0 # Write request sizes (log2) 95system.physmem.writePktSize::4 0 # Write request sizes (log2) 96system.physmem.writePktSize::5 0 # Write request sizes (log2) 97system.physmem.writePktSize::6 0 # Write request sizes (log2) | 91system.physmem.writePktSize::0 0 # Write request sizes (log2) 92system.physmem.writePktSize::1 0 # Write request sizes (log2) 93system.physmem.writePktSize::2 0 # Write request sizes (log2) 94system.physmem.writePktSize::3 0 # Write request sizes (log2) 95system.physmem.writePktSize::4 0 # Write request sizes (log2) 96system.physmem.writePktSize::5 0 # Write request sizes (log2) 97system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 98system.physmem.rdQLenPdf::0 12841 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::1 1014 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::2 173 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::3 85 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see | 98system.physmem.rdQLenPdf::0 12787 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::1 1077 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::2 178 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::3 86 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see |
| 103system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see | 103system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see |
| 104system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::7 28 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::8 26 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see | 104system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see |
| 110system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see --- 68 unchanged lines hidden (view full) --- 186system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 110system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see --- 68 unchanged lines hidden (view full) --- 186system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 194system.physmem.bytesPerActivate::samples 8758 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::mean 104.242978 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::gmean 83.732821 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::stdev 121.093987 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::0-127 6415 73.25% 73.25% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::128-255 1879 21.45% 94.70% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::256-383 191 2.18% 96.88% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::384-511 97 1.11% 97.99% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::512-639 35 0.40% 98.39% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::640-767 31 0.35% 98.74% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::768-895 21 0.24% 98.98% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::896-1023 17 0.19% 99.18% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1024-1151 72 0.82% 100.00% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::total 8758 # Bytes accessed per row activation 208system.physmem.totQLat 205669486 # Total ticks spent queuing 209system.physmem.totMemAccLat 473700736 # Total ticks spent from burst creation until serviced by the DRAM 210system.physmem.totBusLat 71475000 # Total ticks spent in databus transfers 211system.physmem.avgQLat 14387.51 # Average queueing delay per DRAM burst | 194system.physmem.bytesPerActivate::samples 8480 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::mean 108.022642 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::gmean 86.441459 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::stdev 123.287712 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::0-127 5899 69.56% 69.56% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::128-255 2101 24.78% 94.34% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::256-383 209 2.46% 96.80% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::384-511 89 1.05% 97.85% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::512-639 41 0.48% 98.34% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::640-767 36 0.42% 98.76% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::768-895 15 0.18% 98.94% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::896-1023 13 0.15% 99.09% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1024-1151 77 0.91% 100.00% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::total 8480 # Bytes accessed per row activation 208system.physmem.totQLat 1499260235 # Total ticks spent queuing 209system.physmem.totMemAccLat 1767778985 # Total ticks spent from burst creation until serviced by the DRAM 210system.physmem.totBusLat 71605000 # Total ticks spent in databus transfers 211system.physmem.avgQLat 104689.63 # Average queueing delay per DRAM burst |
| 212system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 212system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 213system.physmem.avgMemAccLat 33137.51 # Average memory access latency per DRAM burst 214system.physmem.avgRdBW 10.76 # Average DRAM read bandwidth in MiByte/s | 213system.physmem.avgMemAccLat 123439.63 # Average memory access latency per DRAM burst 214system.physmem.avgRdBW 10.65 # Average DRAM read bandwidth in MiByte/s |
| 215system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 215system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 216system.physmem.avgRdBWSys 10.76 # Average system read bandwidth in MiByte/s | 216system.physmem.avgRdBWSys 10.65 # Average system read bandwidth in MiByte/s |
| 217system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 218system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 219system.physmem.busUtil 0.08 # Data bus utilization in percentage 220system.physmem.busUtilRead 0.08 # Data bus utilization in percentage for reads 221system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 217system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 218system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 219system.physmem.busUtil 0.08 # Data bus utilization in percentage 220system.physmem.busUtilRead 0.08 # Data bus utilization in percentage for reads 221system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 222system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing | 222system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing |
| 223system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 223system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 224system.physmem.readRowHits 5530 # Number of row buffer hits during reads | 224system.physmem.readRowHits 5837 # Number of row buffer hits during reads |
| 225system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 225system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 226system.physmem.readRowHitRate 38.68 # Row buffer hit rate for reads | 226system.physmem.readRowHitRate 40.76 # Row buffer hit rate for reads |
| 227system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 227system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 228system.physmem.avgGap 5949734.00 # Average gap between requests 229system.physmem.pageHitRate 38.68 # Row buffer hit rate, read and write combined 230system.physmem_0.actEnergy 56571480 # Energy for activate commands per rank (pJ) 231system.physmem_0.preEnergy 30867375 # Energy for precharge commands per rank (pJ) 232system.physmem_0.readEnergy 89442600 # Energy for read commands per rank (pJ) | 228system.physmem.avgGap 6008866.39 # Average gap between requests 229system.physmem.pageHitRate 40.76 # Row buffer hit rate, read and write combined 230system.physmem_0.actEnergy 51557940 # Energy for activate commands per rank (pJ) 231system.physmem_0.preEnergy 27392310 # Energy for precharge commands per rank (pJ) 232system.physmem_0.readEnergy 82060020 # Energy for read commands per rank (pJ) |
| 233system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) | 233system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 234system.physmem_0.refreshEnergy 5555000880 # Energy for refresh commands per rank (pJ) 235system.physmem_0.actBackEnergy 17335593540 # Energy for active background per rank (pJ) 236system.physmem_0.preBackEnergy 35823020250 # Energy for precharge background per rank (pJ) 237system.physmem_0.totalEnergy 58890496125 # Total energy per rank (pJ) 238system.physmem_0.averagePower 692.426384 # Core power per rank (mW) 239system.physmem_0.memoryStateTime::IDLE 59484367239 # Time in different power states 240system.physmem_0.memoryStateTime::REF 2839980000 # Time in different power states 241system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 242system.physmem_0.memoryStateTime::ACT 22725351261 # Time in different power states 243system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 244system.physmem_1.actEnergy 9616320 # Energy for activate commands per rank (pJ) 245system.physmem_1.preEnergy 5247000 # Energy for precharge commands per rank (pJ) 246system.physmem_1.readEnergy 21801000 # Energy for read commands per rank (pJ) | 234system.physmem_0.refreshEnergy 5180800560.000001 # Energy for refresh commands per rank (pJ) 235system.physmem_0.actBackEnergy 1120628550 # Energy for active background per rank (pJ) 236system.physmem_0.preBackEnergy 275264640 # Energy for precharge background per rank (pJ) 237system.physmem_0.actPowerDownEnergy 12259963560 # Energy for active power-down per rank (pJ) 238system.physmem_0.prePowerDownEnergy 8345872320 # Energy for precharge power-down per rank (pJ) 239system.physmem_0.selfRefreshEnergy 9276913815 # Energy for self refresh per rank (pJ) 240system.physmem_0.totalEnergy 36622770765 # Total energy per rank (pJ) 241system.physmem_0.averagePower 425.583720 # Core power per rank (mW) 242system.physmem_0.totalIdleTime 82871785017 # Total Idle time Per DRAM Rank 243system.physmem_0.memoryStateTime::IDLE 531109000 # Time in different power states 244system.physmem_0.memoryStateTime::REF 2203210000 # Time in different power states 245system.physmem_0.memoryStateTime::SREF 34253599252 # Time in different power states 246system.physmem_0.memoryStateTime::PRE_PDN 21734056085 # Time in different power states 247system.physmem_0.memoryStateTime::ACT 445220983 # Time in different power states 248system.physmem_0.memoryStateTime::ACT_PDN 26885838680 # Time in different power states 249system.physmem_1.actEnergy 9017820 # Energy for activate commands per rank (pJ) 250system.physmem_1.preEnergy 4789290 # Energy for precharge commands per rank (pJ) 251system.physmem_1.readEnergy 20191920 # Energy for read commands per rank (pJ) |
| 247system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) | 252system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 248system.physmem_1.refreshEnergy 5555000880 # Energy for refresh commands per rank (pJ) 249system.physmem_1.actBackEnergy 4216606920 # Energy for active background per rank (pJ) 250system.physmem_1.preBackEnergy 47330903250 # Energy for precharge background per rank (pJ) 251system.physmem_1.totalEnergy 57139175370 # Total energy per rank (pJ) 252system.physmem_1.averagePower 671.834595 # Core power per rank (mW) 253system.physmem_1.memoryStateTime::IDLE 78723898183 # Time in different power states 254system.physmem_1.memoryStateTime::REF 2839980000 # Time in different power states 255system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 256system.physmem_1.memoryStateTime::ACT 3485604317 # Time in different power states 257system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 258system.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states 259system.cpu.branchPred.lookups 85633597 # Number of BP lookups 260system.cpu.branchPred.condPredicted 68181299 # Number of conditional branches predicted 261system.cpu.branchPred.condIncorrect 5935035 # Number of conditional branches incorrect 262system.cpu.branchPred.BTBLookups 39958046 # Number of BTB lookups 263system.cpu.branchPred.BTBHits 38197568 # Number of BTB hits | 253system.physmem_1.refreshEnergy 882623040.000000 # Energy for refresh commands per rank (pJ) 254system.physmem_1.actBackEnergy 198112620 # Energy for active background per rank (pJ) 255system.physmem_1.preBackEnergy 50847360 # Energy for precharge background per rank (pJ) 256system.physmem_1.actPowerDownEnergy 1971627720 # Energy for active power-down per rank (pJ) 257system.physmem_1.prePowerDownEnergy 1393669440 # Energy for precharge power-down per rank (pJ) 258system.physmem_1.selfRefreshEnergy 18810725700 # Energy for self refresh per rank (pJ) 259system.physmem_1.totalEnergy 23341907430 # Total energy per rank (pJ) 260system.physmem_1.averagePower 271.250252 # Core power per rank (mW) 261system.physmem_1.totalIdleTime 85485463257 # Total Idle time Per DRAM Rank 262system.physmem_1.memoryStateTime::IDLE 101360000 # Time in different power states 263system.physmem_1.memoryStateTime::REF 375610000 # Time in different power states 264system.physmem_1.memoryStateTime::SREF 77532398500 # Time in different power states 265system.physmem_1.memoryStateTime::PRE_PDN 3629358146 # Time in different power states 266system.physmem_1.memoryStateTime::ACT 90573993 # Time in different power states 267system.physmem_1.memoryStateTime::ACT_PDN 4323733361 # Time in different power states 268system.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states 269system.cpu.branchPred.lookups 85625838 # Number of BP lookups 270system.cpu.branchPred.condPredicted 68176243 # Number of conditional branches predicted 271system.cpu.branchPred.condIncorrect 5935432 # Number of conditional branches incorrect 272system.cpu.branchPred.BTBLookups 39943176 # Number of BTB lookups 273system.cpu.branchPred.BTBHits 38184524 # Number of BTB hits |
| 264system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 274system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 265system.cpu.branchPred.BTBHitPct 95.594184 # BTB Hit Percentage 266system.cpu.branchPred.usedRAS 3683467 # Number of times the RAS was used to get a target. 267system.cpu.branchPred.RASInCorrect 81914 # Number of incorrect RAS predictions. 268system.cpu.branchPred.indirectLookups 681978 # Number of indirect predictor lookups. 269system.cpu.branchPred.indirectHits 654112 # Number of indirect target hits. 270system.cpu.branchPred.indirectMisses 27866 # Number of indirect misses. 271system.cpu.branchPredindirectMispredicted 40296 # Number of mispredicted indirect branches. | 275system.cpu.branchPred.BTBHitPct 95.597115 # BTB Hit Percentage 276system.cpu.branchPred.usedRAS 3683485 # Number of times the RAS was used to get a target. 277system.cpu.branchPred.RASInCorrect 81916 # Number of incorrect RAS predictions. 278system.cpu.branchPred.indirectLookups 681521 # Number of indirect predictor lookups. 279system.cpu.branchPred.indirectHits 653387 # Number of indirect target hits. 280system.cpu.branchPred.indirectMisses 28134 # Number of indirect misses. 281system.cpu.branchPredindirectMispredicted 40344 # Number of mispredicted indirect branches. |
| 272system.cpu_clk_domain.clock 500 # Clock period in ticks | 282system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 273system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states | 283system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states |
| 274system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 275system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 278system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 279system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 280system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 281system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 295system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 296system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 297system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 298system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 299system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 300system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 301system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 302system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 284system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 285system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 286system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 287system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 288system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 289system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 290system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 291system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 305system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 306system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 307system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 308system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 309system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 310system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 311system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 312system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 303system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states | 313system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states |
| 304system.cpu.dtb.walker.walks 0 # Table walker walks requested 305system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 306system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 307system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 308system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 309system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 310system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 311system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 325system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 326system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 327system.cpu.dtb.read_accesses 0 # DTB read accesses 328system.cpu.dtb.write_accesses 0 # DTB write accesses 329system.cpu.dtb.inst_accesses 0 # ITB inst accesses 330system.cpu.dtb.hits 0 # DTB hits 331system.cpu.dtb.misses 0 # DTB misses 332system.cpu.dtb.accesses 0 # DTB accesses | 314system.cpu.dtb.walker.walks 0 # Table walker walks requested 315system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 316system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 317system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 318system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 319system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 320system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 321system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 335system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 336system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 337system.cpu.dtb.read_accesses 0 # DTB read accesses 338system.cpu.dtb.write_accesses 0 # DTB write accesses 339system.cpu.dtb.inst_accesses 0 # ITB inst accesses 340system.cpu.dtb.hits 0 # DTB hits 341system.cpu.dtb.misses 0 # DTB misses 342system.cpu.dtb.accesses 0 # DTB accesses |
| 333system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states | 343system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states |
| 334system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 335system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 337system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 338system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 339system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 340system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 341system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 355system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 356system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 357system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 358system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 359system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 360system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 361system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 362system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 344system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 345system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 346system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 347system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 348system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 349system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 350system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 351system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 365system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 366system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 367system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 368system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 369system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 370system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 371system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 372system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 363system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states | 373system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states |
| 364system.cpu.itb.walker.walks 0 # Table walker walks requested 365system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 366system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 367system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 368system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 369system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 370system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 371system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 386system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 387system.cpu.itb.read_accesses 0 # DTB read accesses 388system.cpu.itb.write_accesses 0 # DTB write accesses 389system.cpu.itb.inst_accesses 0 # ITB inst accesses 390system.cpu.itb.hits 0 # DTB hits 391system.cpu.itb.misses 0 # DTB misses 392system.cpu.itb.accesses 0 # DTB accesses 393system.cpu.workload.num_syscalls 400 # Number of system calls | 374system.cpu.itb.walker.walks 0 # Table walker walks requested 375system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 376system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 377system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 378system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 379system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 380system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 381system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 396system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 397system.cpu.itb.read_accesses 0 # DTB read accesses 398system.cpu.itb.write_accesses 0 # DTB write accesses 399system.cpu.itb.inst_accesses 0 # ITB inst accesses 400system.cpu.itb.hits 0 # DTB hits 401system.cpu.itb.misses 0 # DTB misses 402system.cpu.itb.accesses 0 # DTB accesses 403system.cpu.workload.num_syscalls 400 # Number of system calls |
| 394system.cpu.pwrStateResidencyTicks::ON 85051506000 # Cumulative time (in ticks) in various power states 395system.cpu.numCycles 170103013 # number of cpu cycles simulated | 404system.cpu.pwrStateResidencyTicks::ON 86053034000 # Cumulative time (in ticks) in various power states 405system.cpu.numCycles 172106069 # number of cpu cycles simulated |
| 396system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 397system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 406system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 407system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 398system.cpu.fetch.icacheStallCycles 5682904 # Number of cycles fetch is stalled on an Icache miss 399system.cpu.fetch.Insts 347166765 # Number of instructions fetch has processed 400system.cpu.fetch.Branches 85633597 # Number of branches that fetch encountered 401system.cpu.fetch.predictedBranches 42535147 # Number of branches that fetch has predicted taken 402system.cpu.fetch.Cycles 157608501 # Number of cycles fetch has run and was not squashing or blocked 403system.cpu.fetch.SquashCycles 11884039 # Number of cycles fetch has spent squashing 404system.cpu.fetch.MiscStallCycles 2048 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 408system.cpu.fetch.icacheStallCycles 5685351 # Number of cycles fetch is stalled on an Icache miss 409system.cpu.fetch.Insts 347171735 # Number of instructions fetch has processed 410system.cpu.fetch.Branches 85625838 # Number of branches that fetch encountered 411system.cpu.fetch.predictedBranches 42521396 # Number of branches that fetch has predicted taken 412system.cpu.fetch.Cycles 158200265 # Number of cycles fetch has run and was not squashing or blocked 413system.cpu.fetch.SquashCycles 11884759 # Number of cycles fetch has spent squashing 414system.cpu.fetch.MiscStallCycles 4008 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 405system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions | 415system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions |
| 406system.cpu.fetch.IcacheWaitRetryStallCycles 3989 # Number of stall cycles due to full MSHR 407system.cpu.fetch.CacheLines 78333693 # Number of cache lines fetched 408system.cpu.fetch.IcacheSquashes 18018 # Number of outstanding Icache misses that were squashed 409system.cpu.fetch.rateDist::samples 169239484 # Number of instructions fetched each cycle (Total) 410system.cpu.fetch.rateDist::mean 2.146393 # Number of instructions fetched each cycle (Total) 411system.cpu.fetch.rateDist::stdev 1.050401 # Number of instructions fetched each cycle (Total) | 416system.cpu.fetch.IcacheWaitRetryStallCycles 4307 # Number of stall cycles due to full MSHR 417system.cpu.fetch.CacheLines 78326471 # Number of cache lines fetched 418system.cpu.fetch.IcacheSquashes 18089 # Number of outstanding Icache misses that were squashed 419system.cpu.fetch.rateDist::samples 169836333 # Number of instructions fetched each cycle (Total) 420system.cpu.fetch.rateDist::mean 2.138878 # Number of instructions fetched each cycle (Total) 421system.cpu.fetch.rateDist::stdev 1.056220 # Number of instructions fetched each cycle (Total) |
| 412system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 422system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 413system.cpu.fetch.rateDist::0 17572638 10.38% 10.38% # Number of instructions fetched each cycle (Total) 414system.cpu.fetch.rateDist::1 30072408 17.77% 28.15% # Number of instructions fetched each cycle (Total) 415system.cpu.fetch.rateDist::2 31601234 18.67% 46.82% # Number of instructions fetched each cycle (Total) 416system.cpu.fetch.rateDist::3 89993204 53.18% 100.00% # Number of instructions fetched each cycle (Total) | 423system.cpu.fetch.rateDist::0 18169241 10.70% 10.70% # Number of instructions fetched each cycle (Total) 424system.cpu.fetch.rateDist::1 30071574 17.71% 28.40% # Number of instructions fetched each cycle (Total) 425system.cpu.fetch.rateDist::2 31598899 18.61% 47.01% # Number of instructions fetched each cycle (Total) 426system.cpu.fetch.rateDist::3 89996619 52.99% 100.00% # Number of instructions fetched each cycle (Total) |
| 417system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 418system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 419system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 427system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 428system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 429system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 420system.cpu.fetch.rateDist::total 169239484 # Number of instructions fetched each cycle (Total) 421system.cpu.fetch.branchRate 0.503422 # Number of branch fetches per cycle 422system.cpu.fetch.rate 2.040921 # Number of inst fetches per cycle 423system.cpu.decode.IdleCycles 17519961 # Number of cycles decode is idle 424system.cpu.decode.BlockedCycles 17356982 # Number of cycles decode is blocked 425system.cpu.decode.RunCycles 121861075 # Number of cycles decode is running 426system.cpu.decode.UnblockCycles 6734206 # Number of cycles decode is unblocking 427system.cpu.decode.SquashCycles 5767260 # Number of cycles decode is squashing 428system.cpu.decode.BranchResolved 11064637 # Number of times decode resolved a branch 429system.cpu.decode.BranchMispred 189821 # Number of times decode detected a branch misprediction 430system.cpu.decode.DecodedInsts 304987544 # Number of instructions handled by decode 431system.cpu.decode.SquashedInsts 27243895 # Number of squashed instructions handled by decode 432system.cpu.rename.SquashCycles 5767260 # Number of cycles rename is squashing 433system.cpu.rename.IdleCycles 37487022 # Number of cycles rename is idle 434system.cpu.rename.BlockCycles 8574296 # Number of cycles rename is blocking 435system.cpu.rename.serializeStallCycles 598391 # count of cycles rename stalled for serializing inst 436system.cpu.rename.RunCycles 108353196 # Number of cycles rename is running 437system.cpu.rename.UnblockCycles 8459319 # Number of cycles rename is unblocking 438system.cpu.rename.RenamedInsts 277412346 # Number of instructions processed by rename 439system.cpu.rename.SquashedInsts 13179472 # Number of squashed instructions processed by rename 440system.cpu.rename.ROBFullEvents 3059617 # Number of times rename has blocked due to ROB full 441system.cpu.rename.IQFullEvents 843440 # Number of times rename has blocked due to IQ full 442system.cpu.rename.LQFullEvents 2298708 # Number of times rename has blocked due to LQ full 443system.cpu.rename.SQFullEvents 38369 # Number of times rename has blocked due to SQ full 444system.cpu.rename.FullRegisterEvents 27077 # Number of times there has been no free registers 445system.cpu.rename.RenamedOperands 481431446 # Number of destination operands rename has renamed 446system.cpu.rename.RenameLookups 1187749796 # Number of register rename lookups that rename has made 447system.cpu.rename.int_rename_lookups 296450503 # Number of integer rename lookups 448system.cpu.rename.fp_rename_lookups 3005240 # Number of floating rename lookups | 430system.cpu.fetch.rateDist::total 169836333 # Number of instructions fetched each cycle (Total) 431system.cpu.fetch.branchRate 0.497518 # Number of branch fetches per cycle 432system.cpu.fetch.rate 2.017196 # Number of inst fetches per cycle 433system.cpu.decode.IdleCycles 17522714 # Number of cycles decode is idle 434system.cpu.decode.BlockedCycles 17948295 # Number of cycles decode is blocked 435system.cpu.decode.RunCycles 121866676 # Number of cycles decode is running 436system.cpu.decode.UnblockCycles 6730979 # Number of cycles decode is unblocking 437system.cpu.decode.SquashCycles 5767669 # Number of cycles decode is squashing 438system.cpu.decode.BranchResolved 11064280 # Number of times decode resolved a branch 439system.cpu.decode.BranchMispred 189793 # Number of times decode detected a branch misprediction 440system.cpu.decode.DecodedInsts 304996623 # Number of instructions handled by decode 441system.cpu.decode.SquashedInsts 27241409 # Number of squashed instructions handled by decode 442system.cpu.rename.SquashCycles 5767669 # Number of cycles rename is squashing 443system.cpu.rename.IdleCycles 37489750 # Number of cycles rename is idle 444system.cpu.rename.BlockCycles 8834769 # Number of cycles rename is blocking 445system.cpu.rename.serializeStallCycles 601523 # count of cycles rename stalled for serializing inst 446system.cpu.rename.RunCycles 108355832 # Number of cycles rename is running 447system.cpu.rename.UnblockCycles 8786790 # Number of cycles rename is unblocking 448system.cpu.rename.RenamedInsts 277419061 # Number of instructions processed by rename 449system.cpu.rename.SquashedInsts 13180458 # Number of squashed instructions processed by rename 450system.cpu.rename.ROBFullEvents 3061814 # Number of times rename has blocked due to ROB full 451system.cpu.rename.IQFullEvents 846087 # Number of times rename has blocked due to IQ full 452system.cpu.rename.LQFullEvents 2626546 # Number of times rename has blocked due to LQ full 453system.cpu.rename.SQFullEvents 39334 # Number of times rename has blocked due to SQ full 454system.cpu.rename.FullRegisterEvents 27085 # Number of times there has been no free registers 455system.cpu.rename.RenamedOperands 481448286 # Number of destination operands rename has renamed 456system.cpu.rename.RenameLookups 1187772528 # Number of register rename lookups that rename has made 457system.cpu.rename.int_rename_lookups 296460965 # Number of integer rename lookups 458system.cpu.rename.fp_rename_lookups 3003847 # Number of floating rename lookups |
| 449system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed | 459system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed |
| 450system.cpu.rename.UndoneMaps 188454517 # Number of HB maps that are undone due to squashing 451system.cpu.rename.serializingInsts 23636 # count of serializing insts renamed 452system.cpu.rename.tempSerializingInsts 23644 # count of temporary serializing insts renamed 453system.cpu.rename.skidInsts 13356506 # count of insts added to the skid buffer 454system.cpu.memDep0.insertedLoads 33916395 # Number of loads inserted to the mem dependence unit. 455system.cpu.memDep0.insertedStores 14406588 # Number of stores inserted to the mem dependence unit. 456system.cpu.memDep0.conflictingLoads 2541453 # Number of conflicting loads. 457system.cpu.memDep0.conflictingStores 1809916 # Number of conflicting stores. 458system.cpu.iq.iqInstsAdded 263792468 # Number of instructions added to the IQ (excludes non-spec) 459system.cpu.iq.iqNonSpecInstsAdded 45987 # Number of non-speculative instructions added to the IQ 460system.cpu.iq.iqInstsIssued 214404594 # Number of instructions issued 461system.cpu.iq.iqSquashedInstsIssued 5189732 # Number of squashed instructions issued 462system.cpu.iq.iqSquashedInstsExamined 82202501 # Number of squashed instructions iterated over during squash; mainly for profiling 463system.cpu.iq.iqSquashedOperandsExamined 216956580 # Number of squashed operands that are examined and possibly removed from graph 464system.cpu.iq.iqSquashedNonSpecRemoved 771 # Number of squashed non-spec instructions that were removed 465system.cpu.iq.issued_per_cycle::samples 169239484 # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::mean 1.266871 # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::stdev 1.018138 # Number of insts issued each cycle | 460system.cpu.rename.UndoneMaps 188471357 # Number of HB maps that are undone due to squashing 461system.cpu.rename.serializingInsts 23624 # count of serializing insts renamed 462system.cpu.rename.tempSerializingInsts 23625 # count of temporary serializing insts renamed 463system.cpu.rename.skidInsts 13352846 # count of insts added to the skid buffer 464system.cpu.memDep0.insertedLoads 33915531 # Number of loads inserted to the mem dependence unit. 465system.cpu.memDep0.insertedStores 14406995 # Number of stores inserted to the mem dependence unit. 466system.cpu.memDep0.conflictingLoads 2538352 # Number of conflicting loads. 467system.cpu.memDep0.conflictingStores 1801972 # Number of conflicting stores. 468system.cpu.iq.iqInstsAdded 263797881 # Number of instructions added to the IQ (excludes non-spec) 469system.cpu.iq.iqNonSpecInstsAdded 45980 # Number of non-speculative instructions added to the IQ 470system.cpu.iq.iqInstsIssued 214410891 # Number of instructions issued 471system.cpu.iq.iqSquashedInstsIssued 5187410 # Number of squashed instructions issued 472system.cpu.iq.iqSquashedInstsExamined 82207907 # Number of squashed instructions iterated over during squash; mainly for profiling 473system.cpu.iq.iqSquashedOperandsExamined 216953193 # Number of squashed operands that are examined and possibly removed from graph 474system.cpu.iq.iqSquashedNonSpecRemoved 764 # Number of squashed non-spec instructions that were removed 475system.cpu.iq.issued_per_cycle::samples 169836333 # Number of insts issued each cycle 476system.cpu.iq.issued_per_cycle::mean 1.262456 # Number of insts issued each cycle 477system.cpu.iq.issued_per_cycle::stdev 1.019138 # Number of insts issued each cycle |
| 468system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 478system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 469system.cpu.iq.issued_per_cycle::0 52525006 31.04% 31.04% # Number of insts issued each cycle 470system.cpu.iq.issued_per_cycle::1 35947009 21.24% 52.28% # Number of insts issued each cycle 471system.cpu.iq.issued_per_cycle::2 65510390 38.71% 90.98% # Number of insts issued each cycle 472system.cpu.iq.issued_per_cycle::3 13639375 8.06% 99.04% # Number of insts issued each cycle 473system.cpu.iq.issued_per_cycle::4 1570056 0.93% 99.97% # Number of insts issued each cycle 474system.cpu.iq.issued_per_cycle::5 47432 0.03% 100.00% # Number of insts issued each cycle 475system.cpu.iq.issued_per_cycle::6 216 0.00% 100.00% # Number of insts issued each cycle | 479system.cpu.iq.issued_per_cycle::0 53122752 31.28% 31.28% # Number of insts issued each cycle 480system.cpu.iq.issued_per_cycle::1 35940807 21.16% 52.44% # Number of insts issued each cycle 481system.cpu.iq.issued_per_cycle::2 65514665 38.58% 91.02% # Number of insts issued each cycle 482system.cpu.iq.issued_per_cycle::3 13639448 8.03% 99.05% # Number of insts issued each cycle 483system.cpu.iq.issued_per_cycle::4 1571104 0.93% 99.97% # Number of insts issued each cycle 484system.cpu.iq.issued_per_cycle::5 47348 0.03% 100.00% # Number of insts issued each cycle 485system.cpu.iq.issued_per_cycle::6 209 0.00% 100.00% # Number of insts issued each cycle |
| 476system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 477system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 478system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 479system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 480system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle | 486system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 487system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 488system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 489system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 490system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle |
| 481system.cpu.iq.issued_per_cycle::total 169239484 # Number of insts issued each cycle | 491system.cpu.iq.issued_per_cycle::total 169836333 # Number of insts issued each cycle |
| 482system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 492system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 483system.cpu.iq.fu_full::IntAlu 35663808 66.17% 66.17% # attempts to use FU when none available 484system.cpu.iq.fu_full::IntMult 153282 0.28% 66.45% # attempts to use FU when none available 485system.cpu.iq.fu_full::IntDiv 0 0.00% 66.45% # attempts to use FU when none available 486system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.45% # attempts to use FU when none available 487system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.45% # attempts to use FU when none available 488system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.45% # attempts to use FU when none available 489system.cpu.iq.fu_full::FloatMult 0 0.00% 66.45% # attempts to use FU when none available 490system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.45% # attempts to use FU when none available 491system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.45% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.45% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.45% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.45% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.45% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.45% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.45% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdMult 0 0.00% 66.45% # attempts to use FU when none available 499system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.45% # attempts to use FU when none available 500system.cpu.iq.fu_full::SimdShift 0 0.00% 66.45% # attempts to use FU when none available 501system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.45% # attempts to use FU when none available 502system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.45% # attempts to use FU when none available 503system.cpu.iq.fu_full::SimdFloatAdd 1064 0.00% 66.45% # attempts to use FU when none available | 493system.cpu.iq.fu_full::IntAlu 35657368 66.16% 66.16% # attempts to use FU when none available 494system.cpu.iq.fu_full::IntMult 153250 0.28% 66.44% # attempts to use FU when none available 495system.cpu.iq.fu_full::IntDiv 0 0.00% 66.44% # attempts to use FU when none available 496system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.44% # attempts to use FU when none available 497system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.44% # attempts to use FU when none available 498system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.44% # attempts to use FU when none available 499system.cpu.iq.fu_full::FloatMult 0 0.00% 66.44% # attempts to use FU when none available 500system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.44% # attempts to use FU when none available 501system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.44% # attempts to use FU when none available 502system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.44% # attempts to use FU when none available 503system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.44% # attempts to use FU when none available 504system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.44% # attempts to use FU when none available 505system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.44% # attempts to use FU when none available 506system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.44% # attempts to use FU when none available 507system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.44% # attempts to use FU when none available 508system.cpu.iq.fu_full::SimdMult 0 0.00% 66.44% # attempts to use FU when none available 509system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.44% # attempts to use FU when none available 510system.cpu.iq.fu_full::SimdShift 0 0.00% 66.44% # attempts to use FU when none available 511system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.44% # attempts to use FU when none available 512system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.44% # attempts to use FU when none available 513system.cpu.iq.fu_full::SimdFloatAdd 1065 0.00% 66.45% # attempts to use FU when none available |
| 504system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.45% # attempts to use FU when none available | 514system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.45% # attempts to use FU when none available |
| 505system.cpu.iq.fu_full::SimdFloatCmp 35736 0.07% 66.52% # attempts to use FU when none available 506system.cpu.iq.fu_full::SimdFloatCvt 239 0.00% 66.52% # attempts to use FU when none available 507system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.52% # attempts to use FU when none available 508system.cpu.iq.fu_full::SimdFloatMisc 958 0.00% 66.52% # attempts to use FU when none available 509system.cpu.iq.fu_full::SimdFloatMult 34308 0.06% 66.59% # attempts to use FU when none available 510system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.59% # attempts to use FU when none available 511system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.59% # attempts to use FU when none available 512system.cpu.iq.fu_full::MemRead 14056089 26.08% 92.66% # attempts to use FU when none available 513system.cpu.iq.fu_full::MemWrite 3953676 7.34% 100.00% # attempts to use FU when none available | 515system.cpu.iq.fu_full::SimdFloatCmp 35732 0.07% 66.51% # attempts to use FU when none available 516system.cpu.iq.fu_full::SimdFloatCvt 239 0.00% 66.51% # attempts to use FU when none available 517system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.51% # attempts to use FU when none available 518system.cpu.iq.fu_full::SimdFloatMisc 954 0.00% 66.52% # attempts to use FU when none available 519system.cpu.iq.fu_full::SimdFloatMult 34277 0.06% 66.58% # attempts to use FU when none available 520system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.58% # attempts to use FU when none available 521system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.58% # attempts to use FU when none available 522system.cpu.iq.fu_full::MemRead 14055726 26.08% 92.66% # attempts to use FU when none available 523system.cpu.iq.fu_full::MemWrite 3956441 7.34% 100.00% # attempts to use FU when none available |
| 514system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 515system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 516system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 524system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 525system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 526system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 517system.cpu.iq.FU_type_0::IntAlu 166984371 77.88% 77.88% # Type of FU issued 518system.cpu.iq.FU_type_0::IntMult 919276 0.43% 78.31% # Type of FU issued | 527system.cpu.iq.FU_type_0::IntAlu 166991462 77.88% 77.88% # Type of FU issued 528system.cpu.iq.FU_type_0::IntMult 919191 0.43% 78.31% # Type of FU issued |
| 519system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.31% # Type of FU issued 520system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.31% # Type of FU issued 521system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.31% # Type of FU issued 522system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.31% # Type of FU issued 523system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.31% # Type of FU issued 524system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.31% # Type of FU issued 525system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.31% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.31% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.31% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.31% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.31% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.31% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.31% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.31% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.31% # Type of FU issued 534system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.31% # Type of FU issued 535system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.31% # Type of FU issued 536system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.31% # Type of FU issued | 529system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.31% # Type of FU issued 530system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.31% # Type of FU issued 531system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.31% # Type of FU issued 532system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.31% # Type of FU issued 533system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.31% # Type of FU issued 534system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.31% # Type of FU issued 535system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.31% # Type of FU issued 536system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.31% # Type of FU issued 537system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.31% # Type of FU issued 538system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.31% # Type of FU issued 539system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.31% # Type of FU issued 540system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.31% # Type of FU issued 541system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.31% # Type of FU issued 542system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.31% # Type of FU issued 543system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.31% # Type of FU issued 544system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.31% # Type of FU issued 545system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.31% # Type of FU issued 546system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.31% # Type of FU issued |
| 537system.cpu.iq.FU_type_0::SimdFloatAdd 33022 0.02% 78.33% # Type of FU issued | 547system.cpu.iq.FU_type_0::SimdFloatAdd 33016 0.02% 78.33% # Type of FU issued |
| 538system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.33% # Type of FU issued | 548system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.33% # Type of FU issued |
| 539system.cpu.iq.FU_type_0::SimdFloatCmp 165180 0.08% 78.40% # Type of FU issued 540system.cpu.iq.FU_type_0::SimdFloatCvt 245718 0.11% 78.52% # Type of FU issued 541system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.55% # Type of FU issued 542system.cpu.iq.FU_type_0::SimdFloatMisc 460481 0.21% 78.77% # Type of FU issued 543system.cpu.iq.FU_type_0::SimdFloatMult 206631 0.10% 78.87% # Type of FU issued | 549system.cpu.iq.FU_type_0::SimdFloatCmp 165181 0.08% 78.40% # Type of FU issued 550system.cpu.iq.FU_type_0::SimdFloatCvt 245709 0.11% 78.52% # Type of FU issued 551system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.56% # Type of FU issued 552system.cpu.iq.FU_type_0::SimdFloatMisc 460330 0.21% 78.77% # Type of FU issued 553system.cpu.iq.FU_type_0::SimdFloatMult 206622 0.10% 78.87% # Type of FU issued |
| 544system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.90% # Type of FU issued 545system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.90% # Type of FU issued | 554system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.90% # Type of FU issued 555system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.90% # Type of FU issued |
| 546system.cpu.iq.FU_type_0::MemRead 31870339 14.86% 93.76% # Type of FU issued 547system.cpu.iq.FU_type_0::MemWrite 13371616 6.24% 100.00% # Type of FU issued | 556system.cpu.iq.FU_type_0::MemRead 31869240 14.86% 93.76% # Type of FU issued 557system.cpu.iq.FU_type_0::MemWrite 13372180 6.24% 100.00% # Type of FU issued |
| 548system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 549system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 558system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 559system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 550system.cpu.iq.FU_type_0::total 214404594 # Type of FU issued 551system.cpu.iq.rate 1.260440 # Inst issue rate 552system.cpu.iq.fu_busy_cnt 53899365 # FU busy when requested 553system.cpu.iq.fu_busy_rate 0.251391 # FU busy rate (busy events/executed inst) 554system.cpu.iq.int_inst_queue_reads 653186184 # Number of integer instruction queue reads 555system.cpu.iq.int_inst_queue_writes 344036614 # Number of integer instruction queue writes 556system.cpu.iq.int_inst_queue_wakeup_accesses 204245973 # Number of integer instruction queue wakeup accesses 557system.cpu.iq.fp_inst_queue_reads 3951585 # Number of floating instruction queue reads 558system.cpu.iq.fp_inst_queue_writes 2011286 # Number of floating instruction queue writes 559system.cpu.iq.fp_inst_queue_wakeup_accesses 1806392 # Number of floating instruction queue wakeup accesses 560system.cpu.iq.int_alu_accesses 266171590 # Number of integer alu accesses 561system.cpu.iq.fp_alu_accesses 2132369 # Number of floating point alu accesses 562system.cpu.iew.lsq.thread0.forwLoads 1599233 # Number of loads that had data forwarded from stores | 560system.cpu.iq.FU_type_0::total 214410891 # Type of FU issued 561system.cpu.iq.rate 1.245807 # Inst issue rate 562system.cpu.iq.fu_busy_cnt 53895257 # FU busy when requested 563system.cpu.iq.fu_busy_rate 0.251364 # FU busy rate (busy events/executed inst) 564system.cpu.iq.int_inst_queue_reads 653788467 # Number of integer instruction queue reads 565system.cpu.iq.int_inst_queue_writes 344049655 # Number of integer instruction queue writes 566system.cpu.iq.int_inst_queue_wakeup_accesses 204252570 # Number of integer instruction queue wakeup accesses 567system.cpu.iq.fp_inst_queue_reads 3952315 # Number of floating instruction queue reads 568system.cpu.iq.fp_inst_queue_writes 2009022 # Number of floating instruction queue writes 569system.cpu.iq.fp_inst_queue_wakeup_accesses 1806352 # Number of floating instruction queue wakeup accesses 570system.cpu.iq.int_alu_accesses 266172688 # Number of integer alu accesses 571system.cpu.iq.fp_alu_accesses 2133460 # Number of floating point alu accesses 572system.cpu.iew.lsq.thread0.forwLoads 1598637 # Number of loads that had data forwarded from stores |
| 563system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 573system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 564system.cpu.iew.lsq.thread0.squashedLoads 6020251 # Number of loads squashed 565system.cpu.iew.lsq.thread0.ignoredResponses 7425 # Number of memory responses ignored because the instruction is squashed 566system.cpu.iew.lsq.thread0.memOrderViolation 7087 # Number of memory ordering violations 567system.cpu.iew.lsq.thread0.squashedStores 1761954 # Number of stores squashed | 574system.cpu.iew.lsq.thread0.squashedLoads 6019387 # Number of loads squashed 575system.cpu.iew.lsq.thread0.ignoredResponses 7380 # Number of memory responses ignored because the instruction is squashed 576system.cpu.iew.lsq.thread0.memOrderViolation 7051 # Number of memory ordering violations 577system.cpu.iew.lsq.thread0.squashedStores 1762361 # Number of stores squashed |
| 568system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 569system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 578system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 579system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 570system.cpu.iew.lsq.thread0.rescheduledLoads 25499 # Number of loads that were rescheduled 571system.cpu.iew.lsq.thread0.cacheBlocked 790 # Number of times an access to memory failed due to the cache being blocked | 580system.cpu.iew.lsq.thread0.rescheduledLoads 25560 # Number of loads that were rescheduled 581system.cpu.iew.lsq.thread0.cacheBlocked 770 # Number of times an access to memory failed due to the cache being blocked |
| 572system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 582system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 573system.cpu.iew.iewSquashCycles 5767260 # Number of cycles IEW is squashing 574system.cpu.iew.iewBlockCycles 5621824 # Number of cycles IEW is blocking 575system.cpu.iew.iewUnblockCycles 63176 # Number of cycles IEW is unblocking 576system.cpu.iew.iewDispatchedInsts 263858489 # Number of instructions dispatched to IQ | 583system.cpu.iew.iewSquashCycles 5767669 # Number of cycles IEW is squashing 584system.cpu.iew.iewBlockCycles 5624657 # Number of cycles IEW is blocking 585system.cpu.iew.iewUnblockCycles 173600 # Number of cycles IEW is unblocking 586system.cpu.iew.iewDispatchedInsts 263863986 # Number of instructions dispatched to IQ |
| 577system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 587system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 578system.cpu.iew.iewDispLoadInsts 33916395 # Number of dispatched load instructions 579system.cpu.iew.iewDispStoreInsts 14406588 # Number of dispatched store instructions 580system.cpu.iew.iewDispNonSpecInsts 23579 # Number of dispatched non-speculative instructions 581system.cpu.iew.iewIQFullEvents 3874 # Number of times the IQ has become full, causing a stall 582system.cpu.iew.iewLSQFullEvents 56135 # Number of times the LSQ has become full, causing a stall 583system.cpu.iew.memOrderViolationEvents 7087 # Number of memory order violations 584system.cpu.iew.predictedTakenIncorrect 3147809 # Number of branches that were predicted taken incorrectly 585system.cpu.iew.predictedNotTakenIncorrect 3246868 # Number of branches that were predicted not taken incorrectly 586system.cpu.iew.branchMispredicts 6394677 # Number of branch mispredicts detected at execute 587system.cpu.iew.iewExecutedInsts 207120469 # Number of executed instructions 588system.cpu.iew.iewExecLoadInsts 30635063 # Number of load instructions executed 589system.cpu.iew.iewExecSquashedInsts 7284125 # Number of squashed instructions skipped in execute | 588system.cpu.iew.iewDispLoadInsts 33915531 # Number of dispatched load instructions 589system.cpu.iew.iewDispStoreInsts 14406995 # Number of dispatched store instructions 590system.cpu.iew.iewDispNonSpecInsts 23572 # Number of dispatched non-speculative instructions 591system.cpu.iew.iewIQFullEvents 3856 # Number of times the IQ has become full, causing a stall 592system.cpu.iew.iewLSQFullEvents 166551 # Number of times the LSQ has become full, causing a stall 593system.cpu.iew.memOrderViolationEvents 7051 # Number of memory order violations 594system.cpu.iew.predictedTakenIncorrect 3148917 # Number of branches that were predicted taken incorrectly 595system.cpu.iew.predictedNotTakenIncorrect 3246700 # Number of branches that were predicted not taken incorrectly 596system.cpu.iew.branchMispredicts 6395617 # Number of branch mispredicts detected at execute 597system.cpu.iew.iewExecutedInsts 207126816 # Number of executed instructions 598system.cpu.iew.iewExecLoadInsts 30634090 # Number of load instructions executed 599system.cpu.iew.iewExecSquashedInsts 7284075 # Number of squashed instructions skipped in execute |
| 590system.cpu.iew.exec_swp 0 # number of swp insts executed | 600system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 591system.cpu.iew.exec_nop 20034 # number of nop insts executed 592system.cpu.iew.exec_refs 43773548 # number of memory reference insts executed 593system.cpu.iew.exec_branches 44851099 # Number of branches executed 594system.cpu.iew.exec_stores 13138485 # Number of stores executed 595system.cpu.iew.exec_rate 1.217618 # Inst execution rate 596system.cpu.iew.wb_sent 206362307 # cumulative count of insts sent to commit 597system.cpu.iew.wb_count 206052365 # cumulative count of insts written-back 598system.cpu.iew.wb_producers 129396792 # num instructions producing a value 599system.cpu.iew.wb_consumers 221653711 # num instructions consuming a value 600system.cpu.iew.wb_rate 1.211339 # insts written-back per cycle 601system.cpu.iew.wb_fanout 0.583779 # average fanout of values written-back 602system.cpu.commit.commitSquashedInsts 68665439 # The number of squashed insts skipped by commit | 601system.cpu.iew.exec_nop 20125 # number of nop insts executed 602system.cpu.iew.exec_refs 43772682 # number of memory reference insts executed 603system.cpu.iew.exec_branches 44853086 # Number of branches executed 604system.cpu.iew.exec_stores 13138592 # Number of stores executed 605system.cpu.iew.exec_rate 1.203484 # Inst execution rate 606system.cpu.iew.wb_sent 206368979 # cumulative count of insts sent to commit 607system.cpu.iew.wb_count 206058922 # cumulative count of insts written-back 608system.cpu.iew.wb_producers 129395738 # num instructions producing a value 609system.cpu.iew.wb_consumers 221650226 # num instructions consuming a value 610system.cpu.iew.wb_rate 1.197279 # insts written-back per cycle 611system.cpu.iew.wb_fanout 0.583783 # average fanout of values written-back 612system.cpu.commit.commitSquashedInsts 68671574 # The number of squashed insts skipped by commit |
| 603system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards | 613system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards |
| 604system.cpu.commit.branchMispredicts 5760276 # The number of times a branch was mispredicted 605system.cpu.commit.committed_per_cycle::samples 157944348 # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::mean 1.150091 # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::stdev 1.652266 # Number of insts commited each cycle | 614system.cpu.commit.branchMispredicts 5760722 # The number of times a branch was mispredicted 615system.cpu.commit.committed_per_cycle::samples 158539716 # Number of insts commited each cycle 616system.cpu.commit.committed_per_cycle::mean 1.145772 # Number of insts commited each cycle 617system.cpu.commit.committed_per_cycle::stdev 1.650496 # Number of insts commited each cycle |
| 608system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 618system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 609system.cpu.commit.committed_per_cycle::0 73354007 46.44% 46.44% # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::1 41142542 26.05% 72.49% # Number of insts commited each cycle 611system.cpu.commit.committed_per_cycle::2 22532573 14.27% 86.76% # Number of insts commited each cycle 612system.cpu.commit.committed_per_cycle::3 9515365 6.02% 92.78% # Number of insts commited each cycle 613system.cpu.commit.committed_per_cycle::4 3551587 2.25% 95.03% # Number of insts commited each cycle 614system.cpu.commit.committed_per_cycle::5 2142504 1.36% 96.39% # Number of insts commited each cycle 615system.cpu.commit.committed_per_cycle::6 1329210 0.84% 97.23% # Number of insts commited each cycle 616system.cpu.commit.committed_per_cycle::7 1010049 0.64% 97.87% # Number of insts commited each cycle 617system.cpu.commit.committed_per_cycle::8 3366511 2.13% 100.00% # Number of insts commited each cycle | 619system.cpu.commit.committed_per_cycle::0 73944910 46.64% 46.64% # Number of insts commited each cycle 620system.cpu.commit.committed_per_cycle::1 41143540 25.95% 72.59% # Number of insts commited each cycle 621system.cpu.commit.committed_per_cycle::2 22534900 14.21% 86.81% # Number of insts commited each cycle 622system.cpu.commit.committed_per_cycle::3 9516225 6.00% 92.81% # Number of insts commited each cycle 623system.cpu.commit.committed_per_cycle::4 3553894 2.24% 95.05% # Number of insts commited each cycle 624system.cpu.commit.committed_per_cycle::5 2144247 1.35% 96.40% # Number of insts commited each cycle 625system.cpu.commit.committed_per_cycle::6 1327660 0.84% 97.24% # Number of insts commited each cycle 626system.cpu.commit.committed_per_cycle::7 1009164 0.64% 97.88% # Number of insts commited each cycle 627system.cpu.commit.committed_per_cycle::8 3365176 2.12% 100.00% # Number of insts commited each cycle |
| 618system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 619system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 620system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 628system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 629system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 630system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 621system.cpu.commit.committed_per_cycle::total 157944348 # Number of insts commited each cycle | 631system.cpu.commit.committed_per_cycle::total 158539716 # Number of insts commited each cycle |
| 622system.cpu.commit.committedInsts 172317410 # Number of instructions committed 623system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed 624system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 625system.cpu.commit.refs 40540778 # Number of memory references committed 626system.cpu.commit.loads 27896144 # Number of loads committed 627system.cpu.commit.membars 22408 # Number of memory barriers committed 628system.cpu.commit.branches 40300312 # Number of branches committed 629system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 659system.cpu.commit.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction 660system.cpu.commit.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction 661system.cpu.commit.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction 662system.cpu.commit.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction 663system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Class of committed instruction 664system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 665system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 666system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction | 632system.cpu.commit.committedInsts 172317410 # Number of instructions committed 633system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed 634system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 635system.cpu.commit.refs 40540778 # Number of memory references committed 636system.cpu.commit.loads 27896144 # Number of loads committed 637system.cpu.commit.membars 22408 # Number of memory barriers committed 638system.cpu.commit.branches 40300312 # Number of branches committed 639system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 669system.cpu.commit.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction 670system.cpu.commit.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction 671system.cpu.commit.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction 672system.cpu.commit.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction 673system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Class of committed instruction 674system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 675system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 676system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction |
| 667system.cpu.commit.bw_lim_events 3366511 # number cycles where commit BW limit reached 668system.cpu.rob.rob_reads 404888417 # The number of ROB reads 669system.cpu.rob.rob_writes 511940612 # The number of ROB writes 670system.cpu.timesIdled 9843 # Number of times that the entire CPU went into an idle state and unscheduled itself 671system.cpu.idleCycles 863529 # Total number of cycles that the CPU has spent unscheduled due to idling | 677system.cpu.commit.bw_lim_events 3365176 # number cycles where commit BW limit reached 678system.cpu.rob.rob_reads 405491255 # The number of ROB reads 679system.cpu.rob.rob_writes 511954468 # The number of ROB writes 680system.cpu.timesIdled 10012 # Number of times that the entire CPU went into an idle state and unscheduled itself 681system.cpu.idleCycles 2269736 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 672system.cpu.committedInsts 172303022 # Number of Instructions Simulated 673system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated | 682system.cpu.committedInsts 172303022 # Number of Instructions Simulated 683system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated |
| 674system.cpu.cpi 0.987232 # CPI: Cycles Per Instruction 675system.cpu.cpi_total 0.987232 # CPI: Total CPI of All Threads 676system.cpu.ipc 1.012933 # IPC: Instructions Per Cycle 677system.cpu.ipc_total 1.012933 # IPC: Total IPC of All Threads 678system.cpu.int_regfile_reads 218721236 # number of integer regfile reads 679system.cpu.int_regfile_writes 114166498 # number of integer regfile writes 680system.cpu.fp_regfile_reads 2904044 # number of floating regfile reads 681system.cpu.fp_regfile_writes 2441835 # number of floating regfile writes 682system.cpu.cc_regfile_reads 708181937 # number of cc regfile reads 683system.cpu.cc_regfile_writes 229500026 # number of cc regfile writes 684system.cpu.misc_regfile_reads 57441519 # number of misc regfile reads | 684system.cpu.cpi 0.998857 # CPI: Cycles Per Instruction 685system.cpu.cpi_total 0.998857 # CPI: Total CPI of All Threads 686system.cpu.ipc 1.001144 # IPC: Instructions Per Cycle 687system.cpu.ipc_total 1.001144 # IPC: Total IPC of All Threads 688system.cpu.int_regfile_reads 218726711 # number of integer regfile reads 689system.cpu.int_regfile_writes 114168819 # number of integer regfile writes 690system.cpu.fp_regfile_reads 2904003 # number of floating regfile reads 691system.cpu.fp_regfile_writes 2441695 # number of floating regfile writes 692system.cpu.cc_regfile_reads 708199076 # number of cc regfile reads 693system.cpu.cc_regfile_writes 229511616 # number of cc regfile writes 694system.cpu.misc_regfile_reads 57440558 # number of misc regfile reads |
| 685system.cpu.misc_regfile_writes 820036 # number of misc regfile writes | 695system.cpu.misc_regfile_writes 820036 # number of misc regfile writes |
| 686system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states 687system.cpu.dcache.tags.replacements 72593 # number of replacements 688system.cpu.dcache.tags.tagsinuse 511.410345 # Cycle average of tags in use 689system.cpu.dcache.tags.total_refs 41032184 # Total number of references to valid blocks. 690system.cpu.dcache.tags.sampled_refs 73105 # Sample count of references to valid blocks. 691system.cpu.dcache.tags.avg_refs 561.277396 # Average number of references to valid blocks. 692system.cpu.dcache.tags.warmup_cycle 509673500 # Cycle when the warmup percentage was hit. 693system.cpu.dcache.tags.occ_blocks::cpu.data 511.410345 # Average occupied blocks per requestor 694system.cpu.dcache.tags.occ_percent::cpu.data 0.998848 # Average percentage of cache occupancy 695system.cpu.dcache.tags.occ_percent::total 0.998848 # Average percentage of cache occupancy | 696system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states 697system.cpu.dcache.tags.replacements 72579 # number of replacements 698system.cpu.dcache.tags.tagsinuse 511.404028 # Cycle average of tags in use 699system.cpu.dcache.tags.total_refs 41032024 # Total number of references to valid blocks. 700system.cpu.dcache.tags.sampled_refs 73091 # Sample count of references to valid blocks. 701system.cpu.dcache.tags.avg_refs 561.382715 # Average number of references to valid blocks. 702system.cpu.dcache.tags.warmup_cycle 516933500 # Cycle when the warmup percentage was hit. 703system.cpu.dcache.tags.occ_blocks::cpu.data 511.404028 # Average occupied blocks per requestor 704system.cpu.dcache.tags.occ_percent::cpu.data 0.998836 # Average percentage of cache occupancy 705system.cpu.dcache.tags.occ_percent::total 0.998836 # Average percentage of cache occupancy |
| 696system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 706system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 697system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id 698system.cpu.dcache.tags.age_task_id_blocks_1024::1 160 # Occupied blocks per task id | 707system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 708system.cpu.dcache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id |
| 699system.cpu.dcache.tags.age_task_id_blocks_1024::2 230 # Occupied blocks per task id 700system.cpu.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id 701system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id 702system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 709system.cpu.dcache.tags.age_task_id_blocks_1024::2 230 # Occupied blocks per task id 710system.cpu.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id 711system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id 712system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 703system.cpu.dcache.tags.tag_accesses 82362697 # Number of tag accesses 704system.cpu.dcache.tags.data_accesses 82362697 # Number of data accesses 705system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states 706system.cpu.dcache.ReadReq_hits::cpu.data 28645946 # number of ReadReq hits 707system.cpu.dcache.ReadReq_hits::total 28645946 # number of ReadReq hits 708system.cpu.dcache.WriteReq_hits::cpu.data 12341320 # number of WriteReq hits 709system.cpu.dcache.WriteReq_hits::total 12341320 # number of WriteReq hits | 713system.cpu.dcache.tags.tag_accesses 82362375 # Number of tag accesses 714system.cpu.dcache.tags.data_accesses 82362375 # Number of data accesses 715system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states 716system.cpu.dcache.ReadReq_hits::cpu.data 28645802 # number of ReadReq hits 717system.cpu.dcache.ReadReq_hits::total 28645802 # number of ReadReq hits 718system.cpu.dcache.WriteReq_hits::cpu.data 12341304 # number of WriteReq hits 719system.cpu.dcache.WriteReq_hits::total 12341304 # number of WriteReq hits |
| 710system.cpu.dcache.SoftPFReq_hits::cpu.data 364 # number of SoftPFReq hits 711system.cpu.dcache.SoftPFReq_hits::total 364 # number of SoftPFReq hits 712system.cpu.dcache.LoadLockedReq_hits::cpu.data 22147 # number of LoadLockedReq hits 713system.cpu.dcache.LoadLockedReq_hits::total 22147 # number of LoadLockedReq hits 714system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits 715system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits | 720system.cpu.dcache.SoftPFReq_hits::cpu.data 364 # number of SoftPFReq hits 721system.cpu.dcache.SoftPFReq_hits::total 364 # number of SoftPFReq hits 722system.cpu.dcache.LoadLockedReq_hits::cpu.data 22147 # number of LoadLockedReq hits 723system.cpu.dcache.LoadLockedReq_hits::total 22147 # number of LoadLockedReq hits 724system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits 725system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits |
| 716system.cpu.dcache.demand_hits::cpu.data 40987266 # number of demand (read+write) hits 717system.cpu.dcache.demand_hits::total 40987266 # number of demand (read+write) hits 718system.cpu.dcache.overall_hits::cpu.data 40987630 # number of overall hits 719system.cpu.dcache.overall_hits::total 40987630 # number of overall hits 720system.cpu.dcache.ReadReq_misses::cpu.data 89269 # number of ReadReq misses 721system.cpu.dcache.ReadReq_misses::total 89269 # number of ReadReq misses 722system.cpu.dcache.WriteReq_misses::cpu.data 22967 # number of WriteReq misses 723system.cpu.dcache.WriteReq_misses::total 22967 # number of WriteReq misses | 726system.cpu.dcache.demand_hits::cpu.data 40987106 # number of demand (read+write) hits 727system.cpu.dcache.demand_hits::total 40987106 # number of demand (read+write) hits 728system.cpu.dcache.overall_hits::cpu.data 40987470 # number of overall hits 729system.cpu.dcache.overall_hits::total 40987470 # number of overall hits 730system.cpu.dcache.ReadReq_misses::cpu.data 89259 # number of ReadReq misses 731system.cpu.dcache.ReadReq_misses::total 89259 # number of ReadReq misses 732system.cpu.dcache.WriteReq_misses::cpu.data 22983 # number of WriteReq misses 733system.cpu.dcache.WriteReq_misses::total 22983 # number of WriteReq misses |
| 724system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses 725system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses 726system.cpu.dcache.LoadLockedReq_misses::cpu.data 260 # number of LoadLockedReq misses 727system.cpu.dcache.LoadLockedReq_misses::total 260 # number of LoadLockedReq misses | 734system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses 735system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses 736system.cpu.dcache.LoadLockedReq_misses::cpu.data 260 # number of LoadLockedReq misses 737system.cpu.dcache.LoadLockedReq_misses::total 260 # number of LoadLockedReq misses |
| 728system.cpu.dcache.demand_misses::cpu.data 112236 # number of demand (read+write) misses 729system.cpu.dcache.demand_misses::total 112236 # number of demand (read+write) misses 730system.cpu.dcache.overall_misses::cpu.data 112352 # number of overall misses 731system.cpu.dcache.overall_misses::total 112352 # number of overall misses 732system.cpu.dcache.ReadReq_miss_latency::cpu.data 1192862000 # number of ReadReq miss cycles 733system.cpu.dcache.ReadReq_miss_latency::total 1192862000 # number of ReadReq miss cycles 734system.cpu.dcache.WriteReq_miss_latency::cpu.data 244207999 # number of WriteReq miss cycles 735system.cpu.dcache.WriteReq_miss_latency::total 244207999 # number of WriteReq miss cycles 736system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2309000 # number of LoadLockedReq miss cycles 737system.cpu.dcache.LoadLockedReq_miss_latency::total 2309000 # number of LoadLockedReq miss cycles 738system.cpu.dcache.demand_miss_latency::cpu.data 1437069999 # number of demand (read+write) miss cycles 739system.cpu.dcache.demand_miss_latency::total 1437069999 # number of demand (read+write) miss cycles 740system.cpu.dcache.overall_miss_latency::cpu.data 1437069999 # number of overall miss cycles 741system.cpu.dcache.overall_miss_latency::total 1437069999 # number of overall miss cycles 742system.cpu.dcache.ReadReq_accesses::cpu.data 28735215 # number of ReadReq accesses(hits+misses) 743system.cpu.dcache.ReadReq_accesses::total 28735215 # number of ReadReq accesses(hits+misses) | 738system.cpu.dcache.demand_misses::cpu.data 112242 # number of demand (read+write) misses 739system.cpu.dcache.demand_misses::total 112242 # number of demand (read+write) misses 740system.cpu.dcache.overall_misses::cpu.data 112358 # number of overall misses 741system.cpu.dcache.overall_misses::total 112358 # number of overall misses 742system.cpu.dcache.ReadReq_miss_latency::cpu.data 1986737500 # number of ReadReq miss cycles 743system.cpu.dcache.ReadReq_miss_latency::total 1986737500 # number of ReadReq miss cycles 744system.cpu.dcache.WriteReq_miss_latency::cpu.data 247540999 # number of WriteReq miss cycles 745system.cpu.dcache.WriteReq_miss_latency::total 247540999 # number of WriteReq miss cycles 746system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2316500 # number of LoadLockedReq miss cycles 747system.cpu.dcache.LoadLockedReq_miss_latency::total 2316500 # number of LoadLockedReq miss cycles 748system.cpu.dcache.demand_miss_latency::cpu.data 2234278499 # number of demand (read+write) miss cycles 749system.cpu.dcache.demand_miss_latency::total 2234278499 # number of demand (read+write) miss cycles 750system.cpu.dcache.overall_miss_latency::cpu.data 2234278499 # number of overall miss cycles 751system.cpu.dcache.overall_miss_latency::total 2234278499 # number of overall miss cycles 752system.cpu.dcache.ReadReq_accesses::cpu.data 28735061 # number of ReadReq accesses(hits+misses) 753system.cpu.dcache.ReadReq_accesses::total 28735061 # number of ReadReq accesses(hits+misses) |
| 744system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 745system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) 746system.cpu.dcache.SoftPFReq_accesses::cpu.data 480 # number of SoftPFReq accesses(hits+misses) 747system.cpu.dcache.SoftPFReq_accesses::total 480 # number of SoftPFReq accesses(hits+misses) 748system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) 749system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) 750system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) 751system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) | 754system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 755system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) 756system.cpu.dcache.SoftPFReq_accesses::cpu.data 480 # number of SoftPFReq accesses(hits+misses) 757system.cpu.dcache.SoftPFReq_accesses::total 480 # number of SoftPFReq accesses(hits+misses) 758system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) 759system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) 760system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) 761system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) |
| 752system.cpu.dcache.demand_accesses::cpu.data 41099502 # number of demand (read+write) accesses 753system.cpu.dcache.demand_accesses::total 41099502 # number of demand (read+write) accesses 754system.cpu.dcache.overall_accesses::cpu.data 41099982 # number of overall (read+write) accesses 755system.cpu.dcache.overall_accesses::total 41099982 # number of overall (read+write) accesses 756system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003107 # miss rate for ReadReq accesses 757system.cpu.dcache.ReadReq_miss_rate::total 0.003107 # miss rate for ReadReq accesses 758system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001858 # miss rate for WriteReq accesses 759system.cpu.dcache.WriteReq_miss_rate::total 0.001858 # miss rate for WriteReq accesses | 762system.cpu.dcache.demand_accesses::cpu.data 41099348 # number of demand (read+write) accesses 763system.cpu.dcache.demand_accesses::total 41099348 # number of demand (read+write) accesses 764system.cpu.dcache.overall_accesses::cpu.data 41099828 # number of overall (read+write) accesses 765system.cpu.dcache.overall_accesses::total 41099828 # number of overall (read+write) accesses 766system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003106 # miss rate for ReadReq accesses 767system.cpu.dcache.ReadReq_miss_rate::total 0.003106 # miss rate for ReadReq accesses 768system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001859 # miss rate for WriteReq accesses 769system.cpu.dcache.WriteReq_miss_rate::total 0.001859 # miss rate for WriteReq accesses |
| 760system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.241667 # miss rate for SoftPFReq accesses 761system.cpu.dcache.SoftPFReq_miss_rate::total 0.241667 # miss rate for SoftPFReq accesses 762system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011604 # miss rate for LoadLockedReq accesses 763system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011604 # miss rate for LoadLockedReq accesses 764system.cpu.dcache.demand_miss_rate::cpu.data 0.002731 # miss rate for demand accesses 765system.cpu.dcache.demand_miss_rate::total 0.002731 # miss rate for demand accesses 766system.cpu.dcache.overall_miss_rate::cpu.data 0.002734 # miss rate for overall accesses 767system.cpu.dcache.overall_miss_rate::total 0.002734 # miss rate for overall accesses | 770system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.241667 # miss rate for SoftPFReq accesses 771system.cpu.dcache.SoftPFReq_miss_rate::total 0.241667 # miss rate for SoftPFReq accesses 772system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011604 # miss rate for LoadLockedReq accesses 773system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011604 # miss rate for LoadLockedReq accesses 774system.cpu.dcache.demand_miss_rate::cpu.data 0.002731 # miss rate for demand accesses 775system.cpu.dcache.demand_miss_rate::total 0.002731 # miss rate for demand accesses 776system.cpu.dcache.overall_miss_rate::cpu.data 0.002734 # miss rate for overall accesses 777system.cpu.dcache.overall_miss_rate::total 0.002734 # miss rate for overall accesses |
| 768system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13362.555870 # average ReadReq miss latency 769system.cpu.dcache.ReadReq_avg_miss_latency::total 13362.555870 # average ReadReq miss latency 770system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10632.995123 # average WriteReq miss latency 771system.cpu.dcache.WriteReq_avg_miss_latency::total 10632.995123 # average WriteReq miss latency 772system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8880.769231 # average LoadLockedReq miss latency 773system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8880.769231 # average LoadLockedReq miss latency 774system.cpu.dcache.demand_avg_miss_latency::cpu.data 12804.002272 # average overall miss latency 775system.cpu.dcache.demand_avg_miss_latency::total 12804.002272 # average overall miss latency 776system.cpu.dcache.overall_avg_miss_latency::cpu.data 12790.782532 # average overall miss latency 777system.cpu.dcache.overall_avg_miss_latency::total 12790.782532 # average overall miss latency 778system.cpu.dcache.blocked_cycles::no_mshrs 168 # number of cycles access was blocked 779system.cpu.dcache.blocked_cycles::no_targets 10626 # number of cycles access was blocked | 778system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22258.119629 # average ReadReq miss latency 779system.cpu.dcache.ReadReq_avg_miss_latency::total 22258.119629 # average ReadReq miss latency 780system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10770.613018 # average WriteReq miss latency 781system.cpu.dcache.WriteReq_avg_miss_latency::total 10770.613018 # average WriteReq miss latency 782system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8909.615385 # average LoadLockedReq miss latency 783system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8909.615385 # average LoadLockedReq miss latency 784system.cpu.dcache.demand_avg_miss_latency::cpu.data 19905.904198 # average overall miss latency 785system.cpu.dcache.demand_avg_miss_latency::total 19905.904198 # average overall miss latency 786system.cpu.dcache.overall_avg_miss_latency::cpu.data 19885.353059 # average overall miss latency 787system.cpu.dcache.overall_avg_miss_latency::total 19885.353059 # average overall miss latency 788system.cpu.dcache.blocked_cycles::no_mshrs 180 # number of cycles access was blocked 789system.cpu.dcache.blocked_cycles::no_targets 11288 # number of cycles access was blocked |
| 780system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked | 790system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked |
| 781system.cpu.dcache.blocked::no_targets 868 # number of cycles access was blocked 782system.cpu.dcache.avg_blocked_cycles::no_mshrs 84 # average number of cycles each access was blocked 783system.cpu.dcache.avg_blocked_cycles::no_targets 12.241935 # average number of cycles each access was blocked 784system.cpu.dcache.writebacks::writebacks 72593 # number of writebacks 785system.cpu.dcache.writebacks::total 72593 # number of writebacks 786system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24834 # number of ReadReq MSHR hits 787system.cpu.dcache.ReadReq_mshr_hits::total 24834 # number of ReadReq MSHR hits 788system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14410 # number of WriteReq MSHR hits 789system.cpu.dcache.WriteReq_mshr_hits::total 14410 # number of WriteReq MSHR hits | 791system.cpu.dcache.blocked::no_targets 865 # number of cycles access was blocked 792system.cpu.dcache.avg_blocked_cycles::no_mshrs 90 # average number of cycles each access was blocked 793system.cpu.dcache.avg_blocked_cycles::no_targets 13.049711 # average number of cycles each access was blocked 794system.cpu.dcache.writebacks::writebacks 72579 # number of writebacks 795system.cpu.dcache.writebacks::total 72579 # number of writebacks 796system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24837 # number of ReadReq MSHR hits 797system.cpu.dcache.ReadReq_mshr_hits::total 24837 # number of ReadReq MSHR hits 798system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14427 # number of WriteReq MSHR hits 799system.cpu.dcache.WriteReq_mshr_hits::total 14427 # number of WriteReq MSHR hits |
| 790system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 260 # number of LoadLockedReq MSHR hits 791system.cpu.dcache.LoadLockedReq_mshr_hits::total 260 # number of LoadLockedReq MSHR hits | 800system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 260 # number of LoadLockedReq MSHR hits 801system.cpu.dcache.LoadLockedReq_mshr_hits::total 260 # number of LoadLockedReq MSHR hits |
| 792system.cpu.dcache.demand_mshr_hits::cpu.data 39244 # number of demand (read+write) MSHR hits 793system.cpu.dcache.demand_mshr_hits::total 39244 # number of demand (read+write) MSHR hits 794system.cpu.dcache.overall_mshr_hits::cpu.data 39244 # number of overall MSHR hits 795system.cpu.dcache.overall_mshr_hits::total 39244 # number of overall MSHR hits 796system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64435 # number of ReadReq MSHR misses 797system.cpu.dcache.ReadReq_mshr_misses::total 64435 # number of ReadReq MSHR misses 798system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8557 # number of WriteReq MSHR misses 799system.cpu.dcache.WriteReq_mshr_misses::total 8557 # number of WriteReq MSHR misses | 802system.cpu.dcache.demand_mshr_hits::cpu.data 39264 # number of demand (read+write) MSHR hits 803system.cpu.dcache.demand_mshr_hits::total 39264 # number of demand (read+write) MSHR hits 804system.cpu.dcache.overall_mshr_hits::cpu.data 39264 # number of overall MSHR hits 805system.cpu.dcache.overall_mshr_hits::total 39264 # number of overall MSHR hits 806system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64422 # number of ReadReq MSHR misses 807system.cpu.dcache.ReadReq_mshr_misses::total 64422 # number of ReadReq MSHR misses 808system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8556 # number of WriteReq MSHR misses 809system.cpu.dcache.WriteReq_mshr_misses::total 8556 # number of WriteReq MSHR misses |
| 800system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 113 # number of SoftPFReq MSHR misses 801system.cpu.dcache.SoftPFReq_mshr_misses::total 113 # number of SoftPFReq MSHR misses | 810system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 113 # number of SoftPFReq MSHR misses 811system.cpu.dcache.SoftPFReq_mshr_misses::total 113 # number of SoftPFReq MSHR misses |
| 802system.cpu.dcache.demand_mshr_misses::cpu.data 72992 # number of demand (read+write) MSHR misses 803system.cpu.dcache.demand_mshr_misses::total 72992 # number of demand (read+write) MSHR misses 804system.cpu.dcache.overall_mshr_misses::cpu.data 73105 # number of overall MSHR misses 805system.cpu.dcache.overall_mshr_misses::total 73105 # number of overall MSHR misses 806system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 724757000 # number of ReadReq MSHR miss cycles 807system.cpu.dcache.ReadReq_mshr_miss_latency::total 724757000 # number of ReadReq MSHR miss cycles 808system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85765499 # number of WriteReq MSHR miss cycles 809system.cpu.dcache.WriteReq_mshr_miss_latency::total 85765499 # number of WriteReq MSHR miss cycles 810system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 963000 # number of SoftPFReq MSHR miss cycles 811system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 963000 # number of SoftPFReq MSHR miss cycles 812system.cpu.dcache.demand_mshr_miss_latency::cpu.data 810522499 # number of demand (read+write) MSHR miss cycles 813system.cpu.dcache.demand_mshr_miss_latency::total 810522499 # number of demand (read+write) MSHR miss cycles 814system.cpu.dcache.overall_mshr_miss_latency::cpu.data 811485499 # number of overall MSHR miss cycles 815system.cpu.dcache.overall_mshr_miss_latency::total 811485499 # number of overall MSHR miss cycles | 812system.cpu.dcache.demand_mshr_misses::cpu.data 72978 # number of demand (read+write) MSHR misses 813system.cpu.dcache.demand_mshr_misses::total 72978 # number of demand (read+write) MSHR misses 814system.cpu.dcache.overall_mshr_misses::cpu.data 73091 # number of overall MSHR misses 815system.cpu.dcache.overall_mshr_misses::total 73091 # number of overall MSHR misses 816system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1062843500 # number of ReadReq MSHR miss cycles 817system.cpu.dcache.ReadReq_mshr_miss_latency::total 1062843500 # number of ReadReq MSHR miss cycles 818system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 87501999 # number of WriteReq MSHR miss cycles 819system.cpu.dcache.WriteReq_mshr_miss_latency::total 87501999 # number of WriteReq MSHR miss cycles 820system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 969000 # number of SoftPFReq MSHR miss cycles 821system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 969000 # number of SoftPFReq MSHR miss cycles 822system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1150345499 # number of demand (read+write) MSHR miss cycles 823system.cpu.dcache.demand_mshr_miss_latency::total 1150345499 # number of demand (read+write) MSHR miss cycles 824system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1151314499 # number of overall MSHR miss cycles 825system.cpu.dcache.overall_mshr_miss_latency::total 1151314499 # number of overall MSHR miss cycles |
| 816system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002242 # mshr miss rate for ReadReq accesses 817system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002242 # mshr miss rate for ReadReq accesses 818system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses 819system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000692 # mshr miss rate for WriteReq accesses 820system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.235417 # mshr miss rate for SoftPFReq accesses 821system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.235417 # mshr miss rate for SoftPFReq accesses 822system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001776 # mshr miss rate for demand accesses 823system.cpu.dcache.demand_mshr_miss_rate::total 0.001776 # mshr miss rate for demand accesses | 826system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002242 # mshr miss rate for ReadReq accesses 827system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002242 # mshr miss rate for ReadReq accesses 828system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses 829system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000692 # mshr miss rate for WriteReq accesses 830system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.235417 # mshr miss rate for SoftPFReq accesses 831system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.235417 # mshr miss rate for SoftPFReq accesses 832system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001776 # mshr miss rate for demand accesses 833system.cpu.dcache.demand_mshr_miss_rate::total 0.001776 # mshr miss rate for demand accesses |
| 824system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001779 # mshr miss rate for overall accesses 825system.cpu.dcache.overall_mshr_miss_rate::total 0.001779 # mshr miss rate for overall accesses 826system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11247.877706 # average ReadReq mshr miss latency 827system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11247.877706 # average ReadReq mshr miss latency 828system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10022.846675 # average WriteReq mshr miss latency 829system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10022.846675 # average WriteReq mshr miss latency 830system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8522.123894 # average SoftPFReq mshr miss latency 831system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8522.123894 # average SoftPFReq mshr miss latency 832system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11104.264837 # average overall mshr miss latency 833system.cpu.dcache.demand_avg_mshr_miss_latency::total 11104.264837 # average overall mshr miss latency 834system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11100.273565 # average overall mshr miss latency 835system.cpu.dcache.overall_avg_mshr_miss_latency::total 11100.273565 # average overall mshr miss latency 836system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states 837system.cpu.icache.tags.replacements 53637 # number of replacements 838system.cpu.icache.tags.tagsinuse 510.592571 # Cycle average of tags in use 839system.cpu.icache.tags.total_refs 78276090 # Total number of references to valid blocks. 840system.cpu.icache.tags.sampled_refs 54149 # Sample count of references to valid blocks. 841system.cpu.icache.tags.avg_refs 1445.568524 # Average number of references to valid blocks. 842system.cpu.icache.tags.warmup_cycle 84288957500 # Cycle when the warmup percentage was hit. 843system.cpu.icache.tags.occ_blocks::cpu.inst 510.592571 # Average occupied blocks per requestor 844system.cpu.icache.tags.occ_percent::cpu.inst 0.997251 # Average percentage of cache occupancy 845system.cpu.icache.tags.occ_percent::total 0.997251 # Average percentage of cache occupancy | 834system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001778 # mshr miss rate for overall accesses 835system.cpu.dcache.overall_mshr_miss_rate::total 0.001778 # mshr miss rate for overall accesses 836system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16498.145044 # average ReadReq mshr miss latency 837system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16498.145044 # average ReadReq mshr miss latency 838system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10226.975105 # average WriteReq mshr miss latency 839system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10226.975105 # average WriteReq mshr miss latency 840system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8575.221239 # average SoftPFReq mshr miss latency 841system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8575.221239 # average SoftPFReq mshr miss latency 842system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15762.907986 # average overall mshr miss latency 843system.cpu.dcache.demand_avg_mshr_miss_latency::total 15762.907986 # average overall mshr miss latency 844system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15751.795693 # average overall mshr miss latency 845system.cpu.dcache.overall_avg_mshr_miss_latency::total 15751.795693 # average overall mshr miss latency 846system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states 847system.cpu.icache.tags.replacements 53612 # number of replacements 848system.cpu.icache.tags.tagsinuse 510.587809 # Cycle average of tags in use 849system.cpu.icache.tags.total_refs 78268729 # Total number of references to valid blocks. 850system.cpu.icache.tags.sampled_refs 54124 # Sample count of references to valid blocks. 851system.cpu.icache.tags.avg_refs 1446.100233 # Average number of references to valid blocks. 852system.cpu.icache.tags.warmup_cycle 85282294500 # Cycle when the warmup percentage was hit. 853system.cpu.icache.tags.occ_blocks::cpu.inst 510.587809 # Average occupied blocks per requestor 854system.cpu.icache.tags.occ_percent::cpu.inst 0.997242 # Average percentage of cache occupancy 855system.cpu.icache.tags.occ_percent::total 0.997242 # Average percentage of cache occupancy |
| 846system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 856system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 847system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id | 857system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id |
| 848system.cpu.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id | 858system.cpu.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id |
| 849system.cpu.icache.tags.age_task_id_blocks_1024::2 278 # Occupied blocks per task id | 859system.cpu.icache.tags.age_task_id_blocks_1024::2 277 # Occupied blocks per task id |
| 850system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 851system.cpu.icache.tags.age_task_id_blocks_1024::4 49 # Occupied blocks per task id 852system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 860system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 861system.cpu.icache.tags.age_task_id_blocks_1024::4 49 # Occupied blocks per task id 862system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 853system.cpu.icache.tags.tag_accesses 156721475 # Number of tag accesses 854system.cpu.icache.tags.data_accesses 156721475 # Number of data accesses 855system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states 856system.cpu.icache.ReadReq_hits::cpu.inst 78276090 # number of ReadReq hits 857system.cpu.icache.ReadReq_hits::total 78276090 # number of ReadReq hits 858system.cpu.icache.demand_hits::cpu.inst 78276090 # number of demand (read+write) hits 859system.cpu.icache.demand_hits::total 78276090 # number of demand (read+write) hits 860system.cpu.icache.overall_hits::cpu.inst 78276090 # number of overall hits 861system.cpu.icache.overall_hits::total 78276090 # number of overall hits 862system.cpu.icache.ReadReq_misses::cpu.inst 57573 # number of ReadReq misses 863system.cpu.icache.ReadReq_misses::total 57573 # number of ReadReq misses 864system.cpu.icache.demand_misses::cpu.inst 57573 # number of demand (read+write) misses 865system.cpu.icache.demand_misses::total 57573 # number of demand (read+write) misses 866system.cpu.icache.overall_misses::cpu.inst 57573 # number of overall misses 867system.cpu.icache.overall_misses::total 57573 # number of overall misses 868system.cpu.icache.ReadReq_miss_latency::cpu.inst 1245757924 # number of ReadReq miss cycles 869system.cpu.icache.ReadReq_miss_latency::total 1245757924 # number of ReadReq miss cycles 870system.cpu.icache.demand_miss_latency::cpu.inst 1245757924 # number of demand (read+write) miss cycles 871system.cpu.icache.demand_miss_latency::total 1245757924 # number of demand (read+write) miss cycles 872system.cpu.icache.overall_miss_latency::cpu.inst 1245757924 # number of overall miss cycles 873system.cpu.icache.overall_miss_latency::total 1245757924 # number of overall miss cycles 874system.cpu.icache.ReadReq_accesses::cpu.inst 78333663 # number of ReadReq accesses(hits+misses) 875system.cpu.icache.ReadReq_accesses::total 78333663 # number of ReadReq accesses(hits+misses) 876system.cpu.icache.demand_accesses::cpu.inst 78333663 # number of demand (read+write) accesses 877system.cpu.icache.demand_accesses::total 78333663 # number of demand (read+write) accesses 878system.cpu.icache.overall_accesses::cpu.inst 78333663 # number of overall (read+write) accesses 879system.cpu.icache.overall_accesses::total 78333663 # number of overall (read+write) accesses 880system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000735 # miss rate for ReadReq accesses 881system.cpu.icache.ReadReq_miss_rate::total 0.000735 # miss rate for ReadReq accesses 882system.cpu.icache.demand_miss_rate::cpu.inst 0.000735 # miss rate for demand accesses 883system.cpu.icache.demand_miss_rate::total 0.000735 # miss rate for demand accesses 884system.cpu.icache.overall_miss_rate::cpu.inst 0.000735 # miss rate for overall accesses 885system.cpu.icache.overall_miss_rate::total 0.000735 # miss rate for overall accesses 886system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21637.884494 # average ReadReq miss latency 887system.cpu.icache.ReadReq_avg_miss_latency::total 21637.884494 # average ReadReq miss latency 888system.cpu.icache.demand_avg_miss_latency::cpu.inst 21637.884494 # average overall miss latency 889system.cpu.icache.demand_avg_miss_latency::total 21637.884494 # average overall miss latency 890system.cpu.icache.overall_avg_miss_latency::cpu.inst 21637.884494 # average overall miss latency 891system.cpu.icache.overall_avg_miss_latency::total 21637.884494 # average overall miss latency 892system.cpu.icache.blocked_cycles::no_mshrs 76503 # number of cycles access was blocked 893system.cpu.icache.blocked_cycles::no_targets 31 # number of cycles access was blocked 894system.cpu.icache.blocked::no_mshrs 3201 # number of cycles access was blocked | 863system.cpu.icache.tags.tag_accesses 156706996 # Number of tag accesses 864system.cpu.icache.tags.data_accesses 156706996 # Number of data accesses 865system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states 866system.cpu.icache.ReadReq_hits::cpu.inst 78268729 # number of ReadReq hits 867system.cpu.icache.ReadReq_hits::total 78268729 # number of ReadReq hits 868system.cpu.icache.demand_hits::cpu.inst 78268729 # number of demand (read+write) hits 869system.cpu.icache.demand_hits::total 78268729 # number of demand (read+write) hits 870system.cpu.icache.overall_hits::cpu.inst 78268729 # number of overall hits 871system.cpu.icache.overall_hits::total 78268729 # number of overall hits 872system.cpu.icache.ReadReq_misses::cpu.inst 57707 # number of ReadReq misses 873system.cpu.icache.ReadReq_misses::total 57707 # number of ReadReq misses 874system.cpu.icache.demand_misses::cpu.inst 57707 # number of demand (read+write) misses 875system.cpu.icache.demand_misses::total 57707 # number of demand (read+write) misses 876system.cpu.icache.overall_misses::cpu.inst 57707 # number of overall misses 877system.cpu.icache.overall_misses::total 57707 # number of overall misses 878system.cpu.icache.ReadReq_miss_latency::cpu.inst 2245995927 # number of ReadReq miss cycles 879system.cpu.icache.ReadReq_miss_latency::total 2245995927 # number of ReadReq miss cycles 880system.cpu.icache.demand_miss_latency::cpu.inst 2245995927 # number of demand (read+write) miss cycles 881system.cpu.icache.demand_miss_latency::total 2245995927 # number of demand (read+write) miss cycles 882system.cpu.icache.overall_miss_latency::cpu.inst 2245995927 # number of overall miss cycles 883system.cpu.icache.overall_miss_latency::total 2245995927 # number of overall miss cycles 884system.cpu.icache.ReadReq_accesses::cpu.inst 78326436 # number of ReadReq accesses(hits+misses) 885system.cpu.icache.ReadReq_accesses::total 78326436 # number of ReadReq accesses(hits+misses) 886system.cpu.icache.demand_accesses::cpu.inst 78326436 # number of demand (read+write) accesses 887system.cpu.icache.demand_accesses::total 78326436 # number of demand (read+write) accesses 888system.cpu.icache.overall_accesses::cpu.inst 78326436 # number of overall (read+write) accesses 889system.cpu.icache.overall_accesses::total 78326436 # number of overall (read+write) accesses 890system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000737 # miss rate for ReadReq accesses 891system.cpu.icache.ReadReq_miss_rate::total 0.000737 # miss rate for ReadReq accesses 892system.cpu.icache.demand_miss_rate::cpu.inst 0.000737 # miss rate for demand accesses 893system.cpu.icache.demand_miss_rate::total 0.000737 # miss rate for demand accesses 894system.cpu.icache.overall_miss_rate::cpu.inst 0.000737 # miss rate for overall accesses 895system.cpu.icache.overall_miss_rate::total 0.000737 # miss rate for overall accesses 896system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38920.684267 # average ReadReq miss latency 897system.cpu.icache.ReadReq_avg_miss_latency::total 38920.684267 # average ReadReq miss latency 898system.cpu.icache.demand_avg_miss_latency::cpu.inst 38920.684267 # average overall miss latency 899system.cpu.icache.demand_avg_miss_latency::total 38920.684267 # average overall miss latency 900system.cpu.icache.overall_avg_miss_latency::cpu.inst 38920.684267 # average overall miss latency 901system.cpu.icache.overall_avg_miss_latency::total 38920.684267 # average overall miss latency 902system.cpu.icache.blocked_cycles::no_mshrs 93822 # number of cycles access was blocked 903system.cpu.icache.blocked_cycles::no_targets 55 # number of cycles access was blocked 904system.cpu.icache.blocked::no_mshrs 3270 # number of cycles access was blocked |
| 895system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked | 905system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked |
| 896system.cpu.icache.avg_blocked_cycles::no_mshrs 23.899719 # average number of cycles each access was blocked 897system.cpu.icache.avg_blocked_cycles::no_targets 15.500000 # average number of cycles each access was blocked 898system.cpu.icache.writebacks::writebacks 53637 # number of writebacks 899system.cpu.icache.writebacks::total 53637 # number of writebacks 900system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3423 # number of ReadReq MSHR hits 901system.cpu.icache.ReadReq_mshr_hits::total 3423 # number of ReadReq MSHR hits 902system.cpu.icache.demand_mshr_hits::cpu.inst 3423 # number of demand (read+write) MSHR hits 903system.cpu.icache.demand_mshr_hits::total 3423 # number of demand (read+write) MSHR hits 904system.cpu.icache.overall_mshr_hits::cpu.inst 3423 # number of overall MSHR hits 905system.cpu.icache.overall_mshr_hits::total 3423 # number of overall MSHR hits 906system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54150 # number of ReadReq MSHR misses 907system.cpu.icache.ReadReq_mshr_misses::total 54150 # number of ReadReq MSHR misses 908system.cpu.icache.demand_mshr_misses::cpu.inst 54150 # number of demand (read+write) MSHR misses 909system.cpu.icache.demand_mshr_misses::total 54150 # number of demand (read+write) MSHR misses 910system.cpu.icache.overall_mshr_misses::cpu.inst 54150 # number of overall MSHR misses 911system.cpu.icache.overall_mshr_misses::total 54150 # number of overall MSHR misses 912system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1124811450 # number of ReadReq MSHR miss cycles 913system.cpu.icache.ReadReq_mshr_miss_latency::total 1124811450 # number of ReadReq MSHR miss cycles 914system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1124811450 # number of demand (read+write) MSHR miss cycles 915system.cpu.icache.demand_mshr_miss_latency::total 1124811450 # number of demand (read+write) MSHR miss cycles 916system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1124811450 # number of overall MSHR miss cycles 917system.cpu.icache.overall_mshr_miss_latency::total 1124811450 # number of overall MSHR miss cycles | 906system.cpu.icache.avg_blocked_cycles::no_mshrs 28.691743 # average number of cycles each access was blocked 907system.cpu.icache.avg_blocked_cycles::no_targets 27.500000 # average number of cycles each access was blocked 908system.cpu.icache.writebacks::writebacks 53612 # number of writebacks 909system.cpu.icache.writebacks::total 53612 # number of writebacks 910system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3582 # number of ReadReq MSHR hits 911system.cpu.icache.ReadReq_mshr_hits::total 3582 # number of ReadReq MSHR hits 912system.cpu.icache.demand_mshr_hits::cpu.inst 3582 # number of demand (read+write) MSHR hits 913system.cpu.icache.demand_mshr_hits::total 3582 # number of demand (read+write) MSHR hits 914system.cpu.icache.overall_mshr_hits::cpu.inst 3582 # number of overall MSHR hits 915system.cpu.icache.overall_mshr_hits::total 3582 # number of overall MSHR hits 916system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54125 # number of ReadReq MSHR misses 917system.cpu.icache.ReadReq_mshr_misses::total 54125 # number of ReadReq MSHR misses 918system.cpu.icache.demand_mshr_misses::cpu.inst 54125 # number of demand (read+write) MSHR misses 919system.cpu.icache.demand_mshr_misses::total 54125 # number of demand (read+write) MSHR misses 920system.cpu.icache.overall_mshr_misses::cpu.inst 54125 # number of overall MSHR misses 921system.cpu.icache.overall_mshr_misses::total 54125 # number of overall MSHR misses 922system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2049967950 # number of ReadReq MSHR miss cycles 923system.cpu.icache.ReadReq_mshr_miss_latency::total 2049967950 # number of ReadReq MSHR miss cycles 924system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2049967950 # number of demand (read+write) MSHR miss cycles 925system.cpu.icache.demand_mshr_miss_latency::total 2049967950 # number of demand (read+write) MSHR miss cycles 926system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2049967950 # number of overall MSHR miss cycles 927system.cpu.icache.overall_mshr_miss_latency::total 2049967950 # number of overall MSHR miss cycles |
| 918system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for ReadReq accesses 919system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000691 # mshr miss rate for ReadReq accesses 920system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for demand accesses 921system.cpu.icache.demand_mshr_miss_rate::total 0.000691 # mshr miss rate for demand accesses 922system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for overall accesses 923system.cpu.icache.overall_mshr_miss_rate::total 0.000691 # mshr miss rate for overall accesses | 928system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for ReadReq accesses 929system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000691 # mshr miss rate for ReadReq accesses 930system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for demand accesses 931system.cpu.icache.demand_mshr_miss_rate::total 0.000691 # mshr miss rate for demand accesses 932system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for overall accesses 933system.cpu.icache.overall_mshr_miss_rate::total 0.000691 # mshr miss rate for overall accesses |
| 924system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20772.141274 # average ReadReq mshr miss latency 925system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20772.141274 # average ReadReq mshr miss latency 926system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20772.141274 # average overall mshr miss latency 927system.cpu.icache.demand_avg_mshr_miss_latency::total 20772.141274 # average overall mshr miss latency 928system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20772.141274 # average overall mshr miss latency 929system.cpu.icache.overall_avg_mshr_miss_latency::total 20772.141274 # average overall mshr miss latency 930system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states 931system.cpu.l2cache.prefetcher.num_hwpf_issued 9324 # number of hwpf issued 932system.cpu.l2cache.prefetcher.pfIdentified 9324 # number of prefetch candidates identified | 934system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37874.696536 # average ReadReq mshr miss latency 935system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37874.696536 # average ReadReq mshr miss latency 936system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37874.696536 # average overall mshr miss latency 937system.cpu.icache.demand_avg_mshr_miss_latency::total 37874.696536 # average overall mshr miss latency 938system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37874.696536 # average overall mshr miss latency 939system.cpu.icache.overall_avg_mshr_miss_latency::total 37874.696536 # average overall mshr miss latency 940system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states 941system.cpu.l2cache.prefetcher.num_hwpf_issued 9207 # number of hwpf issued 942system.cpu.l2cache.prefetcher.pfIdentified 9207 # number of prefetch candidates identified |
| 933system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 934system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 935system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 943system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 944system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 945system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 936system.cpu.l2cache.prefetcher.pfSpanPage 1388 # number of prefetches not generated due to page crossing 937system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states | 946system.cpu.l2cache.prefetcher.pfSpanPage 1345 # number of prefetches not generated due to page crossing 947system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states |
| 938system.cpu.l2cache.tags.replacements 0 # number of replacements | 948system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 939system.cpu.l2cache.tags.tagsinuse 1802.479960 # Cycle average of tags in use 940system.cpu.l2cache.tags.total_refs 99008 # Total number of references to valid blocks. 941system.cpu.l2cache.tags.sampled_refs 2827 # Sample count of references to valid blocks. 942system.cpu.l2cache.tags.avg_refs 35.022285 # Average number of references to valid blocks. | 949system.cpu.l2cache.tags.tagsinuse 1792.687270 # Cycle average of tags in use 950system.cpu.l2cache.tags.total_refs 99060 # Total number of references to valid blocks. 951system.cpu.l2cache.tags.sampled_refs 2834 # Sample count of references to valid blocks. 952system.cpu.l2cache.tags.avg_refs 34.954128 # Average number of references to valid blocks. |
| 943system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 953system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 944system.cpu.l2cache.tags.occ_blocks::writebacks 1726.446772 # Average occupied blocks per requestor 945system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 76.033188 # Average occupied blocks per requestor 946system.cpu.l2cache.tags.occ_percent::writebacks 0.105374 # Average percentage of cache occupancy 947system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004641 # Average percentage of cache occupancy 948system.cpu.l2cache.tags.occ_percent::total 0.110015 # Average percentage of cache occupancy 949system.cpu.l2cache.tags.occ_task_id_blocks::1022 121 # Occupied blocks per task id | 954system.cpu.l2cache.tags.occ_blocks::writebacks 1727.437863 # Average occupied blocks per requestor 955system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 65.249406 # Average occupied blocks per requestor 956system.cpu.l2cache.tags.occ_percent::writebacks 0.105434 # Average percentage of cache occupancy 957system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.003983 # Average percentage of cache occupancy 958system.cpu.l2cache.tags.occ_percent::total 0.109417 # Average percentage of cache occupancy 959system.cpu.l2cache.tags.occ_task_id_blocks::1022 128 # Occupied blocks per task id |
| 950system.cpu.l2cache.tags.occ_task_id_blocks::1024 2706 # Occupied blocks per task id | 960system.cpu.l2cache.tags.occ_task_id_blocks::1024 2706 # Occupied blocks per task id |
| 951system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id 952system.cpu.l2cache.tags.age_task_id_blocks_1022::1 27 # Occupied blocks per task id 953system.cpu.l2cache.tags.age_task_id_blocks_1022::2 36 # Occupied blocks per task id 954system.cpu.l2cache.tags.age_task_id_blocks_1022::4 56 # Occupied blocks per task id | 961system.cpu.l2cache.tags.age_task_id_blocks_1022::1 26 # Occupied blocks per task id 962system.cpu.l2cache.tags.age_task_id_blocks_1022::2 48 # Occupied blocks per task id 963system.cpu.l2cache.tags.age_task_id_blocks_1022::4 54 # Occupied blocks per task id |
| 955system.cpu.l2cache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id | 964system.cpu.l2cache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id |
| 956system.cpu.l2cache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id 957system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1125 # Occupied blocks per task id 958system.cpu.l2cache.tags.age_task_id_blocks_1024::3 199 # Occupied blocks per task id | 965system.cpu.l2cache.tags.age_task_id_blocks_1024::1 283 # Occupied blocks per task id 966system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1127 # Occupied blocks per task id 967system.cpu.l2cache.tags.age_task_id_blocks_1024::3 200 # Occupied blocks per task id |
| 959system.cpu.l2cache.tags.age_task_id_blocks_1024::4 957 # Occupied blocks per task id | 968system.cpu.l2cache.tags.age_task_id_blocks_1024::4 957 # Occupied blocks per task id |
| 960system.cpu.l2cache.tags.occ_task_id_percent::1022 0.007385 # Percentage of cache occupancy per task id | 969system.cpu.l2cache.tags.occ_task_id_percent::1022 0.007812 # Percentage of cache occupancy per task id |
| 961system.cpu.l2cache.tags.occ_task_id_percent::1024 0.165161 # Percentage of cache occupancy per task id | 970system.cpu.l2cache.tags.occ_task_id_percent::1024 0.165161 # Percentage of cache occupancy per task id |
| 962system.cpu.l2cache.tags.tag_accesses 4005348 # Number of tag accesses 963system.cpu.l2cache.tags.data_accesses 4005348 # Number of data accesses 964system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states 965system.cpu.l2cache.WritebackDirty_hits::writebacks 64707 # number of WritebackDirty hits 966system.cpu.l2cache.WritebackDirty_hits::total 64707 # number of WritebackDirty hits 967system.cpu.l2cache.WritebackClean_hits::writebacks 51067 # number of WritebackClean hits 968system.cpu.l2cache.WritebackClean_hits::total 51067 # number of WritebackClean hits 969system.cpu.l2cache.ReadExReq_hits::cpu.data 8388 # number of ReadExReq hits 970system.cpu.l2cache.ReadExReq_hits::total 8388 # number of ReadExReq hits 971system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 43964 # number of ReadCleanReq hits 972system.cpu.l2cache.ReadCleanReq_hits::total 43964 # number of ReadCleanReq hits 973system.cpu.l2cache.ReadSharedReq_hits::cpu.data 61705 # number of ReadSharedReq hits 974system.cpu.l2cache.ReadSharedReq_hits::total 61705 # number of ReadSharedReq hits 975system.cpu.l2cache.demand_hits::cpu.inst 43964 # number of demand (read+write) hits 976system.cpu.l2cache.demand_hits::cpu.data 70093 # number of demand (read+write) hits 977system.cpu.l2cache.demand_hits::total 114057 # number of demand (read+write) hits 978system.cpu.l2cache.overall_hits::cpu.inst 43964 # number of overall hits 979system.cpu.l2cache.overall_hits::cpu.data 70093 # number of overall hits 980system.cpu.l2cache.overall_hits::total 114057 # number of overall hits 981system.cpu.l2cache.ReadExReq_misses::cpu.data 236 # number of ReadExReq misses 982system.cpu.l2cache.ReadExReq_misses::total 236 # number of ReadExReq misses 983system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10186 # number of ReadCleanReq misses 984system.cpu.l2cache.ReadCleanReq_misses::total 10186 # number of ReadCleanReq misses 985system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2776 # number of ReadSharedReq misses 986system.cpu.l2cache.ReadSharedReq_misses::total 2776 # number of ReadSharedReq misses 987system.cpu.l2cache.demand_misses::cpu.inst 10186 # number of demand (read+write) misses 988system.cpu.l2cache.demand_misses::cpu.data 3012 # number of demand (read+write) misses 989system.cpu.l2cache.demand_misses::total 13198 # number of demand (read+write) misses 990system.cpu.l2cache.overall_misses::cpu.inst 10186 # number of overall misses 991system.cpu.l2cache.overall_misses::cpu.data 3012 # number of overall misses 992system.cpu.l2cache.overall_misses::total 13198 # number of overall misses 993system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 18599500 # number of ReadExReq miss cycles 994system.cpu.l2cache.ReadExReq_miss_latency::total 18599500 # number of ReadExReq miss cycles 995system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 782334000 # number of ReadCleanReq miss cycles 996system.cpu.l2cache.ReadCleanReq_miss_latency::total 782334000 # number of ReadCleanReq miss cycles 997system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 220076500 # number of ReadSharedReq miss cycles 998system.cpu.l2cache.ReadSharedReq_miss_latency::total 220076500 # number of ReadSharedReq miss cycles 999system.cpu.l2cache.demand_miss_latency::cpu.inst 782334000 # number of demand (read+write) miss cycles 1000system.cpu.l2cache.demand_miss_latency::cpu.data 238676000 # number of demand (read+write) miss cycles 1001system.cpu.l2cache.demand_miss_latency::total 1021010000 # number of demand (read+write) miss cycles 1002system.cpu.l2cache.overall_miss_latency::cpu.inst 782334000 # number of overall miss cycles 1003system.cpu.l2cache.overall_miss_latency::cpu.data 238676000 # number of overall miss cycles 1004system.cpu.l2cache.overall_miss_latency::total 1021010000 # number of overall miss cycles 1005system.cpu.l2cache.WritebackDirty_accesses::writebacks 64707 # number of WritebackDirty accesses(hits+misses) 1006system.cpu.l2cache.WritebackDirty_accesses::total 64707 # number of WritebackDirty accesses(hits+misses) 1007system.cpu.l2cache.WritebackClean_accesses::writebacks 51067 # number of WritebackClean accesses(hits+misses) 1008system.cpu.l2cache.WritebackClean_accesses::total 51067 # number of WritebackClean accesses(hits+misses) 1009system.cpu.l2cache.ReadExReq_accesses::cpu.data 8624 # number of ReadExReq accesses(hits+misses) 1010system.cpu.l2cache.ReadExReq_accesses::total 8624 # number of ReadExReq accesses(hits+misses) 1011system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 54150 # number of ReadCleanReq accesses(hits+misses) 1012system.cpu.l2cache.ReadCleanReq_accesses::total 54150 # number of ReadCleanReq accesses(hits+misses) 1013system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64481 # number of ReadSharedReq accesses(hits+misses) 1014system.cpu.l2cache.ReadSharedReq_accesses::total 64481 # number of ReadSharedReq accesses(hits+misses) 1015system.cpu.l2cache.demand_accesses::cpu.inst 54150 # number of demand (read+write) accesses 1016system.cpu.l2cache.demand_accesses::cpu.data 73105 # number of demand (read+write) accesses 1017system.cpu.l2cache.demand_accesses::total 127255 # number of demand (read+write) accesses 1018system.cpu.l2cache.overall_accesses::cpu.inst 54150 # number of overall (read+write) accesses 1019system.cpu.l2cache.overall_accesses::cpu.data 73105 # number of overall (read+write) accesses 1020system.cpu.l2cache.overall_accesses::total 127255 # number of overall (read+write) accesses 1021system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.027365 # miss rate for ReadExReq accesses 1022system.cpu.l2cache.ReadExReq_miss_rate::total 0.027365 # miss rate for ReadExReq accesses 1023system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.188107 # miss rate for ReadCleanReq accesses 1024system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.188107 # miss rate for ReadCleanReq accesses 1025system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043051 # miss rate for ReadSharedReq accesses 1026system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043051 # miss rate for ReadSharedReq accesses 1027system.cpu.l2cache.demand_miss_rate::cpu.inst 0.188107 # miss rate for demand accesses 1028system.cpu.l2cache.demand_miss_rate::cpu.data 0.041201 # miss rate for demand accesses 1029system.cpu.l2cache.demand_miss_rate::total 0.103713 # miss rate for demand accesses 1030system.cpu.l2cache.overall_miss_rate::cpu.inst 0.188107 # miss rate for overall accesses 1031system.cpu.l2cache.overall_miss_rate::cpu.data 0.041201 # miss rate for overall accesses 1032system.cpu.l2cache.overall_miss_rate::total 0.103713 # miss rate for overall accesses 1033system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78811.440678 # average ReadExReq miss latency 1034system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78811.440678 # average ReadExReq miss latency 1035system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76804.830159 # average ReadCleanReq miss latency 1036system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76804.830159 # average ReadCleanReq miss latency 1037system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79278.278098 # average ReadSharedReq miss latency 1038system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79278.278098 # average ReadSharedReq miss latency 1039system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76804.830159 # average overall miss latency 1040system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79241.699867 # average overall miss latency 1041system.cpu.l2cache.demand_avg_miss_latency::total 77360.963782 # average overall miss latency 1042system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76804.830159 # average overall miss latency 1043system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79241.699867 # average overall miss latency 1044system.cpu.l2cache.overall_avg_miss_latency::total 77360.963782 # average overall miss latency | 971system.cpu.l2cache.tags.tag_accesses 4003735 # Number of tag accesses 972system.cpu.l2cache.tags.data_accesses 4003735 # Number of data accesses 973system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states 974system.cpu.l2cache.WritebackDirty_hits::writebacks 64697 # number of WritebackDirty hits 975system.cpu.l2cache.WritebackDirty_hits::total 64697 # number of WritebackDirty hits 976system.cpu.l2cache.WritebackClean_hits::writebacks 51019 # number of WritebackClean hits 977system.cpu.l2cache.WritebackClean_hits::total 51019 # number of WritebackClean hits 978system.cpu.l2cache.ReadExReq_hits::cpu.data 8384 # number of ReadExReq hits 979system.cpu.l2cache.ReadExReq_hits::total 8384 # number of ReadExReq hits 980system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 43929 # number of ReadCleanReq hits 981system.cpu.l2cache.ReadCleanReq_hits::total 43929 # number of ReadCleanReq hits 982system.cpu.l2cache.ReadSharedReq_hits::cpu.data 61675 # number of ReadSharedReq hits 983system.cpu.l2cache.ReadSharedReq_hits::total 61675 # number of ReadSharedReq hits 984system.cpu.l2cache.demand_hits::cpu.inst 43929 # number of demand (read+write) hits 985system.cpu.l2cache.demand_hits::cpu.data 70059 # number of demand (read+write) hits 986system.cpu.l2cache.demand_hits::total 113988 # number of demand (read+write) hits 987system.cpu.l2cache.overall_hits::cpu.inst 43929 # number of overall hits 988system.cpu.l2cache.overall_hits::cpu.data 70059 # number of overall hits 989system.cpu.l2cache.overall_hits::total 113988 # number of overall hits 990system.cpu.l2cache.ReadExReq_misses::cpu.data 239 # number of ReadExReq misses 991system.cpu.l2cache.ReadExReq_misses::total 239 # number of ReadExReq misses 992system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10196 # number of ReadCleanReq misses 993system.cpu.l2cache.ReadCleanReq_misses::total 10196 # number of ReadCleanReq misses 994system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2793 # number of ReadSharedReq misses 995system.cpu.l2cache.ReadSharedReq_misses::total 2793 # number of ReadSharedReq misses 996system.cpu.l2cache.demand_misses::cpu.inst 10196 # number of demand (read+write) misses 997system.cpu.l2cache.demand_misses::cpu.data 3032 # number of demand (read+write) misses 998system.cpu.l2cache.demand_misses::total 13228 # number of demand (read+write) misses 999system.cpu.l2cache.overall_misses::cpu.inst 10196 # number of overall misses 1000system.cpu.l2cache.overall_misses::cpu.data 3032 # number of overall misses 1001system.cpu.l2cache.overall_misses::total 13228 # number of overall misses 1002system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 20303000 # number of ReadExReq miss cycles 1003system.cpu.l2cache.ReadExReq_miss_latency::total 20303000 # number of ReadExReq miss cycles 1004system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1707637000 # number of ReadCleanReq miss cycles 1005system.cpu.l2cache.ReadCleanReq_miss_latency::total 1707637000 # number of ReadCleanReq miss cycles 1006system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 558453500 # number of ReadSharedReq miss cycles 1007system.cpu.l2cache.ReadSharedReq_miss_latency::total 558453500 # number of ReadSharedReq miss cycles 1008system.cpu.l2cache.demand_miss_latency::cpu.inst 1707637000 # number of demand (read+write) miss cycles 1009system.cpu.l2cache.demand_miss_latency::cpu.data 578756500 # number of demand (read+write) miss cycles 1010system.cpu.l2cache.demand_miss_latency::total 2286393500 # number of demand (read+write) miss cycles 1011system.cpu.l2cache.overall_miss_latency::cpu.inst 1707637000 # number of overall miss cycles 1012system.cpu.l2cache.overall_miss_latency::cpu.data 578756500 # number of overall miss cycles 1013system.cpu.l2cache.overall_miss_latency::total 2286393500 # number of overall miss cycles 1014system.cpu.l2cache.WritebackDirty_accesses::writebacks 64697 # number of WritebackDirty accesses(hits+misses) 1015system.cpu.l2cache.WritebackDirty_accesses::total 64697 # number of WritebackDirty accesses(hits+misses) 1016system.cpu.l2cache.WritebackClean_accesses::writebacks 51019 # number of WritebackClean accesses(hits+misses) 1017system.cpu.l2cache.WritebackClean_accesses::total 51019 # number of WritebackClean accesses(hits+misses) 1018system.cpu.l2cache.ReadExReq_accesses::cpu.data 8623 # number of ReadExReq accesses(hits+misses) 1019system.cpu.l2cache.ReadExReq_accesses::total 8623 # number of ReadExReq accesses(hits+misses) 1020system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 54125 # number of ReadCleanReq accesses(hits+misses) 1021system.cpu.l2cache.ReadCleanReq_accesses::total 54125 # number of ReadCleanReq accesses(hits+misses) 1022system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64468 # number of ReadSharedReq accesses(hits+misses) 1023system.cpu.l2cache.ReadSharedReq_accesses::total 64468 # number of ReadSharedReq accesses(hits+misses) 1024system.cpu.l2cache.demand_accesses::cpu.inst 54125 # number of demand (read+write) accesses 1025system.cpu.l2cache.demand_accesses::cpu.data 73091 # number of demand (read+write) accesses 1026system.cpu.l2cache.demand_accesses::total 127216 # number of demand (read+write) accesses 1027system.cpu.l2cache.overall_accesses::cpu.inst 54125 # number of overall (read+write) accesses 1028system.cpu.l2cache.overall_accesses::cpu.data 73091 # number of overall (read+write) accesses 1029system.cpu.l2cache.overall_accesses::total 127216 # number of overall (read+write) accesses 1030system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.027717 # miss rate for ReadExReq accesses 1031system.cpu.l2cache.ReadExReq_miss_rate::total 0.027717 # miss rate for ReadExReq accesses 1032system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.188379 # miss rate for ReadCleanReq accesses 1033system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.188379 # miss rate for ReadCleanReq accesses 1034system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043324 # miss rate for ReadSharedReq accesses 1035system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043324 # miss rate for ReadSharedReq accesses 1036system.cpu.l2cache.demand_miss_rate::cpu.inst 0.188379 # miss rate for demand accesses 1037system.cpu.l2cache.demand_miss_rate::cpu.data 0.041483 # miss rate for demand accesses 1038system.cpu.l2cache.demand_miss_rate::total 0.103981 # miss rate for demand accesses 1039system.cpu.l2cache.overall_miss_rate::cpu.inst 0.188379 # miss rate for overall accesses 1040system.cpu.l2cache.overall_miss_rate::cpu.data 0.041483 # miss rate for overall accesses 1041system.cpu.l2cache.overall_miss_rate::total 0.103981 # miss rate for overall accesses 1042system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84949.790795 # average ReadExReq miss latency 1043system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84949.790795 # average ReadExReq miss latency 1044system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 167481.071008 # average ReadCleanReq miss latency 1045system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 167481.071008 # average ReadCleanReq miss latency 1046system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 199947.547440 # average ReadSharedReq miss latency 1047system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 199947.547440 # average ReadSharedReq miss latency 1048system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 167481.071008 # average overall miss latency 1049system.cpu.l2cache.demand_avg_miss_latency::cpu.data 190882.750660 # average overall miss latency 1050system.cpu.l2cache.demand_avg_miss_latency::total 172844.987904 # average overall miss latency 1051system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 167481.071008 # average overall miss latency 1052system.cpu.l2cache.overall_avg_miss_latency::cpu.data 190882.750660 # average overall miss latency 1053system.cpu.l2cache.overall_avg_miss_latency::total 172844.987904 # average overall miss latency |
| 1045system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1046system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1047system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1048system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1049system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1050system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1054system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1055system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1056system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1057system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1058system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1059system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1060system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1 # number of ReadExReq MSHR hits 1061system.cpu.l2cache.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits |
|
| 1051system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits 1052system.cpu.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits 1053system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 8 # number of ReadSharedReq MSHR hits 1054system.cpu.l2cache.ReadSharedReq_mshr_hits::total 8 # number of ReadSharedReq MSHR hits 1055system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits | 1062system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits 1063system.cpu.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits 1064system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 8 # number of ReadSharedReq MSHR hits 1065system.cpu.l2cache.ReadSharedReq_mshr_hits::total 8 # number of ReadSharedReq MSHR hits 1066system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits |
| 1056system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits 1057system.cpu.l2cache.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits | 1067system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits 1068system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits |
| 1058system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits | 1069system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits |
| 1059system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits 1060system.cpu.l2cache.overall_mshr_hits::total 13 # number of overall MSHR hits 1061system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 2014 # number of HardPFReq MSHR misses 1062system.cpu.l2cache.HardPFReq_mshr_misses::total 2014 # number of HardPFReq MSHR misses 1063system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 236 # number of ReadExReq MSHR misses 1064system.cpu.l2cache.ReadExReq_mshr_misses::total 236 # number of ReadExReq MSHR misses 1065system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10181 # number of ReadCleanReq MSHR misses 1066system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10181 # number of ReadCleanReq MSHR misses 1067system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2768 # number of ReadSharedReq MSHR misses 1068system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2768 # number of ReadSharedReq MSHR misses 1069system.cpu.l2cache.demand_mshr_misses::cpu.inst 10181 # number of demand (read+write) MSHR misses 1070system.cpu.l2cache.demand_mshr_misses::cpu.data 3004 # number of demand (read+write) MSHR misses 1071system.cpu.l2cache.demand_mshr_misses::total 13185 # number of demand (read+write) MSHR misses 1072system.cpu.l2cache.overall_mshr_misses::cpu.inst 10181 # number of overall MSHR misses 1073system.cpu.l2cache.overall_mshr_misses::cpu.data 3004 # number of overall MSHR misses 1074system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 2014 # number of overall MSHR misses 1075system.cpu.l2cache.overall_mshr_misses::total 15199 # number of overall MSHR misses 1076system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 66910636 # number of HardPFReq MSHR miss cycles 1077system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 66910636 # number of HardPFReq MSHR miss cycles 1078system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 17183500 # number of ReadExReq MSHR miss cycles 1079system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 17183500 # number of ReadExReq MSHR miss cycles 1080system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 720935500 # number of ReadCleanReq MSHR miss cycles 1081system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 720935500 # number of ReadCleanReq MSHR miss cycles 1082system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 202978500 # number of ReadSharedReq MSHR miss cycles 1083system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 202978500 # number of ReadSharedReq MSHR miss cycles 1084system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 720935500 # number of demand (read+write) MSHR miss cycles 1085system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 220162000 # number of demand (read+write) MSHR miss cycles 1086system.cpu.l2cache.demand_mshr_miss_latency::total 941097500 # number of demand (read+write) MSHR miss cycles 1087system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 720935500 # number of overall MSHR miss cycles 1088system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 220162000 # number of overall MSHR miss cycles 1089system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 66910636 # number of overall MSHR miss cycles 1090system.cpu.l2cache.overall_mshr_miss_latency::total 1008008136 # number of overall MSHR miss cycles | 1070system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits 1071system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits 1072system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 2057 # number of HardPFReq MSHR misses 1073system.cpu.l2cache.HardPFReq_mshr_misses::total 2057 # number of HardPFReq MSHR misses 1074system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 238 # number of ReadExReq MSHR misses 1075system.cpu.l2cache.ReadExReq_mshr_misses::total 238 # number of ReadExReq MSHR misses 1076system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10191 # number of ReadCleanReq MSHR misses 1077system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10191 # number of ReadCleanReq MSHR misses 1078system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2785 # number of ReadSharedReq MSHR misses 1079system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2785 # number of ReadSharedReq MSHR misses 1080system.cpu.l2cache.demand_mshr_misses::cpu.inst 10191 # number of demand (read+write) MSHR misses 1081system.cpu.l2cache.demand_mshr_misses::cpu.data 3023 # number of demand (read+write) MSHR misses 1082system.cpu.l2cache.demand_mshr_misses::total 13214 # number of demand (read+write) MSHR misses 1083system.cpu.l2cache.overall_mshr_misses::cpu.inst 10191 # number of overall MSHR misses 1084system.cpu.l2cache.overall_mshr_misses::cpu.data 3023 # number of overall MSHR misses 1085system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 2057 # number of overall MSHR misses 1086system.cpu.l2cache.overall_mshr_misses::total 15271 # number of overall MSHR misses 1087system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 97518621 # number of HardPFReq MSHR miss cycles 1088system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 97518621 # number of HardPFReq MSHR miss cycles 1089system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 18660000 # number of ReadExReq MSHR miss cycles 1090system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 18660000 # number of ReadExReq MSHR miss cycles 1091system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1645631000 # number of ReadCleanReq MSHR miss cycles 1092system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1645631000 # number of ReadCleanReq MSHR miss cycles 1093system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 541204500 # number of ReadSharedReq MSHR miss cycles 1094system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 541204500 # number of ReadSharedReq MSHR miss cycles 1095system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1645631000 # number of demand (read+write) MSHR miss cycles 1096system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 559864500 # number of demand (read+write) MSHR miss cycles 1097system.cpu.l2cache.demand_mshr_miss_latency::total 2205495500 # number of demand (read+write) MSHR miss cycles 1098system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1645631000 # number of overall MSHR miss cycles 1099system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 559864500 # number of overall MSHR miss cycles 1100system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 97518621 # number of overall MSHR miss cycles 1101system.cpu.l2cache.overall_mshr_miss_latency::total 2303014121 # number of overall MSHR miss cycles |
| 1091system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1092system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1102system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1103system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 1093system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027365 # mshr miss rate for ReadExReq accesses 1094system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027365 # mshr miss rate for ReadExReq accesses 1095system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.188015 # mshr miss rate for ReadCleanReq accesses 1096system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.188015 # mshr miss rate for ReadCleanReq accesses 1097system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.042927 # mshr miss rate for ReadSharedReq accesses 1098system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.042927 # mshr miss rate for ReadSharedReq accesses 1099system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.188015 # mshr miss rate for demand accesses 1100system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.041092 # mshr miss rate for demand accesses 1101system.cpu.l2cache.demand_mshr_miss_rate::total 0.103611 # mshr miss rate for demand accesses 1102system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.188015 # mshr miss rate for overall accesses 1103system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.041092 # mshr miss rate for overall accesses | 1104system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027601 # mshr miss rate for ReadExReq accesses 1105system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027601 # mshr miss rate for ReadExReq accesses 1106system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.188286 # mshr miss rate for ReadCleanReq accesses 1107system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.188286 # mshr miss rate for ReadCleanReq accesses 1108system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043200 # mshr miss rate for ReadSharedReq accesses 1109system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043200 # mshr miss rate for ReadSharedReq accesses 1110system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.188286 # mshr miss rate for demand accesses 1111system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.041359 # mshr miss rate for demand accesses 1112system.cpu.l2cache.demand_mshr_miss_rate::total 0.103871 # mshr miss rate for demand accesses 1113system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.188286 # mshr miss rate for overall accesses 1114system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.041359 # mshr miss rate for overall accesses |
| 1104system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1115system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1105system.cpu.l2cache.overall_mshr_miss_rate::total 0.119437 # mshr miss rate for overall accesses 1106system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33222.758689 # average HardPFReq mshr miss latency 1107system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33222.758689 # average HardPFReq mshr miss latency 1108system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72811.440678 # average ReadExReq mshr miss latency 1109system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72811.440678 # average ReadExReq mshr miss latency 1110system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70811.855417 # average ReadCleanReq mshr miss latency 1111system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70811.855417 # average ReadCleanReq mshr miss latency 1112system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73330.382948 # average ReadSharedReq mshr miss latency 1113system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73330.382948 # average ReadSharedReq mshr miss latency 1114system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70811.855417 # average overall mshr miss latency 1115system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73289.613848 # average overall mshr miss latency 1116system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71376.374668 # average overall mshr miss latency 1117system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70811.855417 # average overall mshr miss latency 1118system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73289.613848 # average overall mshr miss latency 1119system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33222.758689 # average overall mshr miss latency 1120system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66320.687940 # average overall mshr miss latency 1121system.cpu.toL2Bus.snoop_filter.tot_requests 253485 # Total number of requests made to the snoop filter. 1122system.cpu.toL2Bus.snoop_filter.hit_single_requests 126250 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1123system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10456 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1124system.cpu.toL2Bus.snoop_filter.tot_snoops 904 # Total number of snoops made to the snoop filter. 1125system.cpu.toL2Bus.snoop_filter.hit_single_snoops 903 # Number of snoops hitting in the snoop filter with a single holder of the requested data. | 1116system.cpu.l2cache.overall_mshr_miss_rate::total 0.120040 # mshr miss rate for overall accesses 1117system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 47408.177443 # average HardPFReq mshr miss latency 1118system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 47408.177443 # average HardPFReq mshr miss latency 1119system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78403.361345 # average ReadExReq mshr miss latency 1120system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78403.361345 # average ReadExReq mshr miss latency 1121system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 161478.853891 # average ReadCleanReq mshr miss latency 1122system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 161478.853891 # average ReadCleanReq mshr miss latency 1123system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 194328.366248 # average ReadSharedReq mshr miss latency 1124system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 194328.366248 # average ReadSharedReq mshr miss latency 1125system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 161478.853891 # average overall mshr miss latency 1126system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185201.620906 # average overall mshr miss latency 1127system.cpu.l2cache.demand_avg_mshr_miss_latency::total 166905.970940 # average overall mshr miss latency 1128system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 161478.853891 # average overall mshr miss latency 1129system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185201.620906 # average overall mshr miss latency 1130system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 47408.177443 # average overall mshr miss latency 1131system.cpu.l2cache.overall_avg_mshr_miss_latency::total 150809.647109 # average overall mshr miss latency 1132system.cpu.toL2Bus.snoop_filter.tot_requests 253407 # Total number of requests made to the snoop filter. 1133system.cpu.toL2Bus.snoop_filter.hit_single_requests 126211 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1134system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10475 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1135system.cpu.toL2Bus.snoop_filter.tot_snoops 950 # Total number of snoops made to the snoop filter. 1136system.cpu.toL2Bus.snoop_filter.hit_single_snoops 949 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| 1126system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1137system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1127system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states 1128system.cpu.toL2Bus.trans_dist::ReadResp 118630 # Transaction distribution 1129system.cpu.toL2Bus.trans_dist::WritebackDirty 64707 # Transaction distribution 1130system.cpu.toL2Bus.trans_dist::WritebackClean 61523 # Transaction distribution 1131system.cpu.toL2Bus.trans_dist::HardPFReq 2352 # Transaction distribution 1132system.cpu.toL2Bus.trans_dist::ReadExReq 8624 # Transaction distribution 1133system.cpu.toL2Bus.trans_dist::ReadExResp 8624 # Transaction distribution 1134system.cpu.toL2Bus.trans_dist::ReadCleanReq 54150 # Transaction distribution 1135system.cpu.toL2Bus.trans_dist::ReadSharedReq 64481 # Transaction distribution 1136system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161936 # Packet count per connected master and slave (bytes) 1137system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218803 # Packet count per connected master and slave (bytes) 1138system.cpu.toL2Bus.pkt_count::total 380739 # Packet count per connected master and slave (bytes) 1139system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6898304 # Cumulative packet size per connected master and slave (bytes) 1140system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9324672 # Cumulative packet size per connected master and slave (bytes) 1141system.cpu.toL2Bus.pkt_size::total 16222976 # Cumulative packet size per connected master and slave (bytes) 1142system.cpu.toL2Bus.snoops 2352 # Total snoops (count) | 1138system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states 1139system.cpu.toL2Bus.trans_dist::ReadResp 118592 # Transaction distribution 1140system.cpu.toL2Bus.trans_dist::WritebackDirty 64697 # Transaction distribution 1141system.cpu.toL2Bus.trans_dist::WritebackClean 61494 # Transaction distribution 1142system.cpu.toL2Bus.trans_dist::HardPFReq 2394 # Transaction distribution 1143system.cpu.toL2Bus.trans_dist::ReadExReq 8623 # Transaction distribution 1144system.cpu.toL2Bus.trans_dist::ReadExResp 8623 # Transaction distribution 1145system.cpu.toL2Bus.trans_dist::ReadCleanReq 54125 # Transaction distribution 1146system.cpu.toL2Bus.trans_dist::ReadSharedReq 64468 # Transaction distribution 1147system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161861 # Packet count per connected master and slave (bytes) 1148system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218761 # Packet count per connected master and slave (bytes) 1149system.cpu.toL2Bus.pkt_count::total 380622 # Packet count per connected master and slave (bytes) 1150system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6895104 # Cumulative packet size per connected master and slave (bytes) 1151system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9322880 # Cumulative packet size per connected master and slave (bytes) 1152system.cpu.toL2Bus.pkt_size::total 16217984 # Cumulative packet size per connected master and slave (bytes) 1153system.cpu.toL2Bus.snoops 2394 # Total snoops (count) |
| 1143system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) | 1154system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 1144system.cpu.toL2Bus.snoop_fanout::samples 129607 # Request fanout histogram 1145system.cpu.toL2Bus.snoop_fanout::mean 0.087812 # Request fanout histogram 1146system.cpu.toL2Bus.snoop_fanout::stdev 0.283049 # Request fanout histogram | 1155system.cpu.toL2Bus.snoop_fanout::samples 129610 # Request fanout histogram 1156system.cpu.toL2Bus.snoop_fanout::mean 0.088311 # Request fanout histogram 1157system.cpu.toL2Bus.snoop_fanout::stdev 0.283775 # Request fanout histogram |
| 1147system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1158system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1148system.cpu.toL2Bus.snoop_fanout::0 118227 91.22% 91.22% # Request fanout histogram 1149system.cpu.toL2Bus.snoop_fanout::1 11379 8.78% 100.00% # Request fanout histogram | 1159system.cpu.toL2Bus.snoop_fanout::0 118165 91.17% 91.17% # Request fanout histogram 1160system.cpu.toL2Bus.snoop_fanout::1 11444 8.83% 100.00% # Request fanout histogram |
| 1150system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram 1151system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1152system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1153system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 1161system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram 1162system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1163system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1164system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1154system.cpu.toL2Bus.snoop_fanout::total 129607 # Request fanout histogram 1155system.cpu.toL2Bus.reqLayer0.occupancy 252972500 # Layer occupancy (ticks) | 1165system.cpu.toL2Bus.snoop_fanout::total 129610 # Request fanout histogram 1166system.cpu.toL2Bus.reqLayer0.occupancy 252894500 # Layer occupancy (ticks) |
| 1156system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) | 1167system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) |
| 1157system.cpu.toL2Bus.respLayer0.occupancy 81228989 # Layer occupancy (ticks) | 1168system.cpu.toL2Bus.respLayer0.occupancy 81192487 # Layer occupancy (ticks) |
| 1158system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1169system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1159system.cpu.toL2Bus.respLayer1.occupancy 109661492 # Layer occupancy (ticks) | 1170system.cpu.toL2Bus.respLayer1.occupancy 109641490 # Layer occupancy (ticks) |
| 1160system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 1171system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 1161system.membus.snoop_filter.tot_requests 14295 # Total number of requests made to the snoop filter. 1162system.membus.snoop_filter.hit_single_requests 10463 # Number of requests hitting in the snoop filter with a single holder of the requested data. | 1172system.membus.snoop_filter.tot_requests 14321 # Total number of requests made to the snoop filter. 1173system.membus.snoop_filter.hit_single_requests 10482 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| 1163system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1164system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1165system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1166system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1174system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1175system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1176system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1177system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1167system.membus.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states 1168system.membus.trans_dist::ReadResp 14059 # Transaction distribution 1169system.membus.trans_dist::ReadExReq 236 # Transaction distribution 1170system.membus.trans_dist::ReadExResp 236 # Transaction distribution 1171system.membus.trans_dist::ReadSharedReq 14059 # Transaction distribution 1172system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28590 # Packet count per connected master and slave (bytes) 1173system.membus.pkt_count::total 28590 # Packet count per connected master and slave (bytes) 1174system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 914880 # Cumulative packet size per connected master and slave (bytes) 1175system.membus.pkt_size::total 914880 # Cumulative packet size per connected master and slave (bytes) | 1178system.membus.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states 1179system.membus.trans_dist::ReadResp 14082 # Transaction distribution 1180system.membus.trans_dist::ReadExReq 238 # Transaction distribution 1181system.membus.trans_dist::ReadExResp 238 # Transaction distribution 1182system.membus.trans_dist::ReadSharedReq 14083 # Transaction distribution 1183system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28641 # Packet count per connected master and slave (bytes) 1184system.membus.pkt_count::total 28641 # Packet count per connected master and slave (bytes) 1185system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 916480 # Cumulative packet size per connected master and slave (bytes) 1186system.membus.pkt_size::total 916480 # Cumulative packet size per connected master and slave (bytes) |
| 1176system.membus.snoops 0 # Total snoops (count) 1177system.membus.snoopTraffic 0 # Total snoop traffic (bytes) | 1187system.membus.snoops 0 # Total snoops (count) 1188system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 1178system.membus.snoop_fanout::samples 14295 # Request fanout histogram | 1189system.membus.snoop_fanout::samples 14321 # Request fanout histogram |
| 1179system.membus.snoop_fanout::mean 0 # Request fanout histogram 1180system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1181system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1190system.membus.snoop_fanout::mean 0 # Request fanout histogram 1191system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1192system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1182system.membus.snoop_fanout::0 14295 100.00% 100.00% # Request fanout histogram | 1193system.membus.snoop_fanout::0 14321 100.00% 100.00% # Request fanout histogram |
| 1183system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1184system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1185system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1186system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 1194system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1195system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1196system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1197system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 1187system.membus.snoop_fanout::total 14295 # Request fanout histogram 1188system.membus.reqLayer0.occupancy 18052130 # Layer occupancy (ticks) | 1198system.membus.snoop_fanout::total 14321 # Request fanout histogram 1199system.membus.reqLayer0.occupancy 18093154 # Layer occupancy (ticks) |
| 1189system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1200system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1190system.membus.respLayer1.occupancy 77159307 # Layer occupancy (ticks) | 1201system.membus.respLayer1.occupancy 77218560 # Layer occupancy (ticks) |
| 1191system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1192 1193---------- End Simulation Statistics ---------- | 1202system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1203 1204---------- End Simulation Statistics ---------- |