| stats.txt (11515:c48c7cc5a522) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.084938 # Number of seconds simulated 4sim_ticks 84937723500 # Number of ticks simulated 5final_tick 84937723500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.084938 # Number of seconds simulated 4sim_ticks 84937723500 # Number of ticks simulated 5final_tick 84937723500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 205804 # Simulator instruction rate (inst/s) 8host_op_rate 216952 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 101452217 # Simulator tick rate (ticks/s) 10host_mem_usage 314712 # Number of bytes of host memory used 11host_seconds 837.22 # Real time elapsed on the host | 7host_inst_rate 205612 # Simulator instruction rate (inst/s) 8host_op_rate 216749 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 101357587 # Simulator tick rate (ticks/s) 10host_mem_usage 315376 # Number of bytes of host memory used 11host_seconds 838.00 # Real time elapsed on the host |
| 12sim_insts 172303022 # Number of instructions simulated 13sim_ops 181635954 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 172303022 # Number of instructions simulated 13sim_ops 181635954 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.inst 587328 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 132096 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 70976 # Number of bytes read from this memory 19system.physmem.bytes_read::total 790400 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 587328 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 587328 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 9177 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 2064 # Number of read requests responded to by this memory --- 225 unchanged lines hidden (view full) --- 249system.physmem_1.preBackEnergy 48069226500 # Energy for precharge background per rank (pJ) 250system.physmem_1.totalEnergy 56939300100 # Total energy per rank (pJ) 251system.physmem_1.averagePower 670.405119 # Core power per rank (mW) 252system.physmem_1.memoryStateTime::IDLE 79958437412 # Time in different power states 253system.physmem_1.memoryStateTime::REF 2836080000 # Time in different power states 254system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 255system.physmem_1.memoryStateTime::ACT 2138239588 # Time in different power states 256system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.physmem.bytes_read::cpu.inst 587328 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 132096 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.l2cache.prefetcher 70976 # Number of bytes read from this memory 20system.physmem.bytes_read::total 790400 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 587328 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 587328 # Number of instructions bytes read from this memory 23system.physmem.num_reads::cpu.inst 9177 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 2064 # Number of read requests responded to by this memory --- 225 unchanged lines hidden (view full) --- 250system.physmem_1.preBackEnergy 48069226500 # Energy for precharge background per rank (pJ) 251system.physmem_1.totalEnergy 56939300100 # Total energy per rank (pJ) 252system.physmem_1.averagePower 670.405119 # Core power per rank (mW) 253system.physmem_1.memoryStateTime::IDLE 79958437412 # Time in different power states 254system.physmem_1.memoryStateTime::REF 2836080000 # Time in different power states 255system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 256system.physmem_1.memoryStateTime::ACT 2138239588 # Time in different power states 257system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 258system.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states |
|
| 257system.cpu.branchPred.lookups 85626366 # Number of BP lookups 258system.cpu.branchPred.condPredicted 68177013 # Number of conditional branches predicted 259system.cpu.branchPred.condIncorrect 5935452 # Number of conditional branches incorrect 260system.cpu.branchPred.BTBLookups 39946926 # Number of BTB lookups 261system.cpu.branchPred.BTBHits 38187698 # Number of BTB hits 262system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 263system.cpu.branchPred.BTBHitPct 95.596087 # BTB Hit Percentage 264system.cpu.branchPred.usedRAS 3683716 # Number of times the RAS was used to get a target. 265system.cpu.branchPred.RASInCorrect 81912 # Number of incorrect RAS predictions. 266system.cpu.branchPred.indirectLookups 681689 # Number of indirect predictor lookups. 267system.cpu.branchPred.indirectHits 653746 # Number of indirect target hits. 268system.cpu.branchPred.indirectMisses 27943 # Number of indirect misses. 269system.cpu.branchPredindirectMispredicted 40316 # Number of mispredicted indirect branches. 270system.cpu_clk_domain.clock 500 # Clock period in ticks | 259system.cpu.branchPred.lookups 85626366 # Number of BP lookups 260system.cpu.branchPred.condPredicted 68177013 # Number of conditional branches predicted 261system.cpu.branchPred.condIncorrect 5935452 # Number of conditional branches incorrect 262system.cpu.branchPred.BTBLookups 39946926 # Number of BTB lookups 263system.cpu.branchPred.BTBHits 38187698 # Number of BTB hits 264system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 265system.cpu.branchPred.BTBHitPct 95.596087 # BTB Hit Percentage 266system.cpu.branchPred.usedRAS 3683716 # Number of times the RAS was used to get a target. 267system.cpu.branchPred.RASInCorrect 81912 # Number of incorrect RAS predictions. 268system.cpu.branchPred.indirectLookups 681689 # Number of indirect predictor lookups. 269system.cpu.branchPred.indirectHits 653746 # Number of indirect target hits. 270system.cpu.branchPred.indirectMisses 27943 # Number of indirect misses. 271system.cpu.branchPredindirectMispredicted 40316 # Number of mispredicted indirect branches. 272system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 273system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states |
|
| 271system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 275system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 278system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 292system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 293system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 294system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 295system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 296system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 297system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 298system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 299system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 274system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 275system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 278system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 279system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 280system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 281system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 295system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 296system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 297system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 298system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 299system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 300system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 301system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 302system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 303system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states |
|
| 300system.cpu.dtb.walker.walks 0 # Table walker walks requested 301system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 302system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 303system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 305system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 306system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 307system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 321system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 322system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 323system.cpu.dtb.read_accesses 0 # DTB read accesses 324system.cpu.dtb.write_accesses 0 # DTB write accesses 325system.cpu.dtb.inst_accesses 0 # ITB inst accesses 326system.cpu.dtb.hits 0 # DTB hits 327system.cpu.dtb.misses 0 # DTB misses 328system.cpu.dtb.accesses 0 # DTB accesses | 304system.cpu.dtb.walker.walks 0 # Table walker walks requested 305system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 306system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 307system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 308system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 309system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 310system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 311system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 325system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 326system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 327system.cpu.dtb.read_accesses 0 # DTB read accesses 328system.cpu.dtb.write_accesses 0 # DTB write accesses 329system.cpu.dtb.inst_accesses 0 # ITB inst accesses 330system.cpu.dtb.hits 0 # DTB hits 331system.cpu.dtb.misses 0 # DTB misses 332system.cpu.dtb.accesses 0 # DTB accesses |
| 333system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states |
|
| 329system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 330system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 333system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 334system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 335system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 350system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 351system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 352system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 353system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 354system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 355system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 356system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 357system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 334system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 335system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 337system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 338system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 339system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 340system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 341system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 355system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 356system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 357system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 358system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 359system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 360system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 361system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 362system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 363system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states |
|
| 358system.cpu.itb.walker.walks 0 # Table walker walks requested 359system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 360system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 361system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 362system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 363system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 364system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 365system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 380system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 381system.cpu.itb.read_accesses 0 # DTB read accesses 382system.cpu.itb.write_accesses 0 # DTB write accesses 383system.cpu.itb.inst_accesses 0 # ITB inst accesses 384system.cpu.itb.hits 0 # DTB hits 385system.cpu.itb.misses 0 # DTB misses 386system.cpu.itb.accesses 0 # DTB accesses 387system.cpu.workload.num_syscalls 400 # Number of system calls | 364system.cpu.itb.walker.walks 0 # Table walker walks requested 365system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 366system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 367system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 368system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 369system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 370system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 371system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 386system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 387system.cpu.itb.read_accesses 0 # DTB read accesses 388system.cpu.itb.write_accesses 0 # DTB write accesses 389system.cpu.itb.inst_accesses 0 # ITB inst accesses 390system.cpu.itb.hits 0 # DTB hits 391system.cpu.itb.misses 0 # DTB misses 392system.cpu.itb.accesses 0 # DTB accesses 393system.cpu.workload.num_syscalls 400 # Number of system calls |
| 394system.cpu.pwrStateResidencyTicks::ON 84937723500 # Cumulative time (in ticks) in various power states |
|
| 388system.cpu.numCycles 169875448 # number of cpu cycles simulated 389system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 390system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 391system.cpu.fetch.icacheStallCycles 5671940 # Number of cycles fetch is stalled on an Icache miss 392system.cpu.fetch.Insts 347162762 # Number of instructions fetch has processed 393system.cpu.fetch.Branches 85626366 # Number of branches that fetch encountered 394system.cpu.fetch.predictedBranches 42525160 # Number of branches that fetch has predicted taken 395system.cpu.fetch.Cycles 157499775 # Number of cycles fetch has run and was not squashing or blocked --- 275 unchanged lines hidden (view full) --- 671system.cpu.int_regfile_reads 218725741 # number of integer regfile reads 672system.cpu.int_regfile_writes 114168991 # number of integer regfile writes 673system.cpu.fp_regfile_reads 2904222 # number of floating regfile reads 674system.cpu.fp_regfile_writes 2441435 # number of floating regfile writes 675system.cpu.cc_regfile_reads 708194084 # number of cc regfile reads 676system.cpu.cc_regfile_writes 229512691 # number of cc regfile writes 677system.cpu.misc_regfile_reads 57440840 # number of misc regfile reads 678system.cpu.misc_regfile_writes 820036 # number of misc regfile writes | 395system.cpu.numCycles 169875448 # number of cpu cycles simulated 396system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 397system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 398system.cpu.fetch.icacheStallCycles 5671940 # Number of cycles fetch is stalled on an Icache miss 399system.cpu.fetch.Insts 347162762 # Number of instructions fetch has processed 400system.cpu.fetch.Branches 85626366 # Number of branches that fetch encountered 401system.cpu.fetch.predictedBranches 42525160 # Number of branches that fetch has predicted taken 402system.cpu.fetch.Cycles 157499775 # Number of cycles fetch has run and was not squashing or blocked --- 275 unchanged lines hidden (view full) --- 678system.cpu.int_regfile_reads 218725741 # number of integer regfile reads 679system.cpu.int_regfile_writes 114168991 # number of integer regfile writes 680system.cpu.fp_regfile_reads 2904222 # number of floating regfile reads 681system.cpu.fp_regfile_writes 2441435 # number of floating regfile writes 682system.cpu.cc_regfile_reads 708194084 # number of cc regfile reads 683system.cpu.cc_regfile_writes 229512691 # number of cc regfile writes 684system.cpu.misc_regfile_reads 57440840 # number of misc regfile reads 685system.cpu.misc_regfile_writes 820036 # number of misc regfile writes |
| 686system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states |
|
| 679system.cpu.dcache.tags.replacements 72581 # number of replacements 680system.cpu.dcache.tags.tagsinuse 511.413915 # Cycle average of tags in use 681system.cpu.dcache.tags.total_refs 41031177 # Total number of references to valid blocks. 682system.cpu.dcache.tags.sampled_refs 73093 # Sample count of references to valid blocks. 683system.cpu.dcache.tags.avg_refs 561.355766 # Average number of references to valid blocks. 684system.cpu.dcache.tags.warmup_cycle 508221500 # Cycle when the warmup percentage was hit. 685system.cpu.dcache.tags.occ_blocks::cpu.data 511.413915 # Average occupied blocks per requestor 686system.cpu.dcache.tags.occ_percent::cpu.data 0.998855 # Average percentage of cache occupancy 687system.cpu.dcache.tags.occ_percent::total 0.998855 # Average percentage of cache occupancy 688system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 689system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 690system.cpu.dcache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id 691system.cpu.dcache.tags.age_task_id_blocks_1024::2 229 # Occupied blocks per task id 692system.cpu.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id 693system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id 694system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 695system.cpu.dcache.tags.tag_accesses 82360603 # Number of tag accesses 696system.cpu.dcache.tags.data_accesses 82360603 # Number of data accesses | 687system.cpu.dcache.tags.replacements 72581 # number of replacements 688system.cpu.dcache.tags.tagsinuse 511.413915 # Cycle average of tags in use 689system.cpu.dcache.tags.total_refs 41031177 # Total number of references to valid blocks. 690system.cpu.dcache.tags.sampled_refs 73093 # Sample count of references to valid blocks. 691system.cpu.dcache.tags.avg_refs 561.355766 # Average number of references to valid blocks. 692system.cpu.dcache.tags.warmup_cycle 508221500 # Cycle when the warmup percentage was hit. 693system.cpu.dcache.tags.occ_blocks::cpu.data 511.413915 # Average occupied blocks per requestor 694system.cpu.dcache.tags.occ_percent::cpu.data 0.998855 # Average percentage of cache occupancy 695system.cpu.dcache.tags.occ_percent::total 0.998855 # Average percentage of cache occupancy 696system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 697system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 698system.cpu.dcache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id 699system.cpu.dcache.tags.age_task_id_blocks_1024::2 229 # Occupied blocks per task id 700system.cpu.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id 701system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id 702system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 703system.cpu.dcache.tags.tag_accesses 82360603 # Number of tag accesses 704system.cpu.dcache.tags.data_accesses 82360603 # Number of data accesses |
| 705system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states |
|
| 697system.cpu.dcache.ReadReq_hits::cpu.data 28644947 # number of ReadReq hits 698system.cpu.dcache.ReadReq_hits::total 28644947 # number of ReadReq hits 699system.cpu.dcache.WriteReq_hits::cpu.data 12341311 # number of WriteReq hits 700system.cpu.dcache.WriteReq_hits::total 12341311 # number of WriteReq hits 701system.cpu.dcache.SoftPFReq_hits::cpu.data 364 # number of SoftPFReq hits 702system.cpu.dcache.SoftPFReq_hits::total 364 # number of SoftPFReq hits 703system.cpu.dcache.LoadLockedReq_hits::cpu.data 22148 # number of LoadLockedReq hits 704system.cpu.dcache.LoadLockedReq_hits::total 22148 # number of LoadLockedReq hits --- 114 unchanged lines hidden (view full) --- 819system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9972.822794 # average WriteReq mshr miss latency 820system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9972.822794 # average WriteReq mshr miss latency 821system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8513.274336 # average SoftPFReq mshr miss latency 822system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8513.274336 # average SoftPFReq mshr miss latency 823system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10129.083297 # average overall mshr miss latency 824system.cpu.dcache.demand_avg_mshr_miss_latency::total 10129.083297 # average overall mshr miss latency 825system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10126.585295 # average overall mshr miss latency 826system.cpu.dcache.overall_avg_mshr_miss_latency::total 10126.585295 # average overall mshr miss latency | 706system.cpu.dcache.ReadReq_hits::cpu.data 28644947 # number of ReadReq hits 707system.cpu.dcache.ReadReq_hits::total 28644947 # number of ReadReq hits 708system.cpu.dcache.WriteReq_hits::cpu.data 12341311 # number of WriteReq hits 709system.cpu.dcache.WriteReq_hits::total 12341311 # number of WriteReq hits 710system.cpu.dcache.SoftPFReq_hits::cpu.data 364 # number of SoftPFReq hits 711system.cpu.dcache.SoftPFReq_hits::total 364 # number of SoftPFReq hits 712system.cpu.dcache.LoadLockedReq_hits::cpu.data 22148 # number of LoadLockedReq hits 713system.cpu.dcache.LoadLockedReq_hits::total 22148 # number of LoadLockedReq hits --- 114 unchanged lines hidden (view full) --- 828system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9972.822794 # average WriteReq mshr miss latency 829system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9972.822794 # average WriteReq mshr miss latency 830system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8513.274336 # average SoftPFReq mshr miss latency 831system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8513.274336 # average SoftPFReq mshr miss latency 832system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10129.083297 # average overall mshr miss latency 833system.cpu.dcache.demand_avg_mshr_miss_latency::total 10129.083297 # average overall mshr miss latency 834system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10126.585295 # average overall mshr miss latency 835system.cpu.dcache.overall_avg_mshr_miss_latency::total 10126.585295 # average overall mshr miss latency |
| 836system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states |
|
| 827system.cpu.icache.tags.replacements 53623 # number of replacements 828system.cpu.icache.tags.tagsinuse 510.594536 # Cycle average of tags in use 829system.cpu.icache.tags.total_refs 78269055 # Total number of references to valid blocks. 830system.cpu.icache.tags.sampled_refs 54135 # Sample count of references to valid blocks. 831system.cpu.icache.tags.avg_refs 1445.812413 # Average number of references to valid blocks. 832system.cpu.icache.tags.warmup_cycle 84183071500 # Cycle when the warmup percentage was hit. 833system.cpu.icache.tags.occ_blocks::cpu.inst 510.594536 # Average occupied blocks per requestor 834system.cpu.icache.tags.occ_percent::cpu.inst 0.997255 # Average percentage of cache occupancy 835system.cpu.icache.tags.occ_percent::total 0.997255 # Average percentage of cache occupancy 836system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 837system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id 838system.cpu.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id 839system.cpu.icache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id 840system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 841system.cpu.icache.tags.age_task_id_blocks_1024::4 51 # Occupied blocks per task id 842system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 843system.cpu.icache.tags.tag_accesses 156707315 # Number of tag accesses 844system.cpu.icache.tags.data_accesses 156707315 # Number of data accesses | 837system.cpu.icache.tags.replacements 53623 # number of replacements 838system.cpu.icache.tags.tagsinuse 510.594536 # Cycle average of tags in use 839system.cpu.icache.tags.total_refs 78269055 # Total number of references to valid blocks. 840system.cpu.icache.tags.sampled_refs 54135 # Sample count of references to valid blocks. 841system.cpu.icache.tags.avg_refs 1445.812413 # Average number of references to valid blocks. 842system.cpu.icache.tags.warmup_cycle 84183071500 # Cycle when the warmup percentage was hit. 843system.cpu.icache.tags.occ_blocks::cpu.inst 510.594536 # Average occupied blocks per requestor 844system.cpu.icache.tags.occ_percent::cpu.inst 0.997255 # Average percentage of cache occupancy 845system.cpu.icache.tags.occ_percent::total 0.997255 # Average percentage of cache occupancy 846system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 847system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id 848system.cpu.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id 849system.cpu.icache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id 850system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 851system.cpu.icache.tags.age_task_id_blocks_1024::4 51 # Occupied blocks per task id 852system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 853system.cpu.icache.tags.tag_accesses 156707315 # Number of tag accesses 854system.cpu.icache.tags.data_accesses 156707315 # Number of data accesses |
| 855system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states |
|
| 845system.cpu.icache.ReadReq_hits::cpu.inst 78269055 # number of ReadReq hits 846system.cpu.icache.ReadReq_hits::total 78269055 # number of ReadReq hits 847system.cpu.icache.demand_hits::cpu.inst 78269055 # number of demand (read+write) hits 848system.cpu.icache.demand_hits::total 78269055 # number of demand (read+write) hits 849system.cpu.icache.overall_hits::cpu.inst 78269055 # number of overall hits 850system.cpu.icache.overall_hits::total 78269055 # number of overall hits 851system.cpu.icache.ReadReq_misses::cpu.inst 57535 # number of ReadReq misses 852system.cpu.icache.ReadReq_misses::total 57535 # number of ReadReq misses --- 58 unchanged lines hidden (view full) --- 911system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for overall accesses 912system.cpu.icache.overall_mshr_miss_rate::total 0.000691 # mshr miss rate for overall accesses 913system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19208.778853 # average ReadReq mshr miss latency 914system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19208.778853 # average ReadReq mshr miss latency 915system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19208.778853 # average overall mshr miss latency 916system.cpu.icache.demand_avg_mshr_miss_latency::total 19208.778853 # average overall mshr miss latency 917system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19208.778853 # average overall mshr miss latency 918system.cpu.icache.overall_avg_mshr_miss_latency::total 19208.778853 # average overall mshr miss latency | 856system.cpu.icache.ReadReq_hits::cpu.inst 78269055 # number of ReadReq hits 857system.cpu.icache.ReadReq_hits::total 78269055 # number of ReadReq hits 858system.cpu.icache.demand_hits::cpu.inst 78269055 # number of demand (read+write) hits 859system.cpu.icache.demand_hits::total 78269055 # number of demand (read+write) hits 860system.cpu.icache.overall_hits::cpu.inst 78269055 # number of overall hits 861system.cpu.icache.overall_hits::total 78269055 # number of overall hits 862system.cpu.icache.ReadReq_misses::cpu.inst 57535 # number of ReadReq misses 863system.cpu.icache.ReadReq_misses::total 57535 # number of ReadReq misses --- 58 unchanged lines hidden (view full) --- 922system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for overall accesses 923system.cpu.icache.overall_mshr_miss_rate::total 0.000691 # mshr miss rate for overall accesses 924system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19208.778853 # average ReadReq mshr miss latency 925system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19208.778853 # average ReadReq mshr miss latency 926system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19208.778853 # average overall mshr miss latency 927system.cpu.icache.demand_avg_mshr_miss_latency::total 19208.778853 # average overall mshr miss latency 928system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19208.778853 # average overall mshr miss latency 929system.cpu.icache.overall_avg_mshr_miss_latency::total 19208.778853 # average overall mshr miss latency |
| 930system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states |
|
| 919system.cpu.l2cache.prefetcher.num_hwpf_issued 9269 # number of hwpf issued 920system.cpu.l2cache.prefetcher.pfIdentified 9269 # number of prefetch candidates identified 921system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 922system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 923system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 924system.cpu.l2cache.prefetcher.pfSpanPage 1371 # number of prefetches not generated due to page crossing | 931system.cpu.l2cache.prefetcher.num_hwpf_issued 9269 # number of hwpf issued 932system.cpu.l2cache.prefetcher.pfIdentified 9269 # number of prefetch candidates identified 933system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 934system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 935system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 936system.cpu.l2cache.prefetcher.pfSpanPage 1371 # number of prefetches not generated due to page crossing |
| 937system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states |
|
| 925system.cpu.l2cache.tags.replacements 0 # number of replacements 926system.cpu.l2cache.tags.tagsinuse 2141.370901 # Cycle average of tags in use 927system.cpu.l2cache.tags.total_refs 157591 # Total number of references to valid blocks. 928system.cpu.l2cache.tags.sampled_refs 3198 # Sample count of references to valid blocks. 929system.cpu.l2cache.tags.avg_refs 49.277986 # Average number of references to valid blocks. 930system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 931system.cpu.l2cache.tags.occ_blocks::writebacks 1986.257511 # Average occupied blocks per requestor 932system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 155.113391 # Average occupied blocks per requestor --- 10 unchanged lines hidden (view full) --- 943system.cpu.l2cache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id 944system.cpu.l2cache.tags.age_task_id_blocks_1024::2 856 # Occupied blocks per task id 945system.cpu.l2cache.tags.age_task_id_blocks_1024::3 162 # Occupied blocks per task id 946system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1653 # Occupied blocks per task id 947system.cpu.l2cache.tags.occ_task_id_percent::1022 0.015503 # Percentage of cache occupancy per task id 948system.cpu.l2cache.tags.occ_task_id_percent::1024 0.179688 # Percentage of cache occupancy per task id 949system.cpu.l2cache.tags.tag_accesses 3955418 # Number of tag accesses 950system.cpu.l2cache.tags.data_accesses 3955418 # Number of data accesses | 938system.cpu.l2cache.tags.replacements 0 # number of replacements 939system.cpu.l2cache.tags.tagsinuse 2141.370901 # Cycle average of tags in use 940system.cpu.l2cache.tags.total_refs 157591 # Total number of references to valid blocks. 941system.cpu.l2cache.tags.sampled_refs 3198 # Sample count of references to valid blocks. 942system.cpu.l2cache.tags.avg_refs 49.277986 # Average number of references to valid blocks. 943system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 944system.cpu.l2cache.tags.occ_blocks::writebacks 1986.257511 # Average occupied blocks per requestor 945system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 155.113391 # Average occupied blocks per requestor --- 10 unchanged lines hidden (view full) --- 956system.cpu.l2cache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id 957system.cpu.l2cache.tags.age_task_id_blocks_1024::2 856 # Occupied blocks per task id 958system.cpu.l2cache.tags.age_task_id_blocks_1024::3 162 # Occupied blocks per task id 959system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1653 # Occupied blocks per task id 960system.cpu.l2cache.tags.occ_task_id_percent::1022 0.015503 # Percentage of cache occupancy per task id 961system.cpu.l2cache.tags.occ_task_id_percent::1024 0.179688 # Percentage of cache occupancy per task id 962system.cpu.l2cache.tags.tag_accesses 3955418 # Number of tag accesses 963system.cpu.l2cache.tags.data_accesses 3955418 # Number of data accesses |
| 964system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states |
|
| 951system.cpu.l2cache.WritebackDirty_hits::writebacks 64698 # number of WritebackDirty hits 952system.cpu.l2cache.WritebackDirty_hits::total 64698 # number of WritebackDirty hits 953system.cpu.l2cache.WritebackClean_hits::writebacks 51033 # number of WritebackClean hits 954system.cpu.l2cache.WritebackClean_hits::total 51033 # number of WritebackClean hits 955system.cpu.l2cache.ReadExReq_hits::cpu.data 8387 # number of ReadExReq hits 956system.cpu.l2cache.ReadExReq_hits::total 8387 # number of ReadExReq hits 957system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 44953 # number of ReadCleanReq hits 958system.cpu.l2cache.ReadCleanReq_hits::total 44953 # number of ReadCleanReq hits --- 148 unchanged lines hidden (view full) --- 1107system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34294.294469 # average overall mshr miss latency 1108system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64237.953732 # average overall mshr miss latency 1109system.cpu.toL2Bus.snoop_filter.tot_requests 253433 # Total number of requests made to the snoop filter. 1110system.cpu.toL2Bus.snoop_filter.hit_single_requests 126224 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1111system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10473 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1112system.cpu.toL2Bus.snoop_filter.tot_snoops 11905 # Total number of snoops made to the snoop filter. 1113system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3377 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1114system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8528 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 965system.cpu.l2cache.WritebackDirty_hits::writebacks 64698 # number of WritebackDirty hits 966system.cpu.l2cache.WritebackDirty_hits::total 64698 # number of WritebackDirty hits 967system.cpu.l2cache.WritebackClean_hits::writebacks 51033 # number of WritebackClean hits 968system.cpu.l2cache.WritebackClean_hits::total 51033 # number of WritebackClean hits 969system.cpu.l2cache.ReadExReq_hits::cpu.data 8387 # number of ReadExReq hits 970system.cpu.l2cache.ReadExReq_hits::total 8387 # number of ReadExReq hits 971system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 44953 # number of ReadCleanReq hits 972system.cpu.l2cache.ReadCleanReq_hits::total 44953 # number of ReadCleanReq hits --- 148 unchanged lines hidden (view full) --- 1121system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34294.294469 # average overall mshr miss latency 1122system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64237.953732 # average overall mshr miss latency 1123system.cpu.toL2Bus.snoop_filter.tot_requests 253433 # Total number of requests made to the snoop filter. 1124system.cpu.toL2Bus.snoop_filter.hit_single_requests 126224 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1125system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10473 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1126system.cpu.toL2Bus.snoop_filter.tot_snoops 11905 # Total number of snoops made to the snoop filter. 1127system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3377 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1128system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8528 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1129system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states |
|
| 1115system.cpu.toL2Bus.trans_dist::ReadResp 118606 # Transaction distribution 1116system.cpu.toL2Bus.trans_dist::WritebackDirty 64698 # Transaction distribution 1117system.cpu.toL2Bus.trans_dist::WritebackClean 61506 # Transaction distribution 1118system.cpu.toL2Bus.trans_dist::CleanEvict 11007 # Transaction distribution 1119system.cpu.toL2Bus.trans_dist::HardPFReq 2350 # Transaction distribution 1120system.cpu.toL2Bus.trans_dist::ReadExReq 8622 # Transaction distribution 1121system.cpu.toL2Bus.trans_dist::ReadExResp 8622 # Transaction distribution 1122system.cpu.toL2Bus.trans_dist::ReadCleanReq 54136 # Transaction distribution --- 17 unchanged lines hidden (view full) --- 1140system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1141system.cpu.toL2Bus.snoop_fanout::total 140586 # Request fanout histogram 1142system.cpu.toL2Bus.reqLayer0.occupancy 252920500 # Layer occupancy (ticks) 1143system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 1144system.cpu.toL2Bus.respLayer0.occupancy 81207989 # Layer occupancy (ticks) 1145system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1146system.cpu.toL2Bus.respLayer1.occupancy 109644490 # Layer occupancy (ticks) 1147system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 1130system.cpu.toL2Bus.trans_dist::ReadResp 118606 # Transaction distribution 1131system.cpu.toL2Bus.trans_dist::WritebackDirty 64698 # Transaction distribution 1132system.cpu.toL2Bus.trans_dist::WritebackClean 61506 # Transaction distribution 1133system.cpu.toL2Bus.trans_dist::CleanEvict 11007 # Transaction distribution 1134system.cpu.toL2Bus.trans_dist::HardPFReq 2350 # Transaction distribution 1135system.cpu.toL2Bus.trans_dist::ReadExReq 8622 # Transaction distribution 1136system.cpu.toL2Bus.trans_dist::ReadExResp 8622 # Transaction distribution 1137system.cpu.toL2Bus.trans_dist::ReadCleanReq 54136 # Transaction distribution --- 17 unchanged lines hidden (view full) --- 1155system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1156system.cpu.toL2Bus.snoop_fanout::total 140586 # Request fanout histogram 1157system.cpu.toL2Bus.reqLayer0.occupancy 252920500 # Layer occupancy (ticks) 1158system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 1159system.cpu.toL2Bus.respLayer0.occupancy 81207989 # Layer occupancy (ticks) 1160system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1161system.cpu.toL2Bus.respLayer1.occupancy 109644490 # Layer occupancy (ticks) 1162system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 1163system.membus.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states |
|
| 1148system.membus.trans_dist::ReadResp 12116 # Transaction distribution 1149system.membus.trans_dist::ReadExReq 234 # Transaction distribution 1150system.membus.trans_dist::ReadExResp 234 # Transaction distribution 1151system.membus.trans_dist::ReadSharedReq 12117 # Transaction distribution 1152system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 24701 # Packet count per connected master and slave (bytes) 1153system.membus.pkt_count::total 24701 # Packet count per connected master and slave (bytes) 1154system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 790400 # Cumulative packet size per connected master and slave (bytes) 1155system.membus.pkt_size::total 790400 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- | 1164system.membus.trans_dist::ReadResp 12116 # Transaction distribution 1165system.membus.trans_dist::ReadExReq 234 # Transaction distribution 1166system.membus.trans_dist::ReadExResp 234 # Transaction distribution 1167system.membus.trans_dist::ReadSharedReq 12117 # Transaction distribution 1168system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 24701 # Packet count per connected master and slave (bytes) 1169system.membus.pkt_count::total 24701 # Packet count per connected master and slave (bytes) 1170system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 790400 # Cumulative packet size per connected master and slave (bytes) 1171system.membus.pkt_size::total 790400 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- |