| stats.txt (11441:0edcf757b6a2) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.084938 # Number of seconds simulated 4sim_ticks 84937723500 # Number of ticks simulated 5final_tick 84937723500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.084938 # Number of seconds simulated 4sim_ticks 84937723500 # Number of ticks simulated 5final_tick 84937723500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 146803 # Simulator instruction rate (inst/s) 8host_op_rate 154755 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 72367413 # Simulator tick rate (ticks/s) | 7host_inst_rate 152098 # Simulator instruction rate (inst/s) 8host_op_rate 160337 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 74977715 # Simulator tick rate (ticks/s) |
| 10host_mem_usage 271624 # Number of bytes of host memory used | 10host_mem_usage 271624 # Number of bytes of host memory used |
| 11host_seconds 1173.70 # Real time elapsed on the host | 11host_seconds 1132.84 # Real time elapsed on the host |
| 12sim_insts 172303022 # Number of instructions simulated 13sim_ops 181635954 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 587328 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 132096 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 70976 # Number of bytes read from this memory 19system.physmem.bytes_read::total 790400 # Number of bytes read from this memory --- 747 unchanged lines hidden (view full) --- 767system.cpu.dcache.overall_avg_miss_latency::cpu.data 11644.276561 # average overall miss latency 768system.cpu.dcache.overall_avg_miss_latency::total 11644.276561 # average overall miss latency 769system.cpu.dcache.blocked_cycles::no_mshrs 166 # number of cycles access was blocked 770system.cpu.dcache.blocked_cycles::no_targets 10738 # number of cycles access was blocked 771system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked 772system.cpu.dcache.blocked::no_targets 864 # number of cycles access was blocked 773system.cpu.dcache.avg_blocked_cycles::no_mshrs 83 # average number of cycles each access was blocked 774system.cpu.dcache.avg_blocked_cycles::no_targets 12.428241 # average number of cycles each access was blocked | 12sim_insts 172303022 # Number of instructions simulated 13sim_ops 181635954 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 587328 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 132096 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 70976 # Number of bytes read from this memory 19system.physmem.bytes_read::total 790400 # Number of bytes read from this memory --- 747 unchanged lines hidden (view full) --- 767system.cpu.dcache.overall_avg_miss_latency::cpu.data 11644.276561 # average overall miss latency 768system.cpu.dcache.overall_avg_miss_latency::total 11644.276561 # average overall miss latency 769system.cpu.dcache.blocked_cycles::no_mshrs 166 # number of cycles access was blocked 770system.cpu.dcache.blocked_cycles::no_targets 10738 # number of cycles access was blocked 771system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked 772system.cpu.dcache.blocked::no_targets 864 # number of cycles access was blocked 773system.cpu.dcache.avg_blocked_cycles::no_mshrs 83 # average number of cycles each access was blocked 774system.cpu.dcache.avg_blocked_cycles::no_targets 12.428241 # average number of cycles each access was blocked |
| 775system.cpu.dcache.fast_writes 0 # number of fast writes performed 776system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 777system.cpu.dcache.writebacks::writebacks 72581 # number of writebacks 778system.cpu.dcache.writebacks::total 72581 # number of writebacks 779system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24802 # number of ReadReq MSHR hits 780system.cpu.dcache.ReadReq_mshr_hits::total 24802 # number of ReadReq MSHR hits 781system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14421 # number of WriteReq MSHR hits 782system.cpu.dcache.WriteReq_mshr_hits::total 14421 # number of WriteReq MSHR hits 783system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 259 # number of LoadLockedReq MSHR hits 784system.cpu.dcache.LoadLockedReq_mshr_hits::total 259 # number of LoadLockedReq MSHR hits --- 36 unchanged lines hidden (view full) --- 821system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9972.822794 # average WriteReq mshr miss latency 822system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9972.822794 # average WriteReq mshr miss latency 823system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8513.274336 # average SoftPFReq mshr miss latency 824system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8513.274336 # average SoftPFReq mshr miss latency 825system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10129.083297 # average overall mshr miss latency 826system.cpu.dcache.demand_avg_mshr_miss_latency::total 10129.083297 # average overall mshr miss latency 827system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10126.585295 # average overall mshr miss latency 828system.cpu.dcache.overall_avg_mshr_miss_latency::total 10126.585295 # average overall mshr miss latency | 775system.cpu.dcache.writebacks::writebacks 72581 # number of writebacks 776system.cpu.dcache.writebacks::total 72581 # number of writebacks 777system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24802 # number of ReadReq MSHR hits 778system.cpu.dcache.ReadReq_mshr_hits::total 24802 # number of ReadReq MSHR hits 779system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14421 # number of WriteReq MSHR hits 780system.cpu.dcache.WriteReq_mshr_hits::total 14421 # number of WriteReq MSHR hits 781system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 259 # number of LoadLockedReq MSHR hits 782system.cpu.dcache.LoadLockedReq_mshr_hits::total 259 # number of LoadLockedReq MSHR hits --- 36 unchanged lines hidden (view full) --- 819system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9972.822794 # average WriteReq mshr miss latency 820system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9972.822794 # average WriteReq mshr miss latency 821system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8513.274336 # average SoftPFReq mshr miss latency 822system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8513.274336 # average SoftPFReq mshr miss latency 823system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10129.083297 # average overall mshr miss latency 824system.cpu.dcache.demand_avg_mshr_miss_latency::total 10129.083297 # average overall mshr miss latency 825system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10126.585295 # average overall mshr miss latency 826system.cpu.dcache.overall_avg_mshr_miss_latency::total 10126.585295 # average overall mshr miss latency |
| 829system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 830system.cpu.icache.tags.replacements 53623 # number of replacements 831system.cpu.icache.tags.tagsinuse 510.594536 # Cycle average of tags in use 832system.cpu.icache.tags.total_refs 78269055 # Total number of references to valid blocks. 833system.cpu.icache.tags.sampled_refs 54135 # Sample count of references to valid blocks. 834system.cpu.icache.tags.avg_refs 1445.812413 # Average number of references to valid blocks. 835system.cpu.icache.tags.warmup_cycle 84183071500 # Cycle when the warmup percentage was hit. 836system.cpu.icache.tags.occ_blocks::cpu.inst 510.594536 # Average occupied blocks per requestor 837system.cpu.icache.tags.occ_percent::cpu.inst 0.997255 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 882system.cpu.icache.overall_avg_miss_latency::cpu.inst 20078.185974 # average overall miss latency 883system.cpu.icache.overall_avg_miss_latency::total 20078.185974 # average overall miss latency 884system.cpu.icache.blocked_cycles::no_mshrs 73195 # number of cycles access was blocked 885system.cpu.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked 886system.cpu.icache.blocked::no_mshrs 3246 # number of cycles access was blocked 887system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked 888system.cpu.icache.avg_blocked_cycles::no_mshrs 22.549291 # average number of cycles each access was blocked 889system.cpu.icache.avg_blocked_cycles::no_targets 13.500000 # average number of cycles each access was blocked | 827system.cpu.icache.tags.replacements 53623 # number of replacements 828system.cpu.icache.tags.tagsinuse 510.594536 # Cycle average of tags in use 829system.cpu.icache.tags.total_refs 78269055 # Total number of references to valid blocks. 830system.cpu.icache.tags.sampled_refs 54135 # Sample count of references to valid blocks. 831system.cpu.icache.tags.avg_refs 1445.812413 # Average number of references to valid blocks. 832system.cpu.icache.tags.warmup_cycle 84183071500 # Cycle when the warmup percentage was hit. 833system.cpu.icache.tags.occ_blocks::cpu.inst 510.594536 # Average occupied blocks per requestor 834system.cpu.icache.tags.occ_percent::cpu.inst 0.997255 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 879system.cpu.icache.overall_avg_miss_latency::cpu.inst 20078.185974 # average overall miss latency 880system.cpu.icache.overall_avg_miss_latency::total 20078.185974 # average overall miss latency 881system.cpu.icache.blocked_cycles::no_mshrs 73195 # number of cycles access was blocked 882system.cpu.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked 883system.cpu.icache.blocked::no_mshrs 3246 # number of cycles access was blocked 884system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked 885system.cpu.icache.avg_blocked_cycles::no_mshrs 22.549291 # average number of cycles each access was blocked 886system.cpu.icache.avg_blocked_cycles::no_targets 13.500000 # average number of cycles each access was blocked |
| 890system.cpu.icache.fast_writes 0 # number of fast writes performed 891system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 892system.cpu.icache.writebacks::writebacks 53623 # number of writebacks 893system.cpu.icache.writebacks::total 53623 # number of writebacks 894system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3399 # number of ReadReq MSHR hits 895system.cpu.icache.ReadReq_mshr_hits::total 3399 # number of ReadReq MSHR hits 896system.cpu.icache.demand_mshr_hits::cpu.inst 3399 # number of demand (read+write) MSHR hits 897system.cpu.icache.demand_mshr_hits::total 3399 # number of demand (read+write) MSHR hits 898system.cpu.icache.overall_mshr_hits::cpu.inst 3399 # number of overall MSHR hits 899system.cpu.icache.overall_mshr_hits::total 3399 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 916system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for overall accesses 917system.cpu.icache.overall_mshr_miss_rate::total 0.000691 # mshr miss rate for overall accesses 918system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19208.778853 # average ReadReq mshr miss latency 919system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19208.778853 # average ReadReq mshr miss latency 920system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19208.778853 # average overall mshr miss latency 921system.cpu.icache.demand_avg_mshr_miss_latency::total 19208.778853 # average overall mshr miss latency 922system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19208.778853 # average overall mshr miss latency 923system.cpu.icache.overall_avg_mshr_miss_latency::total 19208.778853 # average overall mshr miss latency | 887system.cpu.icache.writebacks::writebacks 53623 # number of writebacks 888system.cpu.icache.writebacks::total 53623 # number of writebacks 889system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3399 # number of ReadReq MSHR hits 890system.cpu.icache.ReadReq_mshr_hits::total 3399 # number of ReadReq MSHR hits 891system.cpu.icache.demand_mshr_hits::cpu.inst 3399 # number of demand (read+write) MSHR hits 892system.cpu.icache.demand_mshr_hits::total 3399 # number of demand (read+write) MSHR hits 893system.cpu.icache.overall_mshr_hits::cpu.inst 3399 # number of overall MSHR hits 894system.cpu.icache.overall_mshr_hits::total 3399 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 911system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for overall accesses 912system.cpu.icache.overall_mshr_miss_rate::total 0.000691 # mshr miss rate for overall accesses 913system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19208.778853 # average ReadReq mshr miss latency 914system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19208.778853 # average ReadReq mshr miss latency 915system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19208.778853 # average overall mshr miss latency 916system.cpu.icache.demand_avg_mshr_miss_latency::total 19208.778853 # average overall mshr miss latency 917system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19208.778853 # average overall mshr miss latency 918system.cpu.icache.overall_avg_mshr_miss_latency::total 19208.778853 # average overall mshr miss latency |
| 924system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 925system.cpu.l2cache.prefetcher.num_hwpf_issued 9269 # number of hwpf issued 926system.cpu.l2cache.prefetcher.pfIdentified 9269 # number of prefetch candidates identified 927system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 928system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 929system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 930system.cpu.l2cache.prefetcher.pfSpanPage 1371 # number of prefetches not generated due to page crossing 931system.cpu.l2cache.tags.replacements 0 # number of replacements 932system.cpu.l2cache.tags.tagsinuse 2141.370901 # Cycle average of tags in use --- 102 unchanged lines hidden (view full) --- 1035system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77577.627772 # average overall miss latency 1036system.cpu.l2cache.overall_avg_miss_latency::total 75576.174825 # average overall miss latency 1037system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1038system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1039system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1040system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1041system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1042system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 919system.cpu.l2cache.prefetcher.num_hwpf_issued 9269 # number of hwpf issued 920system.cpu.l2cache.prefetcher.pfIdentified 9269 # number of prefetch candidates identified 921system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 922system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 923system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 924system.cpu.l2cache.prefetcher.pfSpanPage 1371 # number of prefetches not generated due to page crossing 925system.cpu.l2cache.tags.replacements 0 # number of replacements 926system.cpu.l2cache.tags.tagsinuse 2141.370901 # Cycle average of tags in use --- 102 unchanged lines hidden (view full) --- 1029system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77577.627772 # average overall miss latency 1030system.cpu.l2cache.overall_avg_miss_latency::total 75576.174825 # average overall miss latency 1031system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1032system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1033system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1034system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1035system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1036system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1043system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1044system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 1045system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1 # number of ReadExReq MSHR hits 1046system.cpu.l2cache.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits 1047system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits 1048system.cpu.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits 1049system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 9 # number of ReadSharedReq MSHR hits 1050system.cpu.l2cache.ReadSharedReq_mshr_hits::total 9 # number of ReadSharedReq MSHR hits 1051system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits 1052system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits --- 56 unchanged lines hidden (view full) --- 1109system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71733.333333 # average ReadSharedReq mshr miss latency 1110system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69132.327304 # average overall mshr miss latency 1111system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71590.843023 # average overall mshr miss latency 1112system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69583.703967 # average overall mshr miss latency 1113system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69132.327304 # average overall mshr miss latency 1114system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71590.843023 # average overall mshr miss latency 1115system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34294.294469 # average overall mshr miss latency 1116system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64237.953732 # average overall mshr miss latency | 1037system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1 # number of ReadExReq MSHR hits 1038system.cpu.l2cache.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits 1039system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits 1040system.cpu.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits 1041system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 9 # number of ReadSharedReq MSHR hits 1042system.cpu.l2cache.ReadSharedReq_mshr_hits::total 9 # number of ReadSharedReq MSHR hits 1043system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits 1044system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits --- 56 unchanged lines hidden (view full) --- 1101system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71733.333333 # average ReadSharedReq mshr miss latency 1102system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69132.327304 # average overall mshr miss latency 1103system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71590.843023 # average overall mshr miss latency 1104system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69583.703967 # average overall mshr miss latency 1105system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69132.327304 # average overall mshr miss latency 1106system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71590.843023 # average overall mshr miss latency 1107system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34294.294469 # average overall mshr miss latency 1108system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64237.953732 # average overall mshr miss latency |
| 1117system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 1118system.cpu.toL2Bus.snoop_filter.tot_requests 253433 # Total number of requests made to the snoop filter. 1119system.cpu.toL2Bus.snoop_filter.hit_single_requests 126224 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1120system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10473 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1121system.cpu.toL2Bus.snoop_filter.tot_snoops 11905 # Total number of snoops made to the snoop filter. 1122system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3377 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1123system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8528 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1124system.cpu.toL2Bus.trans_dist::ReadResp 118606 # Transaction distribution 1125system.cpu.toL2Bus.trans_dist::WritebackDirty 64698 # Transaction distribution --- 56 unchanged lines hidden --- | 1109system.cpu.toL2Bus.snoop_filter.tot_requests 253433 # Total number of requests made to the snoop filter. 1110system.cpu.toL2Bus.snoop_filter.hit_single_requests 126224 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1111system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10473 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1112system.cpu.toL2Bus.snoop_filter.tot_snoops 11905 # Total number of snoops made to the snoop filter. 1113system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3377 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1114system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8528 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1115system.cpu.toL2Bus.trans_dist::ReadResp 118606 # Transaction distribution 1116system.cpu.toL2Bus.trans_dist::WritebackDirty 64698 # Transaction distribution --- 56 unchanged lines hidden --- |