| stats.txt (10726:8a20e2a1562d) | stats.txt (10736:4433fb00fa7d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.085027 # Number of seconds simulated 4sim_ticks 85027009000 # Number of ticks simulated 5final_tick 85027009000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 134467 # Simulator instruction rate (inst/s) 8host_op_rate 141751 # Simulator op (including micro ops) rate (op/s) --- 642 unchanged lines hidden (view full) --- 651system.cpu.commit.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction 652system.cpu.commit.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction 653system.cpu.commit.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction 654system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Class of committed instruction 655system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 656system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 657system.cpu.commit.op_class_0::total 181650341 # Class of committed instruction 658system.cpu.commit.bw_lim_events 3352927 # number cycles where commit BW limit reached | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.085027 # Number of seconds simulated 4sim_ticks 85027009000 # Number of ticks simulated 5final_tick 85027009000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 134467 # Simulator instruction rate (inst/s) 8host_op_rate 141751 # Simulator op (including micro ops) rate (op/s) --- 642 unchanged lines hidden (view full) --- 651system.cpu.commit.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction 652system.cpu.commit.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction 653system.cpu.commit.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction 654system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Class of committed instruction 655system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 656system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 657system.cpu.commit.op_class_0::total 181650341 # Class of committed instruction 658system.cpu.commit.bw_lim_events 3352927 # number cycles where commit BW limit reached |
| 659system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | |
| 660system.cpu.rob.rob_reads 406304779 # The number of ROB reads 661system.cpu.rob.rob_writes 513839131 # The number of ROB writes 662system.cpu.timesIdled 3408 # Number of times that the entire CPU went into an idle state and unscheduled itself 663system.cpu.idleCycles 140895 # Total number of cycles that the CPU has spent unscheduled due to idling 664system.cpu.committedInsts 172303021 # Number of Instructions Simulated 665system.cpu.committedOps 181635953 # Number of Ops (including micro ops) Simulated 666system.cpu.cpi 0.986947 # CPI: Cycles Per Instruction 667system.cpu.cpi_total 0.986947 # CPI: Total CPI of All Threads --- 492 unchanged lines hidden --- | 659system.cpu.rob.rob_reads 406304779 # The number of ROB reads 660system.cpu.rob.rob_writes 513839131 # The number of ROB writes 661system.cpu.timesIdled 3408 # Number of times that the entire CPU went into an idle state and unscheduled itself 662system.cpu.idleCycles 140895 # Total number of cycles that the CPU has spent unscheduled due to idling 663system.cpu.committedInsts 172303021 # Number of Instructions Simulated 664system.cpu.committedOps 181635953 # Number of Ops (including micro ops) Simulated 665system.cpu.cpi 0.986947 # CPI: Cycles Per Instruction 666system.cpu.cpi_total 0.986947 # CPI: Total CPI of All Threads --- 492 unchanged lines hidden --- |