| stats.txt (10229:aae7735450a9) | stats.txt (10242:cb4e86c17767) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.074209 # Number of seconds simulated 4sim_ticks 74208571000 # Number of ticks simulated 5final_tick 74208571000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.074057 # Number of seconds simulated 4sim_ticks 74056845500 # Number of ticks simulated 5final_tick 74056845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 109569 # Simulator instruction rate (inst/s) 8host_op_rate 119969 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 47190079 # Simulator tick rate (ticks/s) 10host_mem_usage 316768 # Number of bytes of host memory used 11host_seconds 1572.55 # Real time elapsed on the host | 7host_inst_rate 115398 # Simulator instruction rate (inst/s) 8host_op_rate 126351 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 49598898 # Simulator tick rate (ticks/s) 10host_mem_usage 265028 # Number of bytes of host memory used 11host_seconds 1493.11 # Real time elapsed on the host |
| 12sim_insts 172303021 # Number of instructions simulated 13sim_ops 188656503 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 172303021 # Number of instructions simulated 13sim_ops 188656503 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 131456 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 111808 # Number of bytes read from this memory 18system.physmem.bytes_read::total 243264 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 131456 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 131456 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 2054 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1747 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 3801 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1771440 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 1506672 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 3278112 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1771440 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1771440 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1771440 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 1506672 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 3278112 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 3802 # Number of read requests accepted | 16system.physmem.bytes_read::cpu.inst 131840 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 112192 # Number of bytes read from this memory 18system.physmem.bytes_read::total 244032 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 131840 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 131840 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 2060 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1753 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 3813 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1780254 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 1514944 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 3295198 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1780254 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1780254 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1780254 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 1514944 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 3295198 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 3814 # Number of read requests accepted |
| 33system.physmem.writeReqs 0 # Number of write requests accepted | 33system.physmem.writeReqs 0 # Number of write requests accepted |
| 34system.physmem.readBursts 3802 # Number of DRAM read bursts, including those serviced by the write queue | 34system.physmem.readBursts 3814 # Number of DRAM read bursts, including those serviced by the write queue |
| 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 36system.physmem.bytesReadDRAM 243328 # Total number of bytes read from DRAM | 36system.physmem.bytesReadDRAM 244096 # Total number of bytes read from DRAM |
| 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 39system.physmem.bytesReadSys 243328 # Total read bytes from the system interface side | 39system.physmem.bytesReadSys 244096 # Total read bytes from the system interface side |
| 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one | 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 306 # Per bank write bursts 45system.physmem.perBankRdBursts::1 216 # Per bank write bursts | 43system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 307 # Per bank write bursts 45system.physmem.perBankRdBursts::1 215 # Per bank write bursts |
| 46system.physmem.perBankRdBursts::2 134 # Per bank write bursts | 46system.physmem.perBankRdBursts::2 134 # Per bank write bursts |
| 47system.physmem.perBankRdBursts::3 308 # Per bank write bursts 48system.physmem.perBankRdBursts::4 298 # Per bank write bursts | 47system.physmem.perBankRdBursts::3 310 # Per bank write bursts 48system.physmem.perBankRdBursts::4 299 # Per bank write bursts |
| 49system.physmem.perBankRdBursts::5 300 # Per bank write bursts 50system.physmem.perBankRdBursts::6 265 # Per bank write bursts | 49system.physmem.perBankRdBursts::5 300 # Per bank write bursts 50system.physmem.perBankRdBursts::6 265 # Per bank write bursts |
| 51system.physmem.perBankRdBursts::7 217 # Per bank write bursts | 51system.physmem.perBankRdBursts::7 223 # Per bank write bursts |
| 52system.physmem.perBankRdBursts::8 246 # Per bank write bursts | 52system.physmem.perBankRdBursts::8 246 # Per bank write bursts |
| 53system.physmem.perBankRdBursts::9 215 # Per bank write bursts | 53system.physmem.perBankRdBursts::9 213 # Per bank write bursts |
| 54system.physmem.perBankRdBursts::10 289 # Per bank write bursts | 54system.physmem.perBankRdBursts::10 289 # Per bank write bursts |
| 55system.physmem.perBankRdBursts::11 192 # Per bank write bursts | 55system.physmem.perBankRdBursts::11 196 # Per bank write bursts |
| 56system.physmem.perBankRdBursts::12 190 # Per bank write bursts | 56system.physmem.perBankRdBursts::12 190 # Per bank write bursts |
| 57system.physmem.perBankRdBursts::13 208 # Per bank write bursts 58system.physmem.perBankRdBursts::14 218 # Per bank write bursts 59system.physmem.perBankRdBursts::15 200 # Per bank write bursts | 57system.physmem.perBankRdBursts::13 207 # Per bank write bursts 58system.physmem.perBankRdBursts::14 219 # Per bank write bursts 59system.physmem.perBankRdBursts::15 201 # Per bank write bursts |
| 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 74208552500 # Total gap between requests | 78system.physmem.totGap 74056827000 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 85system.physmem.readPktSize::6 3802 # Read request sizes (log2) | 85system.physmem.readPktSize::6 3814 # Read request sizes (log2) |
| 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) | 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 93system.physmem.rdQLenPdf::0 2914 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 704 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 139 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see | 93system.physmem.rdQLenPdf::0 2889 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 752 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 131 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 34 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see |
| 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 75 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 75 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 189system.physmem.bytesPerActivate::samples 765 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 315.649673 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 194.993895 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 311.806865 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 244 31.90% 31.90% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 208 27.19% 59.08% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 73 9.54% 68.63% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 46 6.01% 74.64% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 29 3.79% 78.43% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 70 9.15% 87.58% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 12 1.57% 89.15% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 15 1.96% 91.11% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 68 8.89% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 765 # Bytes accessed per row activation 203system.physmem.totQLat 30320750 # Total ticks spent queuing 204system.physmem.totMemAccLat 101608250 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 19010000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 7974.95 # Average queueing delay per DRAM burst | 189system.physmem.bytesPerActivate::samples 775 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 313.641290 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 192.687696 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 311.293227 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 258 33.29% 33.29% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 189 24.39% 57.68% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 87 11.23% 68.90% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 51 6.58% 75.48% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 41 5.29% 80.77% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 31 4.00% 84.77% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 43 5.55% 90.32% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 10 1.29% 91.61% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 65 8.39% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 775 # Bytes accessed per row activation 203system.physmem.totQLat 30109750 # Total ticks spent queuing 204system.physmem.totMemAccLat 101622250 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 19070000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 7894.53 # Average queueing delay per DRAM burst |
| 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 208system.physmem.avgMemAccLat 26724.95 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 3.28 # Average DRAM read bandwidth in MiByte/s | 208system.physmem.avgMemAccLat 26644.53 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 3.30 # Average DRAM read bandwidth in MiByte/s |
| 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 211system.physmem.avgRdBWSys 3.28 # Average system read bandwidth in MiByte/s | 211system.physmem.avgRdBWSys 3.30 # Average system read bandwidth in MiByte/s |
| 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.03 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.03 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 217system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing | 217system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing |
| 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 219system.physmem.readRowHits 3030 # Number of row buffer hits during reads | 219system.physmem.readRowHits 3033 # Number of row buffer hits during reads |
| 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 221system.physmem.readRowHitRate 79.69 # Row buffer hit rate for reads | 221system.physmem.readRowHitRate 79.52 # Row buffer hit rate for reads |
| 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 223system.physmem.avgGap 19518293.66 # Average gap between requests 224system.physmem.pageHitRate 79.69 # Row buffer hit rate, read and write combined 225system.physmem.memoryStateTime::IDLE 70857777500 # Time in different power states 226system.physmem.memoryStateTime::REF 2477800000 # Time in different power states | 223system.physmem.avgGap 19417101.99 # Average gap between requests 224system.physmem.pageHitRate 79.52 # Row buffer hit rate, read and write combined 225system.physmem.memoryStateTime::IDLE 70721348250 # Time in different power states 226system.physmem.memoryStateTime::REF 2472860000 # Time in different power states |
| 227system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 227system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 228system.physmem.memoryStateTime::ACT 867720500 # Time in different power states | 228system.physmem.memoryStateTime::ACT 861203250 # Time in different power states |
| 229system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 229system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 230system.membus.throughput 3278112 # Throughput (bytes/s) 231system.membus.trans_dist::ReadReq 2731 # Transaction distribution 232system.membus.trans_dist::ReadResp 2730 # Transaction distribution 233system.membus.trans_dist::ReadExReq 1071 # Transaction distribution 234system.membus.trans_dist::ReadExResp 1071 # Transaction distribution 235system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7603 # Packet count per connected master and slave (bytes) 236system.membus.pkt_count::total 7603 # Packet count per connected master and slave (bytes) 237system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 243264 # Cumulative packet size per connected master and slave (bytes) 238system.membus.tot_pkt_size::total 243264 # Cumulative packet size per connected master and slave (bytes) 239system.membus.data_through_bus 243264 # Total data (bytes) | 230system.membus.throughput 3295198 # Throughput (bytes/s) 231system.membus.trans_dist::ReadReq 2737 # Transaction distribution 232system.membus.trans_dist::ReadResp 2736 # Transaction distribution 233system.membus.trans_dist::UpgradeReq 2 # Transaction distribution 234system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 235system.membus.trans_dist::ReadExReq 1077 # Transaction distribution 236system.membus.trans_dist::ReadExResp 1077 # Transaction distribution 237system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7631 # Packet count per connected master and slave (bytes) 238system.membus.pkt_count::total 7631 # Packet count per connected master and slave (bytes) 239system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 244032 # Cumulative packet size per connected master and slave (bytes) 240system.membus.tot_pkt_size::total 244032 # Cumulative packet size per connected master and slave (bytes) 241system.membus.data_through_bus 244032 # Total data (bytes) |
| 240system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 242system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 241system.membus.reqLayer0.occupancy 4745000 # Layer occupancy (ticks) | 243system.membus.reqLayer0.occupancy 4541000 # Layer occupancy (ticks) |
| 242system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 244system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 243system.membus.respLayer1.occupancy 35718000 # Layer occupancy (ticks) | 245system.membus.respLayer1.occupancy 35636248 # Layer occupancy (ticks) |
| 244system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 245system.cpu_clk_domain.clock 500 # Clock period in ticks | 246system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 247system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 246system.cpu.branchPred.lookups 94830067 # Number of BP lookups 247system.cpu.branchPred.condPredicted 74823235 # Number of conditional branches predicted 248system.cpu.branchPred.condIncorrect 6280063 # Number of conditional branches incorrect 249system.cpu.branchPred.BTBLookups 44671635 # Number of BTB lookups 250system.cpu.branchPred.BTBHits 43055955 # Number of BTB hits | 248system.cpu.branchPred.lookups 95688557 # Number of BP lookups 249system.cpu.branchPred.condPredicted 75485372 # Number of conditional branches predicted 250system.cpu.branchPred.condIncorrect 6295432 # Number of conditional branches incorrect 251system.cpu.branchPred.BTBLookups 45268261 # Number of BTB lookups 252system.cpu.branchPred.BTBHits 43530249 # Number of BTB hits |
| 251system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 253system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 252system.cpu.branchPred.BTBHitPct 96.383208 # BTB Hit Percentage 253system.cpu.branchPred.usedRAS 4354004 # Number of times the RAS was used to get a target. 254system.cpu.branchPred.RASInCorrect 88575 # Number of incorrect RAS predictions. | 254system.cpu.branchPred.BTBHitPct 96.160639 # BTB Hit Percentage 255system.cpu.branchPred.usedRAS 4420185 # Number of times the RAS was used to get a target. 256system.cpu.branchPred.RASInCorrect 89338 # Number of incorrect RAS predictions. |
| 255system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 256system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 257system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 258system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 259system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 260system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 261system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 262system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 69 unchanged lines hidden (view full) --- 332system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 333system.cpu.itb.read_accesses 0 # DTB read accesses 334system.cpu.itb.write_accesses 0 # DTB write accesses 335system.cpu.itb.inst_accesses 0 # ITB inst accesses 336system.cpu.itb.hits 0 # DTB hits 337system.cpu.itb.misses 0 # DTB misses 338system.cpu.itb.accesses 0 # DTB accesses 339system.cpu.workload.num_syscalls 400 # Number of system calls | 257system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 258system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 259system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 260system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 261system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 262system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 263system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 264system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 69 unchanged lines hidden (view full) --- 334system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 335system.cpu.itb.read_accesses 0 # DTB read accesses 336system.cpu.itb.write_accesses 0 # DTB write accesses 337system.cpu.itb.inst_accesses 0 # ITB inst accesses 338system.cpu.itb.hits 0 # DTB hits 339system.cpu.itb.misses 0 # DTB misses 340system.cpu.itb.accesses 0 # DTB accesses 341system.cpu.workload.num_syscalls 400 # Number of system calls |
| 340system.cpu.numCycles 148417143 # number of cpu cycles simulated | 342system.cpu.numCycles 148113692 # number of cpu cycles simulated |
| 341system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 342system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 343system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 344system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 343system.cpu.fetch.icacheStallCycles 39654365 # Number of cycles fetch is stalled on an Icache miss 344system.cpu.fetch.Insts 380231735 # Number of instructions fetch has processed 345system.cpu.fetch.Branches 94830067 # Number of branches that fetch encountered 346system.cpu.fetch.predictedBranches 47409959 # Number of branches that fetch has predicted taken 347system.cpu.fetch.Cycles 80369944 # Number of cycles fetch has run and was not squashing or blocked 348system.cpu.fetch.SquashCycles 27285630 # Number of cycles fetch has spent squashing 349system.cpu.fetch.BlockedCycles 7202415 # Number of cycles fetch has spent blocked 350system.cpu.fetch.MiscStallCycles 10 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 351system.cpu.fetch.PendingTrapStallCycles 5794 # Number of stall cycles due to pending traps | 345system.cpu.fetch.icacheStallCycles 40192835 # Number of cycles fetch is stalled on an Icache miss 346system.cpu.fetch.Insts 385592009 # Number of instructions fetch has processed 347system.cpu.fetch.Branches 95688557 # Number of branches that fetch encountered 348system.cpu.fetch.predictedBranches 47950434 # Number of branches that fetch has predicted taken 349system.cpu.fetch.Cycles 81543775 # Number of cycles fetch has run and was not squashing or blocked 350system.cpu.fetch.SquashCycles 28012255 # Number of cycles fetch has spent squashing 351system.cpu.fetch.BlockedCycles 4465673 # Number of cycles fetch has spent blocked 352system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 353system.cpu.fetch.PendingTrapStallCycles 5818 # Number of stall cycles due to pending traps |
| 352system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions | 354system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions |
| 353system.cpu.fetch.IcacheWaitRetryStallCycles 50 # Number of stall cycles due to full MSHR 354system.cpu.fetch.CacheLines 36851066 # Number of cache lines fetched 355system.cpu.fetch.IcacheSquashes 1832690 # Number of outstanding Icache misses that were squashed 356system.cpu.fetch.rateDist::samples 148222429 # Number of instructions fetched each cycle (Total) 357system.cpu.fetch.rateDist::mean 2.802512 # Number of instructions fetched each cycle (Total) 358system.cpu.fetch.rateDist::stdev 3.153204 # Number of instructions fetched each cycle (Total) | 355system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR 356system.cpu.fetch.CacheLines 37392446 # Number of cache lines fetched 357system.cpu.fetch.IcacheSquashes 1863811 # Number of outstanding Icache misses that were squashed 358system.cpu.fetch.rateDist::samples 147907378 # Number of instructions fetched each cycle (Total) 359system.cpu.fetch.rateDist::mean 2.849949 # Number of instructions fetched each cycle (Total) 360system.cpu.fetch.rateDist::stdev 3.160123 # Number of instructions fetched each cycle (Total) |
| 359system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 361system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 360system.cpu.fetch.rateDist::0 68020985 45.89% 45.89% # Number of instructions fetched each cycle (Total) 361system.cpu.fetch.rateDist::1 5256509 3.55% 49.44% # Number of instructions fetched each cycle (Total) 362system.cpu.fetch.rateDist::2 10534999 7.11% 56.55% # Number of instructions fetched each cycle (Total) 363system.cpu.fetch.rateDist::3 10284828 6.94% 63.48% # Number of instructions fetched each cycle (Total) 364system.cpu.fetch.rateDist::4 8666572 5.85% 69.33% # Number of instructions fetched each cycle (Total) 365system.cpu.fetch.rateDist::5 6537070 4.41% 73.74% # Number of instructions fetched each cycle (Total) 366system.cpu.fetch.rateDist::6 6246175 4.21% 77.96% # Number of instructions fetched each cycle (Total) 367system.cpu.fetch.rateDist::7 8016813 5.41% 83.36% # Number of instructions fetched each cycle (Total) 368system.cpu.fetch.rateDist::8 24658478 16.64% 100.00% # Number of instructions fetched each cycle (Total) | 362system.cpu.fetch.rateDist::0 66535735 44.98% 44.98% # Number of instructions fetched each cycle (Total) 363system.cpu.fetch.rateDist::1 5361707 3.63% 48.61% # Number of instructions fetched each cycle (Total) 364system.cpu.fetch.rateDist::2 10726789 7.25% 55.86% # Number of instructions fetched each cycle (Total) 365system.cpu.fetch.rateDist::3 10405351 7.04% 62.90% # Number of instructions fetched each cycle (Total) 366system.cpu.fetch.rateDist::4 8725871 5.90% 68.80% # Number of instructions fetched each cycle (Total) 367system.cpu.fetch.rateDist::5 6634741 4.49% 73.28% # Number of instructions fetched each cycle (Total) 368system.cpu.fetch.rateDist::6 6328592 4.28% 77.56% # Number of instructions fetched each cycle (Total) 369system.cpu.fetch.rateDist::7 8060301 5.45% 83.01% # Number of instructions fetched each cycle (Total) 370system.cpu.fetch.rateDist::8 25128291 16.99% 100.00% # Number of instructions fetched each cycle (Total) |
| 369system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 370system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 371system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 371system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 372system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 373system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 372system.cpu.fetch.rateDist::total 148222429 # Number of instructions fetched each cycle (Total) 373system.cpu.fetch.branchRate 0.638943 # Number of branch fetches per cycle 374system.cpu.fetch.rate 2.561913 # Number of inst fetches per cycle 375system.cpu.decode.IdleCycles 45507597 # Number of cycles decode is idle 376system.cpu.decode.BlockedCycles 5871716 # Number of cycles decode is blocked 377system.cpu.decode.RunCycles 74805608 # Number of cycles decode is running 378system.cpu.decode.UnblockCycles 1201041 # Number of cycles decode is unblocking 379system.cpu.decode.SquashCycles 20836467 # Number of cycles decode is squashing 380system.cpu.decode.BranchResolved 14340186 # Number of times decode resolved a branch 381system.cpu.decode.BranchMispred 164591 # Number of times decode detected a branch misprediction 382system.cpu.decode.DecodedInsts 392845308 # Number of instructions handled by decode 383system.cpu.decode.SquashedInsts 733522 # Number of squashed instructions handled by decode 384system.cpu.rename.SquashCycles 20836467 # Number of cycles rename is squashing 385system.cpu.rename.IdleCycles 50894479 # Number of cycles rename is idle 386system.cpu.rename.BlockCycles 722812 # Number of cycles rename is blocking 387system.cpu.rename.serializeStallCycles 602318 # count of cycles rename stalled for serializing inst 388system.cpu.rename.RunCycles 70557272 # Number of cycles rename is running 389system.cpu.rename.UnblockCycles 4609081 # Number of cycles rename is unblocking 390system.cpu.rename.RenamedInsts 371354915 # Number of instructions processed by rename 391system.cpu.rename.ROBFullEvents 44 # Number of times rename has blocked due to ROB full 392system.cpu.rename.IQFullEvents 338748 # Number of times rename has blocked due to IQ full 393system.cpu.rename.LSQFullEvents 3656059 # Number of times rename has blocked due to LSQ full 394system.cpu.rename.FullRegisterEvents 24 # Number of times there has been no free registers 395system.cpu.rename.RenamedOperands 631764461 # Number of destination operands rename has renamed 396system.cpu.rename.RenameLookups 1588652531 # Number of register rename lookups that rename has made 397system.cpu.rename.int_rename_lookups 1506975247 # Number of integer rename lookups 398system.cpu.rename.fp_rename_lookups 3198470 # Number of floating rename lookups | 374system.cpu.fetch.rateDist::total 147907378 # Number of instructions fetched each cycle (Total) 375system.cpu.fetch.branchRate 0.646048 # Number of branch fetches per cycle 376system.cpu.fetch.rate 2.603352 # Number of inst fetches per cycle 377system.cpu.decode.IdleCycles 45234948 # Number of cycles decode is idle 378system.cpu.decode.BlockedCycles 3964725 # Number of cycles decode is blocked 379system.cpu.decode.RunCycles 76674416 # Number of cycles decode is running 380system.cpu.decode.UnblockCycles 488435 # Number of cycles decode is unblocking 381system.cpu.decode.SquashCycles 21544854 # Number of cycles decode is squashing 382system.cpu.decode.BranchResolved 14463585 # Number of times decode resolved a branch 383system.cpu.decode.BranchMispred 165860 # Number of times decode detected a branch misprediction 384system.cpu.decode.DecodedInsts 398867240 # Number of instructions handled by decode 385system.cpu.decode.SquashedInsts 776962 # Number of squashed instructions handled by decode 386system.cpu.rename.SquashCycles 21544854 # Number of cycles rename is squashing 387system.cpu.rename.IdleCycles 49978288 # Number of cycles rename is idle 388system.cpu.rename.BlockCycles 80802 # Number of cycles rename is blocking 389system.cpu.rename.serializeStallCycles 634035 # count of cycles rename stalled for serializing inst 390system.cpu.rename.RunCycles 72417632 # Number of cycles rename is running 391system.cpu.rename.UnblockCycles 3251767 # Number of cycles rename is unblocking 392system.cpu.rename.RenamedInsts 377266574 # Number of instructions processed by rename 393system.cpu.rename.ROBFullEvents 64 # Number of times rename has blocked due to ROB full 394system.cpu.rename.IQFullEvents 883323 # Number of times rename has blocked due to IQ full 395system.cpu.rename.LQFullEvents 2242172 # Number of times rename has blocked due to LQ full 396system.cpu.rename.SQFullEvents 19804 # Number of times rename has blocked due to SQ full 397system.cpu.rename.FullRegisterEvents 7460 # Number of times there has been no free registers 398system.cpu.rename.RenamedOperands 639899653 # Number of destination operands rename has renamed 399system.cpu.rename.RenameLookups 1616068029 # Number of register rename lookups that rename has made 400system.cpu.rename.int_rename_lookups 1531504010 # Number of integer rename lookups 401system.cpu.rename.fp_rename_lookups 3330597 # Number of floating rename lookups |
| 399system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed | 402system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed |
| 400system.cpu.rename.UndoneMaps 333720322 # Number of HB maps that are undone due to squashing 401system.cpu.rename.serializingInsts 25119 # count of serializing insts renamed 402system.cpu.rename.tempSerializingInsts 25116 # count of temporary serializing insts renamed 403system.cpu.rename.skidInsts 13019783 # count of insts added to the skid buffer 404system.cpu.memDep0.insertedLoads 43012506 # Number of loads inserted to the mem dependence unit. 405system.cpu.memDep0.insertedStores 16421309 # Number of stores inserted to the mem dependence unit. 406system.cpu.memDep0.conflictingLoads 5620383 # Number of conflicting loads. 407system.cpu.memDep0.conflictingStores 3639856 # Number of conflicting stores. 408system.cpu.iq.iqInstsAdded 329245944 # Number of instructions added to the IQ (excludes non-spec) 409system.cpu.iq.iqNonSpecInstsAdded 47173 # Number of non-speculative instructions added to the IQ 410system.cpu.iq.iqInstsIssued 249482695 # Number of instructions issued 411system.cpu.iq.iqSquashedInstsIssued 793526 # Number of squashed instructions issued 412system.cpu.iq.iqSquashedInstsExamined 139565421 # Number of squashed instructions iterated over during squash; mainly for profiling 413system.cpu.iq.iqSquashedOperandsExamined 362544222 # Number of squashed operands that are examined and possibly removed from graph 414system.cpu.iq.iqSquashedNonSpecRemoved 1957 # Number of squashed non-spec instructions that were removed 415system.cpu.iq.issued_per_cycle::samples 148222429 # Number of insts issued each cycle 416system.cpu.iq.issued_per_cycle::mean 1.683164 # Number of insts issued each cycle 417system.cpu.iq.issued_per_cycle::stdev 1.761970 # Number of insts issued each cycle | 403system.cpu.rename.UndoneMaps 341855514 # Number of HB maps that are undone due to squashing 404system.cpu.rename.serializingInsts 25341 # count of serializing insts renamed 405system.cpu.rename.tempSerializingInsts 25337 # count of temporary serializing insts renamed 406system.cpu.rename.skidInsts 6011835 # count of insts added to the skid buffer 407system.cpu.memDep0.insertedLoads 44415560 # Number of loads inserted to the mem dependence unit. 408system.cpu.memDep0.insertedStores 16956234 # Number of stores inserted to the mem dependence unit. 409system.cpu.memDep0.conflictingLoads 6645157 # Number of conflicting loads. 410system.cpu.memDep0.conflictingStores 4213095 # Number of conflicting stores. 411system.cpu.iq.iqInstsAdded 334591306 # Number of instructions added to the IQ (excludes non-spec) 412system.cpu.iq.iqNonSpecInstsAdded 47320 # Number of non-speculative instructions added to the IQ 413system.cpu.iq.iqInstsIssued 251099486 # Number of instructions issued 414system.cpu.iq.iqSquashedInstsIssued 1072213 # Number of squashed instructions issued 415system.cpu.iq.iqSquashedInstsExamined 144899766 # Number of squashed instructions iterated over during squash; mainly for profiling 416system.cpu.iq.iqSquashedOperandsExamined 380484892 # Number of squashed operands that are examined and possibly removed from graph 417system.cpu.iq.iqSquashedNonSpecRemoved 2104 # Number of squashed non-spec instructions that were removed 418system.cpu.iq.issued_per_cycle::samples 147907378 # Number of insts issued each cycle 419system.cpu.iq.issued_per_cycle::mean 1.697681 # Number of insts issued each cycle 420system.cpu.iq.issued_per_cycle::stdev 1.790678 # Number of insts issued each cycle |
| 418system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 421system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 419system.cpu.iq.issued_per_cycle::0 56049781 37.81% 37.81% # Number of insts issued each cycle 420system.cpu.iq.issued_per_cycle::1 22646407 15.28% 53.09% # Number of insts issued each cycle 421system.cpu.iq.issued_per_cycle::2 24808421 16.74% 69.83% # Number of insts issued each cycle 422system.cpu.iq.issued_per_cycle::3 20317592 13.71% 83.54% # Number of insts issued each cycle 423system.cpu.iq.issued_per_cycle::4 12547069 8.47% 92.00% # Number of insts issued each cycle 424system.cpu.iq.issued_per_cycle::5 6521251 4.40% 96.40% # Number of insts issued each cycle 425system.cpu.iq.issued_per_cycle::6 4032352 2.72% 99.12% # Number of insts issued each cycle 426system.cpu.iq.issued_per_cycle::7 1118421 0.75% 99.88% # Number of insts issued each cycle 427system.cpu.iq.issued_per_cycle::8 181135 0.12% 100.00% # Number of insts issued each cycle | 422system.cpu.iq.issued_per_cycle::0 56583019 38.26% 38.26% # Number of insts issued each cycle 423system.cpu.iq.issued_per_cycle::1 21897324 14.80% 53.06% # Number of insts issued each cycle 424system.cpu.iq.issued_per_cycle::2 24121591 16.31% 69.37% # Number of insts issued each cycle 425system.cpu.iq.issued_per_cycle::3 20330444 13.75% 83.11% # Number of insts issued each cycle 426system.cpu.iq.issued_per_cycle::4 12466477 8.43% 91.54% # Number of insts issued each cycle 427system.cpu.iq.issued_per_cycle::5 6673732 4.51% 96.06% # Number of insts issued each cycle 428system.cpu.iq.issued_per_cycle::6 4321605 2.92% 98.98% # Number of insts issued each cycle 429system.cpu.iq.issued_per_cycle::7 1302038 0.88% 99.86% # Number of insts issued each cycle 430system.cpu.iq.issued_per_cycle::8 211148 0.14% 100.00% # Number of insts issued each cycle |
| 428system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 429system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 430system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 431system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 432system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 433system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 431system.cpu.iq.issued_per_cycle::total 148222429 # Number of insts issued each cycle | 434system.cpu.iq.issued_per_cycle::total 147907378 # Number of insts issued each cycle |
| 432system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 435system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 433system.cpu.iq.fu_full::IntAlu 964061 38.35% 38.35% # attempts to use FU when none available 434system.cpu.iq.fu_full::IntMult 5595 0.22% 38.57% # attempts to use FU when none available 435system.cpu.iq.fu_full::IntDiv 0 0.00% 38.57% # attempts to use FU when none available 436system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.57% # attempts to use FU when none available 437system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.57% # attempts to use FU when none available 438system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.57% # attempts to use FU when none available 439system.cpu.iq.fu_full::FloatMult 0 0.00% 38.57% # attempts to use FU when none available 440system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.57% # attempts to use FU when none available 441system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.57% # attempts to use FU when none available 442system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.57% # attempts to use FU when none available 443system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.57% # attempts to use FU when none available 444system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.57% # attempts to use FU when none available 445system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.57% # attempts to use FU when none available 446system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.57% # attempts to use FU when none available 447system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.57% # attempts to use FU when none available 448system.cpu.iq.fu_full::SimdMult 0 0.00% 38.57% # attempts to use FU when none available 449system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.57% # attempts to use FU when none available 450system.cpu.iq.fu_full::SimdShift 0 0.00% 38.57% # attempts to use FU when none available 451system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.57% # attempts to use FU when none available 452system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.57% # attempts to use FU when none available 453system.cpu.iq.fu_full::SimdFloatAdd 96 0.00% 38.57% # attempts to use FU when none available 454system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.57% # attempts to use FU when none available 455system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.57% # attempts to use FU when none available 456system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.57% # attempts to use FU when none available 457system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.57% # attempts to use FU when none available 458system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.58% # attempts to use FU when none available 459system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.58% # attempts to use FU when none available 460system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.58% # attempts to use FU when none available 461system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.58% # attempts to use FU when none available 462system.cpu.iq.fu_full::MemRead 1168003 46.46% 85.04% # attempts to use FU when none available 463system.cpu.iq.fu_full::MemWrite 376162 14.96% 100.00% # attempts to use FU when none available | 436system.cpu.iq.fu_full::IntAlu 1040958 39.39% 39.39% # attempts to use FU when none available 437system.cpu.iq.fu_full::IntMult 5589 0.21% 39.60% # attempts to use FU when none available 438system.cpu.iq.fu_full::IntDiv 0 0.00% 39.60% # attempts to use FU when none available 439system.cpu.iq.fu_full::FloatAdd 0 0.00% 39.60% # attempts to use FU when none available 440system.cpu.iq.fu_full::FloatCmp 0 0.00% 39.60% # attempts to use FU when none available 441system.cpu.iq.fu_full::FloatCvt 0 0.00% 39.60% # attempts to use FU when none available 442system.cpu.iq.fu_full::FloatMult 0 0.00% 39.60% # attempts to use FU when none available 443system.cpu.iq.fu_full::FloatDiv 0 0.00% 39.60% # attempts to use FU when none available 444system.cpu.iq.fu_full::FloatSqrt 0 0.00% 39.60% # attempts to use FU when none available 445system.cpu.iq.fu_full::SimdAdd 0 0.00% 39.60% # attempts to use FU when none available 446system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 39.60% # attempts to use FU when none available 447system.cpu.iq.fu_full::SimdAlu 0 0.00% 39.60% # attempts to use FU when none available 448system.cpu.iq.fu_full::SimdCmp 0 0.00% 39.60% # attempts to use FU when none available 449system.cpu.iq.fu_full::SimdCvt 0 0.00% 39.60% # attempts to use FU when none available 450system.cpu.iq.fu_full::SimdMisc 0 0.00% 39.60% # attempts to use FU when none available 451system.cpu.iq.fu_full::SimdMult 0 0.00% 39.60% # attempts to use FU when none available 452system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 39.60% # attempts to use FU when none available 453system.cpu.iq.fu_full::SimdShift 0 0.00% 39.60% # attempts to use FU when none available 454system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 39.60% # attempts to use FU when none available 455system.cpu.iq.fu_full::SimdSqrt 0 0.00% 39.60% # attempts to use FU when none available 456system.cpu.iq.fu_full::SimdFloatAdd 97 0.00% 39.61% # attempts to use FU when none available 457system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 39.61% # attempts to use FU when none available 458system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 39.61% # attempts to use FU when none available 459system.cpu.iq.fu_full::SimdFloatCvt 356 0.01% 39.62% # attempts to use FU when none available 460system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 39.62% # attempts to use FU when none available 461system.cpu.iq.fu_full::SimdFloatMisc 45 0.00% 39.62% # attempts to use FU when none available 462system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 39.62% # attempts to use FU when none available 463system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.62% # attempts to use FU when none available 464system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 39.62% # attempts to use FU when none available 465system.cpu.iq.fu_full::MemRead 1222208 46.25% 85.87% # attempts to use FU when none available 466system.cpu.iq.fu_full::MemWrite 373303 14.13% 100.00% # attempts to use FU when none available |
| 464system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 465system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 466system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 467system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 468system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 469system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 467system.cpu.iq.FU_type_0::IntAlu 194908316 78.12% 78.12% # Type of FU issued 468system.cpu.iq.FU_type_0::IntMult 978999 0.39% 78.52% # Type of FU issued 469system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued 470system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued 471system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued 472system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.52% # Type of FU issued 473system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.52% # Type of FU issued 474system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.52% # Type of FU issued 475system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.52% # Type of FU issued 476system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.52% # Type of FU issued 477system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.52% # Type of FU issued 478system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.52% # Type of FU issued 479system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.52% # Type of FU issued 480system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.52% # Type of FU issued 481system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.52% # Type of FU issued 482system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.52% # Type of FU issued 483system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Type of FU issued 484system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued 485system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued 486system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued 487system.cpu.iq.FU_type_0::SimdFloatAdd 33072 0.01% 78.53% # Type of FU issued 488system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.53% # Type of FU issued 489system.cpu.iq.FU_type_0::SimdFloatCmp 164299 0.07% 78.60% # Type of FU issued 490system.cpu.iq.FU_type_0::SimdFloatCvt 255151 0.10% 78.70% # Type of FU issued 491system.cpu.iq.FU_type_0::SimdFloatDiv 76428 0.03% 78.73% # Type of FU issued 492system.cpu.iq.FU_type_0::SimdFloatMisc 465968 0.19% 78.92% # Type of FU issued 493system.cpu.iq.FU_type_0::SimdFloatMult 206368 0.08% 79.00% # Type of FU issued 494system.cpu.iq.FU_type_0::SimdFloatMultAcc 71868 0.03% 79.03% # Type of FU issued 495system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued 496system.cpu.iq.FU_type_0::MemRead 38371220 15.38% 94.41% # Type of FU issued 497system.cpu.iq.FU_type_0::MemWrite 13950685 5.59% 100.00% # Type of FU issued | 470system.cpu.iq.FU_type_0::IntAlu 195834645 77.99% 77.99% # Type of FU issued 471system.cpu.iq.FU_type_0::IntMult 981127 0.39% 78.38% # Type of FU issued 472system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.38% # Type of FU issued 473system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.38% # Type of FU issued 474system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.38% # Type of FU issued 475system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.38% # Type of FU issued 476system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.38% # Type of FU issued 477system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.38% # Type of FU issued 478system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.38% # Type of FU issued 479system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.38% # Type of FU issued 480system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.38% # Type of FU issued 481system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.38% # Type of FU issued 482system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.38% # Type of FU issued 483system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.38% # Type of FU issued 484system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.38% # Type of FU issued 485system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.38% # Type of FU issued 486system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.38% # Type of FU issued 487system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.38% # Type of FU issued 488system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.38% # Type of FU issued 489system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.38% # Type of FU issued 490system.cpu.iq.FU_type_0::SimdFloatAdd 33203 0.01% 78.39% # Type of FU issued 491system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.39% # Type of FU issued 492system.cpu.iq.FU_type_0::SimdFloatCmp 164429 0.07% 78.46% # Type of FU issued 493system.cpu.iq.FU_type_0::SimdFloatCvt 259909 0.10% 78.56% # Type of FU issued 494system.cpu.iq.FU_type_0::SimdFloatDiv 76654 0.03% 78.59% # Type of FU issued 495system.cpu.iq.FU_type_0::SimdFloatMisc 470113 0.19% 78.78% # Type of FU issued 496system.cpu.iq.FU_type_0::SimdFloatMult 206582 0.08% 78.86% # Type of FU issued 497system.cpu.iq.FU_type_0::SimdFloatMultAcc 71910 0.03% 78.89% # Type of FU issued 498system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 78.89% # Type of FU issued 499system.cpu.iq.FU_type_0::MemRead 38922233 15.50% 94.39% # Type of FU issued 500system.cpu.iq.FU_type_0::MemWrite 14078361 5.61% 100.00% # Type of FU issued |
| 498system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 499system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 501system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 502system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 500system.cpu.iq.FU_type_0::total 249482695 # Type of FU issued 501system.cpu.iq.rate 1.680956 # Inst issue rate 502system.cpu.iq.fu_busy_cnt 2513965 # FU busy when requested 503system.cpu.iq.fu_busy_rate 0.010077 # FU busy rate (busy events/executed inst) 504system.cpu.iq.int_inst_queue_reads 646755779 # Number of integer instruction queue reads 505system.cpu.iq.int_inst_queue_writes 466684925 # Number of integer instruction queue writes 506system.cpu.iq.int_inst_queue_wakeup_accesses 237894917 # Number of integer instruction queue wakeup accesses 507system.cpu.iq.fp_inst_queue_reads 3739531 # Number of floating instruction queue reads 508system.cpu.iq.fp_inst_queue_writes 2191886 # Number of floating instruction queue writes 509system.cpu.iq.fp_inst_queue_wakeup_accesses 1842592 # Number of floating instruction queue wakeup accesses 510system.cpu.iq.int_alu_accesses 250120414 # Number of integer alu accesses 511system.cpu.iq.fp_alu_accesses 1876246 # Number of floating point alu accesses 512system.cpu.iew.lsq.thread0.forwLoads 2009109 # Number of loads that had data forwarded from stores | 503system.cpu.iq.FU_type_0::total 251099486 # Type of FU issued 504system.cpu.iq.rate 1.695316 # Inst issue rate 505system.cpu.iq.fu_busy_cnt 2642556 # FU busy when requested 506system.cpu.iq.fu_busy_rate 0.010524 # FU busy rate (busy events/executed inst) 507system.cpu.iq.int_inst_queue_reads 650051417 # Number of integer instruction queue reads 508system.cpu.iq.int_inst_queue_writes 477257433 # Number of integer instruction queue writes 509system.cpu.iq.int_inst_queue_wakeup_accesses 239511768 # Number of integer instruction queue wakeup accesses 510system.cpu.iq.fp_inst_queue_reads 3769702 # Number of floating instruction queue reads 511system.cpu.iq.fp_inst_queue_writes 2301296 # Number of floating instruction queue writes 512system.cpu.iq.fp_inst_queue_wakeup_accesses 1862518 # Number of floating instruction queue wakeup accesses 513system.cpu.iq.int_alu_accesses 251853224 # Number of integer alu accesses 514system.cpu.iq.fp_alu_accesses 1888818 # Number of floating point alu accesses 515system.cpu.iew.lsq.thread0.forwLoads 2264941 # Number of loads that had data forwarded from stores |
| 513system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 516system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 514system.cpu.iew.lsq.thread0.squashedLoads 13163022 # Number of loads squashed 515system.cpu.iew.lsq.thread0.ignoredResponses 11141 # Number of memory responses ignored because the instruction is squashed 516system.cpu.iew.lsq.thread0.memOrderViolation 18733 # Number of memory ordering violations 517system.cpu.iew.lsq.thread0.squashedStores 3776675 # Number of stores squashed | 517system.cpu.iew.lsq.thread0.squashedLoads 14566076 # Number of loads squashed 518system.cpu.iew.lsq.thread0.ignoredResponses 14946 # Number of memory responses ignored because the instruction is squashed 519system.cpu.iew.lsq.thread0.memOrderViolation 20827 # Number of memory ordering violations 520system.cpu.iew.lsq.thread0.squashedStores 4311600 # Number of stores squashed |
| 518system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 519system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 521system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 522system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 520system.cpu.iew.lsq.thread0.rescheduledLoads 14 # Number of loads that were rescheduled 521system.cpu.iew.lsq.thread0.cacheBlocked 100 # Number of times an access to memory failed due to the cache being blocked | 523system.cpu.iew.lsq.thread0.rescheduledLoads 16 # Number of loads that were rescheduled 524system.cpu.iew.lsq.thread0.cacheBlocked 115 # Number of times an access to memory failed due to the cache being blocked |
| 522system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 525system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 523system.cpu.iew.iewSquashCycles 20836467 # Number of cycles IEW is squashing 524system.cpu.iew.iewBlockCycles 18579 # Number of cycles IEW is blocking 525system.cpu.iew.iewUnblockCycles 909 # Number of cycles IEW is unblocking 526system.cpu.iew.iewDispatchedInsts 329310121 # Number of instructions dispatched to IQ 527system.cpu.iew.iewDispSquashedInsts 781513 # Number of squashed instructions skipped by dispatch 528system.cpu.iew.iewDispLoadInsts 43012506 # Number of dispatched load instructions 529system.cpu.iew.iewDispStoreInsts 16421309 # Number of dispatched store instructions 530system.cpu.iew.iewDispNonSpecInsts 24765 # Number of dispatched non-speculative instructions 531system.cpu.iew.iewIQFullEvents 190 # Number of times the IQ has become full, causing a stall 532system.cpu.iew.iewLSQFullEvents 272 # Number of times the LSQ has become full, causing a stall 533system.cpu.iew.memOrderViolationEvents 18733 # Number of memory order violations 534system.cpu.iew.predictedTakenIncorrect 3888765 # Number of branches that were predicted taken incorrectly 535system.cpu.iew.predictedNotTakenIncorrect 3761308 # Number of branches that were predicted not taken incorrectly 536system.cpu.iew.branchMispredicts 7650073 # Number of branch mispredicts detected at execute 537system.cpu.iew.iewExecutedInsts 242977304 # Number of executed instructions 538system.cpu.iew.iewExecLoadInsts 36862847 # Number of load instructions executed 539system.cpu.iew.iewExecSquashedInsts 6505391 # Number of squashed instructions skipped in execute | 526system.cpu.iew.iewSquashCycles 21544854 # Number of cycles IEW is squashing 527system.cpu.iew.iewBlockCycles 1947 # Number of cycles IEW is blocking 528system.cpu.iew.iewUnblockCycles 2849 # Number of cycles IEW is unblocking 529system.cpu.iew.iewDispatchedInsts 334655682 # Number of instructions dispatched to IQ 530system.cpu.iew.iewDispSquashedInsts 756589 # Number of squashed instructions skipped by dispatch 531system.cpu.iew.iewDispLoadInsts 44415560 # Number of dispatched load instructions 532system.cpu.iew.iewDispStoreInsts 16956234 # Number of dispatched store instructions 533system.cpu.iew.iewDispNonSpecInsts 24912 # Number of dispatched non-speculative instructions 534system.cpu.iew.iewIQFullEvents 319 # Number of times the IQ has become full, causing a stall 535system.cpu.iew.iewLSQFullEvents 2632 # Number of times the LSQ has become full, causing a stall 536system.cpu.iew.memOrderViolationEvents 20827 # Number of memory order violations 537system.cpu.iew.predictedTakenIncorrect 3907560 # Number of branches that were predicted taken incorrectly 538system.cpu.iew.predictedNotTakenIncorrect 3770350 # Number of branches that were predicted not taken incorrectly 539system.cpu.iew.branchMispredicts 7677910 # Number of branch mispredicts detected at execute 540system.cpu.iew.iewExecutedInsts 244706645 # Number of executed instructions 541system.cpu.iew.iewExecLoadInsts 37396904 # Number of load instructions executed 542system.cpu.iew.iewExecSquashedInsts 6392841 # Number of squashed instructions skipped in execute |
| 540system.cpu.iew.exec_swp 0 # number of swp insts executed | 543system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 541system.cpu.iew.exec_nop 17004 # number of nop insts executed 542system.cpu.iew.exec_refs 50511963 # number of memory reference insts executed 543system.cpu.iew.exec_branches 53432662 # Number of branches executed 544system.cpu.iew.exec_stores 13649116 # Number of stores executed 545system.cpu.iew.exec_rate 1.637124 # Inst execution rate 546system.cpu.iew.wb_sent 240796428 # cumulative count of insts sent to commit 547system.cpu.iew.wb_count 239737509 # cumulative count of insts written-back 548system.cpu.iew.wb_producers 148472463 # num instructions producing a value 549system.cpu.iew.wb_consumers 267293668 # num instructions consuming a value | 544system.cpu.iew.exec_nop 17056 # number of nop insts executed 545system.cpu.iew.exec_refs 51162912 # number of memory reference insts executed 546system.cpu.iew.exec_branches 53733408 # Number of branches executed 547system.cpu.iew.exec_stores 13766008 # Number of stores executed 548system.cpu.iew.exec_rate 1.652154 # Inst execution rate 549system.cpu.iew.wb_sent 242463171 # cumulative count of insts sent to commit 550system.cpu.iew.wb_count 241374286 # cumulative count of insts written-back 551system.cpu.iew.wb_producers 150213875 # num instructions producing a value 552system.cpu.iew.wb_consumers 271770811 # num instructions consuming a value |
| 550system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 553system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 551system.cpu.iew.wb_rate 1.615295 # insts written-back per cycle 552system.cpu.iew.wb_fanout 0.555466 # average fanout of values written-back | 554system.cpu.iew.wb_rate 1.629655 # insts written-back per cycle 555system.cpu.iew.wb_fanout 0.552723 # average fanout of values written-back |
| 553system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 556system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 554system.cpu.commit.commitSquashedInsts 140639228 # The number of squashed insts skipped by commit | 557system.cpu.commit.commitSquashedInsts 145985060 # The number of squashed insts skipped by commit |
| 555system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards | 558system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards |
| 556system.cpu.commit.branchMispredicts 6126680 # The number of times a branch was mispredicted 557system.cpu.commit.committed_per_cycle::samples 127385962 # Number of insts commited each cycle 558system.cpu.commit.committed_per_cycle::mean 1.481096 # Number of insts commited each cycle 559system.cpu.commit.committed_per_cycle::stdev 2.186061 # Number of insts commited each cycle | 559system.cpu.commit.branchMispredicts 6141058 # The number of times a branch was mispredicted 560system.cpu.commit.committed_per_cycle::samples 126362524 # Number of insts commited each cycle 561system.cpu.commit.committed_per_cycle::mean 1.493092 # Number of insts commited each cycle 562system.cpu.commit.committed_per_cycle::stdev 2.207919 # Number of insts commited each cycle |
| 560system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 563system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 561system.cpu.commit.committed_per_cycle::0 57702305 45.30% 45.30% # Number of insts commited each cycle 562system.cpu.commit.committed_per_cycle::1 31675528 24.87% 70.16% # Number of insts commited each cycle 563system.cpu.commit.committed_per_cycle::2 13782422 10.82% 80.98% # Number of insts commited each cycle 564system.cpu.commit.committed_per_cycle::3 7634808 5.99% 86.98% # Number of insts commited each cycle 565system.cpu.commit.committed_per_cycle::4 4379316 3.44% 90.41% # Number of insts commited each cycle 566system.cpu.commit.committed_per_cycle::5 1319569 1.04% 91.45% # Number of insts commited each cycle 567system.cpu.commit.committed_per_cycle::6 1705598 1.34% 92.79% # Number of insts commited each cycle 568system.cpu.commit.committed_per_cycle::7 1313930 1.03% 93.82% # Number of insts commited each cycle 569system.cpu.commit.committed_per_cycle::8 7872486 6.18% 100.00% # Number of insts commited each cycle | 564system.cpu.commit.committed_per_cycle::0 57333838 45.37% 45.37% # Number of insts commited each cycle 565system.cpu.commit.committed_per_cycle::1 31277146 24.75% 70.12% # Number of insts commited each cycle 566system.cpu.commit.committed_per_cycle::2 13531640 10.71% 80.83% # Number of insts commited each cycle 567system.cpu.commit.committed_per_cycle::3 7550408 5.98% 86.81% # Number of insts commited each cycle 568system.cpu.commit.committed_per_cycle::4 4276360 3.38% 90.19% # Number of insts commited each cycle 569system.cpu.commit.committed_per_cycle::5 1325331 1.05% 91.24% # Number of insts commited each cycle 570system.cpu.commit.committed_per_cycle::6 1692872 1.34% 92.58% # Number of insts commited each cycle 571system.cpu.commit.committed_per_cycle::7 1209518 0.96% 93.54% # Number of insts commited each cycle 572system.cpu.commit.committed_per_cycle::8 8165411 6.46% 100.00% # Number of insts commited each cycle |
| 570system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 571system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 572system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 573system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 574system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 575system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 573system.cpu.commit.committed_per_cycle::total 127385962 # Number of insts commited each cycle | 576system.cpu.commit.committed_per_cycle::total 126362524 # Number of insts commited each cycle |
| 574system.cpu.commit.committedInsts 172317409 # Number of instructions committed 575system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed 576system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 577system.cpu.commit.refs 42494118 # Number of memory references committed 578system.cpu.commit.loads 29849484 # Number of loads committed 579system.cpu.commit.membars 22408 # Number of memory barriers committed 580system.cpu.commit.branches 40300311 # Number of branches committed 581system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 611system.cpu.commit.op_class_0::SimdFloatMult 200806 0.11% 77.44% # Class of committed instruction 612system.cpu.commit.op_class_0::SimdFloatMultAcc 71617 0.04% 77.48% # Class of committed instruction 613system.cpu.commit.op_class_0::SimdFloatSqrt 318 0.00% 77.48% # Class of committed instruction 614system.cpu.commit.op_class_0::MemRead 29849484 15.82% 93.30% # Class of committed instruction 615system.cpu.commit.op_class_0::MemWrite 12644634 6.70% 100.00% # Class of committed instruction 616system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 617system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 618system.cpu.commit.op_class_0::total 188670891 # Class of committed instruction | 577system.cpu.commit.committedInsts 172317409 # Number of instructions committed 578system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed 579system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 580system.cpu.commit.refs 42494118 # Number of memory references committed 581system.cpu.commit.loads 29849484 # Number of loads committed 582system.cpu.commit.membars 22408 # Number of memory barriers committed 583system.cpu.commit.branches 40300311 # Number of branches committed 584system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 614system.cpu.commit.op_class_0::SimdFloatMult 200806 0.11% 77.44% # Class of committed instruction 615system.cpu.commit.op_class_0::SimdFloatMultAcc 71617 0.04% 77.48% # Class of committed instruction 616system.cpu.commit.op_class_0::SimdFloatSqrt 318 0.00% 77.48% # Class of committed instruction 617system.cpu.commit.op_class_0::MemRead 29849484 15.82% 93.30% # Class of committed instruction 618system.cpu.commit.op_class_0::MemWrite 12644634 6.70% 100.00% # Class of committed instruction 619system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 620system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 621system.cpu.commit.op_class_0::total 188670891 # Class of committed instruction |
| 619system.cpu.commit.bw_lim_events 7872486 # number cycles where commit BW limit reached | 622system.cpu.commit.bw_lim_events 8165411 # number cycles where commit BW limit reached |
| 620system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 623system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 621system.cpu.rob.rob_reads 448818394 # The number of ROB reads 622system.cpu.rob.rob_writes 679565858 # The number of ROB writes 623system.cpu.timesIdled 2789 # Number of times that the entire CPU went into an idle state and unscheduled itself 624system.cpu.idleCycles 194714 # Total number of cycles that the CPU has spent unscheduled due to idling | 624system.cpu.rob.rob_reads 452847863 # The number of ROB reads 625system.cpu.rob.rob_writes 690972129 # The number of ROB writes 626system.cpu.timesIdled 2844 # Number of times that the entire CPU went into an idle state and unscheduled itself 627system.cpu.idleCycles 206314 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 625system.cpu.committedInsts 172303021 # Number of Instructions Simulated 626system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated | 628system.cpu.committedInsts 172303021 # Number of Instructions Simulated 629system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated |
| 627system.cpu.cpi 0.861373 # CPI: Cycles Per Instruction 628system.cpu.cpi_total 0.861373 # CPI: Total CPI of All Threads 629system.cpu.ipc 1.160937 # IPC: Instructions Per Cycle 630system.cpu.ipc_total 1.160937 # IPC: Total IPC of All Threads 631system.cpu.int_regfile_reads 1079497274 # number of integer regfile reads 632system.cpu.int_regfile_writes 384888160 # number of integer regfile writes 633system.cpu.fp_regfile_reads 2912753 # number of floating regfile reads 634system.cpu.fp_regfile_writes 2499155 # number of floating regfile writes 635system.cpu.misc_regfile_reads 64874393 # number of misc regfile reads | 630system.cpu.cpi 0.859612 # CPI: Cycles Per Instruction 631system.cpu.cpi_total 0.859612 # CPI: Total CPI of All Threads 632system.cpu.ipc 1.163316 # IPC: Instructions Per Cycle 633system.cpu.ipc_total 1.163316 # IPC: Total IPC of All Threads 634system.cpu.int_regfile_reads 1087499674 # number of integer regfile reads 635system.cpu.int_regfile_writes 386673292 # number of integer regfile writes 636system.cpu.fp_regfile_reads 2922602 # number of floating regfile reads 637system.cpu.fp_regfile_writes 2532629 # number of floating regfile writes 638system.cpu.misc_regfile_reads 65625361 # number of misc regfile reads |
| 636system.cpu.misc_regfile_writes 820036 # number of misc regfile writes | 639system.cpu.misc_regfile_writes 820036 # number of misc regfile writes |
| 637system.cpu.toL2Bus.throughput 5170292 # Throughput (bytes/s) 638system.cpu.toL2Bus.trans_dist::ReadReq 4896 # Transaction distribution 639system.cpu.toL2Bus.trans_dist::ReadResp 4895 # Transaction distribution 640system.cpu.toL2Bus.trans_dist::Writeback 19 # Transaction distribution 641system.cpu.toL2Bus.trans_dist::ReadExReq 1081 # Transaction distribution 642system.cpu.toL2Bus.trans_dist::ReadExResp 1081 # Transaction distribution 643system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8239 # Packet count per connected master and slave (bytes) 644system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3733 # Packet count per connected master and slave (bytes) 645system.cpu.toL2Bus.pkt_count::total 11972 # Packet count per connected master and slave (bytes) 646system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 263616 # Cumulative packet size per connected master and slave (bytes) | 640system.cpu.toL2Bus.throughput 5184342 # Throughput (bytes/s) 641system.cpu.toL2Bus.trans_dist::ReadReq 4900 # Transaction distribution 642system.cpu.toL2Bus.trans_dist::ReadResp 4899 # Transaction distribution 643system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution 644system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution 645system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution 646system.cpu.toL2Bus.trans_dist::ReadExReq 1084 # Transaction distribution 647system.cpu.toL2Bus.trans_dist::ReadExResp 1084 # Transaction distribution 648system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8245 # Packet count per connected master and slave (bytes) 649system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3740 # Packet count per connected master and slave (bytes) 650system.cpu.toL2Bus.pkt_count::total 11985 # Packet count per connected master and slave (bytes) 651system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 263744 # Cumulative packet size per connected master and slave (bytes) |
| 647system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120064 # Cumulative packet size per connected master and slave (bytes) | 652system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120064 # Cumulative packet size per connected master and slave (bytes) |
| 648system.cpu.toL2Bus.tot_pkt_size::total 383680 # Cumulative packet size per connected master and slave (bytes) 649system.cpu.toL2Bus.data_through_bus 383680 # Total data (bytes) 650system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) | 653system.cpu.toL2Bus.tot_pkt_size::total 383808 # Cumulative packet size per connected master and slave (bytes) 654system.cpu.toL2Bus.data_through_bus 383808 # Total data (bytes) 655system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes) |
| 651system.cpu.toL2Bus.reqLayer0.occupancy 3017000 # Layer occupancy (ticks) 652system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 656system.cpu.toL2Bus.reqLayer0.occupancy 3017000 # Layer occupancy (ticks) 657system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 653system.cpu.toL2Bus.respLayer0.occupancy 6548996 # Layer occupancy (ticks) | 658system.cpu.toL2Bus.respLayer0.occupancy 6552747 # Layer occupancy (ticks) |
| 654system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 659system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 655system.cpu.toL2Bus.respLayer1.occupancy 3099487 # Layer occupancy (ticks) | 660system.cpu.toL2Bus.respLayer1.occupancy 3102991 # Layer occupancy (ticks) |
| 656system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 661system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 657system.cpu.icache.tags.replacements 2388 # number of replacements 658system.cpu.icache.tags.tagsinuse 1346.753946 # Cycle average of tags in use 659system.cpu.icache.tags.total_refs 36845676 # Total number of references to valid blocks. 660system.cpu.icache.tags.sampled_refs 4119 # Sample count of references to valid blocks. 661system.cpu.icache.tags.avg_refs 8945.296431 # Average number of references to valid blocks. | 662system.cpu.icache.tags.replacements 2387 # number of replacements 663system.cpu.icache.tags.tagsinuse 1349.069671 # Cycle average of tags in use 664system.cpu.icache.tags.total_refs 37387126 # Total number of references to valid blocks. 665system.cpu.icache.tags.sampled_refs 4121 # Sample count of references to valid blocks. 666system.cpu.icache.tags.avg_refs 9072.343121 # Average number of references to valid blocks. |
| 662system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 667system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 663system.cpu.icache.tags.occ_blocks::cpu.inst 1346.753946 # Average occupied blocks per requestor 664system.cpu.icache.tags.occ_percent::cpu.inst 0.657595 # Average percentage of cache occupancy 665system.cpu.icache.tags.occ_percent::total 0.657595 # Average percentage of cache occupancy 666system.cpu.icache.tags.occ_task_id_blocks::1024 1731 # Occupied blocks per task id | 668system.cpu.icache.tags.occ_blocks::cpu.inst 1349.069671 # Average occupied blocks per requestor 669system.cpu.icache.tags.occ_percent::cpu.inst 0.658725 # Average percentage of cache occupancy 670system.cpu.icache.tags.occ_percent::total 0.658725 # Average percentage of cache occupancy 671system.cpu.icache.tags.occ_task_id_blocks::1024 1734 # Occupied blocks per task id |
| 667system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id | 672system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id |
| 668system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id 669system.cpu.icache.tags.age_task_id_blocks_1024::2 541 # Occupied blocks per task id 670system.cpu.icache.tags.age_task_id_blocks_1024::3 30 # Occupied blocks per task id 671system.cpu.icache.tags.age_task_id_blocks_1024::4 1037 # Occupied blocks per task id 672system.cpu.icache.tags.occ_task_id_percent::1024 0.845215 # Percentage of cache occupancy per task id 673system.cpu.icache.tags.tag_accesses 73706251 # Number of tag accesses 674system.cpu.icache.tags.data_accesses 73706251 # Number of data accesses 675system.cpu.icache.ReadReq_hits::cpu.inst 36845676 # number of ReadReq hits 676system.cpu.icache.ReadReq_hits::total 36845676 # number of ReadReq hits 677system.cpu.icache.demand_hits::cpu.inst 36845676 # number of demand (read+write) hits 678system.cpu.icache.demand_hits::total 36845676 # number of demand (read+write) hits 679system.cpu.icache.overall_hits::cpu.inst 36845676 # number of overall hits 680system.cpu.icache.overall_hits::total 36845676 # number of overall hits 681system.cpu.icache.ReadReq_misses::cpu.inst 5390 # number of ReadReq misses 682system.cpu.icache.ReadReq_misses::total 5390 # number of ReadReq misses 683system.cpu.icache.demand_misses::cpu.inst 5390 # number of demand (read+write) misses 684system.cpu.icache.demand_misses::total 5390 # number of demand (read+write) misses 685system.cpu.icache.overall_misses::cpu.inst 5390 # number of overall misses 686system.cpu.icache.overall_misses::total 5390 # number of overall misses 687system.cpu.icache.ReadReq_miss_latency::cpu.inst 228751995 # number of ReadReq miss cycles 688system.cpu.icache.ReadReq_miss_latency::total 228751995 # number of ReadReq miss cycles 689system.cpu.icache.demand_miss_latency::cpu.inst 228751995 # number of demand (read+write) miss cycles 690system.cpu.icache.demand_miss_latency::total 228751995 # number of demand (read+write) miss cycles 691system.cpu.icache.overall_miss_latency::cpu.inst 228751995 # number of overall miss cycles 692system.cpu.icache.overall_miss_latency::total 228751995 # number of overall miss cycles 693system.cpu.icache.ReadReq_accesses::cpu.inst 36851066 # number of ReadReq accesses(hits+misses) 694system.cpu.icache.ReadReq_accesses::total 36851066 # number of ReadReq accesses(hits+misses) 695system.cpu.icache.demand_accesses::cpu.inst 36851066 # number of demand (read+write) accesses 696system.cpu.icache.demand_accesses::total 36851066 # number of demand (read+write) accesses 697system.cpu.icache.overall_accesses::cpu.inst 36851066 # number of overall (read+write) accesses 698system.cpu.icache.overall_accesses::total 36851066 # number of overall (read+write) accesses 699system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000146 # miss rate for ReadReq accesses 700system.cpu.icache.ReadReq_miss_rate::total 0.000146 # miss rate for ReadReq accesses 701system.cpu.icache.demand_miss_rate::cpu.inst 0.000146 # miss rate for demand accesses 702system.cpu.icache.demand_miss_rate::total 0.000146 # miss rate for demand accesses 703system.cpu.icache.overall_miss_rate::cpu.inst 0.000146 # miss rate for overall accesses 704system.cpu.icache.overall_miss_rate::total 0.000146 # miss rate for overall accesses 705system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42440.073284 # average ReadReq miss latency 706system.cpu.icache.ReadReq_avg_miss_latency::total 42440.073284 # average ReadReq miss latency 707system.cpu.icache.demand_avg_miss_latency::cpu.inst 42440.073284 # average overall miss latency 708system.cpu.icache.demand_avg_miss_latency::total 42440.073284 # average overall miss latency 709system.cpu.icache.overall_avg_miss_latency::cpu.inst 42440.073284 # average overall miss latency 710system.cpu.icache.overall_avg_miss_latency::total 42440.073284 # average overall miss latency 711system.cpu.icache.blocked_cycles::no_mshrs 1596 # number of cycles access was blocked | 673system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id 674system.cpu.icache.tags.age_task_id_blocks_1024::2 547 # Occupied blocks per task id 675system.cpu.icache.tags.age_task_id_blocks_1024::3 28 # Occupied blocks per task id 676system.cpu.icache.tags.age_task_id_blocks_1024::4 1033 # Occupied blocks per task id 677system.cpu.icache.tags.occ_task_id_percent::1024 0.846680 # Percentage of cache occupancy per task id 678system.cpu.icache.tags.tag_accesses 74789015 # Number of tag accesses 679system.cpu.icache.tags.data_accesses 74789015 # Number of data accesses 680system.cpu.icache.ReadReq_hits::cpu.inst 37387126 # number of ReadReq hits 681system.cpu.icache.ReadReq_hits::total 37387126 # number of ReadReq hits 682system.cpu.icache.demand_hits::cpu.inst 37387126 # number of demand (read+write) hits 683system.cpu.icache.demand_hits::total 37387126 # number of demand (read+write) hits 684system.cpu.icache.overall_hits::cpu.inst 37387126 # number of overall hits 685system.cpu.icache.overall_hits::total 37387126 # number of overall hits 686system.cpu.icache.ReadReq_misses::cpu.inst 5320 # number of ReadReq misses 687system.cpu.icache.ReadReq_misses::total 5320 # number of ReadReq misses 688system.cpu.icache.demand_misses::cpu.inst 5320 # number of demand (read+write) misses 689system.cpu.icache.demand_misses::total 5320 # number of demand (read+write) misses 690system.cpu.icache.overall_misses::cpu.inst 5320 # number of overall misses 691system.cpu.icache.overall_misses::total 5320 # number of overall misses 692system.cpu.icache.ReadReq_miss_latency::cpu.inst 224799997 # number of ReadReq miss cycles 693system.cpu.icache.ReadReq_miss_latency::total 224799997 # number of ReadReq miss cycles 694system.cpu.icache.demand_miss_latency::cpu.inst 224799997 # number of demand (read+write) miss cycles 695system.cpu.icache.demand_miss_latency::total 224799997 # number of demand (read+write) miss cycles 696system.cpu.icache.overall_miss_latency::cpu.inst 224799997 # number of overall miss cycles 697system.cpu.icache.overall_miss_latency::total 224799997 # number of overall miss cycles 698system.cpu.icache.ReadReq_accesses::cpu.inst 37392446 # number of ReadReq accesses(hits+misses) 699system.cpu.icache.ReadReq_accesses::total 37392446 # number of ReadReq accesses(hits+misses) 700system.cpu.icache.demand_accesses::cpu.inst 37392446 # number of demand (read+write) accesses 701system.cpu.icache.demand_accesses::total 37392446 # number of demand (read+write) accesses 702system.cpu.icache.overall_accesses::cpu.inst 37392446 # number of overall (read+write) accesses 703system.cpu.icache.overall_accesses::total 37392446 # number of overall (read+write) accesses 704system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000142 # miss rate for ReadReq accesses 705system.cpu.icache.ReadReq_miss_rate::total 0.000142 # miss rate for ReadReq accesses 706system.cpu.icache.demand_miss_rate::cpu.inst 0.000142 # miss rate for demand accesses 707system.cpu.icache.demand_miss_rate::total 0.000142 # miss rate for demand accesses 708system.cpu.icache.overall_miss_rate::cpu.inst 0.000142 # miss rate for overall accesses 709system.cpu.icache.overall_miss_rate::total 0.000142 # miss rate for overall accesses 710system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42255.638534 # average ReadReq miss latency 711system.cpu.icache.ReadReq_avg_miss_latency::total 42255.638534 # average ReadReq miss latency 712system.cpu.icache.demand_avg_miss_latency::cpu.inst 42255.638534 # average overall miss latency 713system.cpu.icache.demand_avg_miss_latency::total 42255.638534 # average overall miss latency 714system.cpu.icache.overall_avg_miss_latency::cpu.inst 42255.638534 # average overall miss latency 715system.cpu.icache.overall_avg_miss_latency::total 42255.638534 # average overall miss latency 716system.cpu.icache.blocked_cycles::no_mshrs 1071 # number of cycles access was blocked |
| 712system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 717system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 713system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked | 718system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked |
| 714system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 719system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 715system.cpu.icache.avg_blocked_cycles::no_mshrs 84 # average number of cycles each access was blocked | 720system.cpu.icache.avg_blocked_cycles::no_mshrs 59.500000 # average number of cycles each access was blocked |
| 716system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 717system.cpu.icache.fast_writes 0 # number of fast writes performed 718system.cpu.icache.cache_copies 0 # number of cache copies performed | 721system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 722system.cpu.icache.fast_writes 0 # number of fast writes performed 723system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 719system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1270 # number of ReadReq MSHR hits 720system.cpu.icache.ReadReq_mshr_hits::total 1270 # number of ReadReq MSHR hits 721system.cpu.icache.demand_mshr_hits::cpu.inst 1270 # number of demand (read+write) MSHR hits 722system.cpu.icache.demand_mshr_hits::total 1270 # number of demand (read+write) MSHR hits 723system.cpu.icache.overall_mshr_hits::cpu.inst 1270 # number of overall MSHR hits 724system.cpu.icache.overall_mshr_hits::total 1270 # number of overall MSHR hits 725system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4120 # number of ReadReq MSHR misses 726system.cpu.icache.ReadReq_mshr_misses::total 4120 # number of ReadReq MSHR misses 727system.cpu.icache.demand_mshr_misses::cpu.inst 4120 # number of demand (read+write) MSHR misses 728system.cpu.icache.demand_mshr_misses::total 4120 # number of demand (read+write) MSHR misses 729system.cpu.icache.overall_mshr_misses::cpu.inst 4120 # number of overall MSHR misses 730system.cpu.icache.overall_mshr_misses::total 4120 # number of overall MSHR misses 731system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 167326504 # number of ReadReq MSHR miss cycles 732system.cpu.icache.ReadReq_mshr_miss_latency::total 167326504 # number of ReadReq MSHR miss cycles 733system.cpu.icache.demand_mshr_miss_latency::cpu.inst 167326504 # number of demand (read+write) MSHR miss cycles 734system.cpu.icache.demand_mshr_miss_latency::total 167326504 # number of demand (read+write) MSHR miss cycles 735system.cpu.icache.overall_mshr_miss_latency::cpu.inst 167326504 # number of overall MSHR miss cycles 736system.cpu.icache.overall_mshr_miss_latency::total 167326504 # number of overall MSHR miss cycles 737system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses 738system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses 739system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses 740system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses 741system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for overall accesses 742system.cpu.icache.overall_mshr_miss_rate::total 0.000112 # mshr miss rate for overall accesses 743system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40613.229126 # average ReadReq mshr miss latency 744system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40613.229126 # average ReadReq mshr miss latency 745system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40613.229126 # average overall mshr miss latency 746system.cpu.icache.demand_avg_mshr_miss_latency::total 40613.229126 # average overall mshr miss latency 747system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40613.229126 # average overall mshr miss latency 748system.cpu.icache.overall_avg_mshr_miss_latency::total 40613.229126 # average overall mshr miss latency | 724system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1196 # number of ReadReq MSHR hits 725system.cpu.icache.ReadReq_mshr_hits::total 1196 # number of ReadReq MSHR hits 726system.cpu.icache.demand_mshr_hits::cpu.inst 1196 # number of demand (read+write) MSHR hits 727system.cpu.icache.demand_mshr_hits::total 1196 # number of demand (read+write) MSHR hits 728system.cpu.icache.overall_mshr_hits::cpu.inst 1196 # number of overall MSHR hits 729system.cpu.icache.overall_mshr_hits::total 1196 # number of overall MSHR hits 730system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4124 # number of ReadReq MSHR misses 731system.cpu.icache.ReadReq_mshr_misses::total 4124 # number of ReadReq MSHR misses 732system.cpu.icache.demand_mshr_misses::cpu.inst 4124 # number of demand (read+write) MSHR misses 733system.cpu.icache.demand_mshr_misses::total 4124 # number of demand (read+write) MSHR misses 734system.cpu.icache.overall_mshr_misses::cpu.inst 4124 # number of overall MSHR misses 735system.cpu.icache.overall_mshr_misses::total 4124 # number of overall MSHR misses 736system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168596253 # number of ReadReq MSHR miss cycles 737system.cpu.icache.ReadReq_mshr_miss_latency::total 168596253 # number of ReadReq MSHR miss cycles 738system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168596253 # number of demand (read+write) MSHR miss cycles 739system.cpu.icache.demand_mshr_miss_latency::total 168596253 # number of demand (read+write) MSHR miss cycles 740system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168596253 # number of overall MSHR miss cycles 741system.cpu.icache.overall_mshr_miss_latency::total 168596253 # number of overall MSHR miss cycles 742system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000110 # mshr miss rate for ReadReq accesses 743system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000110 # mshr miss rate for ReadReq accesses 744system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000110 # mshr miss rate for demand accesses 745system.cpu.icache.demand_mshr_miss_rate::total 0.000110 # mshr miss rate for demand accesses 746system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000110 # mshr miss rate for overall accesses 747system.cpu.icache.overall_mshr_miss_rate::total 0.000110 # mshr miss rate for overall accesses 748system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40881.729631 # average ReadReq mshr miss latency 749system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40881.729631 # average ReadReq mshr miss latency 750system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40881.729631 # average overall mshr miss latency 751system.cpu.icache.demand_avg_mshr_miss_latency::total 40881.729631 # average overall mshr miss latency 752system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40881.729631 # average overall mshr miss latency 753system.cpu.icache.overall_avg_mshr_miss_latency::total 40881.729631 # average overall mshr miss latency |
| 749system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 750system.cpu.l2cache.tags.replacements 0 # number of replacements | 754system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 755system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 751system.cpu.l2cache.tags.tagsinuse 1966.490721 # Cycle average of tags in use 752system.cpu.l2cache.tags.total_refs 2149 # Total number of references to valid blocks. 753system.cpu.l2cache.tags.sampled_refs 2739 # Sample count of references to valid blocks. 754system.cpu.l2cache.tags.avg_refs 0.784593 # Average number of references to valid blocks. | 756system.cpu.l2cache.tags.tagsinuse 1967.769315 # Cycle average of tags in use 757system.cpu.l2cache.tags.total_refs 2148 # Total number of references to valid blocks. 758system.cpu.l2cache.tags.sampled_refs 2745 # Sample count of references to valid blocks. 759system.cpu.l2cache.tags.avg_refs 0.782514 # Average number of references to valid blocks. |
| 755system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 760system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 756system.cpu.l2cache.tags.occ_blocks::writebacks 4.023907 # Average occupied blocks per requestor 757system.cpu.l2cache.tags.occ_blocks::cpu.inst 1424.627361 # Average occupied blocks per requestor 758system.cpu.l2cache.tags.occ_blocks::cpu.data 537.839452 # Average occupied blocks per requestor | 761system.cpu.l2cache.tags.occ_blocks::writebacks 4.017679 # Average occupied blocks per requestor 762system.cpu.l2cache.tags.occ_blocks::cpu.inst 1427.875766 # Average occupied blocks per requestor 763system.cpu.l2cache.tags.occ_blocks::cpu.data 535.875870 # Average occupied blocks per requestor |
| 759system.cpu.l2cache.tags.occ_percent::writebacks 0.000123 # Average percentage of cache occupancy | 764system.cpu.l2cache.tags.occ_percent::writebacks 0.000123 # Average percentage of cache occupancy |
| 760system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043476 # Average percentage of cache occupancy 761system.cpu.l2cache.tags.occ_percent::cpu.data 0.016414 # Average percentage of cache occupancy 762system.cpu.l2cache.tags.occ_percent::total 0.060013 # Average percentage of cache occupancy 763system.cpu.l2cache.tags.occ_task_id_blocks::1024 2739 # Occupied blocks per task id 764system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 765system.cpu.l2cache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id 766system.cpu.l2cache.tags.age_task_id_blocks_1024::2 607 # Occupied blocks per task id 767system.cpu.l2cache.tags.age_task_id_blocks_1024::3 29 # Occupied blocks per task id 768system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1969 # Occupied blocks per task id 769system.cpu.l2cache.tags.occ_task_id_percent::1024 0.083588 # Percentage of cache occupancy per task id 770system.cpu.l2cache.tags.tag_accesses 51788 # Number of tag accesses 771system.cpu.l2cache.tags.data_accesses 51788 # Number of data accesses 772system.cpu.l2cache.ReadReq_hits::cpu.inst 2061 # number of ReadReq hits 773system.cpu.l2cache.ReadReq_hits::cpu.data 87 # number of ReadReq hits 774system.cpu.l2cache.ReadReq_hits::total 2148 # number of ReadReq hits 775system.cpu.l2cache.Writeback_hits::writebacks 19 # number of Writeback hits 776system.cpu.l2cache.Writeback_hits::total 19 # number of Writeback hits 777system.cpu.l2cache.ReadExReq_hits::cpu.data 10 # number of ReadExReq hits 778system.cpu.l2cache.ReadExReq_hits::total 10 # number of ReadExReq hits 779system.cpu.l2cache.demand_hits::cpu.inst 2061 # number of demand (read+write) hits 780system.cpu.l2cache.demand_hits::cpu.data 97 # number of demand (read+write) hits 781system.cpu.l2cache.demand_hits::total 2158 # number of demand (read+write) hits 782system.cpu.l2cache.overall_hits::cpu.inst 2061 # number of overall hits 783system.cpu.l2cache.overall_hits::cpu.data 97 # number of overall hits 784system.cpu.l2cache.overall_hits::total 2158 # number of overall hits 785system.cpu.l2cache.ReadReq_misses::cpu.inst 2059 # number of ReadReq misses 786system.cpu.l2cache.ReadReq_misses::cpu.data 689 # number of ReadReq misses 787system.cpu.l2cache.ReadReq_misses::total 2748 # number of ReadReq misses 788system.cpu.l2cache.ReadExReq_misses::cpu.data 1071 # number of ReadExReq misses 789system.cpu.l2cache.ReadExReq_misses::total 1071 # number of ReadExReq misses 790system.cpu.l2cache.demand_misses::cpu.inst 2059 # number of demand (read+write) misses 791system.cpu.l2cache.demand_misses::cpu.data 1760 # number of demand (read+write) misses 792system.cpu.l2cache.demand_misses::total 3819 # number of demand (read+write) misses 793system.cpu.l2cache.overall_misses::cpu.inst 2059 # number of overall misses 794system.cpu.l2cache.overall_misses::cpu.data 1760 # number of overall misses 795system.cpu.l2cache.overall_misses::total 3819 # number of overall misses 796system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 142590000 # number of ReadReq miss cycles 797system.cpu.l2cache.ReadReq_miss_latency::cpu.data 50403250 # number of ReadReq miss cycles 798system.cpu.l2cache.ReadReq_miss_latency::total 192993250 # number of ReadReq miss cycles 799system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 74281750 # number of ReadExReq miss cycles 800system.cpu.l2cache.ReadExReq_miss_latency::total 74281750 # number of ReadExReq miss cycles 801system.cpu.l2cache.demand_miss_latency::cpu.inst 142590000 # number of demand (read+write) miss cycles 802system.cpu.l2cache.demand_miss_latency::cpu.data 124685000 # number of demand (read+write) miss cycles 803system.cpu.l2cache.demand_miss_latency::total 267275000 # number of demand (read+write) miss cycles 804system.cpu.l2cache.overall_miss_latency::cpu.inst 142590000 # number of overall miss cycles 805system.cpu.l2cache.overall_miss_latency::cpu.data 124685000 # number of overall miss cycles 806system.cpu.l2cache.overall_miss_latency::total 267275000 # number of overall miss cycles 807system.cpu.l2cache.ReadReq_accesses::cpu.inst 4120 # number of ReadReq accesses(hits+misses) | 765system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043575 # Average percentage of cache occupancy 766system.cpu.l2cache.tags.occ_percent::cpu.data 0.016354 # Average percentage of cache occupancy 767system.cpu.l2cache.tags.occ_percent::total 0.060052 # Average percentage of cache occupancy 768system.cpu.l2cache.tags.occ_task_id_blocks::1024 2745 # Occupied blocks per task id 769system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 770system.cpu.l2cache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id 771system.cpu.l2cache.tags.age_task_id_blocks_1024::2 608 # Occupied blocks per task id 772system.cpu.l2cache.tags.age_task_id_blocks_1024::3 28 # Occupied blocks per task id 773system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1972 # Occupied blocks per task id 774system.cpu.l2cache.tags.occ_task_id_percent::1024 0.083771 # Percentage of cache occupancy per task id 775system.cpu.l2cache.tags.tag_accesses 51829 # Number of tag accesses 776system.cpu.l2cache.tags.data_accesses 51829 # Number of data accesses 777system.cpu.l2cache.ReadReq_hits::cpu.inst 2058 # number of ReadReq hits 778system.cpu.l2cache.ReadReq_hits::cpu.data 89 # number of ReadReq hits 779system.cpu.l2cache.ReadReq_hits::total 2147 # number of ReadReq hits 780system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits 781system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits 782system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # number of ReadExReq hits 783system.cpu.l2cache.ReadExReq_hits::total 7 # number of ReadExReq hits 784system.cpu.l2cache.demand_hits::cpu.inst 2058 # number of demand (read+write) hits 785system.cpu.l2cache.demand_hits::cpu.data 96 # number of demand (read+write) hits 786system.cpu.l2cache.demand_hits::total 2154 # number of demand (read+write) hits 787system.cpu.l2cache.overall_hits::cpu.inst 2058 # number of overall hits 788system.cpu.l2cache.overall_hits::cpu.data 96 # number of overall hits 789system.cpu.l2cache.overall_hits::total 2154 # number of overall hits 790system.cpu.l2cache.ReadReq_misses::cpu.inst 2064 # number of ReadReq misses 791system.cpu.l2cache.ReadReq_misses::cpu.data 687 # number of ReadReq misses 792system.cpu.l2cache.ReadReq_misses::total 2751 # number of ReadReq misses 793system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses 794system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses 795system.cpu.l2cache.ReadExReq_misses::cpu.data 1077 # number of ReadExReq misses 796system.cpu.l2cache.ReadExReq_misses::total 1077 # number of ReadExReq misses 797system.cpu.l2cache.demand_misses::cpu.inst 2064 # number of demand (read+write) misses 798system.cpu.l2cache.demand_misses::cpu.data 1764 # number of demand (read+write) misses 799system.cpu.l2cache.demand_misses::total 3828 # number of demand (read+write) misses 800system.cpu.l2cache.overall_misses::cpu.inst 2064 # number of overall misses 801system.cpu.l2cache.overall_misses::cpu.data 1764 # number of overall misses 802system.cpu.l2cache.overall_misses::total 3828 # number of overall misses 803system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143880250 # number of ReadReq miss cycles 804system.cpu.l2cache.ReadReq_miss_latency::cpu.data 49531000 # number of ReadReq miss cycles 805system.cpu.l2cache.ReadReq_miss_latency::total 193411250 # number of ReadReq miss cycles 806system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 74080000 # number of ReadExReq miss cycles 807system.cpu.l2cache.ReadExReq_miss_latency::total 74080000 # number of ReadExReq miss cycles 808system.cpu.l2cache.demand_miss_latency::cpu.inst 143880250 # number of demand (read+write) miss cycles 809system.cpu.l2cache.demand_miss_latency::cpu.data 123611000 # number of demand (read+write) miss cycles 810system.cpu.l2cache.demand_miss_latency::total 267491250 # number of demand (read+write) miss cycles 811system.cpu.l2cache.overall_miss_latency::cpu.inst 143880250 # number of overall miss cycles 812system.cpu.l2cache.overall_miss_latency::cpu.data 123611000 # number of overall miss cycles 813system.cpu.l2cache.overall_miss_latency::total 267491250 # number of overall miss cycles 814system.cpu.l2cache.ReadReq_accesses::cpu.inst 4122 # number of ReadReq accesses(hits+misses) |
| 808system.cpu.l2cache.ReadReq_accesses::cpu.data 776 # number of ReadReq accesses(hits+misses) | 815system.cpu.l2cache.ReadReq_accesses::cpu.data 776 # number of ReadReq accesses(hits+misses) |
| 809system.cpu.l2cache.ReadReq_accesses::total 4896 # number of ReadReq accesses(hits+misses) 810system.cpu.l2cache.Writeback_accesses::writebacks 19 # number of Writeback accesses(hits+misses) 811system.cpu.l2cache.Writeback_accesses::total 19 # number of Writeback accesses(hits+misses) 812system.cpu.l2cache.ReadExReq_accesses::cpu.data 1081 # number of ReadExReq accesses(hits+misses) 813system.cpu.l2cache.ReadExReq_accesses::total 1081 # number of ReadExReq accesses(hits+misses) 814system.cpu.l2cache.demand_accesses::cpu.inst 4120 # number of demand (read+write) accesses 815system.cpu.l2cache.demand_accesses::cpu.data 1857 # number of demand (read+write) accesses 816system.cpu.l2cache.demand_accesses::total 5977 # number of demand (read+write) accesses 817system.cpu.l2cache.overall_accesses::cpu.inst 4120 # number of overall (read+write) accesses 818system.cpu.l2cache.overall_accesses::cpu.data 1857 # number of overall (read+write) accesses 819system.cpu.l2cache.overall_accesses::total 5977 # number of overall (read+write) accesses 820system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.499757 # miss rate for ReadReq accesses 821system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.887887 # miss rate for ReadReq accesses 822system.cpu.l2cache.ReadReq_miss_rate::total 0.561275 # miss rate for ReadReq accesses 823system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.990749 # miss rate for ReadExReq accesses 824system.cpu.l2cache.ReadExReq_miss_rate::total 0.990749 # miss rate for ReadExReq accesses 825system.cpu.l2cache.demand_miss_rate::cpu.inst 0.499757 # miss rate for demand accesses 826system.cpu.l2cache.demand_miss_rate::cpu.data 0.947765 # miss rate for demand accesses 827system.cpu.l2cache.demand_miss_rate::total 0.638949 # miss rate for demand accesses 828system.cpu.l2cache.overall_miss_rate::cpu.inst 0.499757 # miss rate for overall accesses 829system.cpu.l2cache.overall_miss_rate::cpu.data 0.947765 # miss rate for overall accesses 830system.cpu.l2cache.overall_miss_rate::total 0.638949 # miss rate for overall accesses 831system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69252.064109 # average ReadReq miss latency 832system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73154.208999 # average ReadReq miss latency 833system.cpu.l2cache.ReadReq_avg_miss_latency::total 70230.440320 # average ReadReq miss latency 834system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69357.376284 # average ReadExReq miss latency 835system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69357.376284 # average ReadExReq miss latency 836system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69252.064109 # average overall miss latency 837system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70843.750000 # average overall miss latency 838system.cpu.l2cache.demand_avg_miss_latency::total 69985.598324 # average overall miss latency 839system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69252.064109 # average overall miss latency 840system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70843.750000 # average overall miss latency 841system.cpu.l2cache.overall_avg_miss_latency::total 69985.598324 # average overall miss latency | 816system.cpu.l2cache.ReadReq_accesses::total 4898 # number of ReadReq accesses(hits+misses) 817system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) 818system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) 819system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) 820system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) 821system.cpu.l2cache.ReadExReq_accesses::cpu.data 1084 # number of ReadExReq accesses(hits+misses) 822system.cpu.l2cache.ReadExReq_accesses::total 1084 # number of ReadExReq accesses(hits+misses) 823system.cpu.l2cache.demand_accesses::cpu.inst 4122 # number of demand (read+write) accesses 824system.cpu.l2cache.demand_accesses::cpu.data 1860 # number of demand (read+write) accesses 825system.cpu.l2cache.demand_accesses::total 5982 # number of demand (read+write) accesses 826system.cpu.l2cache.overall_accesses::cpu.inst 4122 # number of overall (read+write) accesses 827system.cpu.l2cache.overall_accesses::cpu.data 1860 # number of overall (read+write) accesses 828system.cpu.l2cache.overall_accesses::total 5982 # number of overall (read+write) accesses 829system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.500728 # miss rate for ReadReq accesses 830system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.885309 # miss rate for ReadReq accesses 831system.cpu.l2cache.ReadReq_miss_rate::total 0.561658 # miss rate for ReadReq accesses 832system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 833system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 834system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993542 # miss rate for ReadExReq accesses 835system.cpu.l2cache.ReadExReq_miss_rate::total 0.993542 # miss rate for ReadExReq accesses 836system.cpu.l2cache.demand_miss_rate::cpu.inst 0.500728 # miss rate for demand accesses 837system.cpu.l2cache.demand_miss_rate::cpu.data 0.948387 # miss rate for demand accesses 838system.cpu.l2cache.demand_miss_rate::total 0.639920 # miss rate for demand accesses 839system.cpu.l2cache.overall_miss_rate::cpu.inst 0.500728 # miss rate for overall accesses 840system.cpu.l2cache.overall_miss_rate::cpu.data 0.948387 # miss rate for overall accesses 841system.cpu.l2cache.overall_miss_rate::total 0.639920 # miss rate for overall accesses 842system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69709.423450 # average ReadReq miss latency 843system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72097.525473 # average ReadReq miss latency 844system.cpu.l2cache.ReadReq_avg_miss_latency::total 70305.797892 # average ReadReq miss latency 845system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68783.658310 # average ReadExReq miss latency 846system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68783.658310 # average ReadExReq miss latency 847system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69709.423450 # average overall miss latency 848system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70074.263039 # average overall miss latency 849system.cpu.l2cache.demand_avg_miss_latency::total 69877.547022 # average overall miss latency 850system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69709.423450 # average overall miss latency 851system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70074.263039 # average overall miss latency 852system.cpu.l2cache.overall_avg_miss_latency::total 69877.547022 # average overall miss latency |
| 842system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 843system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 844system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 845system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 846system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 847system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 848system.cpu.l2cache.fast_writes 0 # number of fast writes performed 849system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 853system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 854system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 855system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 856system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 857system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 858system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 859system.cpu.l2cache.fast_writes 0 # number of fast writes performed 860system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 850system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits 851system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 13 # number of ReadReq MSHR hits 852system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits 853system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits 854system.cpu.l2cache.demand_mshr_hits::cpu.data 13 # number of demand (read+write) MSHR hits 855system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits 856system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits 857system.cpu.l2cache.overall_mshr_hits::cpu.data 13 # number of overall MSHR hits 858system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits 859system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2055 # number of ReadReq MSHR misses | 861system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits 862system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 11 # number of ReadReq MSHR hits 863system.cpu.l2cache.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits 864system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits 865system.cpu.l2cache.demand_mshr_hits::cpu.data 11 # number of demand (read+write) MSHR hits 866system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits 867system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits 868system.cpu.l2cache.overall_mshr_hits::cpu.data 11 # number of overall MSHR hits 869system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits 870system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2061 # number of ReadReq MSHR misses |
| 860system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 676 # number of ReadReq MSHR misses | 871system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 676 # number of ReadReq MSHR misses |
| 861system.cpu.l2cache.ReadReq_mshr_misses::total 2731 # number of ReadReq MSHR misses 862system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1071 # number of ReadExReq MSHR misses 863system.cpu.l2cache.ReadExReq_mshr_misses::total 1071 # number of ReadExReq MSHR misses 864system.cpu.l2cache.demand_mshr_misses::cpu.inst 2055 # number of demand (read+write) MSHR misses 865system.cpu.l2cache.demand_mshr_misses::cpu.data 1747 # number of demand (read+write) MSHR misses 866system.cpu.l2cache.demand_mshr_misses::total 3802 # number of demand (read+write) MSHR misses 867system.cpu.l2cache.overall_mshr_misses::cpu.inst 2055 # number of overall MSHR misses 868system.cpu.l2cache.overall_mshr_misses::cpu.data 1747 # number of overall MSHR misses 869system.cpu.l2cache.overall_mshr_misses::total 3802 # number of overall MSHR misses 870system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 116514500 # number of ReadReq MSHR miss cycles 871system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 41206750 # number of ReadReq MSHR miss cycles 872system.cpu.l2cache.ReadReq_mshr_miss_latency::total 157721250 # number of ReadReq MSHR miss cycles 873system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60687250 # number of ReadExReq MSHR miss cycles 874system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60687250 # number of ReadExReq MSHR miss cycles 875system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116514500 # number of demand (read+write) MSHR miss cycles 876system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101894000 # number of demand (read+write) MSHR miss cycles 877system.cpu.l2cache.demand_mshr_miss_latency::total 218408500 # number of demand (read+write) MSHR miss cycles 878system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116514500 # number of overall MSHR miss cycles 879system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101894000 # number of overall MSHR miss cycles 880system.cpu.l2cache.overall_mshr_miss_latency::total 218408500 # number of overall MSHR miss cycles 881system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.498786 # mshr miss rate for ReadReq accesses | 872system.cpu.l2cache.ReadReq_mshr_misses::total 2737 # number of ReadReq MSHR misses 873system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses 874system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses 875system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1077 # number of ReadExReq MSHR misses 876system.cpu.l2cache.ReadExReq_mshr_misses::total 1077 # number of ReadExReq MSHR misses 877system.cpu.l2cache.demand_mshr_misses::cpu.inst 2061 # number of demand (read+write) MSHR misses 878system.cpu.l2cache.demand_mshr_misses::cpu.data 1753 # number of demand (read+write) MSHR misses 879system.cpu.l2cache.demand_mshr_misses::total 3814 # number of demand (read+write) MSHR misses 880system.cpu.l2cache.overall_mshr_misses::cpu.inst 2061 # number of overall MSHR misses 881system.cpu.l2cache.overall_mshr_misses::cpu.data 1753 # number of overall MSHR misses 882system.cpu.l2cache.overall_mshr_misses::total 3814 # number of overall MSHR misses 883system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117822250 # number of ReadReq MSHR miss cycles 884system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40424500 # number of ReadReq MSHR miss cycles 885system.cpu.l2cache.ReadReq_mshr_miss_latency::total 158246750 # number of ReadReq MSHR miss cycles 886system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles 887system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles 888system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60589000 # number of ReadExReq MSHR miss cycles 889system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60589000 # number of ReadExReq MSHR miss cycles 890system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117822250 # number of demand (read+write) MSHR miss cycles 891system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101013500 # number of demand (read+write) MSHR miss cycles 892system.cpu.l2cache.demand_mshr_miss_latency::total 218835750 # number of demand (read+write) MSHR miss cycles 893system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117822250 # number of overall MSHR miss cycles 894system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101013500 # number of overall MSHR miss cycles 895system.cpu.l2cache.overall_mshr_miss_latency::total 218835750 # number of overall MSHR miss cycles 896system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.500000 # mshr miss rate for ReadReq accesses |
| 882system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871134 # mshr miss rate for ReadReq accesses | 897system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871134 # mshr miss rate for ReadReq accesses |
| 883system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.557802 # mshr miss rate for ReadReq accesses 884system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.990749 # mshr miss rate for ReadExReq accesses 885system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.990749 # mshr miss rate for ReadExReq accesses 886system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.498786 # mshr miss rate for demand accesses 887system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.940765 # mshr miss rate for demand accesses 888system.cpu.l2cache.demand_mshr_miss_rate::total 0.636105 # mshr miss rate for demand accesses 889system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.498786 # mshr miss rate for overall accesses 890system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940765 # mshr miss rate for overall accesses 891system.cpu.l2cache.overall_mshr_miss_rate::total 0.636105 # mshr miss rate for overall accesses 892system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56698.053528 # average ReadReq mshr miss latency 893system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60956.730769 # average ReadReq mshr miss latency 894system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57752.196997 # average ReadReq mshr miss latency 895system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56664.098973 # average ReadExReq mshr miss latency 896system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56664.098973 # average ReadExReq mshr miss latency 897system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56698.053528 # average overall mshr miss latency 898system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58325.128792 # average overall mshr miss latency 899system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57445.686481 # average overall mshr miss latency 900system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56698.053528 # average overall mshr miss latency 901system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58325.128792 # average overall mshr miss latency 902system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57445.686481 # average overall mshr miss latency | 898system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.558800 # mshr miss rate for ReadReq accesses 899system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 900system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 901system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993542 # mshr miss rate for ReadExReq accesses 902system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993542 # mshr miss rate for ReadExReq accesses 903system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.500000 # mshr miss rate for demand accesses 904system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942473 # mshr miss rate for demand accesses 905system.cpu.l2cache.demand_mshr_miss_rate::total 0.637579 # mshr miss rate for demand accesses 906system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.500000 # mshr miss rate for overall accesses 907system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942473 # mshr miss rate for overall accesses 908system.cpu.l2cache.overall_mshr_miss_rate::total 0.637579 # mshr miss rate for overall accesses 909system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57167.515769 # average ReadReq mshr miss latency 910system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59799.556213 # average ReadReq mshr miss latency 911system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57817.592254 # average ReadReq mshr miss latency 912system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 913system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 914system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56257.195915 # average ReadExReq mshr miss latency 915system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56257.195915 # average ReadExReq mshr miss latency 916system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57167.515769 # average overall mshr miss latency 917system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57623.217342 # average overall mshr miss latency 918system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57376.966439 # average overall mshr miss latency 919system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57167.515769 # average overall mshr miss latency 920system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57623.217342 # average overall mshr miss latency 921system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57376.966439 # average overall mshr miss latency |
| 903system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 922system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 904system.cpu.dcache.tags.replacements 60 # number of replacements 905system.cpu.dcache.tags.tagsinuse 1407.063073 # Cycle average of tags in use 906system.cpu.dcache.tags.total_refs 46801066 # Total number of references to valid blocks. 907system.cpu.dcache.tags.sampled_refs 1857 # Sample count of references to valid blocks. 908system.cpu.dcache.tags.avg_refs 25202.512655 # Average number of references to valid blocks. | 923system.cpu.dcache.tags.replacements 56 # number of replacements 924system.cpu.dcache.tags.tagsinuse 1410.171492 # Cycle average of tags in use 925system.cpu.dcache.tags.total_refs 47073011 # Total number of references to valid blocks. 926system.cpu.dcache.tags.sampled_refs 1860 # Sample count of references to valid blocks. 927system.cpu.dcache.tags.avg_refs 25308.070430 # Average number of references to valid blocks. |
| 909system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 928system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 910system.cpu.dcache.tags.occ_blocks::cpu.data 1407.063073 # Average occupied blocks per requestor 911system.cpu.dcache.tags.occ_percent::cpu.data 0.343521 # Average percentage of cache occupancy 912system.cpu.dcache.tags.occ_percent::total 0.343521 # Average percentage of cache occupancy 913system.cpu.dcache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id 914system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id | 929system.cpu.dcache.tags.occ_blocks::cpu.data 1410.171492 # Average occupied blocks per requestor 930system.cpu.dcache.tags.occ_percent::cpu.data 0.344280 # Average percentage of cache occupancy 931system.cpu.dcache.tags.occ_percent::total 0.344280 # Average percentage of cache occupancy 932system.cpu.dcache.tags.occ_task_id_blocks::1024 1804 # Occupied blocks per task id 933system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id |
| 915system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id 916system.cpu.dcache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id | 934system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id 935system.cpu.dcache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id |
| 917system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 918system.cpu.dcache.tags.age_task_id_blocks_1024::4 1378 # Occupied blocks per task id 919system.cpu.dcache.tags.occ_task_id_percent::1024 0.438721 # Percentage of cache occupancy per task id 920system.cpu.dcache.tags.tag_accesses 93623269 # Number of tag accesses 921system.cpu.dcache.tags.data_accesses 93623269 # Number of data accesses 922system.cpu.dcache.ReadReq_hits::cpu.data 34399630 # number of ReadReq hits 923system.cpu.dcache.ReadReq_hits::total 34399630 # number of ReadReq hits 924system.cpu.dcache.WriteReq_hits::cpu.data 12356556 # number of WriteReq hits 925system.cpu.dcache.WriteReq_hits::total 12356556 # number of WriteReq hits 926system.cpu.dcache.LoadLockedReq_hits::cpu.data 22473 # number of LoadLockedReq hits 927system.cpu.dcache.LoadLockedReq_hits::total 22473 # number of LoadLockedReq hits | 936system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id 937system.cpu.dcache.tags.age_task_id_blocks_1024::4 1382 # Occupied blocks per task id 938system.cpu.dcache.tags.occ_task_id_percent::1024 0.440430 # Percentage of cache occupancy per task id 939system.cpu.dcache.tags.tag_accesses 94167216 # Number of tag accesses 940system.cpu.dcache.tags.data_accesses 94167216 # Number of data accesses 941system.cpu.dcache.ReadReq_hits::cpu.data 34671591 # number of ReadReq hits 942system.cpu.dcache.ReadReq_hits::total 34671591 # number of ReadReq hits 943system.cpu.dcache.WriteReq_hits::cpu.data 12356534 # number of WriteReq hits 944system.cpu.dcache.WriteReq_hits::total 12356534 # number of WriteReq hits 945system.cpu.dcache.LoadLockedReq_hits::cpu.data 22477 # number of LoadLockedReq hits 946system.cpu.dcache.LoadLockedReq_hits::total 22477 # number of LoadLockedReq hits |
| 928system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits 929system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits | 947system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits 948system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits |
| 930system.cpu.dcache.demand_hits::cpu.data 46756186 # number of demand (read+write) hits 931system.cpu.dcache.demand_hits::total 46756186 # number of demand (read+write) hits 932system.cpu.dcache.overall_hits::cpu.data 46756186 # number of overall hits 933system.cpu.dcache.overall_hits::total 46756186 # number of overall hits 934system.cpu.dcache.ReadReq_misses::cpu.data 1907 # number of ReadReq misses 935system.cpu.dcache.ReadReq_misses::total 1907 # number of ReadReq misses 936system.cpu.dcache.WriteReq_misses::cpu.data 7731 # number of WriteReq misses 937system.cpu.dcache.WriteReq_misses::total 7731 # number of WriteReq misses | 949system.cpu.dcache.demand_hits::cpu.data 47028125 # number of demand (read+write) hits 950system.cpu.dcache.demand_hits::total 47028125 # number of demand (read+write) hits 951system.cpu.dcache.overall_hits::cpu.data 47028125 # number of overall hits 952system.cpu.dcache.overall_hits::total 47028125 # number of overall hits 953system.cpu.dcache.ReadReq_misses::cpu.data 1914 # number of ReadReq misses 954system.cpu.dcache.ReadReq_misses::total 1914 # number of ReadReq misses 955system.cpu.dcache.WriteReq_misses::cpu.data 7753 # number of WriteReq misses 956system.cpu.dcache.WriteReq_misses::total 7753 # number of WriteReq misses |
| 938system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 939system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses | 957system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 958system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses |
| 940system.cpu.dcache.demand_misses::cpu.data 9638 # number of demand (read+write) misses 941system.cpu.dcache.demand_misses::total 9638 # number of demand (read+write) misses 942system.cpu.dcache.overall_misses::cpu.data 9638 # number of overall misses 943system.cpu.dcache.overall_misses::total 9638 # number of overall misses 944system.cpu.dcache.ReadReq_miss_latency::cpu.data 121525225 # number of ReadReq miss cycles 945system.cpu.dcache.ReadReq_miss_latency::total 121525225 # number of ReadReq miss cycles 946system.cpu.dcache.WriteReq_miss_latency::cpu.data 489452496 # number of WriteReq miss cycles 947system.cpu.dcache.WriteReq_miss_latency::total 489452496 # number of WriteReq miss cycles | 959system.cpu.dcache.demand_misses::cpu.data 9667 # number of demand (read+write) misses 960system.cpu.dcache.demand_misses::total 9667 # number of demand (read+write) misses 961system.cpu.dcache.overall_misses::cpu.data 9667 # number of overall misses 962system.cpu.dcache.overall_misses::total 9667 # number of overall misses 963system.cpu.dcache.ReadReq_miss_latency::cpu.data 120679977 # number of ReadReq miss cycles 964system.cpu.dcache.ReadReq_miss_latency::total 120679977 # number of ReadReq miss cycles 965system.cpu.dcache.WriteReq_miss_latency::cpu.data 501616998 # number of WriteReq miss cycles 966system.cpu.dcache.WriteReq_miss_latency::total 501616998 # number of WriteReq miss cycles |
| 948system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles 949system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles | 967system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles 968system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles |
| 950system.cpu.dcache.demand_miss_latency::cpu.data 610977721 # number of demand (read+write) miss cycles 951system.cpu.dcache.demand_miss_latency::total 610977721 # number of demand (read+write) miss cycles 952system.cpu.dcache.overall_miss_latency::cpu.data 610977721 # number of overall miss cycles 953system.cpu.dcache.overall_miss_latency::total 610977721 # number of overall miss cycles 954system.cpu.dcache.ReadReq_accesses::cpu.data 34401537 # number of ReadReq accesses(hits+misses) 955system.cpu.dcache.ReadReq_accesses::total 34401537 # number of ReadReq accesses(hits+misses) | 969system.cpu.dcache.demand_miss_latency::cpu.data 622296975 # number of demand (read+write) miss cycles 970system.cpu.dcache.demand_miss_latency::total 622296975 # number of demand (read+write) miss cycles 971system.cpu.dcache.overall_miss_latency::cpu.data 622296975 # number of overall miss cycles 972system.cpu.dcache.overall_miss_latency::total 622296975 # number of overall miss cycles 973system.cpu.dcache.ReadReq_accesses::cpu.data 34673505 # number of ReadReq accesses(hits+misses) 974system.cpu.dcache.ReadReq_accesses::total 34673505 # number of ReadReq accesses(hits+misses) |
| 956system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 957system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) | 975system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 976system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) |
| 958system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22475 # number of LoadLockedReq accesses(hits+misses) 959system.cpu.dcache.LoadLockedReq_accesses::total 22475 # number of LoadLockedReq accesses(hits+misses) | 977system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22479 # number of LoadLockedReq accesses(hits+misses) 978system.cpu.dcache.LoadLockedReq_accesses::total 22479 # number of LoadLockedReq accesses(hits+misses) |
| 960system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) 961system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) | 979system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) 980system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) |
| 962system.cpu.dcache.demand_accesses::cpu.data 46765824 # number of demand (read+write) accesses 963system.cpu.dcache.demand_accesses::total 46765824 # number of demand (read+write) accesses 964system.cpu.dcache.overall_accesses::cpu.data 46765824 # number of overall (read+write) accesses 965system.cpu.dcache.overall_accesses::total 46765824 # number of overall (read+write) accesses | 981system.cpu.dcache.demand_accesses::cpu.data 47037792 # number of demand (read+write) accesses 982system.cpu.dcache.demand_accesses::total 47037792 # number of demand (read+write) accesses 983system.cpu.dcache.overall_accesses::cpu.data 47037792 # number of overall (read+write) accesses 984system.cpu.dcache.overall_accesses::total 47037792 # number of overall (read+write) accesses |
| 966system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses 967system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses | 985system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses 986system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses |
| 968system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses 969system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses | 987system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000627 # miss rate for WriteReq accesses 988system.cpu.dcache.WriteReq_miss_rate::total 0.000627 # miss rate for WriteReq accesses |
| 970system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses 971system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses 972system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses 973system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses 974system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses 975system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses | 989system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses 990system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses 991system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses 992system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses 993system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses 994system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses |
| 976system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63725.865233 # average ReadReq miss latency 977system.cpu.dcache.ReadReq_avg_miss_latency::total 63725.865233 # average ReadReq miss latency 978system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63310.373302 # average WriteReq miss latency 979system.cpu.dcache.WriteReq_avg_miss_latency::total 63310.373302 # average WriteReq miss latency | 995system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63051.189655 # average ReadReq miss latency 996system.cpu.dcache.ReadReq_avg_miss_latency::total 63051.189655 # average ReadReq miss latency 997system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64699.728879 # average WriteReq miss latency 998system.cpu.dcache.WriteReq_avg_miss_latency::total 64699.728879 # average WriteReq miss latency |
| 980system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency 981system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency | 999system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency 1000system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency |
| 982system.cpu.dcache.demand_avg_miss_latency::cpu.data 63392.583627 # average overall miss latency 983system.cpu.dcache.demand_avg_miss_latency::total 63392.583627 # average overall miss latency 984system.cpu.dcache.overall_avg_miss_latency::cpu.data 63392.583627 # average overall miss latency 985system.cpu.dcache.overall_avg_miss_latency::total 63392.583627 # average overall miss latency 986system.cpu.dcache.blocked_cycles::no_mshrs 567 # number of cycles access was blocked 987system.cpu.dcache.blocked_cycles::no_targets 318 # number of cycles access was blocked 988system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked 989system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked 990system.cpu.dcache.avg_blocked_cycles::no_mshrs 51.545455 # average number of cycles each access was blocked 991system.cpu.dcache.avg_blocked_cycles::no_targets 79.500000 # average number of cycles each access was blocked | 1001system.cpu.dcache.demand_avg_miss_latency::cpu.data 64373.329368 # average overall miss latency 1002system.cpu.dcache.demand_avg_miss_latency::total 64373.329368 # average overall miss latency 1003system.cpu.dcache.overall_avg_miss_latency::cpu.data 64373.329368 # average overall miss latency 1004system.cpu.dcache.overall_avg_miss_latency::total 64373.329368 # average overall miss latency 1005system.cpu.dcache.blocked_cycles::no_mshrs 706 # number of cycles access was blocked 1006system.cpu.dcache.blocked_cycles::no_targets 99 # number of cycles access was blocked 1007system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked 1008system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked 1009system.cpu.dcache.avg_blocked_cycles::no_mshrs 50.428571 # average number of cycles each access was blocked 1010system.cpu.dcache.avg_blocked_cycles::no_targets 99 # average number of cycles each access was blocked |
| 992system.cpu.dcache.fast_writes 0 # number of fast writes performed 993system.cpu.dcache.cache_copies 0 # number of cache copies performed | 1011system.cpu.dcache.fast_writes 0 # number of fast writes performed 1012system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 994system.cpu.dcache.writebacks::writebacks 19 # number of writebacks 995system.cpu.dcache.writebacks::total 19 # number of writebacks 996system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1130 # number of ReadReq MSHR hits 997system.cpu.dcache.ReadReq_mshr_hits::total 1130 # number of ReadReq MSHR hits 998system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6651 # number of WriteReq MSHR hits 999system.cpu.dcache.WriteReq_mshr_hits::total 6651 # number of WriteReq MSHR hits | 1013system.cpu.dcache.writebacks::writebacks 16 # number of writebacks 1014system.cpu.dcache.writebacks::total 16 # number of writebacks 1015system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1137 # number of ReadReq MSHR hits 1016system.cpu.dcache.ReadReq_mshr_hits::total 1137 # number of ReadReq MSHR hits 1017system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6668 # number of WriteReq MSHR hits 1018system.cpu.dcache.WriteReq_mshr_hits::total 6668 # number of WriteReq MSHR hits |
| 1000system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 1001system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits | 1019system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 1020system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits |
| 1002system.cpu.dcache.demand_mshr_hits::cpu.data 7781 # number of demand (read+write) MSHR hits 1003system.cpu.dcache.demand_mshr_hits::total 7781 # number of demand (read+write) MSHR hits 1004system.cpu.dcache.overall_mshr_hits::cpu.data 7781 # number of overall MSHR hits 1005system.cpu.dcache.overall_mshr_hits::total 7781 # number of overall MSHR hits | 1021system.cpu.dcache.demand_mshr_hits::cpu.data 7805 # number of demand (read+write) MSHR hits 1022system.cpu.dcache.demand_mshr_hits::total 7805 # number of demand (read+write) MSHR hits 1023system.cpu.dcache.overall_mshr_hits::cpu.data 7805 # number of overall MSHR hits 1024system.cpu.dcache.overall_mshr_hits::total 7805 # number of overall MSHR hits |
| 1006system.cpu.dcache.ReadReq_mshr_misses::cpu.data 777 # number of ReadReq MSHR misses 1007system.cpu.dcache.ReadReq_mshr_misses::total 777 # number of ReadReq MSHR misses | 1025system.cpu.dcache.ReadReq_mshr_misses::cpu.data 777 # number of ReadReq MSHR misses 1026system.cpu.dcache.ReadReq_mshr_misses::total 777 # number of ReadReq MSHR misses |
| 1008system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1080 # number of WriteReq MSHR misses 1009system.cpu.dcache.WriteReq_mshr_misses::total 1080 # number of WriteReq MSHR misses 1010system.cpu.dcache.demand_mshr_misses::cpu.data 1857 # number of demand (read+write) MSHR misses 1011system.cpu.dcache.demand_mshr_misses::total 1857 # number of demand (read+write) MSHR misses 1012system.cpu.dcache.overall_mshr_misses::cpu.data 1857 # number of overall MSHR misses 1013system.cpu.dcache.overall_mshr_misses::total 1857 # number of overall MSHR misses 1014system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52119013 # number of ReadReq MSHR miss cycles 1015system.cpu.dcache.ReadReq_mshr_miss_latency::total 52119013 # number of ReadReq MSHR miss cycles 1016system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 75404498 # number of WriteReq MSHR miss cycles 1017system.cpu.dcache.WriteReq_mshr_miss_latency::total 75404498 # number of WriteReq MSHR miss cycles 1018system.cpu.dcache.demand_mshr_miss_latency::cpu.data 127523511 # number of demand (read+write) MSHR miss cycles 1019system.cpu.dcache.demand_mshr_miss_latency::total 127523511 # number of demand (read+write) MSHR miss cycles 1020system.cpu.dcache.overall_mshr_miss_latency::cpu.data 127523511 # number of overall MSHR miss cycles 1021system.cpu.dcache.overall_mshr_miss_latency::total 127523511 # number of overall MSHR miss cycles 1022system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses 1023system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses 1024system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses 1025system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses | 1027system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses 1028system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses 1029system.cpu.dcache.demand_mshr_misses::cpu.data 1862 # number of demand (read+write) MSHR misses 1030system.cpu.dcache.demand_mshr_misses::total 1862 # number of demand (read+write) MSHR misses 1031system.cpu.dcache.overall_mshr_misses::cpu.data 1862 # number of overall MSHR misses 1032system.cpu.dcache.overall_mshr_misses::total 1862 # number of overall MSHR misses 1033system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51275761 # number of ReadReq MSHR miss cycles 1034system.cpu.dcache.ReadReq_mshr_miss_latency::total 51275761 # number of ReadReq MSHR miss cycles 1035system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 75222996 # number of WriteReq MSHR miss cycles 1036system.cpu.dcache.WriteReq_mshr_miss_latency::total 75222996 # number of WriteReq MSHR miss cycles 1037system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126498757 # number of demand (read+write) MSHR miss cycles 1038system.cpu.dcache.demand_mshr_miss_latency::total 126498757 # number of demand (read+write) MSHR miss cycles 1039system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126498757 # number of overall MSHR miss cycles 1040system.cpu.dcache.overall_mshr_miss_latency::total 126498757 # number of overall MSHR miss cycles 1041system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses 1042system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses 1043system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses 1044system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses |
| 1026system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses 1027system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 1028system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses 1029system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses | 1045system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses 1046system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 1047system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses 1048system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses |
| 1030system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67077.236808 # average ReadReq mshr miss latency 1031system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67077.236808 # average ReadReq mshr miss latency 1032system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69818.979630 # average WriteReq mshr miss latency 1033system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69818.979630 # average WriteReq mshr miss latency 1034system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68671.788368 # average overall mshr miss latency 1035system.cpu.dcache.demand_avg_mshr_miss_latency::total 68671.788368 # average overall mshr miss latency 1036system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68671.788368 # average overall mshr miss latency 1037system.cpu.dcache.overall_avg_mshr_miss_latency::total 68671.788368 # average overall mshr miss latency | 1049system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65991.970399 # average ReadReq mshr miss latency 1050system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65991.970399 # average ReadReq mshr miss latency 1051system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69329.950230 # average WriteReq mshr miss latency 1052system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69329.950230 # average WriteReq mshr miss latency 1053system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67937.033835 # average overall mshr miss latency 1054system.cpu.dcache.demand_avg_mshr_miss_latency::total 67937.033835 # average overall mshr miss latency 1055system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67937.033835 # average overall mshr miss latency 1056system.cpu.dcache.overall_avg_mshr_miss_latency::total 67937.033835 # average overall mshr miss latency |
| 1038system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1039 1040---------- End Simulation Statistics ---------- | 1057system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1058 1059---------- End Simulation Statistics ---------- |