| stats.txt (10148:4574d5882066) | stats.txt (10220:9eab5efc02e8) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.074212 # Number of seconds simulated 4sim_ticks 74211770500 # Number of ticks simulated 5final_tick 74211770500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.074209 # Number of seconds simulated 4sim_ticks 74208571000 # Number of ticks simulated 5final_tick 74208571000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 109728 # Simulator instruction rate (inst/s) 8host_op_rate 120142 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 47260193 # Simulator tick rate (ticks/s) 10host_mem_usage 316324 # Number of bytes of host memory used 11host_seconds 1570.28 # Real time elapsed on the host | 7host_inst_rate 109569 # Simulator instruction rate (inst/s) 8host_op_rate 119969 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 47190079 # Simulator tick rate (ticks/s) 10host_mem_usage 316768 # Number of bytes of host memory used 11host_seconds 1572.55 # Real time elapsed on the host |
| 12sim_insts 172303021 # Number of instructions simulated 13sim_ops 188656503 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 172303021 # Number of instructions simulated 13sim_ops 188656503 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 131072 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 112000 # Number of bytes read from this memory 18system.physmem.bytes_read::total 243072 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 131072 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 131072 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 2048 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1750 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 3798 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1766189 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 1509195 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 3275383 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1766189 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1766189 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1766189 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 1509195 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 3275383 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 3799 # Number of read requests accepted | 16system.physmem.bytes_read::cpu.inst 131456 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 111808 # Number of bytes read from this memory 18system.physmem.bytes_read::total 243264 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 131456 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 131456 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 2054 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1747 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 3801 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1771440 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 1506672 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 3278112 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1771440 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1771440 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1771440 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 1506672 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 3278112 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 3802 # Number of read requests accepted |
| 33system.physmem.writeReqs 0 # Number of write requests accepted | 33system.physmem.writeReqs 0 # Number of write requests accepted |
| 34system.physmem.readBursts 3799 # Number of DRAM read bursts, including those serviced by the write queue | 34system.physmem.readBursts 3802 # Number of DRAM read bursts, including those serviced by the write queue |
| 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 36system.physmem.bytesReadDRAM 243136 # Total number of bytes read from DRAM | 36system.physmem.bytesReadDRAM 243328 # Total number of bytes read from DRAM |
| 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 39system.physmem.bytesReadSys 243136 # Total read bytes from the system interface side | 39system.physmem.bytesReadSys 243328 # Total read bytes from the system interface side |
| 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 306 # Per bank write bursts | 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 306 # Per bank write bursts |
| 45system.physmem.perBankRdBursts::1 215 # Per bank write bursts 46system.physmem.perBankRdBursts::2 132 # Per bank write bursts | 45system.physmem.perBankRdBursts::1 216 # Per bank write bursts 46system.physmem.perBankRdBursts::2 134 # Per bank write bursts |
| 47system.physmem.perBankRdBursts::3 308 # Per bank write bursts 48system.physmem.perBankRdBursts::4 298 # Per bank write bursts | 47system.physmem.perBankRdBursts::3 308 # Per bank write bursts 48system.physmem.perBankRdBursts::4 298 # Per bank write bursts |
| 49system.physmem.perBankRdBursts::5 299 # Per bank write bursts | 49system.physmem.perBankRdBursts::5 300 # Per bank write bursts |
| 50system.physmem.perBankRdBursts::6 265 # Per bank write bursts | 50system.physmem.perBankRdBursts::6 265 # Per bank write bursts |
| 51system.physmem.perBankRdBursts::7 218 # Per bank write bursts | 51system.physmem.perBankRdBursts::7 217 # Per bank write bursts |
| 52system.physmem.perBankRdBursts::8 246 # Per bank write bursts | 52system.physmem.perBankRdBursts::8 246 # Per bank write bursts |
| 53system.physmem.perBankRdBursts::9 214 # Per bank write bursts | 53system.physmem.perBankRdBursts::9 215 # Per bank write bursts |
| 54system.physmem.perBankRdBursts::10 289 # Per bank write bursts 55system.physmem.perBankRdBursts::11 192 # Per bank write bursts 56system.physmem.perBankRdBursts::12 190 # Per bank write bursts 57system.physmem.perBankRdBursts::13 208 # Per bank write bursts | 54system.physmem.perBankRdBursts::10 289 # Per bank write bursts 55system.physmem.perBankRdBursts::11 192 # Per bank write bursts 56system.physmem.perBankRdBursts::12 190 # Per bank write bursts 57system.physmem.perBankRdBursts::13 208 # Per bank write bursts |
| 58system.physmem.perBankRdBursts::14 219 # Per bank write bursts | 58system.physmem.perBankRdBursts::14 218 # Per bank write bursts |
| 59system.physmem.perBankRdBursts::15 200 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 59system.physmem.perBankRdBursts::15 200 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 74211752000 # Total gap between requests | 78system.physmem.totGap 74208552500 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 85system.physmem.readPktSize::6 3799 # Read request sizes (log2) | 85system.physmem.readPktSize::6 3802 # Read request sizes (log2) |
| 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) | 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 93system.physmem.rdQLenPdf::0 2838 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 780 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 138 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see | 93system.physmem.rdQLenPdf::0 2914 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 704 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 139 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see |
| 97system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 76 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 97system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 76 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 189system.physmem.bytesPerActivate::samples 252 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 398.476190 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 217.440190 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 401.372897 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 87 34.52% 34.52% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 58 23.02% 57.54% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 17 6.75% 64.29% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 5 1.98% 66.27% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 7 2.78% 69.05% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 8 3.17% 72.22% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 4 1.59% 73.81% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 3 1.19% 75.00% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 63 25.00% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 252 # Bytes accessed per row activation 203system.physmem.totQLat 23847500 # Total ticks spent queuing 204system.physmem.totMemAccLat 100702500 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 18995000 # Total ticks spent in databus transfers 206system.physmem.totBankLat 57860000 # Total ticks spent accessing banks 207system.physmem.avgQLat 6277.31 # Average queueing delay per DRAM burst 208system.physmem.avgBankLat 15230.32 # Average bank access latency per DRAM burst | 189system.physmem.bytesPerActivate::samples 765 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 315.649673 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 194.993895 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 311.806865 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 244 31.90% 31.90% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 208 27.19% 59.08% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 73 9.54% 68.63% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 46 6.01% 74.64% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 29 3.79% 78.43% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 70 9.15% 87.58% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 12 1.57% 89.15% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 15 1.96% 91.11% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 68 8.89% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 765 # Bytes accessed per row activation 203system.physmem.totQLat 30320750 # Total ticks spent queuing 204system.physmem.totMemAccLat 101608250 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 19010000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 7974.95 # Average queueing delay per DRAM burst |
| 209system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 210system.physmem.avgMemAccLat 26507.63 # Average memory access latency per DRAM burst | 208system.physmem.avgMemAccLat 26724.95 # Average memory access latency per DRAM burst |
| 211system.physmem.avgRdBW 3.28 # Average DRAM read bandwidth in MiByte/s 212system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 213system.physmem.avgRdBWSys 3.28 # Average system read bandwidth in MiByte/s 214system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 215system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 216system.physmem.busUtil 0.03 # Data bus utilization in percentage 217system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 218system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 209system.physmem.avgRdBW 3.28 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 3.28 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.03 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 219system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing | 217system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing |
| 220system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 221system.physmem.readRowHits 3018 # Number of row buffer hits during reads | 219system.physmem.readRowHits 3030 # Number of row buffer hits during reads |
| 222system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 223system.physmem.readRowHitRate 79.44 # Row buffer hit rate for reads | 221system.physmem.readRowHitRate 79.69 # Row buffer hit rate for reads |
| 224system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 225system.physmem.avgGap 19534549.09 # Average gap between requests 226system.physmem.pageHitRate 79.44 # Row buffer hit rate, read and write combined 227system.physmem.prechargeAllPercent 0.21 # Percentage of time for which DRAM has all the banks in precharge state 228system.membus.throughput 3275383 # Throughput (bytes/s) 229system.membus.trans_dist::ReadReq 2728 # Transaction distribution 230system.membus.trans_dist::ReadResp 2727 # Transaction distribution | 223system.physmem.avgGap 19518293.66 # Average gap between requests 224system.physmem.pageHitRate 79.69 # Row buffer hit rate, read and write combined 225system.physmem.memoryStateTime::IDLE 70857777500 # Time in different power states 226system.physmem.memoryStateTime::REF 2477800000 # Time in different power states 227system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 228system.physmem.memoryStateTime::ACT 867720500 # Time in different power states 229system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 230system.membus.throughput 3278112 # Throughput (bytes/s) 231system.membus.trans_dist::ReadReq 2731 # Transaction distribution 232system.membus.trans_dist::ReadResp 2730 # Transaction distribution |
| 231system.membus.trans_dist::ReadExReq 1071 # Transaction distribution 232system.membus.trans_dist::ReadExResp 1071 # Transaction distribution | 233system.membus.trans_dist::ReadExReq 1071 # Transaction distribution 234system.membus.trans_dist::ReadExResp 1071 # Transaction distribution |
| 233system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7597 # Packet count per connected master and slave (bytes) 234system.membus.pkt_count::total 7597 # Packet count per connected master and slave (bytes) 235system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 243072 # Cumulative packet size per connected master and slave (bytes) 236system.membus.tot_pkt_size::total 243072 # Cumulative packet size per connected master and slave (bytes) 237system.membus.data_through_bus 243072 # Total data (bytes) | 235system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7603 # Packet count per connected master and slave (bytes) 236system.membus.pkt_count::total 7603 # Packet count per connected master and slave (bytes) 237system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 243264 # Cumulative packet size per connected master and slave (bytes) 238system.membus.tot_pkt_size::total 243264 # Cumulative packet size per connected master and slave (bytes) 239system.membus.data_through_bus 243264 # Total data (bytes) |
| 238system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 240system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 239system.membus.reqLayer0.occupancy 4687500 # Layer occupancy (ticks) | 241system.membus.reqLayer0.occupancy 4745000 # Layer occupancy (ticks) |
| 240system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 242system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 241system.membus.respLayer1.occupancy 35592500 # Layer occupancy (ticks) | 243system.membus.respLayer1.occupancy 35718000 # Layer occupancy (ticks) |
| 242system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 243system.cpu_clk_domain.clock 500 # Clock period in ticks | 244system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 245system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 244system.cpu.branchPred.lookups 94795806 # Number of BP lookups 245system.cpu.branchPred.condPredicted 74795654 # Number of conditional branches predicted 246system.cpu.branchPred.condIncorrect 6279989 # Number of conditional branches incorrect 247system.cpu.branchPred.BTBLookups 44691885 # Number of BTB lookups 248system.cpu.branchPred.BTBHits 43051051 # Number of BTB hits | 246system.cpu.branchPred.lookups 94830067 # Number of BP lookups 247system.cpu.branchPred.condPredicted 74823235 # Number of conditional branches predicted 248system.cpu.branchPred.condIncorrect 6280063 # Number of conditional branches incorrect 249system.cpu.branchPred.BTBLookups 44671635 # Number of BTB lookups 250system.cpu.branchPred.BTBHits 43055955 # Number of BTB hits |
| 249system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 251system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 250system.cpu.branchPred.BTBHitPct 96.328564 # BTB Hit Percentage 251system.cpu.branchPred.usedRAS 4354918 # Number of times the RAS was used to get a target. 252system.cpu.branchPred.RASInCorrect 88426 # Number of incorrect RAS predictions. | 252system.cpu.branchPred.BTBHitPct 96.383208 # BTB Hit Percentage 253system.cpu.branchPred.usedRAS 4354004 # Number of times the RAS was used to get a target. 254system.cpu.branchPred.RASInCorrect 88575 # Number of incorrect RAS predictions. |
| 253system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 254system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 255system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 256system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 257system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 258system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 259system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 260system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 69 unchanged lines hidden (view full) --- 330system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 331system.cpu.itb.read_accesses 0 # DTB read accesses 332system.cpu.itb.write_accesses 0 # DTB write accesses 333system.cpu.itb.inst_accesses 0 # ITB inst accesses 334system.cpu.itb.hits 0 # DTB hits 335system.cpu.itb.misses 0 # DTB misses 336system.cpu.itb.accesses 0 # DTB accesses 337system.cpu.workload.num_syscalls 400 # Number of system calls | 255system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 256system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 257system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 258system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 259system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 260system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 261system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 262system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 69 unchanged lines hidden (view full) --- 332system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 333system.cpu.itb.read_accesses 0 # DTB read accesses 334system.cpu.itb.write_accesses 0 # DTB write accesses 335system.cpu.itb.inst_accesses 0 # ITB inst accesses 336system.cpu.itb.hits 0 # DTB hits 337system.cpu.itb.misses 0 # DTB misses 338system.cpu.itb.accesses 0 # DTB accesses 339system.cpu.workload.num_syscalls 400 # Number of system calls |
| 338system.cpu.numCycles 148423542 # number of cpu cycles simulated | 340system.cpu.numCycles 148417143 # number of cpu cycles simulated |
| 339system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 340system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 341system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 342system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 341system.cpu.fetch.icacheStallCycles 39654967 # Number of cycles fetch is stalled on an Icache miss 342system.cpu.fetch.Insts 380195915 # Number of instructions fetch has processed 343system.cpu.fetch.Branches 94795806 # Number of branches that fetch encountered 344system.cpu.fetch.predictedBranches 47405969 # Number of branches that fetch has predicted taken 345system.cpu.fetch.Cycles 80368300 # Number of cycles fetch has run and was not squashing or blocked 346system.cpu.fetch.SquashCycles 27279262 # Number of cycles fetch has spent squashing 347system.cpu.fetch.BlockedCycles 7212539 # Number of cycles fetch has spent blocked 348system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 349system.cpu.fetch.PendingTrapStallCycles 5988 # Number of stall cycles due to pending traps | 343system.cpu.fetch.icacheStallCycles 39654365 # Number of cycles fetch is stalled on an Icache miss 344system.cpu.fetch.Insts 380231735 # Number of instructions fetch has processed 345system.cpu.fetch.Branches 94830067 # Number of branches that fetch encountered 346system.cpu.fetch.predictedBranches 47409959 # Number of branches that fetch has predicted taken 347system.cpu.fetch.Cycles 80369944 # Number of cycles fetch has run and was not squashing or blocked 348system.cpu.fetch.SquashCycles 27285630 # Number of cycles fetch has spent squashing 349system.cpu.fetch.BlockedCycles 7202415 # Number of cycles fetch has spent blocked 350system.cpu.fetch.MiscStallCycles 10 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 351system.cpu.fetch.PendingTrapStallCycles 5794 # Number of stall cycles due to pending traps |
| 350system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions 351system.cpu.fetch.IcacheWaitRetryStallCycles 50 # Number of stall cycles due to full MSHR | 352system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions 353system.cpu.fetch.IcacheWaitRetryStallCycles 50 # Number of stall cycles due to full MSHR |
| 352system.cpu.fetch.CacheLines 36848695 # Number of cache lines fetched 353system.cpu.fetch.IcacheSquashes 1833193 # Number of outstanding Icache misses that were squashed 354system.cpu.fetch.rateDist::samples 148225221 # Number of instructions fetched each cycle (Total) 355system.cpu.fetch.rateDist::mean 2.802047 # Number of instructions fetched each cycle (Total) 356system.cpu.fetch.rateDist::stdev 3.153051 # Number of instructions fetched each cycle (Total) | 354system.cpu.fetch.CacheLines 36851066 # Number of cache lines fetched 355system.cpu.fetch.IcacheSquashes 1832690 # Number of outstanding Icache misses that were squashed 356system.cpu.fetch.rateDist::samples 148222429 # Number of instructions fetched each cycle (Total) 357system.cpu.fetch.rateDist::mean 2.802512 # Number of instructions fetched each cycle (Total) 358system.cpu.fetch.rateDist::stdev 3.153204 # Number of instructions fetched each cycle (Total) |
| 357system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 359system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 358system.cpu.fetch.rateDist::0 68026374 45.89% 45.89% # Number of instructions fetched each cycle (Total) 359system.cpu.fetch.rateDist::1 5263091 3.55% 49.44% # Number of instructions fetched each cycle (Total) 360system.cpu.fetch.rateDist::2 10536182 7.11% 56.55% # Number of instructions fetched each cycle (Total) 361system.cpu.fetch.rateDist::3 10285653 6.94% 63.49% # Number of instructions fetched each cycle (Total) 362system.cpu.fetch.rateDist::4 8660137 5.84% 69.33% # Number of instructions fetched each cycle (Total) 363system.cpu.fetch.rateDist::5 6544581 4.42% 73.75% # Number of instructions fetched each cycle (Total) 364system.cpu.fetch.rateDist::6 6243734 4.21% 77.96% # Number of instructions fetched each cycle (Total) 365system.cpu.fetch.rateDist::7 8007959 5.40% 83.36% # Number of instructions fetched each cycle (Total) 366system.cpu.fetch.rateDist::8 24657510 16.64% 100.00% # Number of instructions fetched each cycle (Total) | 360system.cpu.fetch.rateDist::0 68020985 45.89% 45.89% # Number of instructions fetched each cycle (Total) 361system.cpu.fetch.rateDist::1 5256509 3.55% 49.44% # Number of instructions fetched each cycle (Total) 362system.cpu.fetch.rateDist::2 10534999 7.11% 56.55% # Number of instructions fetched each cycle (Total) 363system.cpu.fetch.rateDist::3 10284828 6.94% 63.48% # Number of instructions fetched each cycle (Total) 364system.cpu.fetch.rateDist::4 8666572 5.85% 69.33% # Number of instructions fetched each cycle (Total) 365system.cpu.fetch.rateDist::5 6537070 4.41% 73.74% # Number of instructions fetched each cycle (Total) 366system.cpu.fetch.rateDist::6 6246175 4.21% 77.96% # Number of instructions fetched each cycle (Total) 367system.cpu.fetch.rateDist::7 8016813 5.41% 83.36% # Number of instructions fetched each cycle (Total) 368system.cpu.fetch.rateDist::8 24658478 16.64% 100.00% # Number of instructions fetched each cycle (Total) |
| 367system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 368system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 369system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 369system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 370system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 371system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 370system.cpu.fetch.rateDist::total 148225221 # Number of instructions fetched each cycle (Total) 371system.cpu.fetch.branchRate 0.638684 # Number of branch fetches per cycle 372system.cpu.fetch.rate 2.561561 # Number of inst fetches per cycle 373system.cpu.decode.IdleCycles 45510679 # Number of cycles decode is idle 374system.cpu.decode.BlockedCycles 5881311 # Number of cycles decode is blocked 375system.cpu.decode.RunCycles 74801618 # Number of cycles decode is running 376system.cpu.decode.UnblockCycles 1201370 # Number of cycles decode is unblocking 377system.cpu.decode.SquashCycles 20830243 # Number of cycles decode is squashing 378system.cpu.decode.BranchResolved 14327753 # Number of times decode resolved a branch 379system.cpu.decode.BranchMispred 164034 # Number of times decode detected a branch misprediction 380system.cpu.decode.DecodedInsts 392767808 # Number of instructions handled by decode 381system.cpu.decode.SquashedInsts 749358 # Number of squashed instructions handled by decode 382system.cpu.rename.SquashCycles 20830243 # Number of cycles rename is squashing 383system.cpu.rename.IdleCycles 50895494 # Number of cycles rename is idle 384system.cpu.rename.BlockCycles 723680 # Number of cycles rename is blocking 385system.cpu.rename.serializeStallCycles 602483 # count of cycles rename stalled for serializing inst 386system.cpu.rename.RunCycles 70555782 # Number of cycles rename is running 387system.cpu.rename.UnblockCycles 4617539 # Number of cycles rename is unblocking 388system.cpu.rename.RenamedInsts 371309891 # Number of instructions processed by rename 389system.cpu.rename.ROBFullEvents 37 # Number of times rename has blocked due to ROB full 390system.cpu.rename.IQFullEvents 338990 # Number of times rename has blocked due to IQ full 391system.cpu.rename.LSQFullEvents 3664355 # Number of times rename has blocked due to LSQ full 392system.cpu.rename.FullRegisterEvents 25 # Number of times there has been no free registers 393system.cpu.rename.RenamedOperands 631718613 # Number of destination operands rename has renamed 394system.cpu.rename.RenameLookups 1588504211 # Number of register rename lookups that rename has made 395system.cpu.rename.int_rename_lookups 1506839397 # Number of integer rename lookups 396system.cpu.rename.fp_rename_lookups 3198087 # Number of floating rename lookups | 372system.cpu.fetch.rateDist::total 148222429 # Number of instructions fetched each cycle (Total) 373system.cpu.fetch.branchRate 0.638943 # Number of branch fetches per cycle 374system.cpu.fetch.rate 2.561913 # Number of inst fetches per cycle 375system.cpu.decode.IdleCycles 45507597 # Number of cycles decode is idle 376system.cpu.decode.BlockedCycles 5871716 # Number of cycles decode is blocked 377system.cpu.decode.RunCycles 74805608 # Number of cycles decode is running 378system.cpu.decode.UnblockCycles 1201041 # Number of cycles decode is unblocking 379system.cpu.decode.SquashCycles 20836467 # Number of cycles decode is squashing 380system.cpu.decode.BranchResolved 14340186 # Number of times decode resolved a branch 381system.cpu.decode.BranchMispred 164591 # Number of times decode detected a branch misprediction 382system.cpu.decode.DecodedInsts 392845308 # Number of instructions handled by decode 383system.cpu.decode.SquashedInsts 733522 # Number of squashed instructions handled by decode 384system.cpu.rename.SquashCycles 20836467 # Number of cycles rename is squashing 385system.cpu.rename.IdleCycles 50894479 # Number of cycles rename is idle 386system.cpu.rename.BlockCycles 722812 # Number of cycles rename is blocking 387system.cpu.rename.serializeStallCycles 602318 # count of cycles rename stalled for serializing inst 388system.cpu.rename.RunCycles 70557272 # Number of cycles rename is running 389system.cpu.rename.UnblockCycles 4609081 # Number of cycles rename is unblocking 390system.cpu.rename.RenamedInsts 371354915 # Number of instructions processed by rename 391system.cpu.rename.ROBFullEvents 44 # Number of times rename has blocked due to ROB full 392system.cpu.rename.IQFullEvents 338748 # Number of times rename has blocked due to IQ full 393system.cpu.rename.LSQFullEvents 3656059 # Number of times rename has blocked due to LSQ full 394system.cpu.rename.FullRegisterEvents 24 # Number of times there has been no free registers 395system.cpu.rename.RenamedOperands 631764461 # Number of destination operands rename has renamed 396system.cpu.rename.RenameLookups 1588652531 # Number of register rename lookups that rename has made 397system.cpu.rename.int_rename_lookups 1506975247 # Number of integer rename lookups 398system.cpu.rename.fp_rename_lookups 3198470 # Number of floating rename lookups |
| 397system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed | 399system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed |
| 398system.cpu.rename.UndoneMaps 333674474 # Number of HB maps that are undone due to squashing 399system.cpu.rename.serializingInsts 25005 # count of serializing insts renamed 400system.cpu.rename.tempSerializingInsts 25002 # count of temporary serializing insts renamed 401system.cpu.rename.skidInsts 13030816 # count of insts added to the skid buffer 402system.cpu.memDep0.insertedLoads 43005440 # Number of loads inserted to the mem dependence unit. 403system.cpu.memDep0.insertedStores 16429294 # Number of stores inserted to the mem dependence unit. 404system.cpu.memDep0.conflictingLoads 5701095 # Number of conflicting loads. 405system.cpu.memDep0.conflictingStores 3639070 # Number of conflicting stores. 406system.cpu.iq.iqInstsAdded 329189812 # Number of instructions added to the IQ (excludes non-spec) 407system.cpu.iq.iqNonSpecInstsAdded 47090 # Number of non-speculative instructions added to the IQ 408system.cpu.iq.iqInstsIssued 249460239 # Number of instructions issued 409system.cpu.iq.iqSquashedInstsIssued 787524 # Number of squashed instructions issued 410system.cpu.iq.iqSquashedInstsExamined 139505237 # Number of squashed instructions iterated over during squash; mainly for profiling 411system.cpu.iq.iqSquashedOperandsExamined 362363758 # Number of squashed operands that are examined and possibly removed from graph 412system.cpu.iq.iqSquashedNonSpecRemoved 1874 # Number of squashed non-spec instructions that were removed 413system.cpu.iq.issued_per_cycle::samples 148225221 # Number of insts issued each cycle 414system.cpu.iq.issued_per_cycle::mean 1.682981 # Number of insts issued each cycle 415system.cpu.iq.issued_per_cycle::stdev 1.761692 # Number of insts issued each cycle | 400system.cpu.rename.UndoneMaps 333720322 # Number of HB maps that are undone due to squashing 401system.cpu.rename.serializingInsts 25119 # count of serializing insts renamed 402system.cpu.rename.tempSerializingInsts 25116 # count of temporary serializing insts renamed 403system.cpu.rename.skidInsts 13019783 # count of insts added to the skid buffer 404system.cpu.memDep0.insertedLoads 43012506 # Number of loads inserted to the mem dependence unit. 405system.cpu.memDep0.insertedStores 16421309 # Number of stores inserted to the mem dependence unit. 406system.cpu.memDep0.conflictingLoads 5620383 # Number of conflicting loads. 407system.cpu.memDep0.conflictingStores 3639856 # Number of conflicting stores. 408system.cpu.iq.iqInstsAdded 329245944 # Number of instructions added to the IQ (excludes non-spec) 409system.cpu.iq.iqNonSpecInstsAdded 47173 # Number of non-speculative instructions added to the IQ 410system.cpu.iq.iqInstsIssued 249482695 # Number of instructions issued 411system.cpu.iq.iqSquashedInstsIssued 793526 # Number of squashed instructions issued 412system.cpu.iq.iqSquashedInstsExamined 139565421 # Number of squashed instructions iterated over during squash; mainly for profiling 413system.cpu.iq.iqSquashedOperandsExamined 362544222 # Number of squashed operands that are examined and possibly removed from graph 414system.cpu.iq.iqSquashedNonSpecRemoved 1957 # Number of squashed non-spec instructions that were removed 415system.cpu.iq.issued_per_cycle::samples 148222429 # Number of insts issued each cycle 416system.cpu.iq.issued_per_cycle::mean 1.683164 # Number of insts issued each cycle 417system.cpu.iq.issued_per_cycle::stdev 1.761970 # Number of insts issued each cycle |
| 416system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 418system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 417system.cpu.iq.issued_per_cycle::0 56054819 37.82% 37.82% # Number of insts issued each cycle 418system.cpu.iq.issued_per_cycle::1 22642547 15.28% 53.09% # Number of insts issued each cycle 419system.cpu.iq.issued_per_cycle::2 24806201 16.74% 69.83% # Number of insts issued each cycle 420system.cpu.iq.issued_per_cycle::3 20327492 13.71% 83.54% # Number of insts issued each cycle 421system.cpu.iq.issued_per_cycle::4 12550892 8.47% 92.01% # Number of insts issued each cycle 422system.cpu.iq.issued_per_cycle::5 6518173 4.40% 96.41% # Number of insts issued each cycle 423system.cpu.iq.issued_per_cycle::6 4029511 2.72% 99.13% # Number of insts issued each cycle 424system.cpu.iq.issued_per_cycle::7 1113373 0.75% 99.88% # Number of insts issued each cycle 425system.cpu.iq.issued_per_cycle::8 182213 0.12% 100.00% # Number of insts issued each cycle | 419system.cpu.iq.issued_per_cycle::0 56049781 37.81% 37.81% # Number of insts issued each cycle 420system.cpu.iq.issued_per_cycle::1 22646407 15.28% 53.09% # Number of insts issued each cycle 421system.cpu.iq.issued_per_cycle::2 24808421 16.74% 69.83% # Number of insts issued each cycle 422system.cpu.iq.issued_per_cycle::3 20317592 13.71% 83.54% # Number of insts issued each cycle 423system.cpu.iq.issued_per_cycle::4 12547069 8.47% 92.00% # Number of insts issued each cycle 424system.cpu.iq.issued_per_cycle::5 6521251 4.40% 96.40% # Number of insts issued each cycle 425system.cpu.iq.issued_per_cycle::6 4032352 2.72% 99.12% # Number of insts issued each cycle 426system.cpu.iq.issued_per_cycle::7 1118421 0.75% 99.88% # Number of insts issued each cycle 427system.cpu.iq.issued_per_cycle::8 181135 0.12% 100.00% # Number of insts issued each cycle |
| 426system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 427system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 428system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 428system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 429system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 430system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 429system.cpu.iq.issued_per_cycle::total 148225221 # Number of insts issued each cycle | 431system.cpu.iq.issued_per_cycle::total 148222429 # Number of insts issued each cycle |
| 430system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 432system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 431system.cpu.iq.fu_full::IntAlu 964965 38.34% 38.34% # attempts to use FU when none available 432system.cpu.iq.fu_full::IntMult 5593 0.22% 38.56% # attempts to use FU when none available 433system.cpu.iq.fu_full::IntDiv 0 0.00% 38.56% # attempts to use FU when none available 434system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.56% # attempts to use FU when none available 435system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.56% # attempts to use FU when none available 436system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.56% # attempts to use FU when none available 437system.cpu.iq.fu_full::FloatMult 0 0.00% 38.56% # attempts to use FU when none available 438system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.56% # attempts to use FU when none available 439system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.56% # attempts to use FU when none available 440system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.56% # attempts to use FU when none available 441system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.56% # attempts to use FU when none available 442system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.56% # attempts to use FU when none available 443system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.56% # attempts to use FU when none available 444system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.56% # attempts to use FU when none available 445system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.56% # attempts to use FU when none available 446system.cpu.iq.fu_full::SimdMult 0 0.00% 38.56% # attempts to use FU when none available 447system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.56% # attempts to use FU when none available 448system.cpu.iq.fu_full::SimdShift 0 0.00% 38.56% # attempts to use FU when none available 449system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.56% # attempts to use FU when none available 450system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.56% # attempts to use FU when none available 451system.cpu.iq.fu_full::SimdFloatAdd 99 0.00% 38.56% # attempts to use FU when none available 452system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.56% # attempts to use FU when none available 453system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.56% # attempts to use FU when none available 454system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.56% # attempts to use FU when none available 455system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.56% # attempts to use FU when none available 456system.cpu.iq.fu_full::SimdFloatMisc 49 0.00% 38.56% # attempts to use FU when none available 457system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.56% # attempts to use FU when none available 458system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.56% # attempts to use FU when none available 459system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.56% # attempts to use FU when none available 460system.cpu.iq.fu_full::MemRead 1170821 46.51% 85.08% # attempts to use FU when none available 461system.cpu.iq.fu_full::MemWrite 375623 14.92% 100.00% # attempts to use FU when none available | 433system.cpu.iq.fu_full::IntAlu 964061 38.35% 38.35% # attempts to use FU when none available 434system.cpu.iq.fu_full::IntMult 5595 0.22% 38.57% # attempts to use FU when none available 435system.cpu.iq.fu_full::IntDiv 0 0.00% 38.57% # attempts to use FU when none available 436system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.57% # attempts to use FU when none available 437system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.57% # attempts to use FU when none available 438system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.57% # attempts to use FU when none available 439system.cpu.iq.fu_full::FloatMult 0 0.00% 38.57% # attempts to use FU when none available 440system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.57% # attempts to use FU when none available 441system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.57% # attempts to use FU when none available 442system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.57% # attempts to use FU when none available 443system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.57% # attempts to use FU when none available 444system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.57% # attempts to use FU when none available 445system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.57% # attempts to use FU when none available 446system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.57% # attempts to use FU when none available 447system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.57% # attempts to use FU when none available 448system.cpu.iq.fu_full::SimdMult 0 0.00% 38.57% # attempts to use FU when none available 449system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.57% # attempts to use FU when none available 450system.cpu.iq.fu_full::SimdShift 0 0.00% 38.57% # attempts to use FU when none available 451system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.57% # attempts to use FU when none available 452system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.57% # attempts to use FU when none available 453system.cpu.iq.fu_full::SimdFloatAdd 96 0.00% 38.57% # attempts to use FU when none available 454system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.57% # attempts to use FU when none available 455system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.57% # attempts to use FU when none available 456system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.57% # attempts to use FU when none available 457system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.57% # attempts to use FU when none available 458system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.58% # attempts to use FU when none available 459system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.58% # attempts to use FU when none available 460system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.58% # attempts to use FU when none available 461system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.58% # attempts to use FU when none available 462system.cpu.iq.fu_full::MemRead 1168003 46.46% 85.04% # attempts to use FU when none available 463system.cpu.iq.fu_full::MemWrite 376162 14.96% 100.00% # attempts to use FU when none available |
| 462system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 463system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 464system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 464system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 465system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 466system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 465system.cpu.iq.FU_type_0::IntAlu 194894311 78.13% 78.13% # Type of FU issued 466system.cpu.iq.FU_type_0::IntMult 979316 0.39% 78.52% # Type of FU issued | 467system.cpu.iq.FU_type_0::IntAlu 194908316 78.12% 78.12% # Type of FU issued 468system.cpu.iq.FU_type_0::IntMult 978999 0.39% 78.52% # Type of FU issued |
| 467system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued 468system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued 469system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued 470system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.52% # Type of FU issued 471system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.52% # Type of FU issued 472system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.52% # Type of FU issued 473system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.52% # Type of FU issued 474system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.52% # Type of FU issued 475system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.52% # Type of FU issued 476system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.52% # Type of FU issued 477system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.52% # Type of FU issued 478system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.52% # Type of FU issued 479system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.52% # Type of FU issued 480system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.52% # Type of FU issued 481system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Type of FU issued 482system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued 483system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued 484system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued | 469system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued 470system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued 471system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued 472system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.52% # Type of FU issued 473system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.52% # Type of FU issued 474system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.52% # Type of FU issued 475system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.52% # Type of FU issued 476system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.52% # Type of FU issued 477system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.52% # Type of FU issued 478system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.52% # Type of FU issued 479system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.52% # Type of FU issued 480system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.52% # Type of FU issued 481system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.52% # Type of FU issued 482system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.52% # Type of FU issued 483system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Type of FU issued 484system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued 485system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued 486system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued |
| 485system.cpu.iq.FU_type_0::SimdFloatAdd 33075 0.01% 78.53% # Type of FU issued | 487system.cpu.iq.FU_type_0::SimdFloatAdd 33072 0.01% 78.53% # Type of FU issued |
| 486system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.53% # Type of FU issued | 488system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.53% # Type of FU issued |
| 487system.cpu.iq.FU_type_0::SimdFloatCmp 164356 0.07% 78.60% # Type of FU issued 488system.cpu.iq.FU_type_0::SimdFloatCvt 254647 0.10% 78.70% # Type of FU issued 489system.cpu.iq.FU_type_0::SimdFloatDiv 76432 0.03% 78.73% # Type of FU issued 490system.cpu.iq.FU_type_0::SimdFloatMisc 465549 0.19% 78.92% # Type of FU issued 491system.cpu.iq.FU_type_0::SimdFloatMult 206388 0.08% 79.00% # Type of FU issued 492system.cpu.iq.FU_type_0::SimdFloatMultAcc 71859 0.03% 79.03% # Type of FU issued | 489system.cpu.iq.FU_type_0::SimdFloatCmp 164299 0.07% 78.60% # Type of FU issued 490system.cpu.iq.FU_type_0::SimdFloatCvt 255151 0.10% 78.70% # Type of FU issued 491system.cpu.iq.FU_type_0::SimdFloatDiv 76428 0.03% 78.73% # Type of FU issued 492system.cpu.iq.FU_type_0::SimdFloatMisc 465968 0.19% 78.92% # Type of FU issued 493system.cpu.iq.FU_type_0::SimdFloatMult 206368 0.08% 79.00% # Type of FU issued 494system.cpu.iq.FU_type_0::SimdFloatMultAcc 71868 0.03% 79.03% # Type of FU issued |
| 493system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued | 495system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued |
| 494system.cpu.iq.FU_type_0::MemRead 38358541 15.38% 94.41% # Type of FU issued 495system.cpu.iq.FU_type_0::MemWrite 13955444 5.59% 100.00% # Type of FU issued | 496system.cpu.iq.FU_type_0::MemRead 38371220 15.38% 94.41% # Type of FU issued 497system.cpu.iq.FU_type_0::MemWrite 13950685 5.59% 100.00% # Type of FU issued |
| 496system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 497system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 498system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 499system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 498system.cpu.iq.FU_type_0::total 249460239 # Type of FU issued 499system.cpu.iq.rate 1.680732 # Inst issue rate 500system.cpu.iq.fu_busy_cnt 2517150 # FU busy when requested 501system.cpu.iq.fu_busy_rate 0.010090 # FU busy rate (busy events/executed inst) 502system.cpu.iq.int_inst_queue_reads 646712991 # Number of integer instruction queue reads 503system.cpu.iq.int_inst_queue_writes 466571759 # Number of integer instruction queue writes 504system.cpu.iq.int_inst_queue_wakeup_accesses 237891174 # Number of integer instruction queue wakeup accesses 505system.cpu.iq.fp_inst_queue_reads 3737382 # Number of floating instruction queue reads 506system.cpu.iq.fp_inst_queue_writes 2188885 # Number of floating instruction queue writes 507system.cpu.iq.fp_inst_queue_wakeup_accesses 1841279 # Number of floating instruction queue wakeup accesses 508system.cpu.iq.int_alu_accesses 250102160 # Number of integer alu accesses 509system.cpu.iq.fp_alu_accesses 1875229 # Number of floating point alu accesses 510system.cpu.iew.lsq.thread0.forwLoads 2007089 # Number of loads that had data forwarded from stores | 500system.cpu.iq.FU_type_0::total 249482695 # Type of FU issued 501system.cpu.iq.rate 1.680956 # Inst issue rate 502system.cpu.iq.fu_busy_cnt 2513965 # FU busy when requested 503system.cpu.iq.fu_busy_rate 0.010077 # FU busy rate (busy events/executed inst) 504system.cpu.iq.int_inst_queue_reads 646755779 # Number of integer instruction queue reads 505system.cpu.iq.int_inst_queue_writes 466684925 # Number of integer instruction queue writes 506system.cpu.iq.int_inst_queue_wakeup_accesses 237894917 # Number of integer instruction queue wakeup accesses 507system.cpu.iq.fp_inst_queue_reads 3739531 # Number of floating instruction queue reads 508system.cpu.iq.fp_inst_queue_writes 2191886 # Number of floating instruction queue writes 509system.cpu.iq.fp_inst_queue_wakeup_accesses 1842592 # Number of floating instruction queue wakeup accesses 510system.cpu.iq.int_alu_accesses 250120414 # Number of integer alu accesses 511system.cpu.iq.fp_alu_accesses 1876246 # Number of floating point alu accesses 512system.cpu.iew.lsq.thread0.forwLoads 2009109 # Number of loads that had data forwarded from stores |
| 511system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 513system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 512system.cpu.iew.lsq.thread0.squashedLoads 13155956 # Number of loads squashed 513system.cpu.iew.lsq.thread0.ignoredResponses 11631 # Number of memory responses ignored because the instruction is squashed 514system.cpu.iew.lsq.thread0.memOrderViolation 18977 # Number of memory ordering violations 515system.cpu.iew.lsq.thread0.squashedStores 3784660 # Number of stores squashed | 514system.cpu.iew.lsq.thread0.squashedLoads 13163022 # Number of loads squashed 515system.cpu.iew.lsq.thread0.ignoredResponses 11141 # Number of memory responses ignored because the instruction is squashed 516system.cpu.iew.lsq.thread0.memOrderViolation 18733 # Number of memory ordering violations 517system.cpu.iew.lsq.thread0.squashedStores 3776675 # Number of stores squashed |
| 516system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 517system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 518system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 519system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 518system.cpu.iew.lsq.thread0.rescheduledLoads 11 # Number of loads that were rescheduled | 520system.cpu.iew.lsq.thread0.rescheduledLoads 14 # Number of loads that were rescheduled |
| 519system.cpu.iew.lsq.thread0.cacheBlocked 100 # Number of times an access to memory failed due to the cache being blocked 520system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 521system.cpu.iew.lsq.thread0.cacheBlocked 100 # Number of times an access to memory failed due to the cache being blocked 522system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 521system.cpu.iew.iewSquashCycles 20830243 # Number of cycles IEW is squashing 522system.cpu.iew.iewBlockCycles 18508 # Number of cycles IEW is blocking 523system.cpu.iew.iewUnblockCycles 911 # Number of cycles IEW is unblocking 524system.cpu.iew.iewDispatchedInsts 329253924 # Number of instructions dispatched to IQ 525system.cpu.iew.iewDispSquashedInsts 785902 # Number of squashed instructions skipped by dispatch 526system.cpu.iew.iewDispLoadInsts 43005440 # Number of dispatched load instructions 527system.cpu.iew.iewDispStoreInsts 16429294 # Number of dispatched store instructions 528system.cpu.iew.iewDispNonSpecInsts 24682 # Number of dispatched non-speculative instructions 529system.cpu.iew.iewIQFullEvents 206 # Number of times the IQ has become full, causing a stall 530system.cpu.iew.iewLSQFullEvents 274 # Number of times the LSQ has become full, causing a stall 531system.cpu.iew.memOrderViolationEvents 18977 # Number of memory order violations 532system.cpu.iew.predictedTakenIncorrect 3891616 # Number of branches that were predicted taken incorrectly 533system.cpu.iew.predictedNotTakenIncorrect 3758665 # Number of branches that were predicted not taken incorrectly 534system.cpu.iew.branchMispredicts 7650281 # Number of branch mispredicts detected at execute 535system.cpu.iew.iewExecutedInsts 242960344 # Number of executed instructions 536system.cpu.iew.iewExecLoadInsts 36855491 # Number of load instructions executed 537system.cpu.iew.iewExecSquashedInsts 6499895 # Number of squashed instructions skipped in execute | 523system.cpu.iew.iewSquashCycles 20836467 # Number of cycles IEW is squashing 524system.cpu.iew.iewBlockCycles 18579 # Number of cycles IEW is blocking 525system.cpu.iew.iewUnblockCycles 909 # Number of cycles IEW is unblocking 526system.cpu.iew.iewDispatchedInsts 329310121 # Number of instructions dispatched to IQ 527system.cpu.iew.iewDispSquashedInsts 781513 # Number of squashed instructions skipped by dispatch 528system.cpu.iew.iewDispLoadInsts 43012506 # Number of dispatched load instructions 529system.cpu.iew.iewDispStoreInsts 16421309 # Number of dispatched store instructions 530system.cpu.iew.iewDispNonSpecInsts 24765 # Number of dispatched non-speculative instructions 531system.cpu.iew.iewIQFullEvents 190 # Number of times the IQ has become full, causing a stall 532system.cpu.iew.iewLSQFullEvents 272 # Number of times the LSQ has become full, causing a stall 533system.cpu.iew.memOrderViolationEvents 18733 # Number of memory order violations 534system.cpu.iew.predictedTakenIncorrect 3888765 # Number of branches that were predicted taken incorrectly 535system.cpu.iew.predictedNotTakenIncorrect 3761308 # Number of branches that were predicted not taken incorrectly 536system.cpu.iew.branchMispredicts 7650073 # Number of branch mispredicts detected at execute 537system.cpu.iew.iewExecutedInsts 242977304 # Number of executed instructions 538system.cpu.iew.iewExecLoadInsts 36862847 # Number of load instructions executed 539system.cpu.iew.iewExecSquashedInsts 6505391 # Number of squashed instructions skipped in execute |
| 538system.cpu.iew.exec_swp 0 # number of swp insts executed | 540system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 539system.cpu.iew.exec_nop 17022 # number of nop insts executed 540system.cpu.iew.exec_refs 50506525 # number of memory reference insts executed 541system.cpu.iew.exec_branches 53424421 # Number of branches executed 542system.cpu.iew.exec_stores 13651034 # Number of stores executed 543system.cpu.iew.exec_rate 1.636939 # Inst execution rate 544system.cpu.iew.wb_sent 240787816 # cumulative count of insts sent to commit 545system.cpu.iew.wb_count 239732453 # cumulative count of insts written-back 546system.cpu.iew.wb_producers 148473522 # num instructions producing a value 547system.cpu.iew.wb_consumers 267271209 # num instructions consuming a value | 541system.cpu.iew.exec_nop 17004 # number of nop insts executed 542system.cpu.iew.exec_refs 50511963 # number of memory reference insts executed 543system.cpu.iew.exec_branches 53432662 # Number of branches executed 544system.cpu.iew.exec_stores 13649116 # Number of stores executed 545system.cpu.iew.exec_rate 1.637124 # Inst execution rate 546system.cpu.iew.wb_sent 240796428 # cumulative count of insts sent to commit 547system.cpu.iew.wb_count 239737509 # cumulative count of insts written-back 548system.cpu.iew.wb_producers 148472463 # num instructions producing a value 549system.cpu.iew.wb_consumers 267293668 # num instructions consuming a value |
| 548system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 550system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 549system.cpu.iew.wb_rate 1.615192 # insts written-back per cycle 550system.cpu.iew.wb_fanout 0.555516 # average fanout of values written-back | 551system.cpu.iew.wb_rate 1.615295 # insts written-back per cycle 552system.cpu.iew.wb_fanout 0.555466 # average fanout of values written-back |
| 551system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 553system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 552system.cpu.commit.commitSquashedInsts 140583033 # The number of squashed insts skipped by commit | 554system.cpu.commit.commitSquashedInsts 140639228 # The number of squashed insts skipped by commit |
| 553system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards | 555system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards |
| 554system.cpu.commit.branchMispredicts 6126865 # The number of times a branch was mispredicted 555system.cpu.commit.committed_per_cycle::samples 127394978 # Number of insts commited each cycle 556system.cpu.commit.committed_per_cycle::mean 1.480992 # Number of insts commited each cycle 557system.cpu.commit.committed_per_cycle::stdev 2.186196 # Number of insts commited each cycle | 556system.cpu.commit.branchMispredicts 6126680 # The number of times a branch was mispredicted 557system.cpu.commit.committed_per_cycle::samples 127385962 # Number of insts commited each cycle 558system.cpu.commit.committed_per_cycle::mean 1.481096 # Number of insts commited each cycle 559system.cpu.commit.committed_per_cycle::stdev 2.186061 # Number of insts commited each cycle |
| 558system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 560system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 559system.cpu.commit.committed_per_cycle::0 57713917 45.30% 45.30% # Number of insts commited each cycle 560system.cpu.commit.committed_per_cycle::1 31674198 24.86% 70.17% # Number of insts commited each cycle 561system.cpu.commit.committed_per_cycle::2 13788488 10.82% 80.99% # Number of insts commited each cycle 562system.cpu.commit.committed_per_cycle::3 7625423 5.99% 86.98% # Number of insts commited each cycle 563system.cpu.commit.committed_per_cycle::4 4380329 3.44% 90.41% # Number of insts commited each cycle 564system.cpu.commit.committed_per_cycle::5 1321262 1.04% 91.45% # Number of insts commited each cycle 565system.cpu.commit.committed_per_cycle::6 1701589 1.34% 92.79% # Number of insts commited each cycle 566system.cpu.commit.committed_per_cycle::7 1311888 1.03% 93.82% # Number of insts commited each cycle 567system.cpu.commit.committed_per_cycle::8 7877884 6.18% 100.00% # Number of insts commited each cycle | 561system.cpu.commit.committed_per_cycle::0 57702305 45.30% 45.30% # Number of insts commited each cycle 562system.cpu.commit.committed_per_cycle::1 31675528 24.87% 70.16% # Number of insts commited each cycle 563system.cpu.commit.committed_per_cycle::2 13782422 10.82% 80.98% # Number of insts commited each cycle 564system.cpu.commit.committed_per_cycle::3 7634808 5.99% 86.98% # Number of insts commited each cycle 565system.cpu.commit.committed_per_cycle::4 4379316 3.44% 90.41% # Number of insts commited each cycle 566system.cpu.commit.committed_per_cycle::5 1319569 1.04% 91.45% # Number of insts commited each cycle 567system.cpu.commit.committed_per_cycle::6 1705598 1.34% 92.79% # Number of insts commited each cycle 568system.cpu.commit.committed_per_cycle::7 1313930 1.03% 93.82% # Number of insts commited each cycle 569system.cpu.commit.committed_per_cycle::8 7872486 6.18% 100.00% # Number of insts commited each cycle |
| 568system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 569system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 570system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 570system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 571system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 572system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 571system.cpu.commit.committed_per_cycle::total 127394978 # Number of insts commited each cycle | 573system.cpu.commit.committed_per_cycle::total 127385962 # Number of insts commited each cycle |
| 572system.cpu.commit.committedInsts 172317409 # Number of instructions committed 573system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed 574system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 575system.cpu.commit.refs 42494118 # Number of memory references committed 576system.cpu.commit.loads 29849484 # Number of loads committed 577system.cpu.commit.membars 22408 # Number of memory barriers committed 578system.cpu.commit.branches 40300311 # Number of branches committed 579system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. 580system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. 581system.cpu.commit.function_calls 1848934 # Number of function calls committed. | 574system.cpu.commit.committedInsts 172317409 # Number of instructions committed 575system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed 576system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 577system.cpu.commit.refs 42494118 # Number of memory references committed 578system.cpu.commit.loads 29849484 # Number of loads committed 579system.cpu.commit.membars 22408 # Number of memory barriers committed 580system.cpu.commit.branches 40300311 # Number of branches committed 581system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. 582system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. 583system.cpu.commit.function_calls 1848934 # Number of function calls committed. |
| 582system.cpu.commit.bw_lim_events 7877884 # number cycles where commit BW limit reached | 584system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 585system.cpu.commit.op_class_0::IntAlu 144055022 76.35% 76.35% # Class of committed instruction 586system.cpu.commit.op_class_0::IntMult 908940 0.48% 76.83% # Class of committed instruction 587system.cpu.commit.op_class_0::IntDiv 0 0.00% 76.83% # Class of committed instruction 588system.cpu.commit.op_class_0::FloatAdd 0 0.00% 76.83% # Class of committed instruction 589system.cpu.commit.op_class_0::FloatCmp 0 0.00% 76.83% # Class of committed instruction 590system.cpu.commit.op_class_0::FloatCvt 0 0.00% 76.83% # Class of committed instruction 591system.cpu.commit.op_class_0::FloatMult 0 0.00% 76.83% # Class of committed instruction 592system.cpu.commit.op_class_0::FloatDiv 0 0.00% 76.83% # Class of committed instruction 593system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 76.83% # Class of committed instruction 594system.cpu.commit.op_class_0::SimdAdd 0 0.00% 76.83% # Class of committed instruction 595system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 76.83% # Class of committed instruction 596system.cpu.commit.op_class_0::SimdAlu 0 0.00% 76.83% # Class of committed instruction 597system.cpu.commit.op_class_0::SimdCmp 0 0.00% 76.83% # Class of committed instruction 598system.cpu.commit.op_class_0::SimdCvt 0 0.00% 76.83% # Class of committed instruction 599system.cpu.commit.op_class_0::SimdMisc 0 0.00% 76.83% # Class of committed instruction 600system.cpu.commit.op_class_0::SimdMult 0 0.00% 76.83% # Class of committed instruction 601system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 76.83% # Class of committed instruction 602system.cpu.commit.op_class_0::SimdShift 0 0.00% 76.83% # Class of committed instruction 603system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 76.83% # Class of committed instruction 604system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 76.83% # Class of committed instruction 605system.cpu.commit.op_class_0::SimdFloatAdd 32754 0.02% 76.85% # Class of committed instruction 606system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 76.85% # Class of committed instruction 607system.cpu.commit.op_class_0::SimdFloatCmp 154829 0.08% 76.93% # Class of committed instruction 608system.cpu.commit.op_class_0::SimdFloatCvt 238880 0.13% 77.06% # Class of committed instruction 609system.cpu.commit.op_class_0::SimdFloatDiv 76016 0.04% 77.10% # Class of committed instruction 610system.cpu.commit.op_class_0::SimdFloatMisc 437591 0.23% 77.33% # Class of committed instruction 611system.cpu.commit.op_class_0::SimdFloatMult 200806 0.11% 77.44% # Class of committed instruction 612system.cpu.commit.op_class_0::SimdFloatMultAcc 71617 0.04% 77.48% # Class of committed instruction 613system.cpu.commit.op_class_0::SimdFloatSqrt 318 0.00% 77.48% # Class of committed instruction 614system.cpu.commit.op_class_0::MemRead 29849484 15.82% 93.30% # Class of committed instruction 615system.cpu.commit.op_class_0::MemWrite 12644634 6.70% 100.00% # Class of committed instruction 616system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 617system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 618system.cpu.commit.op_class_0::total 188670891 # Class of committed instruction 619system.cpu.commit.bw_lim_events 7872486 # number cycles where commit BW limit reached |
| 583system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 620system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 584system.cpu.rob.rob_reads 448765817 # The number of ROB reads 585system.cpu.rob.rob_writes 679447245 # The number of ROB writes 586system.cpu.timesIdled 2831 # Number of times that the entire CPU went into an idle state and unscheduled itself 587system.cpu.idleCycles 198321 # Total number of cycles that the CPU has spent unscheduled due to idling | 621system.cpu.rob.rob_reads 448818394 # The number of ROB reads 622system.cpu.rob.rob_writes 679565858 # The number of ROB writes 623system.cpu.timesIdled 2789 # Number of times that the entire CPU went into an idle state and unscheduled itself 624system.cpu.idleCycles 194714 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 588system.cpu.committedInsts 172303021 # Number of Instructions Simulated 589system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated 590system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated | 625system.cpu.committedInsts 172303021 # Number of Instructions Simulated 626system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated 627system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated |
| 591system.cpu.cpi 0.861410 # CPI: Cycles Per Instruction 592system.cpu.cpi_total 0.861410 # CPI: Total CPI of All Threads 593system.cpu.ipc 1.160887 # IPC: Instructions Per Cycle 594system.cpu.ipc_total 1.160887 # IPC: Total IPC of All Threads 595system.cpu.int_regfile_reads 1079439987 # number of integer regfile reads 596system.cpu.int_regfile_writes 384873432 # number of integer regfile writes 597system.cpu.fp_regfile_reads 2912671 # number of floating regfile reads 598system.cpu.fp_regfile_writes 2497165 # number of floating regfile writes 599system.cpu.misc_regfile_reads 64868455 # number of misc regfile reads | 628system.cpu.cpi 0.861373 # CPI: Cycles Per Instruction 629system.cpu.cpi_total 0.861373 # CPI: Total CPI of All Threads 630system.cpu.ipc 1.160937 # IPC: Instructions Per Cycle 631system.cpu.ipc_total 1.160937 # IPC: Total IPC of All Threads 632system.cpu.int_regfile_reads 1079497274 # number of integer regfile reads 633system.cpu.int_regfile_writes 384888160 # number of integer regfile writes 634system.cpu.fp_regfile_reads 2912753 # number of floating regfile reads 635system.cpu.fp_regfile_writes 2499155 # number of floating regfile writes 636system.cpu.misc_regfile_reads 64874393 # number of misc regfile reads |
| 600system.cpu.misc_regfile_writes 820036 # number of misc regfile writes | 637system.cpu.misc_regfile_writes 820036 # number of misc regfile writes |
| 601system.cpu.toL2Bus.throughput 5152821 # Throughput (bytes/s) 602system.cpu.toL2Bus.trans_dist::ReadReq 4879 # Transaction distribution 603system.cpu.toL2Bus.trans_dist::ReadResp 4878 # Transaction distribution 604system.cpu.toL2Bus.trans_dist::Writeback 18 # Transaction distribution 605system.cpu.toL2Bus.trans_dist::ReadExReq 1079 # Transaction distribution 606system.cpu.toL2Bus.trans_dist::ReadExResp 1079 # Transaction distribution 607system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8203 # Packet count per connected master and slave (bytes) 608system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3730 # Packet count per connected master and slave (bytes) 609system.cpu.toL2Bus.pkt_count::total 11933 # Packet count per connected master and slave (bytes) 610system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 262464 # Cumulative packet size per connected master and slave (bytes) 611system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119936 # Cumulative packet size per connected master and slave (bytes) 612system.cpu.toL2Bus.tot_pkt_size::total 382400 # Cumulative packet size per connected master and slave (bytes) 613system.cpu.toL2Bus.data_through_bus 382400 # Total data (bytes) | 638system.cpu.toL2Bus.throughput 5170292 # Throughput (bytes/s) 639system.cpu.toL2Bus.trans_dist::ReadReq 4896 # Transaction distribution 640system.cpu.toL2Bus.trans_dist::ReadResp 4895 # Transaction distribution 641system.cpu.toL2Bus.trans_dist::Writeback 19 # Transaction distribution 642system.cpu.toL2Bus.trans_dist::ReadExReq 1081 # Transaction distribution 643system.cpu.toL2Bus.trans_dist::ReadExResp 1081 # Transaction distribution 644system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8239 # Packet count per connected master and slave (bytes) 645system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3733 # Packet count per connected master and slave (bytes) 646system.cpu.toL2Bus.pkt_count::total 11972 # Packet count per connected master and slave (bytes) 647system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 263616 # Cumulative packet size per connected master and slave (bytes) 648system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120064 # Cumulative packet size per connected master and slave (bytes) 649system.cpu.toL2Bus.tot_pkt_size::total 383680 # Cumulative packet size per connected master and slave (bytes) 650system.cpu.toL2Bus.data_through_bus 383680 # Total data (bytes) |
| 614system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) | 651system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 615system.cpu.toL2Bus.reqLayer0.occupancy 3006000 # Layer occupancy (ticks) | 652system.cpu.toL2Bus.reqLayer0.occupancy 3017000 # Layer occupancy (ticks) |
| 616system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 653system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 617system.cpu.toL2Bus.respLayer0.occupancy 6511747 # Layer occupancy (ticks) | 654system.cpu.toL2Bus.respLayer0.occupancy 6548996 # Layer occupancy (ticks) |
| 618system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 655system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 619system.cpu.toL2Bus.respLayer1.occupancy 3051239 # Layer occupancy (ticks) | 656system.cpu.toL2Bus.respLayer1.occupancy 3099487 # Layer occupancy (ticks) |
| 620system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 657system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 621system.cpu.icache.tags.replacements 2374 # number of replacements 622system.cpu.icache.tags.tagsinuse 1347.666302 # Cycle average of tags in use 623system.cpu.icache.tags.total_refs 36843383 # Total number of references to valid blocks. 624system.cpu.icache.tags.sampled_refs 4101 # Sample count of references to valid blocks. 625system.cpu.icache.tags.avg_refs 8983.999756 # Average number of references to valid blocks. | 658system.cpu.icache.tags.replacements 2388 # number of replacements 659system.cpu.icache.tags.tagsinuse 1346.753946 # Cycle average of tags in use 660system.cpu.icache.tags.total_refs 36845676 # Total number of references to valid blocks. 661system.cpu.icache.tags.sampled_refs 4119 # Sample count of references to valid blocks. 662system.cpu.icache.tags.avg_refs 8945.296431 # Average number of references to valid blocks. |
| 626system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 663system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 627system.cpu.icache.tags.occ_blocks::cpu.inst 1347.666302 # Average occupied blocks per requestor 628system.cpu.icache.tags.occ_percent::cpu.inst 0.658040 # Average percentage of cache occupancy 629system.cpu.icache.tags.occ_percent::total 0.658040 # Average percentage of cache occupancy 630system.cpu.icache.tags.occ_task_id_blocks::1024 1727 # Occupied blocks per task id 631system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id | 664system.cpu.icache.tags.occ_blocks::cpu.inst 1346.753946 # Average occupied blocks per requestor 665system.cpu.icache.tags.occ_percent::cpu.inst 0.657595 # Average percentage of cache occupancy 666system.cpu.icache.tags.occ_percent::total 0.657595 # Average percentage of cache occupancy 667system.cpu.icache.tags.occ_task_id_blocks::1024 1731 # Occupied blocks per task id 668system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id |
| 632system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id | 669system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id |
| 633system.cpu.icache.tags.age_task_id_blocks_1024::2 534 # Occupied blocks per task id 634system.cpu.icache.tags.age_task_id_blocks_1024::3 28 # Occupied blocks per task id 635system.cpu.icache.tags.age_task_id_blocks_1024::4 1040 # Occupied blocks per task id 636system.cpu.icache.tags.occ_task_id_percent::1024 0.843262 # Percentage of cache occupancy per task id 637system.cpu.icache.tags.tag_accesses 73701491 # Number of tag accesses 638system.cpu.icache.tags.data_accesses 73701491 # Number of data accesses 639system.cpu.icache.ReadReq_hits::cpu.inst 36843383 # number of ReadReq hits 640system.cpu.icache.ReadReq_hits::total 36843383 # number of ReadReq hits 641system.cpu.icache.demand_hits::cpu.inst 36843383 # number of demand (read+write) hits 642system.cpu.icache.demand_hits::total 36843383 # number of demand (read+write) hits 643system.cpu.icache.overall_hits::cpu.inst 36843383 # number of overall hits 644system.cpu.icache.overall_hits::total 36843383 # number of overall hits 645system.cpu.icache.ReadReq_misses::cpu.inst 5312 # number of ReadReq misses 646system.cpu.icache.ReadReq_misses::total 5312 # number of ReadReq misses 647system.cpu.icache.demand_misses::cpu.inst 5312 # number of demand (read+write) misses 648system.cpu.icache.demand_misses::total 5312 # number of demand (read+write) misses 649system.cpu.icache.overall_misses::cpu.inst 5312 # number of overall misses 650system.cpu.icache.overall_misses::total 5312 # number of overall misses 651system.cpu.icache.ReadReq_miss_latency::cpu.inst 224724996 # number of ReadReq miss cycles 652system.cpu.icache.ReadReq_miss_latency::total 224724996 # number of ReadReq miss cycles 653system.cpu.icache.demand_miss_latency::cpu.inst 224724996 # number of demand (read+write) miss cycles 654system.cpu.icache.demand_miss_latency::total 224724996 # number of demand (read+write) miss cycles 655system.cpu.icache.overall_miss_latency::cpu.inst 224724996 # number of overall miss cycles 656system.cpu.icache.overall_miss_latency::total 224724996 # number of overall miss cycles 657system.cpu.icache.ReadReq_accesses::cpu.inst 36848695 # number of ReadReq accesses(hits+misses) 658system.cpu.icache.ReadReq_accesses::total 36848695 # number of ReadReq accesses(hits+misses) 659system.cpu.icache.demand_accesses::cpu.inst 36848695 # number of demand (read+write) accesses 660system.cpu.icache.demand_accesses::total 36848695 # number of demand (read+write) accesses 661system.cpu.icache.overall_accesses::cpu.inst 36848695 # number of overall (read+write) accesses 662system.cpu.icache.overall_accesses::total 36848695 # number of overall (read+write) accesses 663system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000144 # miss rate for ReadReq accesses 664system.cpu.icache.ReadReq_miss_rate::total 0.000144 # miss rate for ReadReq accesses 665system.cpu.icache.demand_miss_rate::cpu.inst 0.000144 # miss rate for demand accesses 666system.cpu.icache.demand_miss_rate::total 0.000144 # miss rate for demand accesses 667system.cpu.icache.overall_miss_rate::cpu.inst 0.000144 # miss rate for overall accesses 668system.cpu.icache.overall_miss_rate::total 0.000144 # miss rate for overall accesses 669system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42305.157380 # average ReadReq miss latency 670system.cpu.icache.ReadReq_avg_miss_latency::total 42305.157380 # average ReadReq miss latency 671system.cpu.icache.demand_avg_miss_latency::cpu.inst 42305.157380 # average overall miss latency 672system.cpu.icache.demand_avg_miss_latency::total 42305.157380 # average overall miss latency 673system.cpu.icache.overall_avg_miss_latency::cpu.inst 42305.157380 # average overall miss latency 674system.cpu.icache.overall_avg_miss_latency::total 42305.157380 # average overall miss latency 675system.cpu.icache.blocked_cycles::no_mshrs 1646 # number of cycles access was blocked | 670system.cpu.icache.tags.age_task_id_blocks_1024::2 541 # Occupied blocks per task id 671system.cpu.icache.tags.age_task_id_blocks_1024::3 30 # Occupied blocks per task id 672system.cpu.icache.tags.age_task_id_blocks_1024::4 1037 # Occupied blocks per task id 673system.cpu.icache.tags.occ_task_id_percent::1024 0.845215 # Percentage of cache occupancy per task id 674system.cpu.icache.tags.tag_accesses 73706251 # Number of tag accesses 675system.cpu.icache.tags.data_accesses 73706251 # Number of data accesses 676system.cpu.icache.ReadReq_hits::cpu.inst 36845676 # number of ReadReq hits 677system.cpu.icache.ReadReq_hits::total 36845676 # number of ReadReq hits 678system.cpu.icache.demand_hits::cpu.inst 36845676 # number of demand (read+write) hits 679system.cpu.icache.demand_hits::total 36845676 # number of demand (read+write) hits 680system.cpu.icache.overall_hits::cpu.inst 36845676 # number of overall hits 681system.cpu.icache.overall_hits::total 36845676 # number of overall hits 682system.cpu.icache.ReadReq_misses::cpu.inst 5390 # number of ReadReq misses 683system.cpu.icache.ReadReq_misses::total 5390 # number of ReadReq misses 684system.cpu.icache.demand_misses::cpu.inst 5390 # number of demand (read+write) misses 685system.cpu.icache.demand_misses::total 5390 # number of demand (read+write) misses 686system.cpu.icache.overall_misses::cpu.inst 5390 # number of overall misses 687system.cpu.icache.overall_misses::total 5390 # number of overall misses 688system.cpu.icache.ReadReq_miss_latency::cpu.inst 228751995 # number of ReadReq miss cycles 689system.cpu.icache.ReadReq_miss_latency::total 228751995 # number of ReadReq miss cycles 690system.cpu.icache.demand_miss_latency::cpu.inst 228751995 # number of demand (read+write) miss cycles 691system.cpu.icache.demand_miss_latency::total 228751995 # number of demand (read+write) miss cycles 692system.cpu.icache.overall_miss_latency::cpu.inst 228751995 # number of overall miss cycles 693system.cpu.icache.overall_miss_latency::total 228751995 # number of overall miss cycles 694system.cpu.icache.ReadReq_accesses::cpu.inst 36851066 # number of ReadReq accesses(hits+misses) 695system.cpu.icache.ReadReq_accesses::total 36851066 # number of ReadReq accesses(hits+misses) 696system.cpu.icache.demand_accesses::cpu.inst 36851066 # number of demand (read+write) accesses 697system.cpu.icache.demand_accesses::total 36851066 # number of demand (read+write) accesses 698system.cpu.icache.overall_accesses::cpu.inst 36851066 # number of overall (read+write) accesses 699system.cpu.icache.overall_accesses::total 36851066 # number of overall (read+write) accesses 700system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000146 # miss rate for ReadReq accesses 701system.cpu.icache.ReadReq_miss_rate::total 0.000146 # miss rate for ReadReq accesses 702system.cpu.icache.demand_miss_rate::cpu.inst 0.000146 # miss rate for demand accesses 703system.cpu.icache.demand_miss_rate::total 0.000146 # miss rate for demand accesses 704system.cpu.icache.overall_miss_rate::cpu.inst 0.000146 # miss rate for overall accesses 705system.cpu.icache.overall_miss_rate::total 0.000146 # miss rate for overall accesses 706system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42440.073284 # average ReadReq miss latency 707system.cpu.icache.ReadReq_avg_miss_latency::total 42440.073284 # average ReadReq miss latency 708system.cpu.icache.demand_avg_miss_latency::cpu.inst 42440.073284 # average overall miss latency 709system.cpu.icache.demand_avg_miss_latency::total 42440.073284 # average overall miss latency 710system.cpu.icache.overall_avg_miss_latency::cpu.inst 42440.073284 # average overall miss latency 711system.cpu.icache.overall_avg_miss_latency::total 42440.073284 # average overall miss latency 712system.cpu.icache.blocked_cycles::no_mshrs 1596 # number of cycles access was blocked |
| 676system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 677system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked 678system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 713system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 714system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked 715system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 679system.cpu.icache.avg_blocked_cycles::no_mshrs 86.631579 # average number of cycles each access was blocked | 716system.cpu.icache.avg_blocked_cycles::no_mshrs 84 # average number of cycles each access was blocked |
| 680system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 681system.cpu.icache.fast_writes 0 # number of fast writes performed 682system.cpu.icache.cache_copies 0 # number of cache copies performed | 717system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 718system.cpu.icache.fast_writes 0 # number of fast writes performed 719system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 683system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1210 # number of ReadReq MSHR hits 684system.cpu.icache.ReadReq_mshr_hits::total 1210 # number of ReadReq MSHR hits 685system.cpu.icache.demand_mshr_hits::cpu.inst 1210 # number of demand (read+write) MSHR hits 686system.cpu.icache.demand_mshr_hits::total 1210 # number of demand (read+write) MSHR hits 687system.cpu.icache.overall_mshr_hits::cpu.inst 1210 # number of overall MSHR hits 688system.cpu.icache.overall_mshr_hits::total 1210 # number of overall MSHR hits 689system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4102 # number of ReadReq MSHR misses 690system.cpu.icache.ReadReq_mshr_misses::total 4102 # number of ReadReq MSHR misses 691system.cpu.icache.demand_mshr_misses::cpu.inst 4102 # number of demand (read+write) MSHR misses 692system.cpu.icache.demand_mshr_misses::total 4102 # number of demand (read+write) MSHR misses 693system.cpu.icache.overall_mshr_misses::cpu.inst 4102 # number of overall MSHR misses 694system.cpu.icache.overall_mshr_misses::total 4102 # number of overall MSHR misses 695system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 167739253 # number of ReadReq MSHR miss cycles 696system.cpu.icache.ReadReq_mshr_miss_latency::total 167739253 # number of ReadReq MSHR miss cycles 697system.cpu.icache.demand_mshr_miss_latency::cpu.inst 167739253 # number of demand (read+write) MSHR miss cycles 698system.cpu.icache.demand_mshr_miss_latency::total 167739253 # number of demand (read+write) MSHR miss cycles 699system.cpu.icache.overall_mshr_miss_latency::cpu.inst 167739253 # number of overall MSHR miss cycles 700system.cpu.icache.overall_mshr_miss_latency::total 167739253 # number of overall MSHR miss cycles 701system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for ReadReq accesses 702system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000111 # mshr miss rate for ReadReq accesses 703system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for demand accesses 704system.cpu.icache.demand_mshr_miss_rate::total 0.000111 # mshr miss rate for demand accesses 705system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for overall accesses 706system.cpu.icache.overall_mshr_miss_rate::total 0.000111 # mshr miss rate for overall accesses 707system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40892.065578 # average ReadReq mshr miss latency 708system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40892.065578 # average ReadReq mshr miss latency 709system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40892.065578 # average overall mshr miss latency 710system.cpu.icache.demand_avg_mshr_miss_latency::total 40892.065578 # average overall mshr miss latency 711system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40892.065578 # average overall mshr miss latency 712system.cpu.icache.overall_avg_mshr_miss_latency::total 40892.065578 # average overall mshr miss latency | 720system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1270 # number of ReadReq MSHR hits 721system.cpu.icache.ReadReq_mshr_hits::total 1270 # number of ReadReq MSHR hits 722system.cpu.icache.demand_mshr_hits::cpu.inst 1270 # number of demand (read+write) MSHR hits 723system.cpu.icache.demand_mshr_hits::total 1270 # number of demand (read+write) MSHR hits 724system.cpu.icache.overall_mshr_hits::cpu.inst 1270 # number of overall MSHR hits 725system.cpu.icache.overall_mshr_hits::total 1270 # number of overall MSHR hits 726system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4120 # number of ReadReq MSHR misses 727system.cpu.icache.ReadReq_mshr_misses::total 4120 # number of ReadReq MSHR misses 728system.cpu.icache.demand_mshr_misses::cpu.inst 4120 # number of demand (read+write) MSHR misses 729system.cpu.icache.demand_mshr_misses::total 4120 # number of demand (read+write) MSHR misses 730system.cpu.icache.overall_mshr_misses::cpu.inst 4120 # number of overall MSHR misses 731system.cpu.icache.overall_mshr_misses::total 4120 # number of overall MSHR misses 732system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 167326504 # number of ReadReq MSHR miss cycles 733system.cpu.icache.ReadReq_mshr_miss_latency::total 167326504 # number of ReadReq MSHR miss cycles 734system.cpu.icache.demand_mshr_miss_latency::cpu.inst 167326504 # number of demand (read+write) MSHR miss cycles 735system.cpu.icache.demand_mshr_miss_latency::total 167326504 # number of demand (read+write) MSHR miss cycles 736system.cpu.icache.overall_mshr_miss_latency::cpu.inst 167326504 # number of overall MSHR miss cycles 737system.cpu.icache.overall_mshr_miss_latency::total 167326504 # number of overall MSHR miss cycles 738system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses 739system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses 740system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses 741system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses 742system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for overall accesses 743system.cpu.icache.overall_mshr_miss_rate::total 0.000112 # mshr miss rate for overall accesses 744system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40613.229126 # average ReadReq mshr miss latency 745system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40613.229126 # average ReadReq mshr miss latency 746system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40613.229126 # average overall mshr miss latency 747system.cpu.icache.demand_avg_mshr_miss_latency::total 40613.229126 # average overall mshr miss latency 748system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40613.229126 # average overall mshr miss latency 749system.cpu.icache.overall_avg_mshr_miss_latency::total 40613.229126 # average overall mshr miss latency |
| 713system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 714system.cpu.l2cache.tags.replacements 0 # number of replacements | 750system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 751system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 715system.cpu.l2cache.tags.tagsinuse 1968.326603 # Cycle average of tags in use 716system.cpu.l2cache.tags.total_refs 2138 # Total number of references to valid blocks. 717system.cpu.l2cache.tags.sampled_refs 2737 # Sample count of references to valid blocks. 718system.cpu.l2cache.tags.avg_refs 0.781147 # Average number of references to valid blocks. | 752system.cpu.l2cache.tags.tagsinuse 1966.490721 # Cycle average of tags in use 753system.cpu.l2cache.tags.total_refs 2149 # Total number of references to valid blocks. 754system.cpu.l2cache.tags.sampled_refs 2739 # Sample count of references to valid blocks. 755system.cpu.l2cache.tags.avg_refs 0.784593 # Average number of references to valid blocks. |
| 719system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 756system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 720system.cpu.l2cache.tags.occ_blocks::writebacks 4.994032 # Average occupied blocks per requestor 721system.cpu.l2cache.tags.occ_blocks::cpu.inst 1425.493487 # Average occupied blocks per requestor 722system.cpu.l2cache.tags.occ_blocks::cpu.data 537.839084 # Average occupied blocks per requestor 723system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy 724system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043503 # Average percentage of cache occupancy | 757system.cpu.l2cache.tags.occ_blocks::writebacks 4.023907 # Average occupied blocks per requestor 758system.cpu.l2cache.tags.occ_blocks::cpu.inst 1424.627361 # Average occupied blocks per requestor 759system.cpu.l2cache.tags.occ_blocks::cpu.data 537.839452 # Average occupied blocks per requestor 760system.cpu.l2cache.tags.occ_percent::writebacks 0.000123 # Average percentage of cache occupancy 761system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043476 # Average percentage of cache occupancy |
| 725system.cpu.l2cache.tags.occ_percent::cpu.data 0.016414 # Average percentage of cache occupancy | 762system.cpu.l2cache.tags.occ_percent::cpu.data 0.016414 # Average percentage of cache occupancy |
| 726system.cpu.l2cache.tags.occ_percent::total 0.060069 # Average percentage of cache occupancy 727system.cpu.l2cache.tags.occ_task_id_blocks::1024 2737 # Occupied blocks per task id 728system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id | 763system.cpu.l2cache.tags.occ_percent::total 0.060013 # Average percentage of cache occupancy 764system.cpu.l2cache.tags.occ_task_id_blocks::1024 2739 # Occupied blocks per task id 765system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id |
| 729system.cpu.l2cache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id | 766system.cpu.l2cache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id |
| 730system.cpu.l2cache.tags.age_task_id_blocks_1024::2 602 # Occupied blocks per task id 731system.cpu.l2cache.tags.age_task_id_blocks_1024::3 28 # Occupied blocks per task id 732system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1971 # Occupied blocks per task id 733system.cpu.l2cache.tags.occ_task_id_percent::1024 0.083527 # Percentage of cache occupancy per task id 734system.cpu.l2cache.tags.tag_accesses 51624 # Number of tag accesses 735system.cpu.l2cache.tags.data_accesses 51624 # Number of data accesses 736system.cpu.l2cache.ReadReq_hits::cpu.inst 2050 # number of ReadReq hits | 767system.cpu.l2cache.tags.age_task_id_blocks_1024::2 607 # Occupied blocks per task id 768system.cpu.l2cache.tags.age_task_id_blocks_1024::3 29 # Occupied blocks per task id 769system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1969 # Occupied blocks per task id 770system.cpu.l2cache.tags.occ_task_id_percent::1024 0.083588 # Percentage of cache occupancy per task id 771system.cpu.l2cache.tags.tag_accesses 51788 # Number of tag accesses 772system.cpu.l2cache.tags.data_accesses 51788 # Number of data accesses 773system.cpu.l2cache.ReadReq_hits::cpu.inst 2061 # number of ReadReq hits |
| 737system.cpu.l2cache.ReadReq_hits::cpu.data 87 # number of ReadReq hits | 774system.cpu.l2cache.ReadReq_hits::cpu.data 87 # number of ReadReq hits |
| 738system.cpu.l2cache.ReadReq_hits::total 2137 # number of ReadReq hits 739system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits 740system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits 741system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits 742system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits 743system.cpu.l2cache.demand_hits::cpu.inst 2050 # number of demand (read+write) hits 744system.cpu.l2cache.demand_hits::cpu.data 95 # number of demand (read+write) hits 745system.cpu.l2cache.demand_hits::total 2145 # number of demand (read+write) hits 746system.cpu.l2cache.overall_hits::cpu.inst 2050 # number of overall hits 747system.cpu.l2cache.overall_hits::cpu.data 95 # number of overall hits 748system.cpu.l2cache.overall_hits::total 2145 # number of overall hits 749system.cpu.l2cache.ReadReq_misses::cpu.inst 2052 # number of ReadReq misses 750system.cpu.l2cache.ReadReq_misses::cpu.data 690 # number of ReadReq misses 751system.cpu.l2cache.ReadReq_misses::total 2742 # number of ReadReq misses | 775system.cpu.l2cache.ReadReq_hits::total 2148 # number of ReadReq hits 776system.cpu.l2cache.Writeback_hits::writebacks 19 # number of Writeback hits 777system.cpu.l2cache.Writeback_hits::total 19 # number of Writeback hits 778system.cpu.l2cache.ReadExReq_hits::cpu.data 10 # number of ReadExReq hits 779system.cpu.l2cache.ReadExReq_hits::total 10 # number of ReadExReq hits 780system.cpu.l2cache.demand_hits::cpu.inst 2061 # number of demand (read+write) hits 781system.cpu.l2cache.demand_hits::cpu.data 97 # number of demand (read+write) hits 782system.cpu.l2cache.demand_hits::total 2158 # number of demand (read+write) hits 783system.cpu.l2cache.overall_hits::cpu.inst 2061 # number of overall hits 784system.cpu.l2cache.overall_hits::cpu.data 97 # number of overall hits 785system.cpu.l2cache.overall_hits::total 2158 # number of overall hits 786system.cpu.l2cache.ReadReq_misses::cpu.inst 2059 # number of ReadReq misses 787system.cpu.l2cache.ReadReq_misses::cpu.data 689 # number of ReadReq misses 788system.cpu.l2cache.ReadReq_misses::total 2748 # number of ReadReq misses |
| 752system.cpu.l2cache.ReadExReq_misses::cpu.data 1071 # number of ReadExReq misses 753system.cpu.l2cache.ReadExReq_misses::total 1071 # number of ReadExReq misses | 789system.cpu.l2cache.ReadExReq_misses::cpu.data 1071 # number of ReadExReq misses 790system.cpu.l2cache.ReadExReq_misses::total 1071 # number of ReadExReq misses |
| 754system.cpu.l2cache.demand_misses::cpu.inst 2052 # number of demand (read+write) misses 755system.cpu.l2cache.demand_misses::cpu.data 1761 # number of demand (read+write) misses 756system.cpu.l2cache.demand_misses::total 3813 # number of demand (read+write) misses 757system.cpu.l2cache.overall_misses::cpu.inst 2052 # number of overall misses 758system.cpu.l2cache.overall_misses::cpu.data 1761 # number of overall misses 759system.cpu.l2cache.overall_misses::total 3813 # number of overall misses 760system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143127750 # number of ReadReq miss cycles 761system.cpu.l2cache.ReadReq_miss_latency::cpu.data 50855750 # number of ReadReq miss cycles 762system.cpu.l2cache.ReadReq_miss_latency::total 193983500 # number of ReadReq miss cycles 763system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 72887500 # number of ReadExReq miss cycles 764system.cpu.l2cache.ReadExReq_miss_latency::total 72887500 # number of ReadExReq miss cycles 765system.cpu.l2cache.demand_miss_latency::cpu.inst 143127750 # number of demand (read+write) miss cycles 766system.cpu.l2cache.demand_miss_latency::cpu.data 123743250 # number of demand (read+write) miss cycles 767system.cpu.l2cache.demand_miss_latency::total 266871000 # number of demand (read+write) miss cycles 768system.cpu.l2cache.overall_miss_latency::cpu.inst 143127750 # number of overall miss cycles 769system.cpu.l2cache.overall_miss_latency::cpu.data 123743250 # number of overall miss cycles 770system.cpu.l2cache.overall_miss_latency::total 266871000 # number of overall miss cycles 771system.cpu.l2cache.ReadReq_accesses::cpu.inst 4102 # number of ReadReq accesses(hits+misses) 772system.cpu.l2cache.ReadReq_accesses::cpu.data 777 # number of ReadReq accesses(hits+misses) 773system.cpu.l2cache.ReadReq_accesses::total 4879 # number of ReadReq accesses(hits+misses) 774system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) 775system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) 776system.cpu.l2cache.ReadExReq_accesses::cpu.data 1079 # number of ReadExReq accesses(hits+misses) 777system.cpu.l2cache.ReadExReq_accesses::total 1079 # number of ReadExReq accesses(hits+misses) 778system.cpu.l2cache.demand_accesses::cpu.inst 4102 # number of demand (read+write) accesses 779system.cpu.l2cache.demand_accesses::cpu.data 1856 # number of demand (read+write) accesses 780system.cpu.l2cache.demand_accesses::total 5958 # number of demand (read+write) accesses 781system.cpu.l2cache.overall_accesses::cpu.inst 4102 # number of overall (read+write) accesses 782system.cpu.l2cache.overall_accesses::cpu.data 1856 # number of overall (read+write) accesses 783system.cpu.l2cache.overall_accesses::total 5958 # number of overall (read+write) accesses 784system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.500244 # miss rate for ReadReq accesses 785system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888031 # miss rate for ReadReq accesses 786system.cpu.l2cache.ReadReq_miss_rate::total 0.562000 # miss rate for ReadReq accesses 787system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992586 # miss rate for ReadExReq accesses 788system.cpu.l2cache.ReadExReq_miss_rate::total 0.992586 # miss rate for ReadExReq accesses 789system.cpu.l2cache.demand_miss_rate::cpu.inst 0.500244 # miss rate for demand accesses 790system.cpu.l2cache.demand_miss_rate::cpu.data 0.948815 # miss rate for demand accesses 791system.cpu.l2cache.demand_miss_rate::total 0.639980 # miss rate for demand accesses 792system.cpu.l2cache.overall_miss_rate::cpu.inst 0.500244 # miss rate for overall accesses 793system.cpu.l2cache.overall_miss_rate::cpu.data 0.948815 # miss rate for overall accesses 794system.cpu.l2cache.overall_miss_rate::total 0.639980 # miss rate for overall accesses 795system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69750.365497 # average ReadReq miss latency 796system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73703.985507 # average ReadReq miss latency 797system.cpu.l2cache.ReadReq_avg_miss_latency::total 70745.258935 # average ReadReq miss latency 798system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68055.555556 # average ReadExReq miss latency 799system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68055.555556 # average ReadExReq miss latency 800system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69750.365497 # average overall miss latency 801system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70268.739353 # average overall miss latency 802system.cpu.l2cache.demand_avg_miss_latency::total 69989.771833 # average overall miss latency 803system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69750.365497 # average overall miss latency 804system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70268.739353 # average overall miss latency 805system.cpu.l2cache.overall_avg_miss_latency::total 69989.771833 # average overall miss latency | 791system.cpu.l2cache.demand_misses::cpu.inst 2059 # number of demand (read+write) misses 792system.cpu.l2cache.demand_misses::cpu.data 1760 # number of demand (read+write) misses 793system.cpu.l2cache.demand_misses::total 3819 # number of demand (read+write) misses 794system.cpu.l2cache.overall_misses::cpu.inst 2059 # number of overall misses 795system.cpu.l2cache.overall_misses::cpu.data 1760 # number of overall misses 796system.cpu.l2cache.overall_misses::total 3819 # number of overall misses 797system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 142590000 # number of ReadReq miss cycles 798system.cpu.l2cache.ReadReq_miss_latency::cpu.data 50403250 # number of ReadReq miss cycles 799system.cpu.l2cache.ReadReq_miss_latency::total 192993250 # number of ReadReq miss cycles 800system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 74281750 # number of ReadExReq miss cycles 801system.cpu.l2cache.ReadExReq_miss_latency::total 74281750 # number of ReadExReq miss cycles 802system.cpu.l2cache.demand_miss_latency::cpu.inst 142590000 # number of demand (read+write) miss cycles 803system.cpu.l2cache.demand_miss_latency::cpu.data 124685000 # number of demand (read+write) miss cycles 804system.cpu.l2cache.demand_miss_latency::total 267275000 # number of demand (read+write) miss cycles 805system.cpu.l2cache.overall_miss_latency::cpu.inst 142590000 # number of overall miss cycles 806system.cpu.l2cache.overall_miss_latency::cpu.data 124685000 # number of overall miss cycles 807system.cpu.l2cache.overall_miss_latency::total 267275000 # number of overall miss cycles 808system.cpu.l2cache.ReadReq_accesses::cpu.inst 4120 # number of ReadReq accesses(hits+misses) 809system.cpu.l2cache.ReadReq_accesses::cpu.data 776 # number of ReadReq accesses(hits+misses) 810system.cpu.l2cache.ReadReq_accesses::total 4896 # number of ReadReq accesses(hits+misses) 811system.cpu.l2cache.Writeback_accesses::writebacks 19 # number of Writeback accesses(hits+misses) 812system.cpu.l2cache.Writeback_accesses::total 19 # number of Writeback accesses(hits+misses) 813system.cpu.l2cache.ReadExReq_accesses::cpu.data 1081 # number of ReadExReq accesses(hits+misses) 814system.cpu.l2cache.ReadExReq_accesses::total 1081 # number of ReadExReq accesses(hits+misses) 815system.cpu.l2cache.demand_accesses::cpu.inst 4120 # number of demand (read+write) accesses 816system.cpu.l2cache.demand_accesses::cpu.data 1857 # number of demand (read+write) accesses 817system.cpu.l2cache.demand_accesses::total 5977 # number of demand (read+write) accesses 818system.cpu.l2cache.overall_accesses::cpu.inst 4120 # number of overall (read+write) accesses 819system.cpu.l2cache.overall_accesses::cpu.data 1857 # number of overall (read+write) accesses 820system.cpu.l2cache.overall_accesses::total 5977 # number of overall (read+write) accesses 821system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.499757 # miss rate for ReadReq accesses 822system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.887887 # miss rate for ReadReq accesses 823system.cpu.l2cache.ReadReq_miss_rate::total 0.561275 # miss rate for ReadReq accesses 824system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.990749 # miss rate for ReadExReq accesses 825system.cpu.l2cache.ReadExReq_miss_rate::total 0.990749 # miss rate for ReadExReq accesses 826system.cpu.l2cache.demand_miss_rate::cpu.inst 0.499757 # miss rate for demand accesses 827system.cpu.l2cache.demand_miss_rate::cpu.data 0.947765 # miss rate for demand accesses 828system.cpu.l2cache.demand_miss_rate::total 0.638949 # miss rate for demand accesses 829system.cpu.l2cache.overall_miss_rate::cpu.inst 0.499757 # miss rate for overall accesses 830system.cpu.l2cache.overall_miss_rate::cpu.data 0.947765 # miss rate for overall accesses 831system.cpu.l2cache.overall_miss_rate::total 0.638949 # miss rate for overall accesses 832system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69252.064109 # average ReadReq miss latency 833system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73154.208999 # average ReadReq miss latency 834system.cpu.l2cache.ReadReq_avg_miss_latency::total 70230.440320 # average ReadReq miss latency 835system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69357.376284 # average ReadExReq miss latency 836system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69357.376284 # average ReadExReq miss latency 837system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69252.064109 # average overall miss latency 838system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70843.750000 # average overall miss latency 839system.cpu.l2cache.demand_avg_miss_latency::total 69985.598324 # average overall miss latency 840system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69252.064109 # average overall miss latency 841system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70843.750000 # average overall miss latency 842system.cpu.l2cache.overall_avg_miss_latency::total 69985.598324 # average overall miss latency |
| 806system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 807system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 808system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 809system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 810system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 811system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 812system.cpu.l2cache.fast_writes 0 # number of fast writes performed 813system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 843system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 844system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 845system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 846system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 847system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 848system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 849system.cpu.l2cache.fast_writes 0 # number of fast writes performed 850system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 814system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits 815system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 11 # number of ReadReq MSHR hits 816system.cpu.l2cache.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits 817system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits 818system.cpu.l2cache.demand_mshr_hits::cpu.data 11 # number of demand (read+write) MSHR hits 819system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits 820system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits 821system.cpu.l2cache.overall_mshr_hits::cpu.data 11 # number of overall MSHR hits 822system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits 823system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2049 # number of ReadReq MSHR misses 824system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 679 # number of ReadReq MSHR misses 825system.cpu.l2cache.ReadReq_mshr_misses::total 2728 # number of ReadReq MSHR misses | 851system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits 852system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 13 # number of ReadReq MSHR hits 853system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits 854system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits 855system.cpu.l2cache.demand_mshr_hits::cpu.data 13 # number of demand (read+write) MSHR hits 856system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits 857system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits 858system.cpu.l2cache.overall_mshr_hits::cpu.data 13 # number of overall MSHR hits 859system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits 860system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2055 # number of ReadReq MSHR misses 861system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 676 # number of ReadReq MSHR misses 862system.cpu.l2cache.ReadReq_mshr_misses::total 2731 # number of ReadReq MSHR misses |
| 826system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1071 # number of ReadExReq MSHR misses 827system.cpu.l2cache.ReadExReq_mshr_misses::total 1071 # number of ReadExReq MSHR misses | 863system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1071 # number of ReadExReq MSHR misses 864system.cpu.l2cache.ReadExReq_mshr_misses::total 1071 # number of ReadExReq MSHR misses |
| 828system.cpu.l2cache.demand_mshr_misses::cpu.inst 2049 # number of demand (read+write) MSHR misses 829system.cpu.l2cache.demand_mshr_misses::cpu.data 1750 # number of demand (read+write) MSHR misses 830system.cpu.l2cache.demand_mshr_misses::total 3799 # number of demand (read+write) MSHR misses 831system.cpu.l2cache.overall_mshr_misses::cpu.inst 2049 # number of overall MSHR misses 832system.cpu.l2cache.overall_mshr_misses::cpu.data 1750 # number of overall MSHR misses 833system.cpu.l2cache.overall_mshr_misses::total 3799 # number of overall MSHR misses 834system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117223750 # number of ReadReq MSHR miss cycles 835system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 41708750 # number of ReadReq MSHR miss cycles 836system.cpu.l2cache.ReadReq_mshr_miss_latency::total 158932500 # number of ReadReq MSHR miss cycles 837system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 59427500 # number of ReadExReq MSHR miss cycles 838system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 59427500 # number of ReadExReq MSHR miss cycles 839system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117223750 # number of demand (read+write) MSHR miss cycles 840system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101136250 # number of demand (read+write) MSHR miss cycles 841system.cpu.l2cache.demand_mshr_miss_latency::total 218360000 # number of demand (read+write) MSHR miss cycles 842system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117223750 # number of overall MSHR miss cycles 843system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101136250 # number of overall MSHR miss cycles 844system.cpu.l2cache.overall_mshr_miss_latency::total 218360000 # number of overall MSHR miss cycles 845system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.499512 # mshr miss rate for ReadReq accesses 846system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.873874 # mshr miss rate for ReadReq accesses 847system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.559131 # mshr miss rate for ReadReq accesses 848system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992586 # mshr miss rate for ReadExReq accesses 849system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992586 # mshr miss rate for ReadExReq accesses 850system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.499512 # mshr miss rate for demand accesses 851system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942888 # mshr miss rate for demand accesses 852system.cpu.l2cache.demand_mshr_miss_rate::total 0.637630 # mshr miss rate for demand accesses 853system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.499512 # mshr miss rate for overall accesses 854system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942888 # mshr miss rate for overall accesses 855system.cpu.l2cache.overall_mshr_miss_rate::total 0.637630 # mshr miss rate for overall accesses 856system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57210.224500 # average ReadReq mshr miss latency 857system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61426.730486 # average ReadReq mshr miss latency 858system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58259.714076 # average ReadReq mshr miss latency 859system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55487.861811 # average ReadExReq mshr miss latency 860system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55487.861811 # average ReadExReq mshr miss latency 861system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57210.224500 # average overall mshr miss latency 862system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57792.142857 # average overall mshr miss latency 863system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57478.283759 # average overall mshr miss latency 864system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57210.224500 # average overall mshr miss latency 865system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57792.142857 # average overall mshr miss latency 866system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57478.283759 # average overall mshr miss latency | 865system.cpu.l2cache.demand_mshr_misses::cpu.inst 2055 # number of demand (read+write) MSHR misses 866system.cpu.l2cache.demand_mshr_misses::cpu.data 1747 # number of demand (read+write) MSHR misses 867system.cpu.l2cache.demand_mshr_misses::total 3802 # number of demand (read+write) MSHR misses 868system.cpu.l2cache.overall_mshr_misses::cpu.inst 2055 # number of overall MSHR misses 869system.cpu.l2cache.overall_mshr_misses::cpu.data 1747 # number of overall MSHR misses 870system.cpu.l2cache.overall_mshr_misses::total 3802 # number of overall MSHR misses 871system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 116514500 # number of ReadReq MSHR miss cycles 872system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 41206750 # number of ReadReq MSHR miss cycles 873system.cpu.l2cache.ReadReq_mshr_miss_latency::total 157721250 # number of ReadReq MSHR miss cycles 874system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60687250 # number of ReadExReq MSHR miss cycles 875system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60687250 # number of ReadExReq MSHR miss cycles 876system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116514500 # number of demand (read+write) MSHR miss cycles 877system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101894000 # number of demand (read+write) MSHR miss cycles 878system.cpu.l2cache.demand_mshr_miss_latency::total 218408500 # number of demand (read+write) MSHR miss cycles 879system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116514500 # number of overall MSHR miss cycles 880system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101894000 # number of overall MSHR miss cycles 881system.cpu.l2cache.overall_mshr_miss_latency::total 218408500 # number of overall MSHR miss cycles 882system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.498786 # mshr miss rate for ReadReq accesses 883system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871134 # mshr miss rate for ReadReq accesses 884system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.557802 # mshr miss rate for ReadReq accesses 885system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.990749 # mshr miss rate for ReadExReq accesses 886system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.990749 # mshr miss rate for ReadExReq accesses 887system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.498786 # mshr miss rate for demand accesses 888system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.940765 # mshr miss rate for demand accesses 889system.cpu.l2cache.demand_mshr_miss_rate::total 0.636105 # mshr miss rate for demand accesses 890system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.498786 # mshr miss rate for overall accesses 891system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940765 # mshr miss rate for overall accesses 892system.cpu.l2cache.overall_mshr_miss_rate::total 0.636105 # mshr miss rate for overall accesses 893system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56698.053528 # average ReadReq mshr miss latency 894system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60956.730769 # average ReadReq mshr miss latency 895system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57752.196997 # average ReadReq mshr miss latency 896system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56664.098973 # average ReadExReq mshr miss latency 897system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56664.098973 # average ReadExReq mshr miss latency 898system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56698.053528 # average overall mshr miss latency 899system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58325.128792 # average overall mshr miss latency 900system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57445.686481 # average overall mshr miss latency 901system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56698.053528 # average overall mshr miss latency 902system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58325.128792 # average overall mshr miss latency 903system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57445.686481 # average overall mshr miss latency |
| 867system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 904system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 868system.cpu.dcache.tags.replacements 59 # number of replacements 869system.cpu.dcache.tags.tagsinuse 1407.038554 # Cycle average of tags in use 870system.cpu.dcache.tags.total_refs 46795712 # Total number of references to valid blocks. 871system.cpu.dcache.tags.sampled_refs 1856 # Sample count of references to valid blocks. 872system.cpu.dcache.tags.avg_refs 25213.206897 # Average number of references to valid blocks. | 905system.cpu.dcache.tags.replacements 60 # number of replacements 906system.cpu.dcache.tags.tagsinuse 1407.063073 # Cycle average of tags in use 907system.cpu.dcache.tags.total_refs 46801066 # Total number of references to valid blocks. 908system.cpu.dcache.tags.sampled_refs 1857 # Sample count of references to valid blocks. 909system.cpu.dcache.tags.avg_refs 25202.512655 # Average number of references to valid blocks. |
| 873system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 910system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 874system.cpu.dcache.tags.occ_blocks::cpu.data 1407.038554 # Average occupied blocks per requestor 875system.cpu.dcache.tags.occ_percent::cpu.data 0.343515 # Average percentage of cache occupancy 876system.cpu.dcache.tags.occ_percent::total 0.343515 # Average percentage of cache occupancy | 911system.cpu.dcache.tags.occ_blocks::cpu.data 1407.063073 # Average occupied blocks per requestor 912system.cpu.dcache.tags.occ_percent::cpu.data 0.343521 # Average percentage of cache occupancy 913system.cpu.dcache.tags.occ_percent::total 0.343521 # Average percentage of cache occupancy |
| 877system.cpu.dcache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id | 914system.cpu.dcache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id |
| 878system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id | 915system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id |
| 879system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id | 916system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id |
| 880system.cpu.dcache.tags.age_task_id_blocks_1024::2 353 # Occupied blocks per task id | 917system.cpu.dcache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id |
| 881system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 882system.cpu.dcache.tags.age_task_id_blocks_1024::4 1378 # Occupied blocks per task id 883system.cpu.dcache.tags.occ_task_id_percent::1024 0.438721 # Percentage of cache occupancy per task id | 918system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 919system.cpu.dcache.tags.age_task_id_blocks_1024::4 1378 # Occupied blocks per task id 920system.cpu.dcache.tags.occ_task_id_percent::1024 0.438721 # Percentage of cache occupancy per task id |
| 884system.cpu.dcache.tags.tag_accesses 93612504 # Number of tag accesses 885system.cpu.dcache.tags.data_accesses 93612504 # Number of data accesses 886system.cpu.dcache.ReadReq_hits::cpu.data 34394263 # number of ReadReq hits 887system.cpu.dcache.ReadReq_hits::total 34394263 # number of ReadReq hits 888system.cpu.dcache.WriteReq_hits::cpu.data 12356566 # number of WriteReq hits 889system.cpu.dcache.WriteReq_hits::total 12356566 # number of WriteReq hits 890system.cpu.dcache.LoadLockedReq_hits::cpu.data 22476 # number of LoadLockedReq hits 891system.cpu.dcache.LoadLockedReq_hits::total 22476 # number of LoadLockedReq hits | 921system.cpu.dcache.tags.tag_accesses 93623269 # Number of tag accesses 922system.cpu.dcache.tags.data_accesses 93623269 # Number of data accesses 923system.cpu.dcache.ReadReq_hits::cpu.data 34399630 # number of ReadReq hits 924system.cpu.dcache.ReadReq_hits::total 34399630 # number of ReadReq hits 925system.cpu.dcache.WriteReq_hits::cpu.data 12356556 # number of WriteReq hits 926system.cpu.dcache.WriteReq_hits::total 12356556 # number of WriteReq hits 927system.cpu.dcache.LoadLockedReq_hits::cpu.data 22473 # number of LoadLockedReq hits 928system.cpu.dcache.LoadLockedReq_hits::total 22473 # number of LoadLockedReq hits |
| 892system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits 893system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits | 929system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits 930system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits |
| 894system.cpu.dcache.demand_hits::cpu.data 46750829 # number of demand (read+write) hits 895system.cpu.dcache.demand_hits::total 46750829 # number of demand (read+write) hits 896system.cpu.dcache.overall_hits::cpu.data 46750829 # number of overall hits 897system.cpu.dcache.overall_hits::total 46750829 # number of overall hits 898system.cpu.dcache.ReadReq_misses::cpu.data 1889 # number of ReadReq misses 899system.cpu.dcache.ReadReq_misses::total 1889 # number of ReadReq misses 900system.cpu.dcache.WriteReq_misses::cpu.data 7721 # number of WriteReq misses 901system.cpu.dcache.WriteReq_misses::total 7721 # number of WriteReq misses | 931system.cpu.dcache.demand_hits::cpu.data 46756186 # number of demand (read+write) hits 932system.cpu.dcache.demand_hits::total 46756186 # number of demand (read+write) hits 933system.cpu.dcache.overall_hits::cpu.data 46756186 # number of overall hits 934system.cpu.dcache.overall_hits::total 46756186 # number of overall hits 935system.cpu.dcache.ReadReq_misses::cpu.data 1907 # number of ReadReq misses 936system.cpu.dcache.ReadReq_misses::total 1907 # number of ReadReq misses 937system.cpu.dcache.WriteReq_misses::cpu.data 7731 # number of WriteReq misses 938system.cpu.dcache.WriteReq_misses::total 7731 # number of WriteReq misses |
| 902system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 903system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses | 939system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 940system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses |
| 904system.cpu.dcache.demand_misses::cpu.data 9610 # number of demand (read+write) misses 905system.cpu.dcache.demand_misses::total 9610 # number of demand (read+write) misses 906system.cpu.dcache.overall_misses::cpu.data 9610 # number of overall misses 907system.cpu.dcache.overall_misses::total 9610 # number of overall misses 908system.cpu.dcache.ReadReq_miss_latency::cpu.data 119060977 # number of ReadReq miss cycles 909system.cpu.dcache.ReadReq_miss_latency::total 119060977 # number of ReadReq miss cycles 910system.cpu.dcache.WriteReq_miss_latency::cpu.data 479134996 # number of WriteReq miss cycles 911system.cpu.dcache.WriteReq_miss_latency::total 479134996 # number of WriteReq miss cycles | 941system.cpu.dcache.demand_misses::cpu.data 9638 # number of demand (read+write) misses 942system.cpu.dcache.demand_misses::total 9638 # number of demand (read+write) misses 943system.cpu.dcache.overall_misses::cpu.data 9638 # number of overall misses 944system.cpu.dcache.overall_misses::total 9638 # number of overall misses 945system.cpu.dcache.ReadReq_miss_latency::cpu.data 121525225 # number of ReadReq miss cycles 946system.cpu.dcache.ReadReq_miss_latency::total 121525225 # number of ReadReq miss cycles 947system.cpu.dcache.WriteReq_miss_latency::cpu.data 489452496 # number of WriteReq miss cycles 948system.cpu.dcache.WriteReq_miss_latency::total 489452496 # number of WriteReq miss cycles |
| 912system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles 913system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles | 949system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles 950system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles |
| 914system.cpu.dcache.demand_miss_latency::cpu.data 598195973 # number of demand (read+write) miss cycles 915system.cpu.dcache.demand_miss_latency::total 598195973 # number of demand (read+write) miss cycles 916system.cpu.dcache.overall_miss_latency::cpu.data 598195973 # number of overall miss cycles 917system.cpu.dcache.overall_miss_latency::total 598195973 # number of overall miss cycles 918system.cpu.dcache.ReadReq_accesses::cpu.data 34396152 # number of ReadReq accesses(hits+misses) 919system.cpu.dcache.ReadReq_accesses::total 34396152 # number of ReadReq accesses(hits+misses) | 951system.cpu.dcache.demand_miss_latency::cpu.data 610977721 # number of demand (read+write) miss cycles 952system.cpu.dcache.demand_miss_latency::total 610977721 # number of demand (read+write) miss cycles 953system.cpu.dcache.overall_miss_latency::cpu.data 610977721 # number of overall miss cycles 954system.cpu.dcache.overall_miss_latency::total 610977721 # number of overall miss cycles 955system.cpu.dcache.ReadReq_accesses::cpu.data 34401537 # number of ReadReq accesses(hits+misses) 956system.cpu.dcache.ReadReq_accesses::total 34401537 # number of ReadReq accesses(hits+misses) |
| 920system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 921system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) | 957system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 958system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) |
| 922system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22478 # number of LoadLockedReq accesses(hits+misses) 923system.cpu.dcache.LoadLockedReq_accesses::total 22478 # number of LoadLockedReq accesses(hits+misses) | 959system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22475 # number of LoadLockedReq accesses(hits+misses) 960system.cpu.dcache.LoadLockedReq_accesses::total 22475 # number of LoadLockedReq accesses(hits+misses) |
| 924system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) 925system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) | 961system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) 962system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) |
| 926system.cpu.dcache.demand_accesses::cpu.data 46760439 # number of demand (read+write) accesses 927system.cpu.dcache.demand_accesses::total 46760439 # number of demand (read+write) accesses 928system.cpu.dcache.overall_accesses::cpu.data 46760439 # number of overall (read+write) accesses 929system.cpu.dcache.overall_accesses::total 46760439 # number of overall (read+write) accesses | 963system.cpu.dcache.demand_accesses::cpu.data 46765824 # number of demand (read+write) accesses 964system.cpu.dcache.demand_accesses::total 46765824 # number of demand (read+write) accesses 965system.cpu.dcache.overall_accesses::cpu.data 46765824 # number of overall (read+write) accesses 966system.cpu.dcache.overall_accesses::total 46765824 # number of overall (read+write) accesses |
| 930system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses 931system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses | 967system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses 968system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses |
| 932system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses 933system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses | 969system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses 970system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses |
| 934system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses 935system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses 936system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses 937system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses 938system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses 939system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses | 971system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses 972system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses 973system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses 974system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses 975system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses 976system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses |
| 940system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63028.574378 # average ReadReq miss latency 941system.cpu.dcache.ReadReq_avg_miss_latency::total 63028.574378 # average ReadReq miss latency 942system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62056.080300 # average WriteReq miss latency 943system.cpu.dcache.WriteReq_avg_miss_latency::total 62056.080300 # average WriteReq miss latency | 977system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63725.865233 # average ReadReq miss latency 978system.cpu.dcache.ReadReq_avg_miss_latency::total 63725.865233 # average ReadReq miss latency 979system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63310.373302 # average WriteReq miss latency 980system.cpu.dcache.WriteReq_avg_miss_latency::total 63310.373302 # average WriteReq miss latency |
| 944system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency 945system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency | 981system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency 982system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency |
| 946system.cpu.dcache.demand_avg_miss_latency::cpu.data 62247.239646 # average overall miss latency 947system.cpu.dcache.demand_avg_miss_latency::total 62247.239646 # average overall miss latency 948system.cpu.dcache.overall_avg_miss_latency::cpu.data 62247.239646 # average overall miss latency 949system.cpu.dcache.overall_avg_miss_latency::total 62247.239646 # average overall miss latency 950system.cpu.dcache.blocked_cycles::no_mshrs 566 # number of cycles access was blocked | 983system.cpu.dcache.demand_avg_miss_latency::cpu.data 63392.583627 # average overall miss latency 984system.cpu.dcache.demand_avg_miss_latency::total 63392.583627 # average overall miss latency 985system.cpu.dcache.overall_avg_miss_latency::cpu.data 63392.583627 # average overall miss latency 986system.cpu.dcache.overall_avg_miss_latency::total 63392.583627 # average overall miss latency 987system.cpu.dcache.blocked_cycles::no_mshrs 567 # number of cycles access was blocked |
| 951system.cpu.dcache.blocked_cycles::no_targets 318 # number of cycles access was blocked 952system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked 953system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked | 988system.cpu.dcache.blocked_cycles::no_targets 318 # number of cycles access was blocked 989system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked 990system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked |
| 954system.cpu.dcache.avg_blocked_cycles::no_mshrs 51.454545 # average number of cycles each access was blocked | 991system.cpu.dcache.avg_blocked_cycles::no_mshrs 51.545455 # average number of cycles each access was blocked |
| 955system.cpu.dcache.avg_blocked_cycles::no_targets 79.500000 # average number of cycles each access was blocked 956system.cpu.dcache.fast_writes 0 # number of fast writes performed 957system.cpu.dcache.cache_copies 0 # number of cache copies performed | 992system.cpu.dcache.avg_blocked_cycles::no_targets 79.500000 # average number of cycles each access was blocked 993system.cpu.dcache.fast_writes 0 # number of fast writes performed 994system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 958system.cpu.dcache.writebacks::writebacks 18 # number of writebacks 959system.cpu.dcache.writebacks::total 18 # number of writebacks 960system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1111 # number of ReadReq MSHR hits 961system.cpu.dcache.ReadReq_mshr_hits::total 1111 # number of ReadReq MSHR hits 962system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6643 # number of WriteReq MSHR hits 963system.cpu.dcache.WriteReq_mshr_hits::total 6643 # number of WriteReq MSHR hits | 995system.cpu.dcache.writebacks::writebacks 19 # number of writebacks 996system.cpu.dcache.writebacks::total 19 # number of writebacks 997system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1130 # number of ReadReq MSHR hits 998system.cpu.dcache.ReadReq_mshr_hits::total 1130 # number of ReadReq MSHR hits 999system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6651 # number of WriteReq MSHR hits 1000system.cpu.dcache.WriteReq_mshr_hits::total 6651 # number of WriteReq MSHR hits |
| 964system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 965system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits | 1001system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 1002system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits |
| 966system.cpu.dcache.demand_mshr_hits::cpu.data 7754 # number of demand (read+write) MSHR hits 967system.cpu.dcache.demand_mshr_hits::total 7754 # number of demand (read+write) MSHR hits 968system.cpu.dcache.overall_mshr_hits::cpu.data 7754 # number of overall MSHR hits 969system.cpu.dcache.overall_mshr_hits::total 7754 # number of overall MSHR hits 970system.cpu.dcache.ReadReq_mshr_misses::cpu.data 778 # number of ReadReq MSHR misses 971system.cpu.dcache.ReadReq_mshr_misses::total 778 # number of ReadReq MSHR misses 972system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1078 # number of WriteReq MSHR misses 973system.cpu.dcache.WriteReq_mshr_misses::total 1078 # number of WriteReq MSHR misses 974system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses 975system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses 976system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses 977system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses 978system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52580511 # number of ReadReq MSHR miss cycles 979system.cpu.dcache.ReadReq_mshr_miss_latency::total 52580511 # number of ReadReq MSHR miss cycles 980system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73988748 # number of WriteReq MSHR miss cycles 981system.cpu.dcache.WriteReq_mshr_miss_latency::total 73988748 # number of WriteReq MSHR miss cycles 982system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126569259 # number of demand (read+write) MSHR miss cycles 983system.cpu.dcache.demand_mshr_miss_latency::total 126569259 # number of demand (read+write) MSHR miss cycles 984system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126569259 # number of overall MSHR miss cycles 985system.cpu.dcache.overall_mshr_miss_latency::total 126569259 # number of overall MSHR miss cycles | 1003system.cpu.dcache.demand_mshr_hits::cpu.data 7781 # number of demand (read+write) MSHR hits 1004system.cpu.dcache.demand_mshr_hits::total 7781 # number of demand (read+write) MSHR hits 1005system.cpu.dcache.overall_mshr_hits::cpu.data 7781 # number of overall MSHR hits 1006system.cpu.dcache.overall_mshr_hits::total 7781 # number of overall MSHR hits 1007system.cpu.dcache.ReadReq_mshr_misses::cpu.data 777 # number of ReadReq MSHR misses 1008system.cpu.dcache.ReadReq_mshr_misses::total 777 # number of ReadReq MSHR misses 1009system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1080 # number of WriteReq MSHR misses 1010system.cpu.dcache.WriteReq_mshr_misses::total 1080 # number of WriteReq MSHR misses 1011system.cpu.dcache.demand_mshr_misses::cpu.data 1857 # number of demand (read+write) MSHR misses 1012system.cpu.dcache.demand_mshr_misses::total 1857 # number of demand (read+write) MSHR misses 1013system.cpu.dcache.overall_mshr_misses::cpu.data 1857 # number of overall MSHR misses 1014system.cpu.dcache.overall_mshr_misses::total 1857 # number of overall MSHR misses 1015system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52119013 # number of ReadReq MSHR miss cycles 1016system.cpu.dcache.ReadReq_mshr_miss_latency::total 52119013 # number of ReadReq MSHR miss cycles 1017system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 75404498 # number of WriteReq MSHR miss cycles 1018system.cpu.dcache.WriteReq_mshr_miss_latency::total 75404498 # number of WriteReq MSHR miss cycles 1019system.cpu.dcache.demand_mshr_miss_latency::cpu.data 127523511 # number of demand (read+write) MSHR miss cycles 1020system.cpu.dcache.demand_mshr_miss_latency::total 127523511 # number of demand (read+write) MSHR miss cycles 1021system.cpu.dcache.overall_mshr_miss_latency::cpu.data 127523511 # number of overall MSHR miss cycles 1022system.cpu.dcache.overall_mshr_miss_latency::total 127523511 # number of overall MSHR miss cycles |
| 986system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses 987system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses 988system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses 989system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses 990system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses 991system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 992system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses 993system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses | 1023system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses 1024system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses 1025system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses 1026system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses 1027system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses 1028system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 1029system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses 1030system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses |
| 994system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67584.204370 # average ReadReq mshr miss latency 995system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67584.204370 # average ReadReq mshr miss latency 996system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68635.202226 # average WriteReq mshr miss latency 997system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68635.202226 # average WriteReq mshr miss latency 998system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68194.643858 # average overall mshr miss latency 999system.cpu.dcache.demand_avg_mshr_miss_latency::total 68194.643858 # average overall mshr miss latency 1000system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68194.643858 # average overall mshr miss latency 1001system.cpu.dcache.overall_avg_mshr_miss_latency::total 68194.643858 # average overall mshr miss latency | 1031system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67077.236808 # average ReadReq mshr miss latency 1032system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67077.236808 # average ReadReq mshr miss latency 1033system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69818.979630 # average WriteReq mshr miss latency 1034system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69818.979630 # average WriteReq mshr miss latency 1035system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68671.788368 # average overall mshr miss latency 1036system.cpu.dcache.demand_avg_mshr_miss_latency::total 68671.788368 # average overall mshr miss latency 1037system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68671.788368 # average overall mshr miss latency 1038system.cpu.dcache.overall_avg_mshr_miss_latency::total 68671.788368 # average overall mshr miss latency |
| 1002system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1003 1004---------- End Simulation Statistics ---------- | 1039system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1040 1041---------- End Simulation Statistics ---------- |