1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.074156 # Number of seconds simulated 4sim_ticks 74155951500 # Number of ticks simulated 5final_tick 74155951500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 102580 # Simulator instruction rate (inst/s) 8host_op_rate 112316 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 44148416 # Simulator tick rate (ticks/s) 10host_mem_usage 245240 # Number of bytes of host memory used 11host_seconds 1679.70 # Real time elapsed on the host |
12sim_insts 172303021 # Number of instructions simulated 13sim_ops 188656503 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 131776 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 112064 # Number of bytes read from this memory 16system.physmem.bytes_read::total 243840 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 131776 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 131776 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 2059 # Number of read requests responded to by this memory --- 53 unchanged lines hidden (view full) --- 73system.physmem.totGap 74155933000 # Total gap between requests 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 3811 # Categorize read packet sizes |
81system.physmem.writePktSize::0 0 # Categorize write packet sizes 82system.physmem.writePktSize::1 0 # Categorize write packet sizes 83system.physmem.writePktSize::2 0 # Categorize write packet sizes 84system.physmem.writePktSize::3 0 # Categorize write packet sizes 85system.physmem.writePktSize::4 0 # Categorize write packet sizes 86system.physmem.writePktSize::5 0 # Categorize write packet sizes 87system.physmem.writePktSize::6 0 # Categorize write packet sizes |
88system.physmem.rdQLenPdf::0 2809 # What read queue length does an incoming req see 89system.physmem.rdQLenPdf::1 787 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::2 160 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::3 46 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see --- 16 unchanged lines hidden (view full) --- 112system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
120system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 121system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 122system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 123system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 124system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 125system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see --- 16 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
152system.physmem.totQLat 17809500 # Total cycles spent in queuing delays 153system.physmem.totMemAccLat 103882000 # Sum of mem lat for all requests |
154system.physmem.totBusLat 19055000 # Total cycles spent in databus access 155system.physmem.totBankLat 67017500 # Total cycles spent in bank access |
156system.physmem.avgQLat 4673.18 # Average queueing delay per request |
157system.physmem.avgBankLat 17585.28 # Average bank access latency per request 158system.physmem.avgBusLat 5000.00 # Average bus latency per request |
159system.physmem.avgMemAccLat 27258.46 # Average memory access latency |
160system.physmem.avgRdBW 3.29 # Average achieved read bandwidth in MB/s 161system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 162system.physmem.avgConsumedRdBW 3.29 # Average consumed read bandwidth in MB/s 163system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 164system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 165system.physmem.busUtil 0.03 # Data bus utilization in percentage 166system.physmem.avgRdQLen 0.00 # Average read queue length over time 167system.physmem.avgWrQLen 0.00 # Average write queue length over time --- 511 unchanged lines hidden (view full) --- 679system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1076 # number of ReadExReq MSHR misses 680system.cpu.l2cache.ReadExReq_mshr_misses::total 1076 # number of ReadExReq MSHR misses 681system.cpu.l2cache.demand_mshr_misses::cpu.inst 2060 # number of demand (read+write) MSHR misses 682system.cpu.l2cache.demand_mshr_misses::cpu.data 1751 # number of demand (read+write) MSHR misses 683system.cpu.l2cache.demand_mshr_misses::total 3811 # number of demand (read+write) MSHR misses 684system.cpu.l2cache.overall_mshr_misses::cpu.inst 2060 # number of overall MSHR misses 685system.cpu.l2cache.overall_mshr_misses::cpu.data 1751 # number of overall MSHR misses 686system.cpu.l2cache.overall_mshr_misses::total 3811 # number of overall MSHR misses |
687system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 78130246 # number of ReadReq MSHR miss cycles 688system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30984758 # number of ReadReq MSHR miss cycles 689system.cpu.l2cache.ReadReq_mshr_miss_latency::total 109115004 # number of ReadReq MSHR miss cycles 690system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 36313866 # number of ReadExReq MSHR miss cycles 691system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 36313866 # number of ReadExReq MSHR miss cycles 692system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 78130246 # number of demand (read+write) MSHR miss cycles 693system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67298624 # number of demand (read+write) MSHR miss cycles 694system.cpu.l2cache.demand_mshr_miss_latency::total 145428870 # number of demand (read+write) MSHR miss cycles 695system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 78130246 # number of overall MSHR miss cycles 696system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67298624 # number of overall MSHR miss cycles 697system.cpu.l2cache.overall_mshr_miss_latency::total 145428870 # number of overall MSHR miss cycles |
698system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.502439 # mshr miss rate for ReadReq accesses 699system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869845 # mshr miss rate for ReadReq accesses 700system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.560911 # mshr miss rate for ReadReq accesses 701system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991705 # mshr miss rate for ReadExReq accesses 702system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991705 # mshr miss rate for ReadExReq accesses 703system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.502439 # mshr miss rate for demand accesses 704system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.940892 # mshr miss rate for demand accesses 705system.cpu.l2cache.demand_mshr_miss_rate::total 0.639322 # mshr miss rate for demand accesses 706system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.502439 # mshr miss rate for overall accesses 707system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940892 # mshr miss rate for overall accesses 708system.cpu.l2cache.overall_mshr_miss_rate::total 0.639322 # mshr miss rate for overall accesses |
709system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37927.303883 # average ReadReq mshr miss latency 710system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45903.345185 # average ReadReq mshr miss latency 711system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39895.796709 # average ReadReq mshr miss latency 712system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33748.946097 # average ReadExReq mshr miss latency 713system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33748.946097 # average ReadExReq mshr miss latency 714system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37927.303883 # average overall mshr miss latency 715system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38434.394061 # average overall mshr miss latency 716system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38160.291262 # average overall mshr miss latency 717system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37927.303883 # average overall mshr miss latency 718system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38434.394061 # average overall mshr miss latency 719system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38160.291262 # average overall mshr miss latency |
720system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 721system.cpu.dcache.replacements 57 # number of replacements 722system.cpu.dcache.tagsinuse 1410.136977 # Cycle average of tags in use 723system.cpu.dcache.total_refs 46795714 # Total number of references to valid blocks. 724system.cpu.dcache.sampled_refs 1861 # Sample count of references to valid blocks. 725system.cpu.dcache.avg_refs 25145.466953 # Average number of references to valid blocks. 726system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 727system.cpu.dcache.occ_blocks::cpu.data 1410.136977 # Average occupied blocks per requestor --- 121 unchanged lines hidden --- |