1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.076323 # Number of seconds simulated 4sim_ticks 76322764500 # Number of ticks simulated 5final_tick 76322764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 95790 # Simulator instruction rate (inst/s) 8host_op_rate 104880 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 42423254 # Simulator tick rate (ticks/s) 10host_mem_usage 235620 # Number of bytes of host memory used 11host_seconds 1799.08 # Real time elapsed on the host |
12sim_insts 172333279 # Number of instructions simulated 13sim_ops 188686762 # Number of ops (including micro ops) simulated |
14system.physmem.bytes_read::cpu.inst 133376 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 113216 # Number of bytes read from this memory 16system.physmem.bytes_read::total 246592 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 133376 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 133376 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 2084 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 1769 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 3853 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1747526 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 1483384 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 3230910 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1747526 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1747526 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1747526 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 1483384 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 3230910 # Total bandwidth to/from this memory (bytes/s) |
30system.cpu.dtb.inst_hits 0 # ITB inst hits 31system.cpu.dtb.inst_misses 0 # ITB inst misses 32system.cpu.dtb.read_hits 0 # DTB read hits 33system.cpu.dtb.read_misses 0 # DTB read misses 34system.cpu.dtb.write_hits 0 # DTB write hits 35system.cpu.dtb.write_misses 0 # DTB write misses 36system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 37system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 332 unchanged lines hidden (view full) --- 370system.cpu.icache.overall_miss_latency::total 112756500 # number of overall miss cycles 371system.cpu.icache.ReadReq_accesses::cpu.inst 37841460 # number of ReadReq accesses(hits+misses) 372system.cpu.icache.ReadReq_accesses::total 37841460 # number of ReadReq accesses(hits+misses) 373system.cpu.icache.demand_accesses::cpu.inst 37841460 # number of demand (read+write) accesses 374system.cpu.icache.demand_accesses::total 37841460 # number of demand (read+write) accesses 375system.cpu.icache.overall_accesses::cpu.inst 37841460 # number of overall (read+write) accesses 376system.cpu.icache.overall_accesses::total 37841460 # number of overall (read+write) accesses 377system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000137 # miss rate for ReadReq accesses |
378system.cpu.icache.ReadReq_miss_rate::total 0.000137 # miss rate for ReadReq accesses |
379system.cpu.icache.demand_miss_rate::cpu.inst 0.000137 # miss rate for demand accesses |
380system.cpu.icache.demand_miss_rate::total 0.000137 # miss rate for demand accesses |
381system.cpu.icache.overall_miss_rate::cpu.inst 0.000137 # miss rate for overall accesses |
382system.cpu.icache.overall_miss_rate::total 0.000137 # miss rate for overall accesses |
383system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21688.113099 # average ReadReq miss latency |
384system.cpu.icache.ReadReq_avg_miss_latency::total 21688.113099 # average ReadReq miss latency |
385system.cpu.icache.demand_avg_miss_latency::cpu.inst 21688.113099 # average overall miss latency |
386system.cpu.icache.demand_avg_miss_latency::total 21688.113099 # average overall miss latency |
387system.cpu.icache.overall_avg_miss_latency::cpu.inst 21688.113099 # average overall miss latency |
388system.cpu.icache.overall_avg_miss_latency::total 21688.113099 # average overall miss latency |
389system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 390system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 391system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 392system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 393system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 394system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 395system.cpu.icache.fast_writes 0 # number of fast writes performed 396system.cpu.icache.cache_copies 0 # number of cache copies performed --- 11 unchanged lines hidden (view full) --- 408system.cpu.icache.overall_mshr_misses::total 4395 # number of overall MSHR misses 409system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 78893000 # number of ReadReq MSHR miss cycles 410system.cpu.icache.ReadReq_mshr_miss_latency::total 78893000 # number of ReadReq MSHR miss cycles 411system.cpu.icache.demand_mshr_miss_latency::cpu.inst 78893000 # number of demand (read+write) MSHR miss cycles 412system.cpu.icache.demand_mshr_miss_latency::total 78893000 # number of demand (read+write) MSHR miss cycles 413system.cpu.icache.overall_mshr_miss_latency::cpu.inst 78893000 # number of overall MSHR miss cycles 414system.cpu.icache.overall_mshr_miss_latency::total 78893000 # number of overall MSHR miss cycles 415system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for ReadReq accesses |
416system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000116 # mshr miss rate for ReadReq accesses |
417system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for demand accesses |
418system.cpu.icache.demand_mshr_miss_rate::total 0.000116 # mshr miss rate for demand accesses |
419system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for overall accesses |
420system.cpu.icache.overall_mshr_miss_rate::total 0.000116 # mshr miss rate for overall accesses |
421system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17950.625711 # average ReadReq mshr miss latency |
422system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17950.625711 # average ReadReq mshr miss latency |
423system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17950.625711 # average overall mshr miss latency |
424system.cpu.icache.demand_avg_mshr_miss_latency::total 17950.625711 # average overall mshr miss latency |
425system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17950.625711 # average overall mshr miss latency |
426system.cpu.icache.overall_avg_mshr_miss_latency::total 17950.625711 # average overall mshr miss latency |
427system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 428system.cpu.dcache.replacements 59 # number of replacements 429system.cpu.dcache.tagsinuse 1421.643782 # Cycle average of tags in use 430system.cpu.dcache.total_refs 47334662 # Total number of references to valid blocks. 431system.cpu.dcache.sampled_refs 1881 # Sample count of references to valid blocks. 432system.cpu.dcache.avg_refs 25164.626263 # Average number of references to valid blocks. 433system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 434system.cpu.dcache.occ_blocks::cpu.data 1421.643782 # Average occupied blocks per requestor --- 39 unchanged lines hidden (view full) --- 474system.cpu.dcache.LoadLockedReq_accesses::total 30321 # number of LoadLockedReq accesses(hits+misses) 475system.cpu.dcache.StoreCondReq_accesses::cpu.data 28457 # number of StoreCondReq accesses(hits+misses) 476system.cpu.dcache.StoreCondReq_accesses::total 28457 # number of StoreCondReq accesses(hits+misses) 477system.cpu.dcache.demand_accesses::cpu.data 47285356 # number of demand (read+write) accesses 478system.cpu.dcache.demand_accesses::total 47285356 # number of demand (read+write) accesses 479system.cpu.dcache.overall_accesses::cpu.data 47285356 # number of overall (read+write) accesses 480system.cpu.dcache.overall_accesses::total 47285356 # number of overall (read+write) accesses 481system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses |
482system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses |
483system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000615 # miss rate for WriteReq accesses |
484system.cpu.dcache.WriteReq_miss_rate::total 0.000615 # miss rate for WriteReq accesses |
485system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000066 # miss rate for LoadLockedReq accesses |
486system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000066 # miss rate for LoadLockedReq accesses |
487system.cpu.dcache.demand_miss_rate::cpu.data 0.000200 # miss rate for demand accesses |
488system.cpu.dcache.demand_miss_rate::total 0.000200 # miss rate for demand accesses |
489system.cpu.dcache.overall_miss_rate::cpu.data 0.000200 # miss rate for overall accesses |
490system.cpu.dcache.overall_miss_rate::total 0.000200 # miss rate for overall accesses |
491system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32575.806452 # average ReadReq miss latency |
492system.cpu.dcache.ReadReq_avg_miss_latency::total 32575.806452 # average ReadReq miss latency |
493system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31186.530880 # average WriteReq miss latency |
494system.cpu.dcache.WriteReq_avg_miss_latency::total 31186.530880 # average WriteReq miss latency |
495system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32000 # average LoadLockedReq miss latency |
496system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 32000 # average LoadLockedReq miss latency |
497system.cpu.dcache.demand_avg_miss_latency::cpu.data 31459.398099 # average overall miss latency |
498system.cpu.dcache.demand_avg_miss_latency::total 31459.398099 # average overall miss latency |
499system.cpu.dcache.overall_avg_miss_latency::cpu.data 31459.398099 # average overall miss latency |
500system.cpu.dcache.overall_avg_miss_latency::total 31459.398099 # average overall miss latency |
501system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 502system.cpu.dcache.blocked_cycles::no_targets 19500 # number of cycles access was blocked 503system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 504system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked 505system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 506system.cpu.dcache.avg_blocked_cycles::no_targets 9750 # average number of cycles each access was blocked 507system.cpu.dcache.fast_writes 0 # number of fast writes performed 508system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 21 unchanged lines hidden (view full) --- 530system.cpu.dcache.ReadReq_mshr_miss_latency::total 25610500 # number of ReadReq MSHR miss cycles 531system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 37862500 # number of WriteReq MSHR miss cycles 532system.cpu.dcache.WriteReq_mshr_miss_latency::total 37862500 # number of WriteReq MSHR miss cycles 533system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63473000 # number of demand (read+write) MSHR miss cycles 534system.cpu.dcache.demand_mshr_miss_latency::total 63473000 # number of demand (read+write) MSHR miss cycles 535system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63473000 # number of overall MSHR miss cycles 536system.cpu.dcache.overall_mshr_miss_latency::total 63473000 # number of overall MSHR miss cycles 537system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses |
538system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses |
539system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses |
540system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses |
541system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses |
542system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses |
543system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses |
544system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses |
545system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31853.855721 # average ReadReq mshr miss latency |
546system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31853.855721 # average ReadReq mshr miss latency |
547system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35155.524605 # average WriteReq mshr miss latency |
548system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35155.524605 # average WriteReq mshr miss latency |
549system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33744.284955 # average overall mshr miss latency |
550system.cpu.dcache.demand_avg_mshr_miss_latency::total 33744.284955 # average overall mshr miss latency |
551system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33744.284955 # average overall mshr miss latency |
552system.cpu.dcache.overall_avg_mshr_miss_latency::total 33744.284955 # average overall mshr miss latency |
553system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 554system.cpu.l2cache.replacements 0 # number of replacements 555system.cpu.l2cache.tagsinuse 2017.739485 # Cycle average of tags in use 556system.cpu.l2cache.total_refs 2396 # Total number of references to valid blocks. 557system.cpu.l2cache.sampled_refs 2793 # Sample count of references to valid blocks. 558system.cpu.l2cache.avg_refs 0.857859 # Average number of references to valid blocks. 559system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 560system.cpu.l2cache.occ_blocks::writebacks 4.002094 # Average occupied blocks per requestor --- 48 unchanged lines hidden (view full) --- 609system.cpu.l2cache.demand_accesses::cpu.inst 4395 # number of demand (read+write) accesses 610system.cpu.l2cache.demand_accesses::cpu.data 1881 # number of demand (read+write) accesses 611system.cpu.l2cache.demand_accesses::total 6276 # number of demand (read+write) accesses 612system.cpu.l2cache.overall_accesses::cpu.inst 4395 # number of overall (read+write) accesses 613system.cpu.l2cache.overall_accesses::cpu.data 1881 # number of overall (read+write) accesses 614system.cpu.l2cache.overall_accesses::total 6276 # number of overall (read+write) accesses 615system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.474858 # miss rate for ReadReq accesses 616system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.890547 # miss rate for ReadReq accesses |
617system.cpu.l2cache.ReadReq_miss_rate::total 0.539142 # miss rate for ReadReq accesses |
618system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991643 # miss rate for ReadExReq accesses |
619system.cpu.l2cache.ReadExReq_miss_rate::total 0.991643 # miss rate for ReadExReq accesses |
620system.cpu.l2cache.demand_miss_rate::cpu.inst 0.474858 # miss rate for demand accesses 621system.cpu.l2cache.demand_miss_rate::cpu.data 0.948432 # miss rate for demand accesses |
622system.cpu.l2cache.demand_miss_rate::total 0.616794 # miss rate for demand accesses |
623system.cpu.l2cache.overall_miss_rate::cpu.inst 0.474858 # miss rate for overall accesses 624system.cpu.l2cache.overall_miss_rate::cpu.data 0.948432 # miss rate for overall accesses |
625system.cpu.l2cache.overall_miss_rate::total 0.616794 # miss rate for overall accesses |
626system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34256.109248 # average ReadReq miss latency 627system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34321.229050 # average ReadReq miss latency |
628system.cpu.l2cache.ReadReq_avg_miss_latency::total 34272.743489 # average ReadReq miss latency |
629system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34368.913858 # average ReadExReq miss latency |
630system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34368.913858 # average ReadExReq miss latency |
631system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34256.109248 # average overall miss latency 632system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34349.775785 # average overall miss latency |
633system.cpu.l2cache.demand_avg_miss_latency::total 34299.276673 # average overall miss latency |
634system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34256.109248 # average overall miss latency 635system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34349.775785 # average overall miss latency |
636system.cpu.l2cache.overall_avg_miss_latency::total 34299.276673 # average overall miss latency |
637system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 638system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 639system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 640system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 641system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 642system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 643system.cpu.l2cache.fast_writes 0 # number of fast writes performed 644system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 25 unchanged lines hidden (view full) --- 670system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64692000 # number of demand (read+write) MSHR miss cycles 671system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 55013000 # number of demand (read+write) MSHR miss cycles 672system.cpu.l2cache.demand_mshr_miss_latency::total 119705000 # number of demand (read+write) MSHR miss cycles 673system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64692000 # number of overall MSHR miss cycles 674system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 55013000 # number of overall MSHR miss cycles 675system.cpu.l2cache.overall_mshr_miss_latency::total 119705000 # number of overall MSHR miss cycles 676system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for ReadReq accesses 677system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871891 # mshr miss rate for ReadReq accesses |
678system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.535680 # mshr miss rate for ReadReq accesses |
679system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991643 # mshr miss rate for ReadExReq accesses |
680system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991643 # mshr miss rate for ReadExReq accesses |
681system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for demand accesses 682system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.940457 # mshr miss rate for demand accesses |
683system.cpu.l2cache.demand_mshr_miss_rate::total 0.613926 # mshr miss rate for demand accesses |
684system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for overall accesses 685system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940457 # mshr miss rate for overall accesses |
686system.cpu.l2cache.overall_mshr_miss_rate::total 0.613926 # mshr miss rate for overall accesses |
687system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31042.226488 # average ReadReq mshr miss latency 688system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31179.743224 # average ReadReq mshr miss latency |
689system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31076.840215 # average ReadReq mshr miss latency |
690system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31044.943820 # average ReadExReq mshr miss latency |
691system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31044.943820 # average ReadExReq mshr miss latency |
692system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31042.226488 # average overall mshr miss latency 693system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31098.360656 # average overall mshr miss latency |
694system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31067.998962 # average overall mshr miss latency |
695system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31042.226488 # average overall mshr miss latency 696system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31098.360656 # average overall mshr miss latency |
697system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31067.998962 # average overall mshr miss latency |
698system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 699 700---------- End Simulation Statistics ---------- |